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Merge remote-tracking branch 'mst/tags/for_anthony' into staging
[qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw/hw.h"
26 #include "qemu-timer.h"
27 #include "hw/usb.h"
28 #include "hw/pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
137
138 /* Internal periodic / asynchronous schedule state machine states
139 */
140 typedef enum {
141 EST_INACTIVE = 1000,
142 EST_ACTIVE,
143 EST_EXECUTING,
144 EST_SLEEPING,
145 /* The following states are internal to the state machine function
146 */
147 EST_WAITLISTHEAD,
148 EST_FETCHENTRY,
149 EST_FETCHQH,
150 EST_FETCHITD,
151 EST_FETCHSITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIPacket EHCIPacket;
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIPacket {
348 EHCIQueue *queue;
349 QTAILQ_ENTRY(EHCIPacket) next;
350
351 EHCIqtd qtd; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr; /* address QTD read from */
353
354 USBPacket packet;
355 QEMUSGList sgl;
356 int pid;
357 uint32_t tbytes;
358 enum async_state async;
359 int usb_status;
360 };
361
362 struct EHCIQueue {
363 EHCIState *ehci;
364 QTAILQ_ENTRY(EHCIQueue) next;
365 uint32_t seen;
366 uint64_t ts;
367 int async;
368
369 /* cached data from guest - needs to be flushed
370 * when guest removes an entry (doorbell, handshake sequence)
371 */
372 EHCIqh qh; /* copy of current QH (being worked on) */
373 uint32_t qhaddr; /* address QH read from */
374 uint32_t qtdaddr; /* address QTD read from */
375 USBDevice *dev;
376 QTAILQ_HEAD(, EHCIPacket) packets;
377 };
378
379 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
380
381 struct EHCIState {
382 PCIDevice dev;
383 USBBus bus;
384 qemu_irq irq;
385 MemoryRegion mem;
386 int companion_count;
387
388 /* properties */
389 uint32_t maxframes;
390
391 /*
392 * EHCI spec version 1.0 Section 2.3
393 * Host Controller Operational Registers
394 */
395 union {
396 uint8_t mmio[MMIO_SIZE];
397 struct {
398 uint8_t cap[OPREGBASE];
399 uint32_t usbcmd;
400 uint32_t usbsts;
401 uint32_t usbintr;
402 uint32_t frindex;
403 uint32_t ctrldssegment;
404 uint32_t periodiclistbase;
405 uint32_t asynclistaddr;
406 uint32_t notused[9];
407 uint32_t configflag;
408 uint32_t portsc[NB_PORTS];
409 };
410 };
411
412 /*
413 * Internal states, shadow registers, etc
414 */
415 QEMUTimer *frame_timer;
416 QEMUBH *async_bh;
417 int astate; // Current state in asynchronous schedule
418 int pstate; // Current state in periodic schedule
419 USBPort ports[NB_PORTS];
420 USBPort *companion_ports[NB_PORTS];
421 uint32_t usbsts_pending;
422 EHCIQueueHead aqueues;
423 EHCIQueueHead pqueues;
424
425 uint32_t a_fetch_addr; // which address to look at next
426 uint32_t p_fetch_addr; // which address to look at next
427
428 USBPacket ipacket;
429 QEMUSGList isgl;
430
431 uint64_t last_run_ns;
432 uint32_t async_stepdown;
433 };
434
435 #define SET_LAST_RUN_CLOCK(s) \
436 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
437
438 /* nifty macros from Arnon's EHCI version */
439 #define get_field(data, field) \
440 (((data) & field##_MASK) >> field##_SH)
441
442 #define set_field(data, newval, field) do { \
443 uint32_t val = *data; \
444 val &= ~ field##_MASK; \
445 val |= ((newval) << field##_SH) & field##_MASK; \
446 *data = val; \
447 } while(0)
448
449 static const char *ehci_state_names[] = {
450 [EST_INACTIVE] = "INACTIVE",
451 [EST_ACTIVE] = "ACTIVE",
452 [EST_EXECUTING] = "EXECUTING",
453 [EST_SLEEPING] = "SLEEPING",
454 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
455 [EST_FETCHENTRY] = "FETCH ENTRY",
456 [EST_FETCHQH] = "FETCH QH",
457 [EST_FETCHITD] = "FETCH ITD",
458 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
459 [EST_FETCHQTD] = "FETCH QTD",
460 [EST_EXECUTE] = "EXECUTE",
461 [EST_WRITEBACK] = "WRITEBACK",
462 [EST_HORIZONTALQH] = "HORIZONTALQH",
463 };
464
465 static const char *ehci_mmio_names[] = {
466 [CAPLENGTH] = "CAPLENGTH",
467 [HCIVERSION] = "HCIVERSION",
468 [HCSPARAMS] = "HCSPARAMS",
469 [HCCPARAMS] = "HCCPARAMS",
470 [USBCMD] = "USBCMD",
471 [USBSTS] = "USBSTS",
472 [USBINTR] = "USBINTR",
473 [FRINDEX] = "FRINDEX",
474 [PERIODICLISTBASE] = "P-LIST BASE",
475 [ASYNCLISTADDR] = "A-LIST ADDR",
476 [PORTSC_BEGIN] = "PORTSC #0",
477 [PORTSC_BEGIN + 4] = "PORTSC #1",
478 [PORTSC_BEGIN + 8] = "PORTSC #2",
479 [PORTSC_BEGIN + 12] = "PORTSC #3",
480 [PORTSC_BEGIN + 16] = "PORTSC #4",
481 [PORTSC_BEGIN + 20] = "PORTSC #5",
482 [CONFIGFLAG] = "CONFIGFLAG",
483 };
484
485 static const char *nr2str(const char **n, size_t len, uint32_t nr)
486 {
487 if (nr < len && n[nr] != NULL) {
488 return n[nr];
489 } else {
490 return "unknown";
491 }
492 }
493
494 static const char *state2str(uint32_t state)
495 {
496 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
497 }
498
499 static const char *addr2str(target_phys_addr_t addr)
500 {
501 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
502 }
503
504 static void ehci_trace_usbsts(uint32_t mask, int state)
505 {
506 /* interrupts */
507 if (mask & USBSTS_INT) {
508 trace_usb_ehci_usbsts("INT", state);
509 }
510 if (mask & USBSTS_ERRINT) {
511 trace_usb_ehci_usbsts("ERRINT", state);
512 }
513 if (mask & USBSTS_PCD) {
514 trace_usb_ehci_usbsts("PCD", state);
515 }
516 if (mask & USBSTS_FLR) {
517 trace_usb_ehci_usbsts("FLR", state);
518 }
519 if (mask & USBSTS_HSE) {
520 trace_usb_ehci_usbsts("HSE", state);
521 }
522 if (mask & USBSTS_IAA) {
523 trace_usb_ehci_usbsts("IAA", state);
524 }
525
526 /* status */
527 if (mask & USBSTS_HALT) {
528 trace_usb_ehci_usbsts("HALT", state);
529 }
530 if (mask & USBSTS_REC) {
531 trace_usb_ehci_usbsts("REC", state);
532 }
533 if (mask & USBSTS_PSS) {
534 trace_usb_ehci_usbsts("PSS", state);
535 }
536 if (mask & USBSTS_ASS) {
537 trace_usb_ehci_usbsts("ASS", state);
538 }
539 }
540
541 static inline void ehci_set_usbsts(EHCIState *s, int mask)
542 {
543 if ((s->usbsts & mask) == mask) {
544 return;
545 }
546 ehci_trace_usbsts(mask, 1);
547 s->usbsts |= mask;
548 }
549
550 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
551 {
552 if ((s->usbsts & mask) == 0) {
553 return;
554 }
555 ehci_trace_usbsts(mask, 0);
556 s->usbsts &= ~mask;
557 }
558
559 static inline void ehci_set_interrupt(EHCIState *s, int intr)
560 {
561 int level = 0;
562
563 // TODO honour interrupt threshold requests
564
565 ehci_set_usbsts(s, intr);
566
567 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
568 level = 1;
569 }
570
571 qemu_set_irq(s->irq, level);
572 }
573
574 static inline void ehci_record_interrupt(EHCIState *s, int intr)
575 {
576 s->usbsts_pending |= intr;
577 }
578
579 static inline void ehci_commit_interrupt(EHCIState *s)
580 {
581 if (!s->usbsts_pending) {
582 return;
583 }
584 ehci_set_interrupt(s, s->usbsts_pending);
585 s->usbsts_pending = 0;
586 }
587
588 static void ehci_update_halt(EHCIState *s)
589 {
590 if (s->usbcmd & USBCMD_RUNSTOP) {
591 ehci_clear_usbsts(s, USBSTS_HALT);
592 } else {
593 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
594 ehci_set_usbsts(s, USBSTS_HALT);
595 }
596 }
597 }
598
599 static void ehci_set_state(EHCIState *s, int async, int state)
600 {
601 if (async) {
602 trace_usb_ehci_state("async", state2str(state));
603 s->astate = state;
604 if (s->astate == EST_INACTIVE) {
605 ehci_clear_usbsts(s, USBSTS_ASS);
606 ehci_update_halt(s);
607 } else {
608 ehci_set_usbsts(s, USBSTS_ASS);
609 }
610 } else {
611 trace_usb_ehci_state("periodic", state2str(state));
612 s->pstate = state;
613 if (s->pstate == EST_INACTIVE) {
614 ehci_clear_usbsts(s, USBSTS_PSS);
615 ehci_update_halt(s);
616 } else {
617 ehci_set_usbsts(s, USBSTS_PSS);
618 }
619 }
620 }
621
622 static int ehci_get_state(EHCIState *s, int async)
623 {
624 return async ? s->astate : s->pstate;
625 }
626
627 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
628 {
629 if (async) {
630 s->a_fetch_addr = addr;
631 } else {
632 s->p_fetch_addr = addr;
633 }
634 }
635
636 static int ehci_get_fetch_addr(EHCIState *s, int async)
637 {
638 return async ? s->a_fetch_addr : s->p_fetch_addr;
639 }
640
641 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
642 {
643 /* need three here due to argument count limits */
644 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
645 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
646 trace_usb_ehci_qh_fields(addr,
647 get_field(qh->epchar, QH_EPCHAR_RL),
648 get_field(qh->epchar, QH_EPCHAR_MPLEN),
649 get_field(qh->epchar, QH_EPCHAR_EPS),
650 get_field(qh->epchar, QH_EPCHAR_EP),
651 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
652 trace_usb_ehci_qh_bits(addr,
653 (bool)(qh->epchar & QH_EPCHAR_C),
654 (bool)(qh->epchar & QH_EPCHAR_H),
655 (bool)(qh->epchar & QH_EPCHAR_DTC),
656 (bool)(qh->epchar & QH_EPCHAR_I));
657 }
658
659 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
660 {
661 /* need three here due to argument count limits */
662 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
663 trace_usb_ehci_qtd_fields(addr,
664 get_field(qtd->token, QTD_TOKEN_TBYTES),
665 get_field(qtd->token, QTD_TOKEN_CPAGE),
666 get_field(qtd->token, QTD_TOKEN_CERR),
667 get_field(qtd->token, QTD_TOKEN_PID));
668 trace_usb_ehci_qtd_bits(addr,
669 (bool)(qtd->token & QTD_TOKEN_IOC),
670 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
671 (bool)(qtd->token & QTD_TOKEN_HALT),
672 (bool)(qtd->token & QTD_TOKEN_BABBLE),
673 (bool)(qtd->token & QTD_TOKEN_XACTERR));
674 }
675
676 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
677 {
678 trace_usb_ehci_itd(addr, itd->next,
679 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
680 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
681 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
682 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
683 }
684
685 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
686 EHCIsitd *sitd)
687 {
688 trace_usb_ehci_sitd(addr, sitd->next,
689 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
690 }
691
692 static inline bool ehci_enabled(EHCIState *s)
693 {
694 return s->usbcmd & USBCMD_RUNSTOP;
695 }
696
697 static inline bool ehci_async_enabled(EHCIState *s)
698 {
699 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
700 }
701
702 static inline bool ehci_periodic_enabled(EHCIState *s)
703 {
704 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
705 }
706
707 /* packet management */
708
709 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
710 {
711 EHCIPacket *p;
712
713 p = g_new0(EHCIPacket, 1);
714 p->queue = q;
715 usb_packet_init(&p->packet);
716 QTAILQ_INSERT_TAIL(&q->packets, p, next);
717 trace_usb_ehci_packet_action(p->queue, p, "alloc");
718 return p;
719 }
720
721 static void ehci_free_packet(EHCIPacket *p)
722 {
723 trace_usb_ehci_packet_action(p->queue, p, "free");
724 if (p->async == EHCI_ASYNC_INFLIGHT) {
725 usb_cancel_packet(&p->packet);
726 }
727 QTAILQ_REMOVE(&p->queue->packets, p, next);
728 usb_packet_cleanup(&p->packet);
729 g_free(p);
730 }
731
732 /* queue management */
733
734 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
735 {
736 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
737 EHCIQueue *q;
738
739 q = g_malloc0(sizeof(*q));
740 q->ehci = ehci;
741 q->qhaddr = addr;
742 q->async = async;
743 QTAILQ_INIT(&q->packets);
744 QTAILQ_INSERT_HEAD(head, q, next);
745 trace_usb_ehci_queue_action(q, "alloc");
746 return q;
747 }
748
749 static void ehci_free_queue(EHCIQueue *q)
750 {
751 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
752 EHCIPacket *p;
753
754 trace_usb_ehci_queue_action(q, "free");
755 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
756 ehci_free_packet(p);
757 }
758 QTAILQ_REMOVE(head, q, next);
759 g_free(q);
760 }
761
762 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
763 int async)
764 {
765 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
766 EHCIQueue *q;
767
768 QTAILQ_FOREACH(q, head, next) {
769 if (addr == q->qhaddr) {
770 return q;
771 }
772 }
773 return NULL;
774 }
775
776 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush)
777 {
778 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
779 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
780 EHCIQueue *q, *tmp;
781
782 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
783 if (q->seen) {
784 q->seen = 0;
785 q->ts = ehci->last_run_ns;
786 continue;
787 }
788 if (!flush && ehci->last_run_ns < q->ts + maxage) {
789 continue;
790 }
791 ehci_free_queue(q);
792 }
793 }
794
795 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
796 {
797 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
798 EHCIQueue *q, *tmp;
799
800 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
801 if (q->dev != dev) {
802 continue;
803 }
804 ehci_free_queue(q);
805 }
806 }
807
808 static void ehci_queues_rip_all(EHCIState *ehci, int async)
809 {
810 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
811 EHCIQueue *q, *tmp;
812
813 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
814 ehci_free_queue(q);
815 }
816 }
817
818 /* Attach or detach a device on root hub */
819
820 static void ehci_attach(USBPort *port)
821 {
822 EHCIState *s = port->opaque;
823 uint32_t *portsc = &s->portsc[port->index];
824
825 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
826
827 if (*portsc & PORTSC_POWNER) {
828 USBPort *companion = s->companion_ports[port->index];
829 companion->dev = port->dev;
830 companion->ops->attach(companion);
831 return;
832 }
833
834 *portsc |= PORTSC_CONNECT;
835 *portsc |= PORTSC_CSC;
836
837 ehci_set_interrupt(s, USBSTS_PCD);
838 }
839
840 static void ehci_detach(USBPort *port)
841 {
842 EHCIState *s = port->opaque;
843 uint32_t *portsc = &s->portsc[port->index];
844
845 trace_usb_ehci_port_detach(port->index);
846
847 if (*portsc & PORTSC_POWNER) {
848 USBPort *companion = s->companion_ports[port->index];
849 companion->ops->detach(companion);
850 companion->dev = NULL;
851 /*
852 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
853 * the port ownership is returned immediately to the EHCI controller."
854 */
855 *portsc &= ~PORTSC_POWNER;
856 return;
857 }
858
859 ehci_queues_rip_device(s, port->dev, 0);
860 ehci_queues_rip_device(s, port->dev, 1);
861
862 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
863 *portsc |= PORTSC_CSC;
864
865 ehci_set_interrupt(s, USBSTS_PCD);
866 }
867
868 static void ehci_child_detach(USBPort *port, USBDevice *child)
869 {
870 EHCIState *s = port->opaque;
871 uint32_t portsc = s->portsc[port->index];
872
873 if (portsc & PORTSC_POWNER) {
874 USBPort *companion = s->companion_ports[port->index];
875 companion->ops->child_detach(companion, child);
876 return;
877 }
878
879 ehci_queues_rip_device(s, child, 0);
880 ehci_queues_rip_device(s, child, 1);
881 }
882
883 static void ehci_wakeup(USBPort *port)
884 {
885 EHCIState *s = port->opaque;
886 uint32_t portsc = s->portsc[port->index];
887
888 if (portsc & PORTSC_POWNER) {
889 USBPort *companion = s->companion_ports[port->index];
890 if (companion->ops->wakeup) {
891 companion->ops->wakeup(companion);
892 } else {
893 qemu_bh_schedule(s->async_bh);
894 }
895 }
896 }
897
898 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
899 uint32_t portcount, uint32_t firstport)
900 {
901 EHCIState *s = container_of(bus, EHCIState, bus);
902 uint32_t i;
903
904 if (firstport + portcount > NB_PORTS) {
905 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
906 "firstport on masterbus");
907 error_printf_unless_qmp(
908 "firstport value of %u makes companion take ports %u - %u, which "
909 "is outside of the valid range of 0 - %u\n", firstport, firstport,
910 firstport + portcount - 1, NB_PORTS - 1);
911 return -1;
912 }
913
914 for (i = 0; i < portcount; i++) {
915 if (s->companion_ports[firstport + i]) {
916 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
917 "an USB masterbus");
918 error_printf_unless_qmp(
919 "port %u on masterbus %s already has a companion assigned\n",
920 firstport + i, bus->qbus.name);
921 return -1;
922 }
923 }
924
925 for (i = 0; i < portcount; i++) {
926 s->companion_ports[firstport + i] = ports[i];
927 s->ports[firstport + i].speedmask |=
928 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
929 /* Ensure devs attached before the initial reset go to the companion */
930 s->portsc[firstport + i] = PORTSC_POWNER;
931 }
932
933 s->companion_count++;
934 s->mmio[0x05] = (s->companion_count << 4) | portcount;
935
936 return 0;
937 }
938
939 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
940 {
941 USBDevice *dev;
942 USBPort *port;
943 int i;
944
945 for (i = 0; i < NB_PORTS; i++) {
946 port = &ehci->ports[i];
947 if (!(ehci->portsc[i] & PORTSC_PED)) {
948 DPRINTF("Port %d not enabled\n", i);
949 continue;
950 }
951 dev = usb_find_device(port, addr);
952 if (dev != NULL) {
953 return dev;
954 }
955 }
956 return NULL;
957 }
958
959 /* 4.1 host controller initialization */
960 static void ehci_reset(void *opaque)
961 {
962 EHCIState *s = opaque;
963 int i;
964 USBDevice *devs[NB_PORTS];
965
966 trace_usb_ehci_reset();
967
968 /*
969 * Do the detach before touching portsc, so that it correctly gets send to
970 * us or to our companion based on PORTSC_POWNER before the reset.
971 */
972 for(i = 0; i < NB_PORTS; i++) {
973 devs[i] = s->ports[i].dev;
974 if (devs[i] && devs[i]->attached) {
975 usb_detach(&s->ports[i]);
976 }
977 }
978
979 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
980
981 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
982 s->usbsts = USBSTS_HALT;
983
984 s->astate = EST_INACTIVE;
985 s->pstate = EST_INACTIVE;
986
987 for(i = 0; i < NB_PORTS; i++) {
988 if (s->companion_ports[i]) {
989 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
990 } else {
991 s->portsc[i] = PORTSC_PPOWER;
992 }
993 if (devs[i] && devs[i]->attached) {
994 usb_attach(&s->ports[i]);
995 usb_device_reset(devs[i]);
996 }
997 }
998 ehci_queues_rip_all(s, 0);
999 ehci_queues_rip_all(s, 1);
1000 qemu_del_timer(s->frame_timer);
1001 qemu_bh_cancel(s->async_bh);
1002 }
1003
1004 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
1005 {
1006 EHCIState *s = ptr;
1007 uint32_t val;
1008
1009 val = s->mmio[addr];
1010
1011 return val;
1012 }
1013
1014 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
1015 {
1016 EHCIState *s = ptr;
1017 uint32_t val;
1018
1019 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
1020
1021 return val;
1022 }
1023
1024 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
1025 {
1026 EHCIState *s = ptr;
1027 uint32_t val;
1028
1029 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
1030 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
1031
1032 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
1033 return val;
1034 }
1035
1036 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
1037 {
1038 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
1039 exit(1);
1040 }
1041
1042 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
1043 {
1044 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
1045 exit(1);
1046 }
1047
1048 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
1049 {
1050 USBDevice *dev = s->ports[port].dev;
1051 uint32_t *portsc = &s->portsc[port];
1052 uint32_t orig;
1053
1054 if (s->companion_ports[port] == NULL)
1055 return;
1056
1057 owner = owner & PORTSC_POWNER;
1058 orig = *portsc & PORTSC_POWNER;
1059
1060 if (!(owner ^ orig)) {
1061 return;
1062 }
1063
1064 if (dev && dev->attached) {
1065 usb_detach(&s->ports[port]);
1066 }
1067
1068 *portsc &= ~PORTSC_POWNER;
1069 *portsc |= owner;
1070
1071 if (dev && dev->attached) {
1072 usb_attach(&s->ports[port]);
1073 }
1074 }
1075
1076 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1077 {
1078 uint32_t *portsc = &s->portsc[port];
1079 USBDevice *dev = s->ports[port].dev;
1080
1081 /* Clear rwc bits */
1082 *portsc &= ~(val & PORTSC_RWC_MASK);
1083 /* The guest may clear, but not set the PED bit */
1084 *portsc &= val | ~PORTSC_PED;
1085 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1086 handle_port_owner_write(s, port, val);
1087 /* And finally apply RO_MASK */
1088 val &= PORTSC_RO_MASK;
1089
1090 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1091 trace_usb_ehci_port_reset(port, 1);
1092 }
1093
1094 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1095 trace_usb_ehci_port_reset(port, 0);
1096 if (dev && dev->attached) {
1097 usb_port_reset(&s->ports[port]);
1098 *portsc &= ~PORTSC_CSC;
1099 }
1100
1101 /*
1102 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1103 * to SW that this port has a high speed device attached
1104 */
1105 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1106 val |= PORTSC_PED;
1107 }
1108 }
1109
1110 *portsc &= ~PORTSC_RO_MASK;
1111 *portsc |= val;
1112 }
1113
1114 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1115 {
1116 EHCIState *s = ptr;
1117 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1118 uint32_t old = *mmio;
1119 int i;
1120
1121 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1122
1123 /* Only aligned reads are allowed on OHCI */
1124 if (addr & 3) {
1125 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1126 TARGET_FMT_plx "\n", addr);
1127 return;
1128 }
1129
1130 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1131 handle_port_status_write(s, (addr-PORTSC)/4, val);
1132 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1133 return;
1134 }
1135
1136 if (addr < OPREGBASE) {
1137 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1138 TARGET_FMT_plx "\n", addr);
1139 return;
1140 }
1141
1142
1143 /* Do any register specific pre-write processing here. */
1144 switch(addr) {
1145 case USBCMD:
1146 if (val & USBCMD_HCRESET) {
1147 ehci_reset(s);
1148 val = s->usbcmd;
1149 break;
1150 }
1151
1152 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1153 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1154 if (s->pstate == EST_INACTIVE) {
1155 SET_LAST_RUN_CLOCK(s);
1156 }
1157 ehci_update_halt(s);
1158 s->async_stepdown = 0;
1159 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1160 }
1161
1162 /* not supporting dynamic frame list size at the moment */
1163 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1164 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1165 val & USBCMD_FLS);
1166 val &= ~USBCMD_FLS;
1167 }
1168 break;
1169
1170 case USBSTS:
1171 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1172 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1173 val = s->usbsts;
1174 ehci_set_interrupt(s, 0);
1175 break;
1176
1177 case USBINTR:
1178 val &= USBINTR_MASK;
1179 break;
1180
1181 case FRINDEX:
1182 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1183 break;
1184
1185 case CONFIGFLAG:
1186 val &= 0x1;
1187 if (val) {
1188 for(i = 0; i < NB_PORTS; i++)
1189 handle_port_owner_write(s, i, 0);
1190 }
1191 break;
1192
1193 case PERIODICLISTBASE:
1194 if (ehci_periodic_enabled(s)) {
1195 fprintf(stderr,
1196 "ehci: PERIODIC list base register set while periodic schedule\n"
1197 " is enabled and HC is enabled\n");
1198 }
1199 break;
1200
1201 case ASYNCLISTADDR:
1202 if (ehci_async_enabled(s)) {
1203 fprintf(stderr,
1204 "ehci: ASYNC list address register set while async schedule\n"
1205 " is enabled and HC is enabled\n");
1206 }
1207 break;
1208 }
1209
1210 *mmio = val;
1211 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1212 }
1213
1214
1215 // TODO : Put in common header file, duplication from usb-ohci.c
1216
1217 /* Get an array of dwords from main memory */
1218 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1219 uint32_t *buf, int num)
1220 {
1221 int i;
1222
1223 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1224 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1225 *buf = le32_to_cpu(*buf);
1226 }
1227
1228 return 1;
1229 }
1230
1231 /* Put an array of dwords in to main memory */
1232 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1233 uint32_t *buf, int num)
1234 {
1235 int i;
1236
1237 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1238 uint32_t tmp = cpu_to_le32(*buf);
1239 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1240 }
1241
1242 return 1;
1243 }
1244
1245 // 4.10.2
1246
1247 static int ehci_qh_do_overlay(EHCIQueue *q)
1248 {
1249 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1250 int i;
1251 int dtoggle;
1252 int ping;
1253 int eps;
1254 int reload;
1255
1256 assert(p != NULL);
1257 assert(p->qtdaddr == q->qtdaddr);
1258
1259 // remember values in fields to preserve in qh after overlay
1260
1261 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1262 ping = q->qh.token & QTD_TOKEN_PING;
1263
1264 q->qh.current_qtd = p->qtdaddr;
1265 q->qh.next_qtd = p->qtd.next;
1266 q->qh.altnext_qtd = p->qtd.altnext;
1267 q->qh.token = p->qtd.token;
1268
1269
1270 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1271 if (eps == EHCI_QH_EPS_HIGH) {
1272 q->qh.token &= ~QTD_TOKEN_PING;
1273 q->qh.token |= ping;
1274 }
1275
1276 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1277 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1278
1279 for (i = 0; i < 5; i++) {
1280 q->qh.bufptr[i] = p->qtd.bufptr[i];
1281 }
1282
1283 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1284 // preserve QH DT bit
1285 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1286 q->qh.token |= dtoggle;
1287 }
1288
1289 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1290 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1291
1292 put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh,
1293 sizeof(EHCIqh) >> 2);
1294
1295 return 0;
1296 }
1297
1298 static int ehci_init_transfer(EHCIPacket *p)
1299 {
1300 uint32_t cpage, offset, bytes, plen;
1301 dma_addr_t page;
1302
1303 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1304 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1305 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1306 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
1307
1308 while (bytes > 0) {
1309 if (cpage > 4) {
1310 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1311 return USB_RET_PROCERR;
1312 }
1313
1314 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1315 page += offset;
1316 plen = bytes;
1317 if (plen > 4096 - offset) {
1318 plen = 4096 - offset;
1319 offset = 0;
1320 cpage++;
1321 }
1322
1323 qemu_sglist_add(&p->sgl, page, plen);
1324 bytes -= plen;
1325 }
1326 return 0;
1327 }
1328
1329 static void ehci_finish_transfer(EHCIQueue *q, int status)
1330 {
1331 uint32_t cpage, offset;
1332
1333 if (status > 0) {
1334 /* update cpage & offset */
1335 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1336 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1337
1338 offset += status;
1339 cpage += offset >> QTD_BUFPTR_SH;
1340 offset &= ~QTD_BUFPTR_MASK;
1341
1342 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1343 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1344 q->qh.bufptr[0] |= offset;
1345 }
1346 }
1347
1348 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1349 {
1350 EHCIPacket *p;
1351 EHCIState *s = port->opaque;
1352 uint32_t portsc = s->portsc[port->index];
1353
1354 if (portsc & PORTSC_POWNER) {
1355 USBPort *companion = s->companion_ports[port->index];
1356 companion->ops->complete(companion, packet);
1357 return;
1358 }
1359
1360 p = container_of(packet, EHCIPacket, packet);
1361 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1362 assert(p->async == EHCI_ASYNC_INFLIGHT);
1363 p->async = EHCI_ASYNC_FINISHED;
1364 p->usb_status = packet->result;
1365
1366 if (p->queue->async) {
1367 qemu_bh_schedule(p->queue->ehci->async_bh);
1368 }
1369 }
1370
1371 static void ehci_execute_complete(EHCIQueue *q)
1372 {
1373 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1374
1375 assert(p != NULL);
1376 assert(p->qtdaddr == q->qtdaddr);
1377 assert(p->async != EHCI_ASYNC_INFLIGHT);
1378 p->async = EHCI_ASYNC_NONE;
1379
1380 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1381 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1382
1383 if (p->usb_status < 0) {
1384 switch (p->usb_status) {
1385 case USB_RET_IOERROR:
1386 case USB_RET_NODEV:
1387 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1388 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1389 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1390 break;
1391 case USB_RET_STALL:
1392 q->qh.token |= QTD_TOKEN_HALT;
1393 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1394 break;
1395 case USB_RET_NAK:
1396 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1397 return; /* We're not done yet with this transaction */
1398 case USB_RET_BABBLE:
1399 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1400 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1401 break;
1402 default:
1403 /* should not be triggerable */
1404 fprintf(stderr, "USB invalid response %d\n", p->usb_status);
1405 assert(0);
1406 break;
1407 }
1408 } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) {
1409 p->usb_status = USB_RET_BABBLE;
1410 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1411 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1412 } else {
1413 // TODO check 4.12 for splits
1414
1415 if (p->tbytes && p->pid == USB_TOKEN_IN) {
1416 p->tbytes -= p->usb_status;
1417 } else {
1418 p->tbytes = 0;
1419 }
1420
1421 DPRINTF("updating tbytes to %d\n", p->tbytes);
1422 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES);
1423 }
1424 ehci_finish_transfer(q, p->usb_status);
1425 qemu_sglist_destroy(&p->sgl);
1426 usb_packet_unmap(&p->packet);
1427
1428 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1429 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1430
1431 if (q->qh.token & QTD_TOKEN_IOC) {
1432 ehci_record_interrupt(q->ehci, USBSTS_INT);
1433 }
1434 }
1435
1436 // 4.10.3
1437
1438 static int ehci_execute(EHCIPacket *p, const char *action)
1439 {
1440 USBEndpoint *ep;
1441 int ret;
1442 int endp;
1443
1444 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1445 fprintf(stderr, "Attempting to execute inactive qtd\n");
1446 return USB_RET_PROCERR;
1447 }
1448
1449 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1450 if (p->tbytes > BUFF_SIZE) {
1451 fprintf(stderr, "Request for more bytes than allowed\n");
1452 return USB_RET_PROCERR;
1453 }
1454
1455 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1456 switch (p->pid) {
1457 case 0:
1458 p->pid = USB_TOKEN_OUT;
1459 break;
1460 case 1:
1461 p->pid = USB_TOKEN_IN;
1462 break;
1463 case 2:
1464 p->pid = USB_TOKEN_SETUP;
1465 break;
1466 default:
1467 fprintf(stderr, "bad token\n");
1468 break;
1469 }
1470
1471 if (ehci_init_transfer(p) != 0) {
1472 return USB_RET_PROCERR;
1473 }
1474
1475 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1476 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1477
1478 usb_packet_setup(&p->packet, p->pid, ep);
1479 usb_packet_map(&p->packet, &p->sgl);
1480
1481 trace_usb_ehci_packet_action(p->queue, p, action);
1482 ret = usb_handle_packet(p->queue->dev, &p->packet);
1483 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1484 "(total %d) endp %x ret %d\n",
1485 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1486 q->packet.iov.size, q->tbytes, endp, ret);
1487
1488 if (ret > BUFF_SIZE) {
1489 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1490 return USB_RET_PROCERR;
1491 }
1492
1493 return ret;
1494 }
1495
1496 /* 4.7.2
1497 */
1498
1499 static int ehci_process_itd(EHCIState *ehci,
1500 EHCIitd *itd)
1501 {
1502 USBDevice *dev;
1503 USBEndpoint *ep;
1504 int ret;
1505 uint32_t i, len, pid, dir, devaddr, endp;
1506 uint32_t pg, off, ptr1, ptr2, max, mult;
1507
1508 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1509 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1510 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1511 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1512 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1513
1514 for(i = 0; i < 8; i++) {
1515 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1516 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1517 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1518 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1519 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1520 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1521
1522 if (len > max * mult) {
1523 len = max * mult;
1524 }
1525
1526 if (len > BUFF_SIZE) {
1527 return USB_RET_PROCERR;
1528 }
1529
1530 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1531 if (off + len > 4096) {
1532 /* transfer crosses page border */
1533 uint32_t len2 = off + len - 4096;
1534 uint32_t len1 = len - len2;
1535 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1536 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1537 } else {
1538 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1539 }
1540
1541 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1542
1543 dev = ehci_find_device(ehci, devaddr);
1544 ep = usb_ep_get(dev, pid, endp);
1545 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1546 usb_packet_setup(&ehci->ipacket, pid, ep);
1547 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1548 ret = usb_handle_packet(dev, &ehci->ipacket);
1549 assert(ret != USB_RET_ASYNC);
1550 usb_packet_unmap(&ehci->ipacket);
1551 } else {
1552 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1553 ret = USB_RET_NAK;
1554 }
1555 qemu_sglist_destroy(&ehci->isgl);
1556
1557 if (ret < 0) {
1558 switch (ret) {
1559 default:
1560 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1561 /* Fall through */
1562 case USB_RET_IOERROR:
1563 case USB_RET_NODEV:
1564 /* 3.3.2: XACTERR is only allowed on IN transactions */
1565 if (dir) {
1566 itd->transact[i] |= ITD_XACT_XACTERR;
1567 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1568 }
1569 break;
1570 case USB_RET_BABBLE:
1571 itd->transact[i] |= ITD_XACT_BABBLE;
1572 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1573 break;
1574 case USB_RET_NAK:
1575 /* no data for us, so do a zero-length transfer */
1576 ret = 0;
1577 break;
1578 }
1579 }
1580 if (ret >= 0) {
1581 if (!dir) {
1582 /* OUT */
1583 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1584 } else {
1585 /* IN */
1586 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1587 }
1588 }
1589 if (itd->transact[i] & ITD_XACT_IOC) {
1590 ehci_record_interrupt(ehci, USBSTS_INT);
1591 }
1592 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1593 }
1594 }
1595 return 0;
1596 }
1597
1598
1599 /*
1600 * Write the qh back to guest physical memory. This step isn't
1601 * in the EHCI spec but we need to do it since we don't share
1602 * physical memory with our guest VM.
1603 *
1604 * The first three dwords are read-only for the EHCI, so skip them
1605 * when writing back the qh.
1606 */
1607 static void ehci_flush_qh(EHCIQueue *q)
1608 {
1609 uint32_t *qh = (uint32_t *) &q->qh;
1610 uint32_t dwords = sizeof(EHCIqh) >> 2;
1611 uint32_t addr = NLPTR_GET(q->qhaddr);
1612
1613 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1614 }
1615
1616 /* This state is the entry point for asynchronous schedule
1617 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1618 */
1619 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1620 {
1621 EHCIqh qh;
1622 int i = 0;
1623 int again = 0;
1624 uint32_t entry = ehci->asynclistaddr;
1625
1626 /* set reclamation flag at start event (4.8.6) */
1627 if (async) {
1628 ehci_set_usbsts(ehci, USBSTS_REC);
1629 }
1630
1631 ehci_queues_rip_unused(ehci, async, 0);
1632
1633 /* Find the head of the list (4.9.1.1) */
1634 for(i = 0; i < MAX_QH; i++) {
1635 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1636 sizeof(EHCIqh) >> 2);
1637 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1638
1639 if (qh.epchar & QH_EPCHAR_H) {
1640 if (async) {
1641 entry |= (NLPTR_TYPE_QH << 1);
1642 }
1643
1644 ehci_set_fetch_addr(ehci, async, entry);
1645 ehci_set_state(ehci, async, EST_FETCHENTRY);
1646 again = 1;
1647 goto out;
1648 }
1649
1650 entry = qh.next;
1651 if (entry == ehci->asynclistaddr) {
1652 break;
1653 }
1654 }
1655
1656 /* no head found for list. */
1657
1658 ehci_set_state(ehci, async, EST_ACTIVE);
1659
1660 out:
1661 return again;
1662 }
1663
1664
1665 /* This state is the entry point for periodic schedule processing as
1666 * well as being a continuation state for async processing.
1667 */
1668 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1669 {
1670 int again = 0;
1671 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1672
1673 if (NLPTR_TBIT(entry)) {
1674 ehci_set_state(ehci, async, EST_ACTIVE);
1675 goto out;
1676 }
1677
1678 /* section 4.8, only QH in async schedule */
1679 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1680 fprintf(stderr, "non queue head request in async schedule\n");
1681 return -1;
1682 }
1683
1684 switch (NLPTR_TYPE_GET(entry)) {
1685 case NLPTR_TYPE_QH:
1686 ehci_set_state(ehci, async, EST_FETCHQH);
1687 again = 1;
1688 break;
1689
1690 case NLPTR_TYPE_ITD:
1691 ehci_set_state(ehci, async, EST_FETCHITD);
1692 again = 1;
1693 break;
1694
1695 case NLPTR_TYPE_STITD:
1696 ehci_set_state(ehci, async, EST_FETCHSITD);
1697 again = 1;
1698 break;
1699
1700 default:
1701 /* TODO: handle FSTN type */
1702 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1703 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1704 return -1;
1705 }
1706
1707 out:
1708 return again;
1709 }
1710
1711 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1712 {
1713 EHCIPacket *p;
1714 uint32_t entry, devaddr;
1715 EHCIQueue *q;
1716
1717 entry = ehci_get_fetch_addr(ehci, async);
1718 q = ehci_find_queue_by_qh(ehci, entry, async);
1719 if (NULL == q) {
1720 q = ehci_alloc_queue(ehci, entry, async);
1721 }
1722 p = QTAILQ_FIRST(&q->packets);
1723
1724 q->seen++;
1725 if (q->seen > 1) {
1726 /* we are going in circles -- stop processing */
1727 ehci_set_state(ehci, async, EST_ACTIVE);
1728 q = NULL;
1729 goto out;
1730 }
1731
1732 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1733 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1734 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1735
1736 devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1737 if (q->dev != NULL && q->dev->addr != devaddr) {
1738 if (!QTAILQ_EMPTY(&q->packets)) {
1739 /* should not happen (guest bug) */
1740 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
1741 ehci_free_packet(p);
1742 }
1743 }
1744 q->dev = NULL;
1745 }
1746 if (q->dev == NULL) {
1747 q->dev = ehci_find_device(q->ehci, devaddr);
1748 }
1749
1750 if (p && p->async == EHCI_ASYNC_INFLIGHT) {
1751 /* I/O still in progress -- skip queue */
1752 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1753 goto out;
1754 }
1755 if (p && p->async == EHCI_ASYNC_FINISHED) {
1756 /* I/O finished -- continue processing queue */
1757 trace_usb_ehci_packet_action(p->queue, p, "complete");
1758 ehci_set_state(ehci, async, EST_EXECUTING);
1759 goto out;
1760 }
1761
1762 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1763
1764 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1765 if (ehci->usbsts & USBSTS_REC) {
1766 ehci_clear_usbsts(ehci, USBSTS_REC);
1767 } else {
1768 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1769 " - done processing\n", q->qhaddr);
1770 ehci_set_state(ehci, async, EST_ACTIVE);
1771 q = NULL;
1772 goto out;
1773 }
1774 }
1775
1776 #if EHCI_DEBUG
1777 if (q->qhaddr != q->qh.next) {
1778 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1779 q->qhaddr,
1780 q->qh.epchar & QH_EPCHAR_H,
1781 q->qh.token & QTD_TOKEN_HALT,
1782 q->qh.token & QTD_TOKEN_ACTIVE,
1783 q->qh.next);
1784 }
1785 #endif
1786
1787 if (q->qh.token & QTD_TOKEN_HALT) {
1788 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1789
1790 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1791 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1792 q->qtdaddr = q->qh.current_qtd;
1793 ehci_set_state(ehci, async, EST_FETCHQTD);
1794
1795 } else {
1796 /* EHCI spec version 1.0 Section 4.10.2 */
1797 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1798 }
1799
1800 out:
1801 return q;
1802 }
1803
1804 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1805 {
1806 uint32_t entry;
1807 EHCIitd itd;
1808
1809 assert(!async);
1810 entry = ehci_get_fetch_addr(ehci, async);
1811
1812 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1813 sizeof(EHCIitd) >> 2);
1814 ehci_trace_itd(ehci, entry, &itd);
1815
1816 if (ehci_process_itd(ehci, &itd) != 0) {
1817 return -1;
1818 }
1819
1820 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1821 sizeof(EHCIitd) >> 2);
1822 ehci_set_fetch_addr(ehci, async, itd.next);
1823 ehci_set_state(ehci, async, EST_FETCHENTRY);
1824
1825 return 1;
1826 }
1827
1828 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1829 {
1830 uint32_t entry;
1831 EHCIsitd sitd;
1832
1833 assert(!async);
1834 entry = ehci_get_fetch_addr(ehci, async);
1835
1836 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1837 sizeof(EHCIsitd) >> 2);
1838 ehci_trace_sitd(ehci, entry, &sitd);
1839
1840 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1841 /* siTD is not active, nothing to do */;
1842 } else {
1843 /* TODO: split transfers are not implemented */
1844 fprintf(stderr, "WARNING: Skipping active siTD\n");
1845 }
1846
1847 ehci_set_fetch_addr(ehci, async, sitd.next);
1848 ehci_set_state(ehci, async, EST_FETCHENTRY);
1849 return 1;
1850 }
1851
1852 /* Section 4.10.2 - paragraph 3 */
1853 static int ehci_state_advqueue(EHCIQueue *q)
1854 {
1855 #if 0
1856 /* TO-DO: 4.10.2 - paragraph 2
1857 * if I-bit is set to 1 and QH is not active
1858 * go to horizontal QH
1859 */
1860 if (I-bit set) {
1861 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1862 goto out;
1863 }
1864 #endif
1865
1866 /*
1867 * want data and alt-next qTD is valid
1868 */
1869 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1870 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1871 q->qtdaddr = q->qh.altnext_qtd;
1872 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1873
1874 /*
1875 * next qTD is valid
1876 */
1877 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1878 q->qtdaddr = q->qh.next_qtd;
1879 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1880
1881 /*
1882 * no valid qTD, try next QH
1883 */
1884 } else {
1885 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1886 }
1887
1888 return 1;
1889 }
1890
1891 /* Section 4.10.2 - paragraph 4 */
1892 static int ehci_state_fetchqtd(EHCIQueue *q)
1893 {
1894 EHCIqtd qtd;
1895 EHCIPacket *p;
1896 int again = 0;
1897
1898 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1899 sizeof(EHCIqtd) >> 2);
1900 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1901
1902 p = QTAILQ_FIRST(&q->packets);
1903 while (p != NULL && p->qtdaddr != q->qtdaddr) {
1904 /* should not happen (guest bug) */
1905 ehci_free_packet(p);
1906 p = QTAILQ_FIRST(&q->packets);
1907 }
1908 if (p != NULL) {
1909 ehci_qh_do_overlay(q);
1910 ehci_flush_qh(q);
1911 if (p->async == EHCI_ASYNC_INFLIGHT) {
1912 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1913 } else {
1914 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1915 }
1916 again = 1;
1917 } else if (qtd.token & QTD_TOKEN_ACTIVE) {
1918 p = ehci_alloc_packet(q);
1919 p->qtdaddr = q->qtdaddr;
1920 p->qtd = qtd;
1921 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1922 again = 1;
1923 } else {
1924 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1925 again = 1;
1926 }
1927
1928 return again;
1929 }
1930
1931 static int ehci_state_horizqh(EHCIQueue *q)
1932 {
1933 int again = 0;
1934
1935 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1936 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1937 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1938 again = 1;
1939 } else {
1940 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1941 }
1942
1943 return again;
1944 }
1945
1946 static void ehci_fill_queue(EHCIPacket *p)
1947 {
1948 EHCIQueue *q = p->queue;
1949 EHCIqtd qtd = p->qtd;
1950 uint32_t qtdaddr;
1951
1952 for (;;) {
1953 if (NLPTR_TBIT(qtd.altnext) == 0) {
1954 break;
1955 }
1956 if (NLPTR_TBIT(qtd.next) != 0) {
1957 break;
1958 }
1959 qtdaddr = qtd.next;
1960 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1961 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
1962 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1963 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1964 break;
1965 }
1966 p = ehci_alloc_packet(q);
1967 p->qtdaddr = qtdaddr;
1968 p->qtd = qtd;
1969 p->usb_status = ehci_execute(p, "queue");
1970 assert(p->usb_status = USB_RET_ASYNC);
1971 p->async = EHCI_ASYNC_INFLIGHT;
1972 }
1973 }
1974
1975 static int ehci_state_execute(EHCIQueue *q)
1976 {
1977 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1978 int again = 0;
1979
1980 assert(p != NULL);
1981 assert(p->qtdaddr == q->qtdaddr);
1982
1983 if (ehci_qh_do_overlay(q) != 0) {
1984 return -1;
1985 }
1986
1987 // TODO verify enough time remains in the uframe as in 4.4.1.1
1988 // TODO write back ptr to async list when done or out of time
1989 // TODO Windows does not seem to ever set the MULT field
1990
1991 if (!q->async) {
1992 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1993 if (!transactCtr) {
1994 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1995 again = 1;
1996 goto out;
1997 }
1998 }
1999
2000 if (q->async) {
2001 ehci_set_usbsts(q->ehci, USBSTS_REC);
2002 }
2003
2004 p->usb_status = ehci_execute(p, "process");
2005 if (p->usb_status == USB_RET_PROCERR) {
2006 again = -1;
2007 goto out;
2008 }
2009 if (p->usb_status == USB_RET_ASYNC) {
2010 ehci_flush_qh(q);
2011 trace_usb_ehci_packet_action(p->queue, p, "async");
2012 p->async = EHCI_ASYNC_INFLIGHT;
2013 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2014 again = 1;
2015 ehci_fill_queue(p);
2016 goto out;
2017 }
2018
2019 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
2020 again = 1;
2021
2022 out:
2023 return again;
2024 }
2025
2026 static int ehci_state_executing(EHCIQueue *q)
2027 {
2028 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2029 int again = 0;
2030
2031 assert(p != NULL);
2032 assert(p->qtdaddr == q->qtdaddr);
2033
2034 ehci_execute_complete(q);
2035 if (p->usb_status == USB_RET_ASYNC) {
2036 goto out;
2037 }
2038 if (p->usb_status == USB_RET_PROCERR) {
2039 again = -1;
2040 goto out;
2041 }
2042
2043 // 4.10.3
2044 if (!q->async) {
2045 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2046 transactCtr--;
2047 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
2048 // 4.10.3, bottom of page 82, should exit this state when transaction
2049 // counter decrements to 0
2050 }
2051
2052 /* 4.10.5 */
2053 if (p->usb_status == USB_RET_NAK) {
2054 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2055 } else {
2056 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
2057 }
2058
2059 again = 1;
2060
2061 out:
2062 ehci_flush_qh(q);
2063 return again;
2064 }
2065
2066
2067 static int ehci_state_writeback(EHCIQueue *q)
2068 {
2069 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2070 int again = 0;
2071
2072 /* Write back the QTD from the QH area */
2073 assert(p != NULL);
2074 assert(p->qtdaddr == q->qtdaddr);
2075
2076 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2077 put_dwords(q->ehci, NLPTR_GET(p->qtdaddr), (uint32_t *) &q->qh.next_qtd,
2078 sizeof(EHCIqtd) >> 2);
2079 ehci_free_packet(p);
2080
2081 /*
2082 * EHCI specs say go horizontal here.
2083 *
2084 * We can also advance the queue here for performance reasons. We
2085 * need to take care to only take that shortcut in case we've
2086 * processed the qtd just written back without errors, i.e. halt
2087 * bit is clear.
2088 */
2089 if (q->qh.token & QTD_TOKEN_HALT) {
2090 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2091 again = 1;
2092 } else {
2093 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2094 again = 1;
2095 }
2096 return again;
2097 }
2098
2099 /*
2100 * This is the state machine that is common to both async and periodic
2101 */
2102
2103 static void ehci_advance_state(EHCIState *ehci, int async)
2104 {
2105 EHCIQueue *q = NULL;
2106 int again;
2107
2108 do {
2109 switch(ehci_get_state(ehci, async)) {
2110 case EST_WAITLISTHEAD:
2111 again = ehci_state_waitlisthead(ehci, async);
2112 break;
2113
2114 case EST_FETCHENTRY:
2115 again = ehci_state_fetchentry(ehci, async);
2116 break;
2117
2118 case EST_FETCHQH:
2119 q = ehci_state_fetchqh(ehci, async);
2120 if (q != NULL) {
2121 assert(q->async == async);
2122 again = 1;
2123 } else {
2124 again = 0;
2125 }
2126 break;
2127
2128 case EST_FETCHITD:
2129 again = ehci_state_fetchitd(ehci, async);
2130 break;
2131
2132 case EST_FETCHSITD:
2133 again = ehci_state_fetchsitd(ehci, async);
2134 break;
2135
2136 case EST_ADVANCEQUEUE:
2137 again = ehci_state_advqueue(q);
2138 break;
2139
2140 case EST_FETCHQTD:
2141 again = ehci_state_fetchqtd(q);
2142 break;
2143
2144 case EST_HORIZONTALQH:
2145 again = ehci_state_horizqh(q);
2146 break;
2147
2148 case EST_EXECUTE:
2149 again = ehci_state_execute(q);
2150 if (async) {
2151 ehci->async_stepdown = 0;
2152 }
2153 break;
2154
2155 case EST_EXECUTING:
2156 assert(q != NULL);
2157 if (async) {
2158 ehci->async_stepdown = 0;
2159 }
2160 again = ehci_state_executing(q);
2161 break;
2162
2163 case EST_WRITEBACK:
2164 assert(q != NULL);
2165 again = ehci_state_writeback(q);
2166 break;
2167
2168 default:
2169 fprintf(stderr, "Bad state!\n");
2170 again = -1;
2171 assert(0);
2172 break;
2173 }
2174
2175 if (again < 0) {
2176 fprintf(stderr, "processing error - resetting ehci HC\n");
2177 ehci_reset(ehci);
2178 again = 0;
2179 }
2180 }
2181 while (again);
2182
2183 ehci_commit_interrupt(ehci);
2184 }
2185
2186 static void ehci_advance_async_state(EHCIState *ehci)
2187 {
2188 const int async = 1;
2189
2190 switch(ehci_get_state(ehci, async)) {
2191 case EST_INACTIVE:
2192 if (!ehci_async_enabled(ehci)) {
2193 break;
2194 }
2195 ehci_set_state(ehci, async, EST_ACTIVE);
2196 // No break, fall through to ACTIVE
2197
2198 case EST_ACTIVE:
2199 if (!ehci_async_enabled(ehci)) {
2200 ehci_queues_rip_all(ehci, async);
2201 ehci_set_state(ehci, async, EST_INACTIVE);
2202 break;
2203 }
2204
2205 /* make sure guest has acknowledged the doorbell interrupt */
2206 /* TO-DO: is this really needed? */
2207 if (ehci->usbsts & USBSTS_IAA) {
2208 DPRINTF("IAA status bit still set.\n");
2209 break;
2210 }
2211
2212 /* check that address register has been set */
2213 if (ehci->asynclistaddr == 0) {
2214 break;
2215 }
2216
2217 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2218 ehci_advance_state(ehci, async);
2219
2220 /* If the doorbell is set, the guest wants to make a change to the
2221 * schedule. The host controller needs to release cached data.
2222 * (section 4.8.2)
2223 */
2224 if (ehci->usbcmd & USBCMD_IAAD) {
2225 /* Remove all unseen qhs from the async qhs queue */
2226 ehci_queues_rip_unused(ehci, async, 1);
2227 DPRINTF("ASYNC: doorbell request acknowledged\n");
2228 ehci->usbcmd &= ~USBCMD_IAAD;
2229 ehci_set_interrupt(ehci, USBSTS_IAA);
2230 }
2231 break;
2232
2233 default:
2234 /* this should only be due to a developer mistake */
2235 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2236 "Resetting to active\n", ehci->astate);
2237 assert(0);
2238 }
2239 }
2240
2241 static void ehci_advance_periodic_state(EHCIState *ehci)
2242 {
2243 uint32_t entry;
2244 uint32_t list;
2245 const int async = 0;
2246
2247 // 4.6
2248
2249 switch(ehci_get_state(ehci, async)) {
2250 case EST_INACTIVE:
2251 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2252 ehci_set_state(ehci, async, EST_ACTIVE);
2253 // No break, fall through to ACTIVE
2254 } else
2255 break;
2256
2257 case EST_ACTIVE:
2258 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2259 ehci_queues_rip_all(ehci, async);
2260 ehci_set_state(ehci, async, EST_INACTIVE);
2261 break;
2262 }
2263
2264 list = ehci->periodiclistbase & 0xfffff000;
2265 /* check that register has been set */
2266 if (list == 0) {
2267 break;
2268 }
2269 list |= ((ehci->frindex & 0x1ff8) >> 1);
2270
2271 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2272 entry = le32_to_cpu(entry);
2273
2274 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2275 ehci->frindex / 8, list, entry);
2276 ehci_set_fetch_addr(ehci, async,entry);
2277 ehci_set_state(ehci, async, EST_FETCHENTRY);
2278 ehci_advance_state(ehci, async);
2279 ehci_queues_rip_unused(ehci, async, 0);
2280 break;
2281
2282 default:
2283 /* this should only be due to a developer mistake */
2284 fprintf(stderr, "ehci: Bad periodic state %d. "
2285 "Resetting to active\n", ehci->pstate);
2286 assert(0);
2287 }
2288 }
2289
2290 static void ehci_update_frindex(EHCIState *ehci, int frames)
2291 {
2292 int i;
2293
2294 if (!ehci_enabled(ehci)) {
2295 return;
2296 }
2297
2298 for (i = 0; i < frames; i++) {
2299 ehci->frindex += 8;
2300
2301 if (ehci->frindex == 0x00002000) {
2302 ehci_set_interrupt(ehci, USBSTS_FLR);
2303 }
2304
2305 if (ehci->frindex == 0x00004000) {
2306 ehci_set_interrupt(ehci, USBSTS_FLR);
2307 ehci->frindex = 0;
2308 }
2309 }
2310 }
2311
2312 static void ehci_frame_timer(void *opaque)
2313 {
2314 EHCIState *ehci = opaque;
2315 int schedules = 0;
2316 int64_t expire_time, t_now;
2317 uint64_t ns_elapsed;
2318 int frames, skipped_frames;
2319 int i;
2320
2321 t_now = qemu_get_clock_ns(vm_clock);
2322 ns_elapsed = t_now - ehci->last_run_ns;
2323 frames = ns_elapsed / FRAME_TIMER_NS;
2324
2325 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2326 schedules++;
2327 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
2328
2329 if (frames > ehci->maxframes) {
2330 skipped_frames = frames - ehci->maxframes;
2331 ehci_update_frindex(ehci, skipped_frames);
2332 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2333 frames -= skipped_frames;
2334 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2335 }
2336
2337 for (i = 0; i < frames; i++) {
2338 ehci_update_frindex(ehci, 1);
2339 ehci_advance_periodic_state(ehci);
2340 ehci->last_run_ns += FRAME_TIMER_NS;
2341 }
2342 } else {
2343 if (ehci->async_stepdown < ehci->maxframes / 2) {
2344 ehci->async_stepdown++;
2345 }
2346 expire_time = t_now + (get_ticks_per_sec()
2347 * ehci->async_stepdown / FRAME_TIMER_FREQ);
2348 ehci_update_frindex(ehci, frames);
2349 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2350 }
2351
2352 /* Async is not inside loop since it executes everything it can once
2353 * called
2354 */
2355 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2356 schedules++;
2357 qemu_bh_schedule(ehci->async_bh);
2358 }
2359
2360 if (schedules) {
2361 qemu_mod_timer(ehci->frame_timer, expire_time);
2362 }
2363 }
2364
2365 static void ehci_async_bh(void *opaque)
2366 {
2367 EHCIState *ehci = opaque;
2368 ehci_advance_async_state(ehci);
2369 }
2370
2371 static const MemoryRegionOps ehci_mem_ops = {
2372 .old_mmio = {
2373 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2374 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2375 },
2376 .endianness = DEVICE_LITTLE_ENDIAN,
2377 };
2378
2379 static int usb_ehci_initfn(PCIDevice *dev);
2380
2381 static USBPortOps ehci_port_ops = {
2382 .attach = ehci_attach,
2383 .detach = ehci_detach,
2384 .child_detach = ehci_child_detach,
2385 .wakeup = ehci_wakeup,
2386 .complete = ehci_async_complete_packet,
2387 };
2388
2389 static USBBusOps ehci_bus_ops = {
2390 .register_companion = ehci_register_companion,
2391 };
2392
2393 static const VMStateDescription vmstate_ehci = {
2394 .name = "ehci",
2395 .unmigratable = 1,
2396 };
2397
2398 static Property ehci_properties[] = {
2399 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2400 DEFINE_PROP_END_OF_LIST(),
2401 };
2402
2403 static void ehci_class_init(ObjectClass *klass, void *data)
2404 {
2405 DeviceClass *dc = DEVICE_CLASS(klass);
2406 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2407
2408 k->init = usb_ehci_initfn;
2409 k->vendor_id = PCI_VENDOR_ID_INTEL;
2410 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2411 k->revision = 0x10;
2412 k->class_id = PCI_CLASS_SERIAL_USB;
2413 dc->vmsd = &vmstate_ehci;
2414 dc->props = ehci_properties;
2415 }
2416
2417 static TypeInfo ehci_info = {
2418 .name = "usb-ehci",
2419 .parent = TYPE_PCI_DEVICE,
2420 .instance_size = sizeof(EHCIState),
2421 .class_init = ehci_class_init,
2422 };
2423
2424 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2425 {
2426 DeviceClass *dc = DEVICE_CLASS(klass);
2427 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2428
2429 k->init = usb_ehci_initfn;
2430 k->vendor_id = PCI_VENDOR_ID_INTEL;
2431 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2432 k->revision = 0x03;
2433 k->class_id = PCI_CLASS_SERIAL_USB;
2434 dc->vmsd = &vmstate_ehci;
2435 dc->props = ehci_properties;
2436 }
2437
2438 static TypeInfo ich9_ehci_info = {
2439 .name = "ich9-usb-ehci1",
2440 .parent = TYPE_PCI_DEVICE,
2441 .instance_size = sizeof(EHCIState),
2442 .class_init = ich9_ehci_class_init,
2443 };
2444
2445 static int usb_ehci_initfn(PCIDevice *dev)
2446 {
2447 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2448 uint8_t *pci_conf = s->dev.config;
2449 int i;
2450
2451 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2452
2453 /* capabilities pointer */
2454 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2455 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2456
2457 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2458 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2459 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2460
2461 // pci_conf[0x50] = 0x01; // power management caps
2462
2463 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2464 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2465 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2466
2467 pci_conf[0x64] = 0x00;
2468 pci_conf[0x65] = 0x00;
2469 pci_conf[0x66] = 0x00;
2470 pci_conf[0x67] = 0x00;
2471 pci_conf[0x68] = 0x01;
2472 pci_conf[0x69] = 0x00;
2473 pci_conf[0x6a] = 0x00;
2474 pci_conf[0x6b] = 0x00; // USBLEGSUP
2475 pci_conf[0x6c] = 0x00;
2476 pci_conf[0x6d] = 0x00;
2477 pci_conf[0x6e] = 0x00;
2478 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2479
2480 // 2.2 host controller interface version
2481 s->mmio[0x00] = (uint8_t) OPREGBASE;
2482 s->mmio[0x01] = 0x00;
2483 s->mmio[0x02] = 0x00;
2484 s->mmio[0x03] = 0x01; // HC version
2485 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2486 s->mmio[0x05] = 0x00; // No companion ports at present
2487 s->mmio[0x06] = 0x00;
2488 s->mmio[0x07] = 0x00;
2489 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2490 s->mmio[0x09] = 0x68; // EECP
2491 s->mmio[0x0a] = 0x00;
2492 s->mmio[0x0b] = 0x00;
2493
2494 s->irq = s->dev.irq[3];
2495
2496 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2497 for(i = 0; i < NB_PORTS; i++) {
2498 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2499 USB_SPEED_MASK_HIGH);
2500 s->ports[i].dev = 0;
2501 }
2502
2503 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2504 s->async_bh = qemu_bh_new(ehci_async_bh, s);
2505 QTAILQ_INIT(&s->aqueues);
2506 QTAILQ_INIT(&s->pqueues);
2507
2508 qemu_register_reset(ehci_reset, s);
2509
2510 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2511 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2512
2513 return 0;
2514 }
2515
2516 static void ehci_register_types(void)
2517 {
2518 type_register_static(&ehci_info);
2519 type_register_static(&ich9_ehci_info);
2520 }
2521
2522 type_init(ehci_register_types)
2523
2524 /*
2525 * vim: expandtab ts=4
2526 */
Qemu copy for testing