hw/usb/hcd-uhci.c

   1 /*
   2  * USB UHCI controller emulation
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Copyright (c) 2008 Max Krasnyansky
   7  *     Magor rewrite of the UHCI data structures parser and frame processor
   8  *     Support for fully async operation and multiple outstanding transactions
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28 #include "hw/hw.h"
  29 #include "hw/usb.h"
  30 #include "hw/pci.h"
  31 #include "qemu-timer.h"
  32 #include "iov.h"
  33 #include "dma.h"
  34 #include "trace.h"
  35
  36 //#define DEBUG
  37 //#define DEBUG_DUMP_DATA
  38
  39 #define UHCI_CMD_FGR      (1 << 4)
  40 #define UHCI_CMD_EGSM     (1 << 3)
  41 #define UHCI_CMD_GRESET   (1 << 2)
  42 #define UHCI_CMD_HCRESET  (1 << 1)
  43 #define UHCI_CMD_RS       (1 << 0)
  44
  45 #define UHCI_STS_HCHALTED (1 << 5)
  46 #define UHCI_STS_HCPERR   (1 << 4)
  47 #define UHCI_STS_HSERR    (1 << 3)
  48 #define UHCI_STS_RD       (1 << 2)
  49 #define UHCI_STS_USBERR   (1 << 1)
  50 #define UHCI_STS_USBINT   (1 << 0)
  51
  52 #define TD_CTRL_SPD     (1 << 29)
  53 #define TD_CTRL_ERROR_SHIFT  27
  54 #define TD_CTRL_IOS     (1 << 25)
  55 #define TD_CTRL_IOC     (1 << 24)
  56 #define TD_CTRL_ACTIVE  (1 << 23)
  57 #define TD_CTRL_STALL   (1 << 22)
  58 #define TD_CTRL_BABBLE  (1 << 20)
  59 #define TD_CTRL_NAK     (1 << 19)
  60 #define TD_CTRL_TIMEOUT (1 << 18)
  61
  62 #define UHCI_PORT_SUSPEND (1 << 12)
  63 #define UHCI_PORT_RESET (1 << 9)
  64 #define UHCI_PORT_LSDA  (1 << 8)
  65 #define UHCI_PORT_RD    (1 << 6)
  66 #define UHCI_PORT_ENC   (1 << 3)
  67 #define UHCI_PORT_EN    (1 << 2)
  68 #define UHCI_PORT_CSC   (1 << 1)
  69 #define UHCI_PORT_CCS   (1 << 0)
  70
  71 #define UHCI_PORT_READ_ONLY    (0x1bb)
  72 #define UHCI_PORT_WRITE_CLEAR  (UHCI_PORT_CSC | UHCI_PORT_ENC)
  73
  74 #define FRAME_TIMER_FREQ 1000
  75
  76 #define FRAME_MAX_LOOPS  256
  77
  78 #define NB_PORTS 2
  79
  80 enum {
  81     TD_RESULT_STOP_FRAME = 10,
  82     TD_RESULT_COMPLETE,
  83     TD_RESULT_NEXT_QH,
  84     TD_RESULT_ASYNC_START,
  85     TD_RESULT_ASYNC_CONT,
  86 };
  87
  88 typedef struct UHCIState UHCIState;
  89 typedef struct UHCIAsync UHCIAsync;
  90 typedef struct UHCIQueue UHCIQueue;
  91
  92 /*
  93  * Pending async transaction.
  94  * 'packet' must be the first field because completion
  95  * handler does "(UHCIAsync *) pkt" cast.
  96  */
  97
  98 struct UHCIAsync {
  99     USBPacket packet;
 100     QEMUSGList sgl;
 101     UHCIQueue *queue;
 102     QTAILQ_ENTRY(UHCIAsync) next;
 103     uint32_t  td;
 104     uint8_t   isoc;
 105     uint8_t   done;
 106 };
 107
 108 struct UHCIQueue {
 109     uint32_t  token;
 110     UHCIState *uhci;
 111     QTAILQ_ENTRY(UHCIQueue) next;
 112     QTAILQ_HEAD(, UHCIAsync) asyncs;
 113     int8_t    valid;
 114 };
 115
 116 typedef struct UHCIPort {
 117     USBPort port;
 118     uint16_t ctrl;
 119 } UHCIPort;
 120
 121 struct UHCIState {
 122     PCIDevice dev;
 123     MemoryRegion io_bar;
 124     USBBus bus; /* Note unused when we're a companion controller */
 125     uint16_t cmd; /* cmd register */
 126     uint16_t status;
 127     uint16_t intr; /* interrupt enable register */
 128     uint16_t frnum; /* frame number */
 129     uint32_t fl_base_addr; /* frame list base address */
 130     uint8_t sof_timing;
 131     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
 132     int64_t expire_time;
 133     QEMUTimer *frame_timer;
 134     QEMUBH *bh;
 135     uint32_t frame_bytes;
 136     uint32_t frame_bandwidth;
 137     UHCIPort ports[NB_PORTS];
 138
 139     /* Interrupts that should be raised at the end of the current frame.  */
 140     uint32_t pending_int_mask;
 141     int irq_pin;
 142
 143     /* Active packets */
 144     QTAILQ_HEAD(, UHCIQueue) queues;
 145     uint8_t num_ports_vmstate;
 146
 147     /* Properties */
 148     char *masterbus;
 149     uint32_t firstport;
 150 };
 151
 152 typedef struct UHCI_TD {
 153     uint32_t link;
 154     uint32_t ctrl; /* see TD_CTRL_xxx */
 155     uint32_t token;
 156     uint32_t buffer;
 157 } UHCI_TD;
 158
 159 typedef struct UHCI_QH {
 160     uint32_t link;
 161     uint32_t el_link;
 162 } UHCI_QH;
 163
 164 static inline int32_t uhci_queue_token(UHCI_TD *td)
 165 {
 166     /* covers ep, dev, pid -> identifies the endpoint */
 167     return td->token & 0x7ffff;
 168 }
 169
 170 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td)
 171 {
 172     uint32_t token = uhci_queue_token(td);
 173     UHCIQueue *queue;
 174
 175     QTAILQ_FOREACH(queue, &s->queues, next) {
 176         if (queue->token == token) {
 177             return queue;
 178         }
 179     }
 180
 181     queue = g_new0(UHCIQueue, 1);
 182     queue->uhci = s;
 183     queue->token = token;
 184     QTAILQ_INIT(&queue->asyncs);
 185     QTAILQ_INSERT_HEAD(&s->queues, queue, next);
 186     trace_usb_uhci_queue_add(queue->token);
 187     return queue;
 188 }
 189
 190 static void uhci_queue_free(UHCIQueue *queue)
 191 {
 192     UHCIState *s = queue->uhci;
 193
 194     trace_usb_uhci_queue_del(queue->token);
 195     QTAILQ_REMOVE(&s->queues, queue, next);
 196     g_free(queue);
 197 }
 198
 199 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr)
 200 {
 201     UHCIAsync *async = g_new0(UHCIAsync, 1);
 202
 203     async->queue = queue;
 204     async->td = addr;
 205     usb_packet_init(&async->packet);
 206     pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
 207     trace_usb_uhci_packet_add(async->queue->token, async->td);
 208
 209     return async;
 210 }
 211
 212 static void uhci_async_free(UHCIAsync *async)
 213 {
 214     trace_usb_uhci_packet_del(async->queue->token, async->td);
 215     usb_packet_cleanup(&async->packet);
 216     qemu_sglist_destroy(&async->sgl);
 217     g_free(async);
 218 }
 219
 220 static void uhci_async_link(UHCIAsync *async)
 221 {
 222     UHCIQueue *queue = async->queue;
 223     QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
 224     trace_usb_uhci_packet_link_async(async->queue->token, async->td);
 225 }
 226
 227 static void uhci_async_unlink(UHCIAsync *async)
 228 {
 229     UHCIQueue *queue = async->queue;
 230     QTAILQ_REMOVE(&queue->asyncs, async, next);
 231     trace_usb_uhci_packet_unlink_async(async->queue->token, async->td);
 232 }
 233
 234 static void uhci_async_cancel(UHCIAsync *async)
 235 {
 236     trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done);
 237     if (!async->done)
 238         usb_cancel_packet(&async->packet);
 239     usb_packet_unmap(&async->packet, &async->sgl);
 240     uhci_async_free(async);
 241 }
 242
 243 /*
 244  * Mark all outstanding async packets as invalid.
 245  * This is used for canceling them when TDs are removed by the HCD.
 246  */
 247 static void uhci_async_validate_begin(UHCIState *s)
 248 {
 249     UHCIQueue *queue;
 250
 251     QTAILQ_FOREACH(queue, &s->queues, next) {
 252         queue->valid--;
 253     }
 254 }
 255
 256 /*
 257  * Cancel async packets that are no longer valid
 258  */
 259 static void uhci_async_validate_end(UHCIState *s)
 260 {
 261     UHCIQueue *queue, *n;
 262     UHCIAsync *async;
 263
 264     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
 265         if (queue->valid > 0) {
 266             continue;
 267         }
 268         while (!QTAILQ_EMPTY(&queue->asyncs)) {
 269             async = QTAILQ_FIRST(&queue->asyncs);
 270             uhci_async_unlink(async);
 271             uhci_async_cancel(async);
 272         }
 273         uhci_queue_free(queue);
 274     }
 275 }
 276
 277 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
 278 {
 279     UHCIQueue *queue;
 280     UHCIAsync *curr, *n;
 281
 282     QTAILQ_FOREACH(queue, &s->queues, next) {
 283         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 284             if (!usb_packet_is_inflight(&curr->packet) ||
 285                 curr->packet.ep->dev != dev) {
 286                 continue;
 287             }
 288             uhci_async_unlink(curr);
 289             uhci_async_cancel(curr);
 290         }
 291     }
 292 }
 293
 294 static void uhci_async_cancel_all(UHCIState *s)
 295 {
 296     UHCIQueue *queue, *nq;
 297     UHCIAsync *curr, *n;
 298
 299     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
 300         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 301             uhci_async_unlink(curr);
 302             uhci_async_cancel(curr);
 303         }
 304         uhci_queue_free(queue);
 305     }
 306 }
 307
 308 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td)
 309 {
 310     uint32_t token = uhci_queue_token(td);
 311     UHCIQueue *queue;
 312     UHCIAsync *async;
 313
 314     QTAILQ_FOREACH(queue, &s->queues, next) {
 315         if (queue->token == token) {
 316             break;
 317         }
 318     }
 319     if (queue == NULL) {
 320         return NULL;
 321     }
 322
 323     QTAILQ_FOREACH(async, &queue->asyncs, next) {
 324         if (async->td == addr) {
 325             return async;
 326         }
 327     }
 328
 329     return NULL;
 330 }
 331
 332 static void uhci_update_irq(UHCIState *s)
 333 {
 334     int level;
 335     if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
 336         ((s->status2 & 2) && (s->intr & (1 << 3))) ||
 337         ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
 338         ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
 339         (s->status & UHCI_STS_HSERR) ||
 340         (s->status & UHCI_STS_HCPERR)) {
 341         level = 1;
 342     } else {
 343         level = 0;
 344     }
 345     qemu_set_irq(s->dev.irq[s->irq_pin], level);
 346 }
 347
 348 static void uhci_reset(void *opaque)
 349 {
 350     UHCIState *s = opaque;
 351     uint8_t *pci_conf;
 352     int i;
 353     UHCIPort *port;
 354
 355     trace_usb_uhci_reset();
 356
 357     pci_conf = s->dev.config;
 358
 359     pci_conf[0x6a] = 0x01; /* usb clock */
 360     pci_conf[0x6b] = 0x00;
 361     s->cmd = 0;
 362     s->status = 0;
 363     s->status2 = 0;
 364     s->intr = 0;
 365     s->fl_base_addr = 0;
 366     s->sof_timing = 64;
 367
 368     for(i = 0; i < NB_PORTS; i++) {
 369         port = &s->ports[i];
 370         port->ctrl = 0x0080;
 371         if (port->port.dev && port->port.dev->attached) {
 372             usb_port_reset(&port->port);
 373         }
 374     }
 375
 376     uhci_async_cancel_all(s);
 377     qemu_bh_cancel(s->bh);
 378     uhci_update_irq(s);
 379 }
 380
 381 static const VMStateDescription vmstate_uhci_port = {
 382     .name = "uhci port",
 383     .version_id = 1,
 384     .minimum_version_id = 1,
 385     .minimum_version_id_old = 1,
 386     .fields      = (VMStateField []) {
 387         VMSTATE_UINT16(ctrl, UHCIPort),
 388         VMSTATE_END_OF_LIST()
 389     }
 390 };
 391
 392 static int uhci_post_load(void *opaque, int version_id)
 393 {
 394     UHCIState *s = opaque;
 395
 396     if (version_id < 2) {
 397         s->expire_time = qemu_get_clock_ns(vm_clock) +
 398             (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 399     }
 400     return 0;
 401 }
 402
 403 static const VMStateDescription vmstate_uhci = {
 404     .name = "uhci",
 405     .version_id = 2,
 406     .minimum_version_id = 1,
 407     .minimum_version_id_old = 1,
 408     .post_load = uhci_post_load,
 409     .fields      = (VMStateField []) {
 410         VMSTATE_PCI_DEVICE(dev, UHCIState),
 411         VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
 412         VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
 413                              vmstate_uhci_port, UHCIPort),
 414         VMSTATE_UINT16(cmd, UHCIState),
 415         VMSTATE_UINT16(status, UHCIState),
 416         VMSTATE_UINT16(intr, UHCIState),
 417         VMSTATE_UINT16(frnum, UHCIState),
 418         VMSTATE_UINT32(fl_base_addr, UHCIState),
 419         VMSTATE_UINT8(sof_timing, UHCIState),
 420         VMSTATE_UINT8(status2, UHCIState),
 421         VMSTATE_TIMER(frame_timer, UHCIState),
 422         VMSTATE_INT64_V(expire_time, UHCIState, 2),
 423         VMSTATE_END_OF_LIST()
 424     }
 425 };
 426
 427 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 428 {
 429     UHCIState *s = opaque;
 430
 431     addr &= 0x1f;
 432     switch(addr) {
 433     case 0x0c:
 434         s->sof_timing = val;
 435         break;
 436     }
 437 }
 438
 439 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
 440 {
 441     UHCIState *s = opaque;
 442     uint32_t val;
 443
 444     addr &= 0x1f;
 445     switch(addr) {
 446     case 0x0c:
 447         val = s->sof_timing;
 448         break;
 449     default:
 450         val = 0xff;
 451         break;
 452     }
 453     return val;
 454 }
 455
 456 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 457 {
 458     UHCIState *s = opaque;
 459
 460     addr &= 0x1f;
 461     trace_usb_uhci_mmio_writew(addr, val);
 462
 463     switch(addr) {
 464     case 0x00:
 465         if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
 466             /* start frame processing */
 467             trace_usb_uhci_schedule_start();
 468             s->expire_time = qemu_get_clock_ns(vm_clock) +
 469                 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 470             qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
 471             s->status &= ~UHCI_STS_HCHALTED;
 472         } else if (!(val & UHCI_CMD_RS)) {
 473             s->status |= UHCI_STS_HCHALTED;
 474         }
 475         if (val & UHCI_CMD_GRESET) {
 476             UHCIPort *port;
 477             int i;
 478
 479             /* send reset on the USB bus */
 480             for(i = 0; i < NB_PORTS; i++) {
 481                 port = &s->ports[i];
 482                 usb_device_reset(port->port.dev);
 483             }
 484             uhci_reset(s);
 485             return;
 486         }
 487         if (val & UHCI_CMD_HCRESET) {
 488             uhci_reset(s);
 489             return;
 490         }
 491         s->cmd = val;
 492         break;
 493     case 0x02:
 494         s->status &= ~val;
 495         /* XXX: the chip spec is not coherent, so we add a hidden
 496            register to distinguish between IOC and SPD */
 497         if (val & UHCI_STS_USBINT)
 498             s->status2 = 0;
 499         uhci_update_irq(s);
 500         break;
 501     case 0x04:
 502         s->intr = val;
 503         uhci_update_irq(s);
 504         break;
 505     case 0x06:
 506         if (s->status & UHCI_STS_HCHALTED)
 507             s->frnum = val & 0x7ff;
 508         break;
 509     case 0x10 ... 0x1f:
 510         {
 511             UHCIPort *port;
 512             USBDevice *dev;
 513             int n;
 514
 515             n = (addr >> 1) & 7;
 516             if (n >= NB_PORTS)
 517                 return;
 518             port = &s->ports[n];
 519             dev = port->port.dev;
 520             if (dev && dev->attached) {
 521                 /* port reset */
 522                 if ( (val & UHCI_PORT_RESET) &&
 523                      !(port->ctrl & UHCI_PORT_RESET) ) {
 524                     usb_device_reset(dev);
 525                 }
 526             }
 527             port->ctrl &= UHCI_PORT_READ_ONLY;
 528             port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
 529             /* some bits are reset when a '1' is written to them */
 530             port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
 531         }
 532         break;
 533     }
 534 }
 535
 536 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
 537 {
 538     UHCIState *s = opaque;
 539     uint32_t val;
 540
 541     addr &= 0x1f;
 542     switch(addr) {
 543     case 0x00:
 544         val = s->cmd;
 545         break;
 546     case 0x02:
 547         val = s->status;
 548         break;
 549     case 0x04:
 550         val = s->intr;
 551         break;
 552     case 0x06:
 553         val = s->frnum;
 554         break;
 555     case 0x10 ... 0x1f:
 556         {
 557             UHCIPort *port;
 558             int n;
 559             n = (addr >> 1) & 7;
 560             if (n >= NB_PORTS)
 561                 goto read_default;
 562             port = &s->ports[n];
 563             val = port->ctrl;
 564         }
 565         break;
 566     default:
 567     read_default:
 568         val = 0xff7f; /* disabled port */
 569         break;
 570     }
 571
 572     trace_usb_uhci_mmio_readw(addr, val);
 573
 574     return val;
 575 }
 576
 577 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 578 {
 579     UHCIState *s = opaque;
 580
 581     addr &= 0x1f;
 582     trace_usb_uhci_mmio_writel(addr, val);
 583
 584     switch(addr) {
 585     case 0x08:
 586         s->fl_base_addr = val & ~0xfff;
 587         break;
 588     }
 589 }
 590
 591 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
 592 {
 593     UHCIState *s = opaque;
 594     uint32_t val;
 595
 596     addr &= 0x1f;
 597     switch(addr) {
 598     case 0x08:
 599         val = s->fl_base_addr;
 600         break;
 601     default:
 602         val = 0xffffffff;
 603         break;
 604     }
 605     trace_usb_uhci_mmio_readl(addr, val);
 606     return val;
 607 }
 608
 609 /* signal resume if controller suspended */
 610 static void uhci_resume (void *opaque)
 611 {
 612     UHCIState *s = (UHCIState *)opaque;
 613
 614     if (!s)
 615         return;
 616
 617     if (s->cmd & UHCI_CMD_EGSM) {
 618         s->cmd |= UHCI_CMD_FGR;
 619         s->status |= UHCI_STS_RD;
 620         uhci_update_irq(s);
 621     }
 622 }
 623
 624 static void uhci_attach(USBPort *port1)
 625 {
 626     UHCIState *s = port1->opaque;
 627     UHCIPort *port = &s->ports[port1->index];
 628
 629     /* set connect status */
 630     port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
 631
 632     /* update speed */
 633     if (port->port.dev->speed == USB_SPEED_LOW) {
 634         port->ctrl |= UHCI_PORT_LSDA;
 635     } else {
 636         port->ctrl &= ~UHCI_PORT_LSDA;
 637     }
 638
 639     uhci_resume(s);
 640 }
 641
 642 static void uhci_detach(USBPort *port1)
 643 {
 644     UHCIState *s = port1->opaque;
 645     UHCIPort *port = &s->ports[port1->index];
 646
 647     uhci_async_cancel_device(s, port1->dev);
 648
 649     /* set connect status */
 650     if (port->ctrl & UHCI_PORT_CCS) {
 651         port->ctrl &= ~UHCI_PORT_CCS;
 652         port->ctrl |= UHCI_PORT_CSC;
 653     }
 654     /* disable port */
 655     if (port->ctrl & UHCI_PORT_EN) {
 656         port->ctrl &= ~UHCI_PORT_EN;
 657         port->ctrl |= UHCI_PORT_ENC;
 658     }
 659
 660     uhci_resume(s);
 661 }
 662
 663 static void uhci_child_detach(USBPort *port1, USBDevice *child)
 664 {
 665     UHCIState *s = port1->opaque;
 666
 667     uhci_async_cancel_device(s, child);
 668 }
 669
 670 static void uhci_wakeup(USBPort *port1)
 671 {
 672     UHCIState *s = port1->opaque;
 673     UHCIPort *port = &s->ports[port1->index];
 674
 675     if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
 676         port->ctrl |= UHCI_PORT_RD;
 677         uhci_resume(s);
 678     }
 679 }
 680
 681 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
 682 {
 683     USBDevice *dev;
 684     int i;
 685
 686     for (i = 0; i < NB_PORTS; i++) {
 687         UHCIPort *port = &s->ports[i];
 688         if (!(port->ctrl & UHCI_PORT_EN)) {
 689             continue;
 690         }
 691         dev = usb_find_device(&port->port, addr);
 692         if (dev != NULL) {
 693             return dev;
 694         }
 695     }
 696     return NULL;
 697 }
 698
 699 static void uhci_async_complete(USBPort *port, USBPacket *packet);
 700 static void uhci_process_frame(UHCIState *s);
 701
 702 /* return -1 if fatal error (frame must be stopped)
 703           0 if TD successful
 704           1 if TD unsuccessful or inactive
 705 */
 706 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
 707 {
 708     int len = 0, max_len, err, ret;
 709     uint8_t pid;
 710
 711     max_len = ((td->token >> 21) + 1) & 0x7ff;
 712     pid = td->token & 0xff;
 713
 714     ret = async->packet.result;
 715
 716     if (td->ctrl & TD_CTRL_IOS)
 717         td->ctrl &= ~TD_CTRL_ACTIVE;
 718
 719     if (ret < 0)
 720         goto out;
 721
 722     len = async->packet.result;
 723     td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
 724
 725     /* The NAK bit may have been set by a previous frame, so clear it
 726        here.  The docs are somewhat unclear, but win2k relies on this
 727        behavior.  */
 728     td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
 729     if (td->ctrl & TD_CTRL_IOC)
 730         *int_mask |= 0x01;
 731
 732     if (pid == USB_TOKEN_IN) {
 733         if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
 734             *int_mask |= 0x02;
 735             /* short packet: do not update QH */
 736             trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
 737                                                     async->td);
 738             return TD_RESULT_NEXT_QH;
 739         }
 740     }
 741
 742     /* success */
 743     trace_usb_uhci_packet_complete_success(async->queue->token, async->td);
 744     return TD_RESULT_COMPLETE;
 745
 746 out:
 747     switch(ret) {
 748     case USB_RET_STALL:
 749         td->ctrl |= TD_CTRL_STALL;
 750         td->ctrl &= ~TD_CTRL_ACTIVE;
 751         s->status |= UHCI_STS_USBERR;
 752         if (td->ctrl & TD_CTRL_IOC) {
 753             *int_mask |= 0x01;
 754         }
 755         uhci_update_irq(s);
 756         trace_usb_uhci_packet_complete_stall(async->queue->token, async->td);
 757         return TD_RESULT_NEXT_QH;
 758
 759     case USB_RET_BABBLE:
 760         td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
 761         td->ctrl &= ~TD_CTRL_ACTIVE;
 762         s->status |= UHCI_STS_USBERR;
 763         if (td->ctrl & TD_CTRL_IOC) {
 764             *int_mask |= 0x01;
 765         }
 766         uhci_update_irq(s);
 767         /* frame interrupted */
 768         trace_usb_uhci_packet_complete_babble(async->queue->token, async->td);
 769         return TD_RESULT_STOP_FRAME;
 770
 771     case USB_RET_NAK:
 772         td->ctrl |= TD_CTRL_NAK;
 773         if (pid == USB_TOKEN_SETUP)
 774             break;
 775         return TD_RESULT_NEXT_QH;
 776
 777     case USB_RET_IOERROR:
 778     case USB_RET_NODEV:
 779     default:
 780         break;
 781     }
 782
 783     /* Retry the TD if error count is not zero */
 784
 785     td->ctrl |= TD_CTRL_TIMEOUT;
 786     err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
 787     if (err != 0) {
 788         err--;
 789         if (err == 0) {
 790             td->ctrl &= ~TD_CTRL_ACTIVE;
 791             s->status |= UHCI_STS_USBERR;
 792             if (td->ctrl & TD_CTRL_IOC)
 793                 *int_mask |= 0x01;
 794             uhci_update_irq(s);
 795             trace_usb_uhci_packet_complete_error(async->queue->token,
 796                                                  async->td);
 797         }
 798     }
 799     td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
 800         (err << TD_CTRL_ERROR_SHIFT);
 801     return TD_RESULT_NEXT_QH;
 802 }
 803
 804 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td,
 805                           uint32_t *int_mask, bool queuing,
 806                           struct USBEndpoint **ep_ret)
 807 {
 808     UHCIAsync *async;
 809     int len = 0, max_len;
 810     uint8_t pid;
 811     bool spd;
 812     USBDevice *dev;
 813     USBEndpoint *ep;
 814
 815     /* Is active ? */
 816     if (!(td->ctrl & TD_CTRL_ACTIVE)) {
 817         /*
 818          * ehci11d spec page 22: "Even if the Active bit in the TD is already
 819          * cleared when the TD is fetched ... an IOC interrupt is generated"
 820          */
 821         if (td->ctrl & TD_CTRL_IOC) {
 822                 *int_mask |= 0x01;
 823         }
 824         return TD_RESULT_NEXT_QH;
 825     }
 826
 827     async = uhci_async_find_td(s, addr, td);
 828     if (async) {
 829         /* Already submitted */
 830         async->queue->valid = 32;
 831
 832         if (!async->done)
 833             return TD_RESULT_ASYNC_CONT;
 834         if (queuing) {
 835             /* we are busy filling the queue, we are not prepared
 836                to consume completed packages then, just leave them
 837                in async state */
 838             return TD_RESULT_ASYNC_CONT;
 839         }
 840
 841         uhci_async_unlink(async);
 842         goto done;
 843     }
 844
 845     /* Allocate new packet */
 846     async = uhci_async_alloc(uhci_queue_get(s, td), addr);
 847
 848     /* valid needs to be large enough to handle 10 frame delay
 849      * for initial isochronous requests
 850      */
 851     async->queue->valid = 32;
 852     async->isoc = td->ctrl & TD_CTRL_IOS;
 853
 854     max_len = ((td->token >> 21) + 1) & 0x7ff;
 855     pid = td->token & 0xff;
 856     spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
 857
 858     dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
 859     ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
 860     if (ep_ret) {
 861         *ep_ret = ep;
 862     }
 863     usb_packet_setup(&async->packet, pid, ep, addr, spd);
 864     qemu_sglist_add(&async->sgl, td->buffer, max_len);
 865     usb_packet_map(&async->packet, &async->sgl);
 866
 867     switch(pid) {
 868     case USB_TOKEN_OUT:
 869     case USB_TOKEN_SETUP:
 870         len = usb_handle_packet(dev, &async->packet);
 871         if (len >= 0)
 872             len = max_len;
 873         break;
 874
 875     case USB_TOKEN_IN:
 876         len = usb_handle_packet(dev, &async->packet);
 877         break;
 878
 879     default:
 880         /* invalid pid : frame interrupted */
 881         usb_packet_unmap(&async->packet, &async->sgl);
 882         uhci_async_free(async);
 883         s->status |= UHCI_STS_HCPERR;
 884         uhci_update_irq(s);
 885         return TD_RESULT_STOP_FRAME;
 886     }
 887
 888     if (len == USB_RET_ASYNC) {
 889         uhci_async_link(async);
 890         return TD_RESULT_ASYNC_START;
 891     }
 892
 893     async->packet.result = len;
 894
 895 done:
 896     len = uhci_complete_td(s, td, async, int_mask);
 897     usb_packet_unmap(&async->packet, &async->sgl);
 898     uhci_async_free(async);
 899     return len;
 900 }
 901
 902 static void uhci_async_complete(USBPort *port, USBPacket *packet)
 903 {
 904     UHCIAsync *async = container_of(packet, UHCIAsync, packet);
 905     UHCIState *s = async->queue->uhci;
 906
 907     if (packet->result == USB_RET_REMOVE_FROM_QUEUE) {
 908         uhci_async_unlink(async);
 909         uhci_async_cancel(async);
 910         return;
 911     }
 912
 913     if (async->isoc) {
 914         UHCI_TD td;
 915         uint32_t link = async->td;
 916         uint32_t int_mask = 0, val;
 917
 918         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
 919         le32_to_cpus(&td.link);
 920         le32_to_cpus(&td.ctrl);
 921         le32_to_cpus(&td.token);
 922         le32_to_cpus(&td.buffer);
 923
 924         uhci_async_unlink(async);
 925         uhci_complete_td(s, &td, async, &int_mask);
 926         s->pending_int_mask |= int_mask;
 927
 928         /* update the status bits of the TD */
 929         val = cpu_to_le32(td.ctrl);
 930         pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
 931         uhci_async_free(async);
 932     } else {
 933         async->done = 1;
 934         if (s->frame_bytes < s->frame_bandwidth) {
 935             qemu_bh_schedule(s->bh);
 936         }
 937     }
 938 }
 939
 940 static int is_valid(uint32_t link)
 941 {
 942     return (link & 1) == 0;
 943 }
 944
 945 static int is_qh(uint32_t link)
 946 {
 947     return (link & 2) != 0;
 948 }
 949
 950 static int depth_first(uint32_t link)
 951 {
 952     return (link & 4) != 0;
 953 }
 954
 955 /* QH DB used for detecting QH loops */
 956 #define UHCI_MAX_QUEUES 128
 957 typedef struct {
 958     uint32_t addr[UHCI_MAX_QUEUES];
 959     int      count;
 960 } QhDb;
 961
 962 static void qhdb_reset(QhDb *db)
 963 {
 964     db->count = 0;
 965 }
 966
 967 /* Add QH to DB. Returns 1 if already present or DB is full. */
 968 static int qhdb_insert(QhDb *db, uint32_t addr)
 969 {
 970     int i;
 971     for (i = 0; i < db->count; i++)
 972         if (db->addr[i] == addr)
 973             return 1;
 974
 975     if (db->count >= UHCI_MAX_QUEUES)
 976         return 1;
 977
 978     db->addr[db->count++] = addr;
 979     return 0;
 980 }
 981
 982 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td, struct USBEndpoint *ep)
 983 {
 984     uint32_t int_mask = 0;
 985     uint32_t plink = td->link;
 986     uint32_t token = uhci_queue_token(td);
 987     UHCI_TD ptd;
 988     int ret;
 989
 990     while (is_valid(plink)) {
 991         pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd));
 992         le32_to_cpus(&ptd.link);
 993         le32_to_cpus(&ptd.ctrl);
 994         le32_to_cpus(&ptd.token);
 995         le32_to_cpus(&ptd.buffer);
 996         if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
 997             break;
 998         }
 999         if (uhci_queue_token(&ptd) != token) {
1000             break;
1001         }
1002         trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
1003         ret = uhci_handle_td(s, plink, &ptd, &int_mask, true, NULL);
1004         if (ret == TD_RESULT_ASYNC_CONT) {
1005             break;
1006         }
1007         assert(ret == TD_RESULT_ASYNC_START);
1008         assert(int_mask == 0);
1009         plink = ptd.link;
1010     }
1011     usb_device_flush_ep_queue(ep->dev, ep);
1012 }
1013
1014 static void uhci_process_frame(UHCIState *s)
1015 {
1016     uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
1017     uint32_t curr_qh, td_count = 0;
1018     struct USBEndpoint *curr_ep;
1019     int cnt, ret;
1020     UHCI_TD td;
1021     UHCI_QH qh;
1022     QhDb qhdb;
1023
1024     frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
1025
1026     pci_dma_read(&s->dev, frame_addr, &link, 4);
1027     le32_to_cpus(&link);
1028
1029     int_mask = 0;
1030     curr_qh  = 0;
1031
1032     qhdb_reset(&qhdb);
1033
1034     for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1035         if (s->frame_bytes >= s->frame_bandwidth) {
1036             /* We've reached the usb 1.1 bandwidth, which is
1037                1280 bytes/frame, stop processing */
1038             trace_usb_uhci_frame_stop_bandwidth();
1039             break;
1040         }
1041         if (is_qh(link)) {
1042             /* QH */
1043             trace_usb_uhci_qh_load(link & ~0xf);
1044
1045             if (qhdb_insert(&qhdb, link)) {
1046                 /*
1047                  * We're going in circles. Which is not a bug because
1048                  * HCD is allowed to do that as part of the BW management.
1049                  *
1050                  * Stop processing here if no transaction has been done
1051                  * since we've been here last time.
1052                  */
1053                 if (td_count == 0) {
1054                     trace_usb_uhci_frame_loop_stop_idle();
1055                     break;
1056                 } else {
1057                     trace_usb_uhci_frame_loop_continue();
1058                     td_count = 0;
1059                     qhdb_reset(&qhdb);
1060                     qhdb_insert(&qhdb, link);
1061                 }
1062             }
1063
1064             pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1065             le32_to_cpus(&qh.link);
1066             le32_to_cpus(&qh.el_link);
1067
1068             if (!is_valid(qh.el_link)) {
1069                 /* QH w/o elements */
1070                 curr_qh = 0;
1071                 link = qh.link;
1072             } else {
1073                 /* QH with elements */
1074                 curr_qh = link;
1075                 link = qh.el_link;
1076             }
1077             continue;
1078         }
1079
1080         /* TD */
1081         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
1082         le32_to_cpus(&td.link);
1083         le32_to_cpus(&td.ctrl);
1084         le32_to_cpus(&td.token);
1085         le32_to_cpus(&td.buffer);
1086         trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1087
1088         old_td_ctrl = td.ctrl;
1089         ret = uhci_handle_td(s, link, &td, &int_mask, false, &curr_ep);
1090         if (old_td_ctrl != td.ctrl) {
1091             /* update the status bits of the TD */
1092             val = cpu_to_le32(td.ctrl);
1093             pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1094         }
1095
1096         switch (ret) {
1097         case TD_RESULT_STOP_FRAME: /* interrupted frame */
1098             goto out;
1099
1100         case TD_RESULT_NEXT_QH:
1101         case TD_RESULT_ASYNC_CONT:
1102             trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1103             link = curr_qh ? qh.link : td.link;
1104             continue;
1105
1106         case TD_RESULT_ASYNC_START:
1107             trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1108             uhci_fill_queue(s, &td, curr_ep);
1109             link = curr_qh ? qh.link : td.link;
1110             continue;
1111
1112         case TD_RESULT_COMPLETE:
1113             trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1114             link = td.link;
1115             td_count++;
1116             s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1117
1118             if (curr_qh) {
1119                 /* update QH element link */
1120                 qh.el_link = link;
1121                 val = cpu_to_le32(qh.el_link);
1122                 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1123
1124                 if (!depth_first(link)) {
1125                     /* done with this QH */
1126                     curr_qh = 0;
1127                     link    = qh.link;
1128                 }
1129             }
1130             break;
1131
1132         default:
1133             assert(!"unknown return code");
1134         }
1135
1136         /* go to the next entry */
1137     }
1138
1139 out:
1140     s->pending_int_mask |= int_mask;
1141 }
1142
1143 static void uhci_bh(void *opaque)
1144 {
1145     UHCIState *s = opaque;
1146     uhci_process_frame(s);
1147 }
1148
1149 static void uhci_frame_timer(void *opaque)
1150 {
1151     UHCIState *s = opaque;
1152
1153     /* prepare the timer for the next frame */
1154     s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1155     s->frame_bytes = 0;
1156     qemu_bh_cancel(s->bh);
1157
1158     if (!(s->cmd & UHCI_CMD_RS)) {
1159         /* Full stop */
1160         trace_usb_uhci_schedule_stop();
1161         qemu_del_timer(s->frame_timer);
1162         uhci_async_cancel_all(s);
1163         /* set hchalted bit in status - UHCI11D 2.1.2 */
1164         s->status |= UHCI_STS_HCHALTED;
1165         return;
1166     }
1167
1168     /* Complete the previous frame */
1169     if (s->pending_int_mask) {
1170         s->status2 |= s->pending_int_mask;
1171         s->status  |= UHCI_STS_USBINT;
1172         uhci_update_irq(s);
1173     }
1174     s->pending_int_mask = 0;
1175
1176     /* Start new frame */
1177     s->frnum = (s->frnum + 1) & 0x7ff;
1178
1179     trace_usb_uhci_frame_start(s->frnum);
1180
1181     uhci_async_validate_begin(s);
1182
1183     uhci_process_frame(s);
1184
1185     uhci_async_validate_end(s);
1186
1187     qemu_mod_timer(s->frame_timer, s->expire_time);
1188 }
1189
1190 static const MemoryRegionPortio uhci_portio[] = {
1191     { 0, 32, 2, .write = uhci_ioport_writew, },
1192     { 0, 32, 2, .read = uhci_ioport_readw, },
1193     { 0, 32, 4, .write = uhci_ioport_writel, },
1194     { 0, 32, 4, .read = uhci_ioport_readl, },
1195     { 0, 32, 1, .write = uhci_ioport_writeb, },
1196     { 0, 32, 1, .read = uhci_ioport_readb, },
1197     PORTIO_END_OF_LIST()
1198 };
1199
1200 static const MemoryRegionOps uhci_ioport_ops = {
1201     .old_portio = uhci_portio,
1202 };
1203
1204 static USBPortOps uhci_port_ops = {
1205     .attach = uhci_attach,
1206     .detach = uhci_detach,
1207     .child_detach = uhci_child_detach,
1208     .wakeup = uhci_wakeup,
1209     .complete = uhci_async_complete,
1210 };
1211
1212 static USBBusOps uhci_bus_ops = {
1213 };
1214
1215 static int usb_uhci_common_initfn(PCIDevice *dev)
1216 {
1217     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1218     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1219     uint8_t *pci_conf = s->dev.config;
1220     int i;
1221
1222     pci_conf[PCI_CLASS_PROG] = 0x00;
1223     /* TODO: reset value should be 0. */
1224     pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1225
1226     switch (pc->device_id) {
1227     case PCI_DEVICE_ID_INTEL_82801I_UHCI1:
1228         s->irq_pin = 0;  /* A */
1229         break;
1230     case PCI_DEVICE_ID_INTEL_82801I_UHCI2:
1231         s->irq_pin = 1;  /* B */
1232         break;
1233     case PCI_DEVICE_ID_INTEL_82801I_UHCI3:
1234         s->irq_pin = 2;  /* C */
1235         break;
1236     default:
1237         s->irq_pin = 3;  /* D */
1238         break;
1239     }
1240     pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1);
1241
1242     if (s->masterbus) {
1243         USBPort *ports[NB_PORTS];
1244         for(i = 0; i < NB_PORTS; i++) {
1245             ports[i] = &s->ports[i].port;
1246         }
1247         if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1248                 s->firstport, s, &uhci_port_ops,
1249                 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1250             return -1;
1251         }
1252     } else {
1253         usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1254         for (i = 0; i < NB_PORTS; i++) {
1255             usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1256                               USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1257         }
1258     }
1259     s->bh = qemu_bh_new(uhci_bh, s);
1260     s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1261     s->num_ports_vmstate = NB_PORTS;
1262     QTAILQ_INIT(&s->queues);
1263
1264     qemu_register_reset(uhci_reset, s);
1265
1266     memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1267     /* Use region 4 for consistency with real hardware.  BSD guests seem
1268        to rely on this.  */
1269     pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1270
1271     return 0;
1272 }
1273
1274 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1275 {
1276     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1277     uint8_t *pci_conf = s->dev.config;
1278
1279     /* USB misc control 1/2 */
1280     pci_set_long(pci_conf + 0x40,0x00001000);
1281     /* PM capability */
1282     pci_set_long(pci_conf + 0x80,0x00020001);
1283     /* USB legacy support  */
1284     pci_set_long(pci_conf + 0xc0,0x00002000);
1285
1286     return usb_uhci_common_initfn(dev);
1287 }
1288
1289 static void usb_uhci_exit(PCIDevice *dev)
1290 {
1291     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1292
1293     memory_region_destroy(&s->io_bar);
1294 }
1295
1296 static Property uhci_properties[] = {
1297     DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1298     DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1299     DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1300     DEFINE_PROP_END_OF_LIST(),
1301 };
1302
1303 static void piix3_uhci_class_init(ObjectClass *klass, void *data)
1304 {
1305     DeviceClass *dc = DEVICE_CLASS(klass);
1306     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1307
1308     k->init = usb_uhci_common_initfn;
1309     k->exit = usb_uhci_exit;
1310     k->vendor_id = PCI_VENDOR_ID_INTEL;
1311     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
1312     k->revision = 0x01;
1313     k->class_id = PCI_CLASS_SERIAL_USB;
1314     dc->vmsd = &vmstate_uhci;
1315     dc->props = uhci_properties;
1316 }
1317
1318 static TypeInfo piix3_uhci_info = {
1319     .name          = "piix3-usb-uhci",
1320     .parent        = TYPE_PCI_DEVICE,
1321     .instance_size = sizeof(UHCIState),
1322     .class_init    = piix3_uhci_class_init,
1323 };
1324
1325 static void piix4_uhci_class_init(ObjectClass *klass, void *data)
1326 {
1327     DeviceClass *dc = DEVICE_CLASS(klass);
1328     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1329
1330     k->init = usb_uhci_common_initfn;
1331     k->exit = usb_uhci_exit;
1332     k->vendor_id = PCI_VENDOR_ID_INTEL;
1333     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
1334     k->revision = 0x01;
1335     k->class_id = PCI_CLASS_SERIAL_USB;
1336     dc->vmsd = &vmstate_uhci;
1337     dc->props = uhci_properties;
1338 }
1339
1340 static TypeInfo piix4_uhci_info = {
1341     .name          = "piix4-usb-uhci",
1342     .parent        = TYPE_PCI_DEVICE,
1343     .instance_size = sizeof(UHCIState),
1344     .class_init    = piix4_uhci_class_init,
1345 };
1346
1347 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data)
1348 {
1349     DeviceClass *dc = DEVICE_CLASS(klass);
1350     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1351
1352     k->init = usb_uhci_vt82c686b_initfn;
1353     k->exit = usb_uhci_exit;
1354     k->vendor_id = PCI_VENDOR_ID_VIA;
1355     k->device_id = PCI_DEVICE_ID_VIA_UHCI;
1356     k->revision = 0x01;
1357     k->class_id = PCI_CLASS_SERIAL_USB;
1358     dc->vmsd = &vmstate_uhci;
1359     dc->props = uhci_properties;
1360 }
1361
1362 static TypeInfo vt82c686b_uhci_info = {
1363     .name          = "vt82c686b-usb-uhci",
1364     .parent        = TYPE_PCI_DEVICE,
1365     .instance_size = sizeof(UHCIState),
1366     .class_init    = vt82c686b_uhci_class_init,
1367 };
1368
1369 static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
1370 {
1371     DeviceClass *dc = DEVICE_CLASS(klass);
1372     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1373
1374     k->init = usb_uhci_common_initfn;
1375     k->vendor_id = PCI_VENDOR_ID_INTEL;
1376     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
1377     k->revision = 0x03;
1378     k->class_id = PCI_CLASS_SERIAL_USB;
1379     dc->vmsd = &vmstate_uhci;
1380     dc->props = uhci_properties;
1381 }
1382
1383 static TypeInfo ich9_uhci1_info = {
1384     .name          = "ich9-usb-uhci1",
1385     .parent        = TYPE_PCI_DEVICE,
1386     .instance_size = sizeof(UHCIState),
1387     .class_init    = ich9_uhci1_class_init,
1388 };
1389
1390 static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
1391 {
1392     DeviceClass *dc = DEVICE_CLASS(klass);
1393     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1394
1395     k->init = usb_uhci_common_initfn;
1396     k->vendor_id = PCI_VENDOR_ID_INTEL;
1397     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
1398     k->revision = 0x03;
1399     k->class_id = PCI_CLASS_SERIAL_USB;
1400     dc->vmsd = &vmstate_uhci;
1401     dc->props = uhci_properties;
1402 }
1403
1404 static TypeInfo ich9_uhci2_info = {
1405     .name          = "ich9-usb-uhci2",
1406     .parent        = TYPE_PCI_DEVICE,
1407     .instance_size = sizeof(UHCIState),
1408     .class_init    = ich9_uhci2_class_init,
1409 };
1410
1411 static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
1412 {
1413     DeviceClass *dc = DEVICE_CLASS(klass);
1414     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1415
1416     k->init = usb_uhci_common_initfn;
1417     k->vendor_id = PCI_VENDOR_ID_INTEL;
1418     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
1419     k->revision = 0x03;
1420     k->class_id = PCI_CLASS_SERIAL_USB;
1421     dc->vmsd = &vmstate_uhci;
1422     dc->props = uhci_properties;
1423 }
1424
1425 static TypeInfo ich9_uhci3_info = {
1426     .name          = "ich9-usb-uhci3",
1427     .parent        = TYPE_PCI_DEVICE,
1428     .instance_size = sizeof(UHCIState),
1429     .class_init    = ich9_uhci3_class_init,
1430 };
1431
1432 static void uhci_register_types(void)
1433 {
1434     type_register_static(&piix3_uhci_info);
1435     type_register_static(&piix4_uhci_info);
1436     type_register_static(&vt82c686b_uhci_info);
1437     type_register_static(&ich9_uhci1_info);
1438     type_register_static(&ich9_uhci2_info);
1439     type_register_static(&ich9_uhci3_info);
1440 }
1441
1442 type_init(uhci_register_types)