2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu-timer.h"
37 //#define DEBUG_DUMP_DATA
39 #define UHCI_CMD_FGR (1 << 4)
40 #define UHCI_CMD_EGSM (1 << 3)
41 #define UHCI_CMD_GRESET (1 << 2)
42 #define UHCI_CMD_HCRESET (1 << 1)
43 #define UHCI_CMD_RS (1 << 0)
45 #define UHCI_STS_HCHALTED (1 << 5)
46 #define UHCI_STS_HCPERR (1 << 4)
47 #define UHCI_STS_HSERR (1 << 3)
48 #define UHCI_STS_RD (1 << 2)
49 #define UHCI_STS_USBERR (1 << 1)
50 #define UHCI_STS_USBINT (1 << 0)
52 #define TD_CTRL_SPD (1 << 29)
53 #define TD_CTRL_ERROR_SHIFT 27
54 #define TD_CTRL_IOS (1 << 25)
55 #define TD_CTRL_IOC (1 << 24)
56 #define TD_CTRL_ACTIVE (1 << 23)
57 #define TD_CTRL_STALL (1 << 22)
58 #define TD_CTRL_BABBLE (1 << 20)
59 #define TD_CTRL_NAK (1 << 19)
60 #define TD_CTRL_TIMEOUT (1 << 18)
62 #define UHCI_PORT_SUSPEND (1 << 12)
63 #define UHCI_PORT_RESET (1 << 9)
64 #define UHCI_PORT_LSDA (1 << 8)
65 #define UHCI_PORT_RD (1 << 6)
66 #define UHCI_PORT_ENC (1 << 3)
67 #define UHCI_PORT_EN (1 << 2)
68 #define UHCI_PORT_CSC (1 << 1)
69 #define UHCI_PORT_CCS (1 << 0)
71 #define UHCI_PORT_READ_ONLY (0x1bb)
72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
74 #define FRAME_TIMER_FREQ 1000
76 #define FRAME_MAX_LOOPS 256
81 TD_RESULT_STOP_FRAME
= 10,
84 TD_RESULT_ASYNC_START
,
88 typedef struct UHCIState UHCIState
;
89 typedef struct UHCIAsync UHCIAsync
;
90 typedef struct UHCIQueue UHCIQueue
;
93 * Pending async transaction.
94 * 'packet' must be the first field because completion
95 * handler does "(UHCIAsync *) pkt" cast.
102 QTAILQ_ENTRY(UHCIAsync
) next
;
111 QTAILQ_ENTRY(UHCIQueue
) next
;
112 QTAILQ_HEAD(, UHCIAsync
) asyncs
;
116 typedef struct UHCIPort
{
124 USBBus bus
; /* Note unused when we're a companion controller */
125 uint16_t cmd
; /* cmd register */
127 uint16_t intr
; /* interrupt enable register */
128 uint16_t frnum
; /* frame number */
129 uint32_t fl_base_addr
; /* frame list base address */
131 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
133 QEMUTimer
*frame_timer
;
135 uint32_t frame_bytes
;
136 uint32_t frame_bandwidth
;
137 UHCIPort ports
[NB_PORTS
];
139 /* Interrupts that should be raised at the end of the current frame. */
140 uint32_t pending_int_mask
;
144 QTAILQ_HEAD(, UHCIQueue
) queues
;
145 uint8_t num_ports_vmstate
;
152 typedef struct UHCI_TD
{
154 uint32_t ctrl
; /* see TD_CTRL_xxx */
159 typedef struct UHCI_QH
{
164 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
166 /* covers ep, dev, pid -> identifies the endpoint */
167 return td
->token
& 0x7ffff;
170 static UHCIQueue
*uhci_queue_get(UHCIState
*s
, UHCI_TD
*td
)
172 uint32_t token
= uhci_queue_token(td
);
175 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
176 if (queue
->token
== token
) {
181 queue
= g_new0(UHCIQueue
, 1);
183 queue
->token
= token
;
184 QTAILQ_INIT(&queue
->asyncs
);
185 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
186 trace_usb_uhci_queue_add(queue
->token
);
190 static void uhci_queue_free(UHCIQueue
*queue
)
192 UHCIState
*s
= queue
->uhci
;
194 trace_usb_uhci_queue_del(queue
->token
);
195 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
199 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
, uint32_t addr
)
201 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
203 async
->queue
= queue
;
205 usb_packet_init(&async
->packet
);
206 pci_dma_sglist_init(&async
->sgl
, &queue
->uhci
->dev
, 1);
207 trace_usb_uhci_packet_add(async
->queue
->token
, async
->td
);
212 static void uhci_async_free(UHCIAsync
*async
)
214 trace_usb_uhci_packet_del(async
->queue
->token
, async
->td
);
215 usb_packet_cleanup(&async
->packet
);
216 qemu_sglist_destroy(&async
->sgl
);
220 static void uhci_async_link(UHCIAsync
*async
)
222 UHCIQueue
*queue
= async
->queue
;
223 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
224 trace_usb_uhci_packet_link_async(async
->queue
->token
, async
->td
);
227 static void uhci_async_unlink(UHCIAsync
*async
)
229 UHCIQueue
*queue
= async
->queue
;
230 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
231 trace_usb_uhci_packet_unlink_async(async
->queue
->token
, async
->td
);
234 static void uhci_async_cancel(UHCIAsync
*async
)
236 trace_usb_uhci_packet_cancel(async
->queue
->token
, async
->td
, async
->done
);
238 usb_cancel_packet(&async
->packet
);
239 usb_packet_unmap(&async
->packet
, &async
->sgl
);
240 uhci_async_free(async
);
244 * Mark all outstanding async packets as invalid.
245 * This is used for canceling them when TDs are removed by the HCD.
247 static void uhci_async_validate_begin(UHCIState
*s
)
251 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
257 * Cancel async packets that are no longer valid
259 static void uhci_async_validate_end(UHCIState
*s
)
261 UHCIQueue
*queue
, *n
;
264 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
265 if (queue
->valid
> 0) {
268 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
269 async
= QTAILQ_FIRST(&queue
->asyncs
);
270 uhci_async_unlink(async
);
271 uhci_async_cancel(async
);
273 uhci_queue_free(queue
);
277 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
282 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
283 QTAILQ_FOREACH_SAFE(curr
, &queue
->asyncs
, next
, n
) {
284 if (!usb_packet_is_inflight(&curr
->packet
) ||
285 curr
->packet
.ep
->dev
!= dev
) {
288 uhci_async_unlink(curr
);
289 uhci_async_cancel(curr
);
294 static void uhci_async_cancel_all(UHCIState
*s
)
296 UHCIQueue
*queue
, *nq
;
299 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, nq
) {
300 QTAILQ_FOREACH_SAFE(curr
, &queue
->asyncs
, next
, n
) {
301 uhci_async_unlink(curr
);
302 uhci_async_cancel(curr
);
304 uhci_queue_free(queue
);
308 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t addr
, UHCI_TD
*td
)
310 uint32_t token
= uhci_queue_token(td
);
314 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
315 if (queue
->token
== token
) {
323 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
324 if (async
->td
== addr
) {
332 static void uhci_update_irq(UHCIState
*s
)
335 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
336 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
337 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
338 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
339 (s
->status
& UHCI_STS_HSERR
) ||
340 (s
->status
& UHCI_STS_HCPERR
)) {
345 qemu_set_irq(s
->dev
.irq
[s
->irq_pin
], level
);
348 static void uhci_reset(void *opaque
)
350 UHCIState
*s
= opaque
;
355 trace_usb_uhci_reset();
357 pci_conf
= s
->dev
.config
;
359 pci_conf
[0x6a] = 0x01; /* usb clock */
360 pci_conf
[0x6b] = 0x00;
368 for(i
= 0; i
< NB_PORTS
; i
++) {
371 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
372 usb_port_reset(&port
->port
);
376 uhci_async_cancel_all(s
);
377 qemu_bh_cancel(s
->bh
);
381 static const VMStateDescription vmstate_uhci_port
= {
384 .minimum_version_id
= 1,
385 .minimum_version_id_old
= 1,
386 .fields
= (VMStateField
[]) {
387 VMSTATE_UINT16(ctrl
, UHCIPort
),
388 VMSTATE_END_OF_LIST()
392 static int uhci_post_load(void *opaque
, int version_id
)
394 UHCIState
*s
= opaque
;
396 if (version_id
< 2) {
397 s
->expire_time
= qemu_get_clock_ns(vm_clock
) +
398 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
403 static const VMStateDescription vmstate_uhci
= {
406 .minimum_version_id
= 1,
407 .minimum_version_id_old
= 1,
408 .post_load
= uhci_post_load
,
409 .fields
= (VMStateField
[]) {
410 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
411 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
),
412 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
413 vmstate_uhci_port
, UHCIPort
),
414 VMSTATE_UINT16(cmd
, UHCIState
),
415 VMSTATE_UINT16(status
, UHCIState
),
416 VMSTATE_UINT16(intr
, UHCIState
),
417 VMSTATE_UINT16(frnum
, UHCIState
),
418 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
419 VMSTATE_UINT8(sof_timing
, UHCIState
),
420 VMSTATE_UINT8(status2
, UHCIState
),
421 VMSTATE_TIMER(frame_timer
, UHCIState
),
422 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
423 VMSTATE_END_OF_LIST()
427 static void uhci_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
429 UHCIState
*s
= opaque
;
439 static uint32_t uhci_ioport_readb(void *opaque
, uint32_t addr
)
441 UHCIState
*s
= opaque
;
456 static void uhci_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
458 UHCIState
*s
= opaque
;
461 trace_usb_uhci_mmio_writew(addr
, val
);
465 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
466 /* start frame processing */
467 trace_usb_uhci_schedule_start();
468 s
->expire_time
= qemu_get_clock_ns(vm_clock
) +
469 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
470 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
471 s
->status
&= ~UHCI_STS_HCHALTED
;
472 } else if (!(val
& UHCI_CMD_RS
)) {
473 s
->status
|= UHCI_STS_HCHALTED
;
475 if (val
& UHCI_CMD_GRESET
) {
479 /* send reset on the USB bus */
480 for(i
= 0; i
< NB_PORTS
; i
++) {
482 usb_device_reset(port
->port
.dev
);
487 if (val
& UHCI_CMD_HCRESET
) {
495 /* XXX: the chip spec is not coherent, so we add a hidden
496 register to distinguish between IOC and SPD */
497 if (val
& UHCI_STS_USBINT
)
506 if (s
->status
& UHCI_STS_HCHALTED
)
507 s
->frnum
= val
& 0x7ff;
519 dev
= port
->port
.dev
;
520 if (dev
&& dev
->attached
) {
522 if ( (val
& UHCI_PORT_RESET
) &&
523 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
524 usb_device_reset(dev
);
527 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
528 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
529 /* some bits are reset when a '1' is written to them */
530 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
536 static uint32_t uhci_ioport_readw(void *opaque
, uint32_t addr
)
538 UHCIState
*s
= opaque
;
568 val
= 0xff7f; /* disabled port */
572 trace_usb_uhci_mmio_readw(addr
, val
);
577 static void uhci_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
579 UHCIState
*s
= opaque
;
582 trace_usb_uhci_mmio_writel(addr
, val
);
586 s
->fl_base_addr
= val
& ~0xfff;
591 static uint32_t uhci_ioport_readl(void *opaque
, uint32_t addr
)
593 UHCIState
*s
= opaque
;
599 val
= s
->fl_base_addr
;
605 trace_usb_uhci_mmio_readl(addr
, val
);
609 /* signal resume if controller suspended */
610 static void uhci_resume (void *opaque
)
612 UHCIState
*s
= (UHCIState
*)opaque
;
617 if (s
->cmd
& UHCI_CMD_EGSM
) {
618 s
->cmd
|= UHCI_CMD_FGR
;
619 s
->status
|= UHCI_STS_RD
;
624 static void uhci_attach(USBPort
*port1
)
626 UHCIState
*s
= port1
->opaque
;
627 UHCIPort
*port
= &s
->ports
[port1
->index
];
629 /* set connect status */
630 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
633 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
634 port
->ctrl
|= UHCI_PORT_LSDA
;
636 port
->ctrl
&= ~UHCI_PORT_LSDA
;
642 static void uhci_detach(USBPort
*port1
)
644 UHCIState
*s
= port1
->opaque
;
645 UHCIPort
*port
= &s
->ports
[port1
->index
];
647 uhci_async_cancel_device(s
, port1
->dev
);
649 /* set connect status */
650 if (port
->ctrl
& UHCI_PORT_CCS
) {
651 port
->ctrl
&= ~UHCI_PORT_CCS
;
652 port
->ctrl
|= UHCI_PORT_CSC
;
655 if (port
->ctrl
& UHCI_PORT_EN
) {
656 port
->ctrl
&= ~UHCI_PORT_EN
;
657 port
->ctrl
|= UHCI_PORT_ENC
;
663 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
665 UHCIState
*s
= port1
->opaque
;
667 uhci_async_cancel_device(s
, child
);
670 static void uhci_wakeup(USBPort
*port1
)
672 UHCIState
*s
= port1
->opaque
;
673 UHCIPort
*port
= &s
->ports
[port1
->index
];
675 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
676 port
->ctrl
|= UHCI_PORT_RD
;
681 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
686 for (i
= 0; i
< NB_PORTS
; i
++) {
687 UHCIPort
*port
= &s
->ports
[i
];
688 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
691 dev
= usb_find_device(&port
->port
, addr
);
699 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
);
700 static void uhci_process_frame(UHCIState
*s
);
702 /* return -1 if fatal error (frame must be stopped)
704 1 if TD unsuccessful or inactive
706 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
708 int len
= 0, max_len
, err
, ret
;
711 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
712 pid
= td
->token
& 0xff;
714 ret
= async
->packet
.result
;
716 if (td
->ctrl
& TD_CTRL_IOS
)
717 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
722 len
= async
->packet
.result
;
723 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
725 /* The NAK bit may have been set by a previous frame, so clear it
726 here. The docs are somewhat unclear, but win2k relies on this
728 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
729 if (td
->ctrl
& TD_CTRL_IOC
)
732 if (pid
== USB_TOKEN_IN
) {
733 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
735 /* short packet: do not update QH */
736 trace_usb_uhci_packet_complete_shortxfer(async
->queue
->token
,
738 return TD_RESULT_NEXT_QH
;
743 trace_usb_uhci_packet_complete_success(async
->queue
->token
, async
->td
);
744 return TD_RESULT_COMPLETE
;
749 td
->ctrl
|= TD_CTRL_STALL
;
750 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
751 s
->status
|= UHCI_STS_USBERR
;
752 if (td
->ctrl
& TD_CTRL_IOC
) {
756 trace_usb_uhci_packet_complete_stall(async
->queue
->token
, async
->td
);
757 return TD_RESULT_NEXT_QH
;
760 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
761 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
762 s
->status
|= UHCI_STS_USBERR
;
763 if (td
->ctrl
& TD_CTRL_IOC
) {
767 /* frame interrupted */
768 trace_usb_uhci_packet_complete_babble(async
->queue
->token
, async
->td
);
769 return TD_RESULT_STOP_FRAME
;
772 td
->ctrl
|= TD_CTRL_NAK
;
773 if (pid
== USB_TOKEN_SETUP
)
775 return TD_RESULT_NEXT_QH
;
777 case USB_RET_IOERROR
:
783 /* Retry the TD if error count is not zero */
785 td
->ctrl
|= TD_CTRL_TIMEOUT
;
786 err
= (td
->ctrl
>> TD_CTRL_ERROR_SHIFT
) & 3;
790 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
791 s
->status
|= UHCI_STS_USBERR
;
792 if (td
->ctrl
& TD_CTRL_IOC
)
795 trace_usb_uhci_packet_complete_error(async
->queue
->token
,
799 td
->ctrl
= (td
->ctrl
& ~(3 << TD_CTRL_ERROR_SHIFT
)) |
800 (err
<< TD_CTRL_ERROR_SHIFT
);
801 return TD_RESULT_NEXT_QH
;
804 static int uhci_handle_td(UHCIState
*s
, uint32_t addr
, UHCI_TD
*td
,
805 uint32_t *int_mask
, bool queuing
,
806 struct USBEndpoint
**ep_ret
)
809 int len
= 0, max_len
;
816 if (!(td
->ctrl
& TD_CTRL_ACTIVE
)) {
818 * ehci11d spec page 22: "Even if the Active bit in the TD is already
819 * cleared when the TD is fetched ... an IOC interrupt is generated"
821 if (td
->ctrl
& TD_CTRL_IOC
) {
824 return TD_RESULT_NEXT_QH
;
827 async
= uhci_async_find_td(s
, addr
, td
);
829 /* Already submitted */
830 async
->queue
->valid
= 32;
833 return TD_RESULT_ASYNC_CONT
;
835 /* we are busy filling the queue, we are not prepared
836 to consume completed packages then, just leave them
838 return TD_RESULT_ASYNC_CONT
;
841 uhci_async_unlink(async
);
845 /* Allocate new packet */
846 async
= uhci_async_alloc(uhci_queue_get(s
, td
), addr
);
848 /* valid needs to be large enough to handle 10 frame delay
849 * for initial isochronous requests
851 async
->queue
->valid
= 32;
852 async
->isoc
= td
->ctrl
& TD_CTRL_IOS
;
854 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
855 pid
= td
->token
& 0xff;
856 spd
= (pid
== USB_TOKEN_IN
&& (td
->ctrl
& TD_CTRL_SPD
) != 0);
858 dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
859 ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
863 usb_packet_setup(&async
->packet
, pid
, ep
, addr
, spd
);
864 qemu_sglist_add(&async
->sgl
, td
->buffer
, max_len
);
865 usb_packet_map(&async
->packet
, &async
->sgl
);
869 case USB_TOKEN_SETUP
:
870 len
= usb_handle_packet(dev
, &async
->packet
);
876 len
= usb_handle_packet(dev
, &async
->packet
);
880 /* invalid pid : frame interrupted */
881 usb_packet_unmap(&async
->packet
, &async
->sgl
);
882 uhci_async_free(async
);
883 s
->status
|= UHCI_STS_HCPERR
;
885 return TD_RESULT_STOP_FRAME
;
888 if (len
== USB_RET_ASYNC
) {
889 uhci_async_link(async
);
890 return TD_RESULT_ASYNC_START
;
893 async
->packet
.result
= len
;
896 len
= uhci_complete_td(s
, td
, async
, int_mask
);
897 usb_packet_unmap(&async
->packet
, &async
->sgl
);
898 uhci_async_free(async
);
902 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
904 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
905 UHCIState
*s
= async
->queue
->uhci
;
907 if (packet
->result
== USB_RET_REMOVE_FROM_QUEUE
) {
908 uhci_async_unlink(async
);
909 uhci_async_cancel(async
);
915 uint32_t link
= async
->td
;
916 uint32_t int_mask
= 0, val
;
918 pci_dma_read(&s
->dev
, link
& ~0xf, &td
, sizeof(td
));
919 le32_to_cpus(&td
.link
);
920 le32_to_cpus(&td
.ctrl
);
921 le32_to_cpus(&td
.token
);
922 le32_to_cpus(&td
.buffer
);
924 uhci_async_unlink(async
);
925 uhci_complete_td(s
, &td
, async
, &int_mask
);
926 s
->pending_int_mask
|= int_mask
;
928 /* update the status bits of the TD */
929 val
= cpu_to_le32(td
.ctrl
);
930 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
931 uhci_async_free(async
);
934 if (s
->frame_bytes
< s
->frame_bandwidth
) {
935 qemu_bh_schedule(s
->bh
);
940 static int is_valid(uint32_t link
)
942 return (link
& 1) == 0;
945 static int is_qh(uint32_t link
)
947 return (link
& 2) != 0;
950 static int depth_first(uint32_t link
)
952 return (link
& 4) != 0;
955 /* QH DB used for detecting QH loops */
956 #define UHCI_MAX_QUEUES 128
958 uint32_t addr
[UHCI_MAX_QUEUES
];
962 static void qhdb_reset(QhDb
*db
)
967 /* Add QH to DB. Returns 1 if already present or DB is full. */
968 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
971 for (i
= 0; i
< db
->count
; i
++)
972 if (db
->addr
[i
] == addr
)
975 if (db
->count
>= UHCI_MAX_QUEUES
)
978 db
->addr
[db
->count
++] = addr
;
982 static void uhci_fill_queue(UHCIState
*s
, UHCI_TD
*td
, struct USBEndpoint
*ep
)
984 uint32_t int_mask
= 0;
985 uint32_t plink
= td
->link
;
986 uint32_t token
= uhci_queue_token(td
);
990 while (is_valid(plink
)) {
991 pci_dma_read(&s
->dev
, plink
& ~0xf, &ptd
, sizeof(ptd
));
992 le32_to_cpus(&ptd
.link
);
993 le32_to_cpus(&ptd
.ctrl
);
994 le32_to_cpus(&ptd
.token
);
995 le32_to_cpus(&ptd
.buffer
);
996 if (!(ptd
.ctrl
& TD_CTRL_ACTIVE
)) {
999 if (uhci_queue_token(&ptd
) != token
) {
1002 trace_usb_uhci_td_queue(plink
& ~0xf, ptd
.ctrl
, ptd
.token
);
1003 ret
= uhci_handle_td(s
, plink
, &ptd
, &int_mask
, true, NULL
);
1004 if (ret
== TD_RESULT_ASYNC_CONT
) {
1007 assert(ret
== TD_RESULT_ASYNC_START
);
1008 assert(int_mask
== 0);
1011 usb_device_flush_ep_queue(ep
->dev
, ep
);
1014 static void uhci_process_frame(UHCIState
*s
)
1016 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
1017 uint32_t curr_qh
, td_count
= 0;
1018 struct USBEndpoint
*curr_ep
;
1024 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
1026 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
1027 le32_to_cpus(&link
);
1034 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
1035 if (s
->frame_bytes
>= s
->frame_bandwidth
) {
1036 /* We've reached the usb 1.1 bandwidth, which is
1037 1280 bytes/frame, stop processing */
1038 trace_usb_uhci_frame_stop_bandwidth();
1043 trace_usb_uhci_qh_load(link
& ~0xf);
1045 if (qhdb_insert(&qhdb
, link
)) {
1047 * We're going in circles. Which is not a bug because
1048 * HCD is allowed to do that as part of the BW management.
1050 * Stop processing here if no transaction has been done
1051 * since we've been here last time.
1053 if (td_count
== 0) {
1054 trace_usb_uhci_frame_loop_stop_idle();
1057 trace_usb_uhci_frame_loop_continue();
1060 qhdb_insert(&qhdb
, link
);
1064 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
1065 le32_to_cpus(&qh
.link
);
1066 le32_to_cpus(&qh
.el_link
);
1068 if (!is_valid(qh
.el_link
)) {
1069 /* QH w/o elements */
1073 /* QH with elements */
1081 pci_dma_read(&s
->dev
, link
& ~0xf, &td
, sizeof(td
));
1082 le32_to_cpus(&td
.link
);
1083 le32_to_cpus(&td
.ctrl
);
1084 le32_to_cpus(&td
.token
);
1085 le32_to_cpus(&td
.buffer
);
1086 trace_usb_uhci_td_load(curr_qh
& ~0xf, link
& ~0xf, td
.ctrl
, td
.token
);
1088 old_td_ctrl
= td
.ctrl
;
1089 ret
= uhci_handle_td(s
, link
, &td
, &int_mask
, false, &curr_ep
);
1090 if (old_td_ctrl
!= td
.ctrl
) {
1091 /* update the status bits of the TD */
1092 val
= cpu_to_le32(td
.ctrl
);
1093 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1097 case TD_RESULT_STOP_FRAME
: /* interrupted frame */
1100 case TD_RESULT_NEXT_QH
:
1101 case TD_RESULT_ASYNC_CONT
:
1102 trace_usb_uhci_td_nextqh(curr_qh
& ~0xf, link
& ~0xf);
1103 link
= curr_qh
? qh
.link
: td
.link
;
1106 case TD_RESULT_ASYNC_START
:
1107 trace_usb_uhci_td_async(curr_qh
& ~0xf, link
& ~0xf);
1108 uhci_fill_queue(s
, &td
, curr_ep
);
1109 link
= curr_qh
? qh
.link
: td
.link
;
1112 case TD_RESULT_COMPLETE
:
1113 trace_usb_uhci_td_complete(curr_qh
& ~0xf, link
& ~0xf);
1116 s
->frame_bytes
+= (td
.ctrl
& 0x7ff) + 1;
1119 /* update QH element link */
1121 val
= cpu_to_le32(qh
.el_link
);
1122 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1124 if (!depth_first(link
)) {
1125 /* done with this QH */
1133 assert(!"unknown return code");
1136 /* go to the next entry */
1140 s
->pending_int_mask
|= int_mask
;
1143 static void uhci_bh(void *opaque
)
1145 UHCIState
*s
= opaque
;
1146 uhci_process_frame(s
);
1149 static void uhci_frame_timer(void *opaque
)
1151 UHCIState
*s
= opaque
;
1153 /* prepare the timer for the next frame */
1154 s
->expire_time
+= (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
1156 qemu_bh_cancel(s
->bh
);
1158 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1160 trace_usb_uhci_schedule_stop();
1161 qemu_del_timer(s
->frame_timer
);
1162 uhci_async_cancel_all(s
);
1163 /* set hchalted bit in status - UHCI11D 2.1.2 */
1164 s
->status
|= UHCI_STS_HCHALTED
;
1168 /* Complete the previous frame */
1169 if (s
->pending_int_mask
) {
1170 s
->status2
|= s
->pending_int_mask
;
1171 s
->status
|= UHCI_STS_USBINT
;
1174 s
->pending_int_mask
= 0;
1176 /* Start new frame */
1177 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1179 trace_usb_uhci_frame_start(s
->frnum
);
1181 uhci_async_validate_begin(s
);
1183 uhci_process_frame(s
);
1185 uhci_async_validate_end(s
);
1187 qemu_mod_timer(s
->frame_timer
, s
->expire_time
);
1190 static const MemoryRegionPortio uhci_portio
[] = {
1191 { 0, 32, 2, .write
= uhci_ioport_writew
, },
1192 { 0, 32, 2, .read
= uhci_ioport_readw
, },
1193 { 0, 32, 4, .write
= uhci_ioport_writel
, },
1194 { 0, 32, 4, .read
= uhci_ioport_readl
, },
1195 { 0, 32, 1, .write
= uhci_ioport_writeb
, },
1196 { 0, 32, 1, .read
= uhci_ioport_readb
, },
1197 PORTIO_END_OF_LIST()
1200 static const MemoryRegionOps uhci_ioport_ops
= {
1201 .old_portio
= uhci_portio
,
1204 static USBPortOps uhci_port_ops
= {
1205 .attach
= uhci_attach
,
1206 .detach
= uhci_detach
,
1207 .child_detach
= uhci_child_detach
,
1208 .wakeup
= uhci_wakeup
,
1209 .complete
= uhci_async_complete
,
1212 static USBBusOps uhci_bus_ops
= {
1215 static int usb_uhci_common_initfn(PCIDevice
*dev
)
1217 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1218 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1219 uint8_t *pci_conf
= s
->dev
.config
;
1222 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1223 /* TODO: reset value should be 0. */
1224 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; // release number
1226 switch (pc
->device_id
) {
1227 case PCI_DEVICE_ID_INTEL_82801I_UHCI1
:
1228 s
->irq_pin
= 0; /* A */
1230 case PCI_DEVICE_ID_INTEL_82801I_UHCI2
:
1231 s
->irq_pin
= 1; /* B */
1233 case PCI_DEVICE_ID_INTEL_82801I_UHCI3
:
1234 s
->irq_pin
= 2; /* C */
1237 s
->irq_pin
= 3; /* D */
1240 pci_config_set_interrupt_pin(pci_conf
, s
->irq_pin
+ 1);
1243 USBPort
*ports
[NB_PORTS
];
1244 for(i
= 0; i
< NB_PORTS
; i
++) {
1245 ports
[i
] = &s
->ports
[i
].port
;
1247 if (usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1248 s
->firstport
, s
, &uhci_port_ops
,
1249 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
) != 0) {
1253 usb_bus_new(&s
->bus
, &uhci_bus_ops
, &s
->dev
.qdev
);
1254 for (i
= 0; i
< NB_PORTS
; i
++) {
1255 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1256 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1259 s
->bh
= qemu_bh_new(uhci_bh
, s
);
1260 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, uhci_frame_timer
, s
);
1261 s
->num_ports_vmstate
= NB_PORTS
;
1262 QTAILQ_INIT(&s
->queues
);
1264 qemu_register_reset(uhci_reset
, s
);
1266 memory_region_init_io(&s
->io_bar
, &uhci_ioport_ops
, s
, "uhci", 0x20);
1267 /* Use region 4 for consistency with real hardware. BSD guests seem
1269 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1274 static int usb_uhci_vt82c686b_initfn(PCIDevice
*dev
)
1276 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1277 uint8_t *pci_conf
= s
->dev
.config
;
1279 /* USB misc control 1/2 */
1280 pci_set_long(pci_conf
+ 0x40,0x00001000);
1282 pci_set_long(pci_conf
+ 0x80,0x00020001);
1283 /* USB legacy support */
1284 pci_set_long(pci_conf
+ 0xc0,0x00002000);
1286 return usb_uhci_common_initfn(dev
);
1289 static void usb_uhci_exit(PCIDevice
*dev
)
1291 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1293 memory_region_destroy(&s
->io_bar
);
1296 static Property uhci_properties
[] = {
1297 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1298 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1299 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1300 DEFINE_PROP_END_OF_LIST(),
1303 static void piix3_uhci_class_init(ObjectClass
*klass
, void *data
)
1305 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1306 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1308 k
->init
= usb_uhci_common_initfn
;
1309 k
->exit
= usb_uhci_exit
;
1310 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1311 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
;
1313 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1314 dc
->vmsd
= &vmstate_uhci
;
1315 dc
->props
= uhci_properties
;
1318 static TypeInfo piix3_uhci_info
= {
1319 .name
= "piix3-usb-uhci",
1320 .parent
= TYPE_PCI_DEVICE
,
1321 .instance_size
= sizeof(UHCIState
),
1322 .class_init
= piix3_uhci_class_init
,
1325 static void piix4_uhci_class_init(ObjectClass
*klass
, void *data
)
1327 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1328 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1330 k
->init
= usb_uhci_common_initfn
;
1331 k
->exit
= usb_uhci_exit
;
1332 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1333 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
;
1335 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1336 dc
->vmsd
= &vmstate_uhci
;
1337 dc
->props
= uhci_properties
;
1340 static TypeInfo piix4_uhci_info
= {
1341 .name
= "piix4-usb-uhci",
1342 .parent
= TYPE_PCI_DEVICE
,
1343 .instance_size
= sizeof(UHCIState
),
1344 .class_init
= piix4_uhci_class_init
,
1347 static void vt82c686b_uhci_class_init(ObjectClass
*klass
, void *data
)
1349 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1350 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1352 k
->init
= usb_uhci_vt82c686b_initfn
;
1353 k
->exit
= usb_uhci_exit
;
1354 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
1355 k
->device_id
= PCI_DEVICE_ID_VIA_UHCI
;
1357 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1358 dc
->vmsd
= &vmstate_uhci
;
1359 dc
->props
= uhci_properties
;
1362 static TypeInfo vt82c686b_uhci_info
= {
1363 .name
= "vt82c686b-usb-uhci",
1364 .parent
= TYPE_PCI_DEVICE
,
1365 .instance_size
= sizeof(UHCIState
),
1366 .class_init
= vt82c686b_uhci_class_init
,
1369 static void ich9_uhci1_class_init(ObjectClass
*klass
, void *data
)
1371 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1372 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1374 k
->init
= usb_uhci_common_initfn
;
1375 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1376 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
;
1378 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1379 dc
->vmsd
= &vmstate_uhci
;
1380 dc
->props
= uhci_properties
;
1383 static TypeInfo ich9_uhci1_info
= {
1384 .name
= "ich9-usb-uhci1",
1385 .parent
= TYPE_PCI_DEVICE
,
1386 .instance_size
= sizeof(UHCIState
),
1387 .class_init
= ich9_uhci1_class_init
,
1390 static void ich9_uhci2_class_init(ObjectClass
*klass
, void *data
)
1392 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1393 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1395 k
->init
= usb_uhci_common_initfn
;
1396 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1397 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
;
1399 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1400 dc
->vmsd
= &vmstate_uhci
;
1401 dc
->props
= uhci_properties
;
1404 static TypeInfo ich9_uhci2_info
= {
1405 .name
= "ich9-usb-uhci2",
1406 .parent
= TYPE_PCI_DEVICE
,
1407 .instance_size
= sizeof(UHCIState
),
1408 .class_init
= ich9_uhci2_class_init
,
1411 static void ich9_uhci3_class_init(ObjectClass
*klass
, void *data
)
1413 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1414 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1416 k
->init
= usb_uhci_common_initfn
;
1417 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1418 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
;
1420 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1421 dc
->vmsd
= &vmstate_uhci
;
1422 dc
->props
= uhci_properties
;
1425 static TypeInfo ich9_uhci3_info
= {
1426 .name
= "ich9-usb-uhci3",
1427 .parent
= TYPE_PCI_DEVICE
,
1428 .instance_size
= sizeof(UHCIState
),
1429 .class_init
= ich9_uhci3_class_init
,
1432 static void uhci_register_types(void)
1434 type_register_static(&piix3_uhci_info
);
1435 type_register_static(&piix4_uhci_info
);
1436 type_register_static(&vt82c686b_uhci_info
);
1437 type_register_static(&ich9_uhci1_info
);
1438 type_register_static(&ich9_uhci2_info
);
1439 type_register_static(&ich9_uhci3_info
);
1442 type_init(uhci_register_types
)