]> git.proxmox.com Git - qemu.git/blob - hw/usb-musb.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
usb: rework attach/detach workflow
[qemu.git] / hw / usb-musb.c
1 /*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "usb.h"
26 #include "irq.h"
27 #include "hw.h"
28
29 /* Common USB registers */
30 #define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31 #define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33 #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34 #define MUSB_HDRC_INTRRX 0x04
35 #define MUSB_HDRC_INTRTXE 0x06
36 #define MUSB_HDRC_INTRRXE 0x08
37 #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38 #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39 #define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40 #define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41 #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43 /* Per-EP registers in indexed mode */
44 #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46 /* EP FIFOs */
47 #define MUSB_HDRC_FIFO 0x20
48
49 /* Additional Control Registers */
50 #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52 /* These are indexed */
53 #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54 #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55 #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56 #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58 /* Some more registers */
59 #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60 #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
63 /* ULPI pass-through */
64 #define MUSB_HDRC_ULPI_VBUSCTL 0x70
65 #define MUSB_HDRC_ULPI_REGDATA 0x74
66 #define MUSB_HDRC_ULPI_REGADDR 0x75
67 #define MUSB_HDRC_ULPI_REGCTL 0x76
68
69 /* Extended config & PHY control */
70 #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71 #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72 #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73 #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74 #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75 #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76 #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78 /* Per-EP BUSCTL registers */
79 #define MUSB_HDRC_BUSCTL 0x80
80
81 /* Per-EP registers in flat mode */
82 #define MUSB_HDRC_EP 0x100
83
84 /* offsets to registers in flat model */
85 #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86 #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87 #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88 #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89 #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90 #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91 #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92 #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93 #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94 #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95 #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96 #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97 #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98 #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99 #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101 /* "Bus control" registers */
102 #define MUSB_HDRC_TXFUNCADDR 0x00
103 #define MUSB_HDRC_TXHUBADDR 0x02
104 #define MUSB_HDRC_TXHUBPORT 0x03
105
106 #define MUSB_HDRC_RXFUNCADDR 0x04
107 #define MUSB_HDRC_RXHUBADDR 0x06
108 #define MUSB_HDRC_RXHUBPORT 0x07
109
110 /*
111 * MUSBHDRC Register bit masks
112 */
113
114 /* POWER */
115 #define MGC_M_POWER_ISOUPDATE 0x80
116 #define MGC_M_POWER_SOFTCONN 0x40
117 #define MGC_M_POWER_HSENAB 0x20
118 #define MGC_M_POWER_HSMODE 0x10
119 #define MGC_M_POWER_RESET 0x08
120 #define MGC_M_POWER_RESUME 0x04
121 #define MGC_M_POWER_SUSPENDM 0x02
122 #define MGC_M_POWER_ENSUSPEND 0x01
123
124 /* INTRUSB */
125 #define MGC_M_INTR_SUSPEND 0x01
126 #define MGC_M_INTR_RESUME 0x02
127 #define MGC_M_INTR_RESET 0x04
128 #define MGC_M_INTR_BABBLE 0x04
129 #define MGC_M_INTR_SOF 0x08
130 #define MGC_M_INTR_CONNECT 0x10
131 #define MGC_M_INTR_DISCONNECT 0x20
132 #define MGC_M_INTR_SESSREQ 0x40
133 #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134 #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136 /* DEVCTL */
137 #define MGC_M_DEVCTL_BDEVICE 0x80
138 #define MGC_M_DEVCTL_FSDEV 0x40
139 #define MGC_M_DEVCTL_LSDEV 0x20
140 #define MGC_M_DEVCTL_VBUS 0x18
141 #define MGC_S_DEVCTL_VBUS 3
142 #define MGC_M_DEVCTL_HM 0x04
143 #define MGC_M_DEVCTL_HR 0x02
144 #define MGC_M_DEVCTL_SESSION 0x01
145
146 /* TESTMODE */
147 #define MGC_M_TEST_FORCE_HOST 0x80
148 #define MGC_M_TEST_FIFO_ACCESS 0x40
149 #define MGC_M_TEST_FORCE_FS 0x20
150 #define MGC_M_TEST_FORCE_HS 0x10
151 #define MGC_M_TEST_PACKET 0x08
152 #define MGC_M_TEST_K 0x04
153 #define MGC_M_TEST_J 0x02
154 #define MGC_M_TEST_SE0_NAK 0x01
155
156 /* CSR0 */
157 #define MGC_M_CSR0_FLUSHFIFO 0x0100
158 #define MGC_M_CSR0_TXPKTRDY 0x0002
159 #define MGC_M_CSR0_RXPKTRDY 0x0001
160
161 /* CSR0 in Peripheral mode */
162 #define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163 #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164 #define MGC_M_CSR0_P_SENDSTALL 0x0020
165 #define MGC_M_CSR0_P_SETUPEND 0x0010
166 #define MGC_M_CSR0_P_DATAEND 0x0008
167 #define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169 /* CSR0 in Host mode */
170 #define MGC_M_CSR0_H_NO_PING 0x0800
171 #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172 #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173 #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174 #define MGC_M_CSR0_H_STATUSPKT 0x0040
175 #define MGC_M_CSR0_H_REQPKT 0x0020
176 #define MGC_M_CSR0_H_ERROR 0x0010
177 #define MGC_M_CSR0_H_SETUPPKT 0x0008
178 #define MGC_M_CSR0_H_RXSTALL 0x0004
179
180 /* CONFIGDATA */
181 #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182 #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183 #define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184 #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185 #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186 #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187 #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188 #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190 /* TXCSR in Peripheral and Host mode */
191 #define MGC_M_TXCSR_AUTOSET 0x8000
192 #define MGC_M_TXCSR_ISO 0x4000
193 #define MGC_M_TXCSR_MODE 0x2000
194 #define MGC_M_TXCSR_DMAENAB 0x1000
195 #define MGC_M_TXCSR_FRCDATATOG 0x0800
196 #define MGC_M_TXCSR_DMAMODE 0x0400
197 #define MGC_M_TXCSR_CLRDATATOG 0x0040
198 #define MGC_M_TXCSR_FLUSHFIFO 0x0008
199 #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200 #define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202 /* TXCSR in Peripheral mode */
203 #define MGC_M_TXCSR_P_INCOMPTX 0x0080
204 #define MGC_M_TXCSR_P_SENTSTALL 0x0020
205 #define MGC_M_TXCSR_P_SENDSTALL 0x0010
206 #define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208 /* TXCSR in Host mode */
209 #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210 #define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211 #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212 #define MGC_M_TXCSR_H_RXSTALL 0x0020
213 #define MGC_M_TXCSR_H_ERROR 0x0004
214
215 /* RXCSR in Peripheral and Host mode */
216 #define MGC_M_RXCSR_AUTOCLEAR 0x8000
217 #define MGC_M_RXCSR_DMAENAB 0x2000
218 #define MGC_M_RXCSR_DISNYET 0x1000
219 #define MGC_M_RXCSR_DMAMODE 0x0800
220 #define MGC_M_RXCSR_INCOMPRX 0x0100
221 #define MGC_M_RXCSR_CLRDATATOG 0x0080
222 #define MGC_M_RXCSR_FLUSHFIFO 0x0010
223 #define MGC_M_RXCSR_DATAERROR 0x0008
224 #define MGC_M_RXCSR_FIFOFULL 0x0002
225 #define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227 /* RXCSR in Peripheral mode */
228 #define MGC_M_RXCSR_P_ISO 0x4000
229 #define MGC_M_RXCSR_P_SENTSTALL 0x0040
230 #define MGC_M_RXCSR_P_SENDSTALL 0x0020
231 #define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233 /* RXCSR in Host mode */
234 #define MGC_M_RXCSR_H_AUTOREQ 0x4000
235 #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236 #define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237 #define MGC_M_RXCSR_H_RXSTALL 0x0040
238 #define MGC_M_RXCSR_H_REQPKT 0x0020
239 #define MGC_M_RXCSR_H_ERROR 0x0004
240
241 /* HUBADDR */
242 #define MGC_M_HUBADDR_MULTI_TT 0x80
243
244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247 #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248 #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249 #define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250 #define MGC_M_ULPI_REGCTL_REG 0x01
251
252 /* #define MUSB_DEBUG */
253
254 #ifdef MUSB_DEBUG
255 #define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257 #else
258 #define TRACE(...)
259 #endif
260
261
262 static void musb_attach(USBPort *port);
263 static void musb_detach(USBPort *port);
264
265 static USBPortOps musb_port_ops = {
266 .attach = musb_attach,
267 .detach = musb_detach,
268 };
269
270 typedef struct {
271 uint16_t faddr[2];
272 uint8_t haddr[2];
273 uint8_t hport[2];
274 uint16_t csr[2];
275 uint16_t maxp[2];
276 uint16_t rxcount;
277 uint8_t type[2];
278 uint8_t interval[2];
279 uint8_t config;
280 uint8_t fifosize;
281 int timeout[2]; /* Always in microframes */
282
283 uint8_t *buf[2];
284 int fifolen[2];
285 int fifostart[2];
286 int fifoaddr[2];
287 USBPacket packey[2];
288 int status[2];
289 int ext_size[2];
290
291 /* For callbacks' use */
292 int epnum;
293 int interrupt[2];
294 MUSBState *musb;
295 USBCallback *delayed_cb[2];
296 QEMUTimer *intv_timer[2];
297 } MUSBEndPoint;
298
299 struct MUSBState {
300 qemu_irq *irqs;
301 USBBus bus;
302 USBPort port;
303
304 int idx;
305 uint8_t devctl;
306 uint8_t power;
307 uint8_t faddr;
308
309 uint8_t intr;
310 uint8_t mask;
311 uint16_t tx_intr;
312 uint16_t tx_mask;
313 uint16_t rx_intr;
314 uint16_t rx_mask;
315
316 int setup_len;
317 int session;
318
319 uint8_t buf[0x8000];
320
321 /* Duplicating the world since 2008!... probably we should have 32
322 * logical, single endpoints instead. */
323 MUSBEndPoint ep[16];
324 } *musb_init(qemu_irq *irqs)
325 {
326 MUSBState *s = qemu_mallocz(sizeof(*s));
327 int i;
328
329 s->irqs = irqs;
330
331 s->faddr = 0x00;
332 s->power = MGC_M_POWER_HSENAB;
333 s->tx_intr = 0x0000;
334 s->rx_intr = 0x0000;
335 s->tx_mask = 0xffff;
336 s->rx_mask = 0xffff;
337 s->intr = 0x00;
338 s->mask = 0x06;
339 s->idx = 0;
340
341 /* TODO: _DW */
342 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
343 for (i = 0; i < 16; i ++) {
344 s->ep[i].fifosize = 64;
345 s->ep[i].maxp[0] = 0x40;
346 s->ep[i].maxp[1] = 0x40;
347 s->ep[i].musb = s;
348 s->ep[i].epnum = i;
349 }
350
351 usb_bus_new(&s->bus, NULL /* FIXME */);
352 usb_register_port(&s->bus, &s->port, s, 0, NULL, &musb_port_ops);
353
354 return s;
355 }
356
357 static void musb_vbus_set(MUSBState *s, int level)
358 {
359 if (level)
360 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
361 else
362 s->devctl &= ~MGC_M_DEVCTL_VBUS;
363
364 qemu_set_irq(s->irqs[musb_set_vbus], level);
365 }
366
367 static void musb_intr_set(MUSBState *s, int line, int level)
368 {
369 if (!level) {
370 s->intr &= ~(1 << line);
371 qemu_irq_lower(s->irqs[line]);
372 } else if (s->mask & (1 << line)) {
373 s->intr |= 1 << line;
374 qemu_irq_raise(s->irqs[line]);
375 }
376 }
377
378 static void musb_tx_intr_set(MUSBState *s, int line, int level)
379 {
380 if (!level) {
381 s->tx_intr &= ~(1 << line);
382 if (!s->tx_intr)
383 qemu_irq_lower(s->irqs[musb_irq_tx]);
384 } else if (s->tx_mask & (1 << line)) {
385 s->tx_intr |= 1 << line;
386 qemu_irq_raise(s->irqs[musb_irq_tx]);
387 }
388 }
389
390 static void musb_rx_intr_set(MUSBState *s, int line, int level)
391 {
392 if (line) {
393 if (!level) {
394 s->rx_intr &= ~(1 << line);
395 if (!s->rx_intr)
396 qemu_irq_lower(s->irqs[musb_irq_rx]);
397 } else if (s->rx_mask & (1 << line)) {
398 s->rx_intr |= 1 << line;
399 qemu_irq_raise(s->irqs[musb_irq_rx]);
400 }
401 } else
402 musb_tx_intr_set(s, line, level);
403 }
404
405 uint32_t musb_core_intr_get(MUSBState *s)
406 {
407 return (s->rx_intr << 15) | s->tx_intr;
408 }
409
410 void musb_core_intr_clear(MUSBState *s, uint32_t mask)
411 {
412 if (s->rx_intr) {
413 s->rx_intr &= mask >> 15;
414 if (!s->rx_intr)
415 qemu_irq_lower(s->irqs[musb_irq_rx]);
416 }
417
418 if (s->tx_intr) {
419 s->tx_intr &= mask & 0xffff;
420 if (!s->tx_intr)
421 qemu_irq_lower(s->irqs[musb_irq_tx]);
422 }
423 }
424
425 void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
426 {
427 s->ep[epnum].ext_size[!is_tx] = size;
428 s->ep[epnum].fifostart[0] = 0;
429 s->ep[epnum].fifostart[1] = 0;
430 s->ep[epnum].fifolen[0] = 0;
431 s->ep[epnum].fifolen[1] = 0;
432 }
433
434 static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
435 {
436 int detect_prev = prev_dev && prev_sess;
437 int detect = !!s->port.dev && s->session;
438
439 if (detect && !detect_prev) {
440 /* Let's skip the ID pin sense and VBUS sense formalities and
441 * and signal a successful SRP directly. This should work at least
442 * for the Linux driver stack. */
443 musb_intr_set(s, musb_irq_connect, 1);
444
445 if (s->port.dev->speed == USB_SPEED_LOW) {
446 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
447 s->devctl |= MGC_M_DEVCTL_LSDEV;
448 } else {
449 s->devctl |= MGC_M_DEVCTL_FSDEV;
450 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
451 }
452
453 /* A-mode? */
454 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
455
456 /* Host-mode bit? */
457 s->devctl |= MGC_M_DEVCTL_HM;
458 #if 1
459 musb_vbus_set(s, 1);
460 #endif
461 } else if (!detect && detect_prev) {
462 #if 1
463 musb_vbus_set(s, 0);
464 #endif
465 }
466 }
467
468 /* Attach or detach a device on our only port. */
469 static void musb_attach(USBPort *port)
470 {
471 MUSBState *s = (MUSBState *) port->opaque;
472
473 musb_intr_set(s, musb_irq_vbus_request, 1);
474 musb_session_update(s, 0, s->session);
475 }
476
477 static void musb_detach(USBPort *port)
478 {
479 MUSBState *s = (MUSBState *) port->opaque;
480
481 musb_intr_set(s, musb_irq_disconnect, 1);
482 musb_session_update(s, 1, s->session);
483 }
484
485 static inline void musb_cb_tick0(void *opaque)
486 {
487 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
488
489 ep->delayed_cb[0](&ep->packey[0], opaque);
490 }
491
492 static inline void musb_cb_tick1(void *opaque)
493 {
494 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
495
496 ep->delayed_cb[1](&ep->packey[1], opaque);
497 }
498
499 #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
500
501 static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
502 {
503 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
504 int timeout = 0;
505
506 if (ep->status[dir] == USB_RET_NAK)
507 timeout = ep->timeout[dir];
508 else if (ep->interrupt[dir])
509 timeout = 8;
510 else
511 return musb_cb_tick(opaque);
512
513 if (!ep->intv_timer[dir])
514 ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque);
515
516 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) +
517 muldiv64(timeout, get_ticks_per_sec(), 8000));
518 }
519
520 static void musb_schedule0_cb(USBPacket *packey, void *opaque)
521 {
522 return musb_schedule_cb(packey, opaque, 0);
523 }
524
525 static void musb_schedule1_cb(USBPacket *packey, void *opaque)
526 {
527 return musb_schedule_cb(packey, opaque, 1);
528 }
529
530 static int musb_timeout(int ttype, int speed, int val)
531 {
532 #if 1
533 return val << 3;
534 #endif
535
536 switch (ttype) {
537 case USB_ENDPOINT_XFER_CONTROL:
538 if (val < 2)
539 return 0;
540 else if (speed == USB_SPEED_HIGH)
541 return 1 << (val - 1);
542 else
543 return 8 << (val - 1);
544
545 case USB_ENDPOINT_XFER_INT:
546 if (speed == USB_SPEED_HIGH)
547 if (val < 2)
548 return 0;
549 else
550 return 1 << (val - 1);
551 else
552 return val << 3;
553
554 case USB_ENDPOINT_XFER_BULK:
555 case USB_ENDPOINT_XFER_ISOC:
556 if (val < 2)
557 return 0;
558 else if (speed == USB_SPEED_HIGH)
559 return 1 << (val - 1);
560 else
561 return 8 << (val - 1);
562 /* TODO: what with low-speed Bulk and Isochronous? */
563 }
564
565 hw_error("bad interval\n");
566 }
567
568 static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
569 int epnum, int pid, int len, USBCallback cb, int dir)
570 {
571 int ret;
572 int idx = epnum && dir;
573 int ttype;
574
575 /* ep->type[0,1] contains:
576 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
577 * in bits 5:4 the transfer type (BULK / INT)
578 * in bits 3:0 the EP num
579 */
580 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
581
582 ep->timeout[dir] = musb_timeout(ttype,
583 ep->type[idx] >> 6, ep->interval[idx]);
584 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
585 ep->delayed_cb[dir] = cb;
586 cb = dir ? musb_schedule1_cb : musb_schedule0_cb;
587
588 ep->packey[dir].pid = pid;
589 /* A wild guess on the FADDR semantics... */
590 ep->packey[dir].devaddr = ep->faddr[idx];
591 ep->packey[dir].devep = ep->type[idx] & 0xf;
592 ep->packey[dir].data = (void *) ep->buf[idx];
593 ep->packey[dir].len = len;
594 ep->packey[dir].complete_cb = cb;
595 ep->packey[dir].complete_opaque = ep;
596
597 if (s->port.dev)
598 ret = s->port.dev->info->handle_packet(s->port.dev, &ep->packey[dir]);
599 else
600 ret = USB_RET_NODEV;
601
602 if (ret == USB_RET_ASYNC) {
603 ep->status[dir] = len;
604 return;
605 }
606
607 ep->status[dir] = ret;
608 usb_packet_complete(&ep->packey[dir]);
609 }
610
611 static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
612 {
613 /* Unfortunately we can't use packey->devep because that's the remote
614 * endpoint number and may be different than our local. */
615 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
616 int epnum = ep->epnum;
617 MUSBState *s = ep->musb;
618
619 ep->fifostart[0] = 0;
620 ep->fifolen[0] = 0;
621 #ifdef CLEAR_NAK
622 if (ep->status[0] != USB_RET_NAK) {
623 #endif
624 if (epnum)
625 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
626 else
627 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
628 #ifdef CLEAR_NAK
629 }
630 #endif
631
632 /* Clear all of the error bits first */
633 if (epnum)
634 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
635 MGC_M_TXCSR_H_NAKTIMEOUT);
636 else
637 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
638 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
639
640 if (ep->status[0] == USB_RET_STALL) {
641 /* Command not supported by target! */
642 ep->status[0] = 0;
643
644 if (epnum)
645 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
646 else
647 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
648 }
649
650 if (ep->status[0] == USB_RET_NAK) {
651 ep->status[0] = 0;
652
653 /* NAK timeouts are only generated in Bulk transfers and
654 * Data-errors in Isochronous. */
655 if (ep->interrupt[0]) {
656 return;
657 }
658
659 if (epnum)
660 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
661 else
662 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
663 }
664
665 if (ep->status[0] < 0) {
666 if (ep->status[0] == USB_RET_BABBLE)
667 musb_intr_set(s, musb_irq_rst_babble, 1);
668
669 /* Pretend we've tried three times already and failed (in
670 * case of USB_TOKEN_SETUP). */
671 if (epnum)
672 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
673 else
674 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
675
676 musb_tx_intr_set(s, epnum, 1);
677 return;
678 }
679 /* TODO: check len for over/underruns of an OUT packet? */
680
681 #ifdef SETUPLEN_HACK
682 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
683 s->setup_len = ep->packey[0].data[6];
684 #endif
685
686 /* In DMA mode: if no error, assert DMA request for this EP,
687 * and skip the interrupt. */
688 musb_tx_intr_set(s, epnum, 1);
689 }
690
691 static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
692 {
693 /* Unfortunately we can't use packey->devep because that's the remote
694 * endpoint number and may be different than our local. */
695 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
696 int epnum = ep->epnum;
697 MUSBState *s = ep->musb;
698
699 ep->fifostart[1] = 0;
700 ep->fifolen[1] = 0;
701
702 #ifdef CLEAR_NAK
703 if (ep->status[1] != USB_RET_NAK) {
704 #endif
705 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
706 if (!epnum)
707 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
708 #ifdef CLEAR_NAK
709 }
710 #endif
711
712 /* Clear all of the imaginable error bits first */
713 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
714 MGC_M_RXCSR_DATAERROR);
715 if (!epnum)
716 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
717 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
718
719 if (ep->status[1] == USB_RET_STALL) {
720 ep->status[1] = 0;
721 packey->len = 0;
722
723 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
724 if (!epnum)
725 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
726 }
727
728 if (ep->status[1] == USB_RET_NAK) {
729 ep->status[1] = 0;
730
731 /* NAK timeouts are only generated in Bulk transfers and
732 * Data-errors in Isochronous. */
733 if (ep->interrupt[1])
734 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
735 packey->len, musb_rx_packet_complete, 1);
736
737 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
738 if (!epnum)
739 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
740 }
741
742 if (ep->status[1] < 0) {
743 if (ep->status[1] == USB_RET_BABBLE) {
744 musb_intr_set(s, musb_irq_rst_babble, 1);
745 return;
746 }
747
748 /* Pretend we've tried three times already and failed (in
749 * case of a control transfer). */
750 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
751 if (!epnum)
752 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
753
754 musb_rx_intr_set(s, epnum, 1);
755 return;
756 }
757 /* TODO: check len for over/underruns of an OUT packet? */
758 /* TODO: perhaps make use of e->ext_size[1] here. */
759
760 packey->len = ep->status[1];
761
762 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
763 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
764 if (!epnum)
765 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
766
767 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
768 /* In DMA mode: assert DMA request for this EP */
769 }
770
771 /* Only if DMA has not been asserted */
772 musb_rx_intr_set(s, epnum, 1);
773 }
774
775 static void musb_tx_rdy(MUSBState *s, int epnum)
776 {
777 MUSBEndPoint *ep = s->ep + epnum;
778 int pid;
779 int total, valid = 0;
780 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
781 ep->fifostart[0] += ep->fifolen[0];
782 ep->fifolen[0] = 0;
783
784 /* XXX: how's the total size of the packet retrieved exactly in
785 * the generic case? */
786 total = ep->maxp[0] & 0x3ff;
787
788 if (ep->ext_size[0]) {
789 total = ep->ext_size[0];
790 ep->ext_size[0] = 0;
791 valid = 1;
792 }
793
794 /* If the packet is not fully ready yet, wait for a next segment. */
795 if (epnum && (ep->fifostart[0]) < total)
796 return;
797
798 if (!valid)
799 total = ep->fifostart[0];
800
801 pid = USB_TOKEN_OUT;
802 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
803 pid = USB_TOKEN_SETUP;
804 if (total != 8) {
805 TRACE("illegal SETUPPKT length of %i bytes", total);
806 }
807 /* Controller should retry SETUP packets three times on errors
808 * but it doesn't make sense for us to do that. */
809 }
810
811 return musb_packet(s, ep, epnum, pid,
812 total, musb_tx_packet_complete, 0);
813 }
814
815 static void musb_rx_req(MUSBState *s, int epnum)
816 {
817 MUSBEndPoint *ep = s->ep + epnum;
818 int total;
819
820 /* If we already have a packet, which didn't fit into the
821 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
822 if (ep->packey[1].pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
823 (ep->fifostart[1]) + ep->rxcount <
824 ep->packey[1].len) {
825 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
826 ep->fifostart[1] += ep->rxcount;
827 ep->fifolen[1] = 0;
828
829 ep->rxcount = MIN(ep->packey[0].len - (ep->fifostart[1]),
830 ep->maxp[1]);
831
832 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
833 if (!epnum)
834 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
835
836 /* Clear all of the error bits first */
837 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
838 MGC_M_RXCSR_DATAERROR);
839 if (!epnum)
840 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
841 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
842
843 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
844 if (!epnum)
845 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
846 musb_rx_intr_set(s, epnum, 1);
847 return;
848 }
849
850 /* The driver sets maxp[1] to 64 or less because it knows the hardware
851 * FIFO is this deep. Bigger packets get split in
852 * usb_generic_handle_packet but we can also do the splitting locally
853 * for performance. It turns out we can also have a bigger FIFO and
854 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
855 * OK with single packets of even 32KB and we avoid splitting, however
856 * usb_msd.c sometimes sends a packet bigger than what Linux expects
857 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
858 * hides this overrun from Linux. Up to 4096 everything is fine
859 * though. Currently this is disabled.
860 *
861 * XXX: mind ep->fifosize. */
862 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
863
864 #ifdef SETUPLEN_HACK
865 /* Why should *we* do that instead of Linux? */
866 if (!epnum) {
867 if (ep->packey[0].devaddr == 2)
868 total = MIN(s->setup_len, 8);
869 else
870 total = MIN(s->setup_len, 64);
871 s->setup_len -= total;
872 }
873 #endif
874
875 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
876 total, musb_rx_packet_complete, 1);
877 }
878
879 static uint8_t musb_read_fifo(MUSBEndPoint *ep)
880 {
881 uint8_t value;
882 if (ep->fifolen[1] >= 64) {
883 /* We have a FIFO underrun */
884 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
885 return 0x00000000;
886 }
887 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
888 * (if AUTOREQ is set) */
889
890 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
891 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
892 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
893 return value;
894 }
895
896 static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
897 {
898 TRACE("EP%d = %02x", ep->epnum, value);
899 if (ep->fifolen[0] >= 64) {
900 /* We have a FIFO overrun */
901 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
902 return;
903 }
904
905 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
906 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
907 }
908
909 static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
910 {
911 if (ep->intv_timer[dir])
912 qemu_del_timer(ep->intv_timer[dir]);
913 }
914
915 /* Bus control */
916 static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
917 {
918 MUSBState *s = (MUSBState *) opaque;
919
920 switch (addr) {
921 /* For USB2.0 HS hubs only */
922 case MUSB_HDRC_TXHUBADDR:
923 return s->ep[ep].haddr[0];
924 case MUSB_HDRC_TXHUBPORT:
925 return s->ep[ep].hport[0];
926 case MUSB_HDRC_RXHUBADDR:
927 return s->ep[ep].haddr[1];
928 case MUSB_HDRC_RXHUBPORT:
929 return s->ep[ep].hport[1];
930
931 default:
932 TRACE("unknown register 0x%02x", addr);
933 return 0x00;
934 };
935 }
936
937 static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
938 {
939 MUSBState *s = (MUSBState *) opaque;
940
941 switch (addr) {
942 case MUSB_HDRC_TXFUNCADDR:
943 s->ep[ep].faddr[0] = value;
944 break;
945 case MUSB_HDRC_RXFUNCADDR:
946 s->ep[ep].faddr[1] = value;
947 break;
948 case MUSB_HDRC_TXHUBADDR:
949 s->ep[ep].haddr[0] = value;
950 break;
951 case MUSB_HDRC_TXHUBPORT:
952 s->ep[ep].hport[0] = value;
953 break;
954 case MUSB_HDRC_RXHUBADDR:
955 s->ep[ep].haddr[1] = value;
956 break;
957 case MUSB_HDRC_RXHUBPORT:
958 s->ep[ep].hport[1] = value;
959 break;
960
961 default:
962 TRACE("unknown register 0x%02x", addr);
963 break;
964 };
965 }
966
967 static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
968 {
969 MUSBState *s = (MUSBState *) opaque;
970
971 switch (addr) {
972 case MUSB_HDRC_TXFUNCADDR:
973 return s->ep[ep].faddr[0];
974 case MUSB_HDRC_RXFUNCADDR:
975 return s->ep[ep].faddr[1];
976
977 default:
978 return musb_busctl_readb(s, ep, addr) |
979 (musb_busctl_readb(s, ep, addr | 1) << 8);
980 };
981 }
982
983 static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
984 {
985 MUSBState *s = (MUSBState *) opaque;
986
987 switch (addr) {
988 case MUSB_HDRC_TXFUNCADDR:
989 s->ep[ep].faddr[0] = value;
990 break;
991 case MUSB_HDRC_RXFUNCADDR:
992 s->ep[ep].faddr[1] = value;
993 break;
994
995 default:
996 musb_busctl_writeb(s, ep, addr, value & 0xff);
997 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
998 };
999 }
1000
1001 /* Endpoint control */
1002 static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1003 {
1004 MUSBState *s = (MUSBState *) opaque;
1005
1006 switch (addr) {
1007 case MUSB_HDRC_TXTYPE:
1008 return s->ep[ep].type[0];
1009 case MUSB_HDRC_TXINTERVAL:
1010 return s->ep[ep].interval[0];
1011 case MUSB_HDRC_RXTYPE:
1012 return s->ep[ep].type[1];
1013 case MUSB_HDRC_RXINTERVAL:
1014 return s->ep[ep].interval[1];
1015 case (MUSB_HDRC_FIFOSIZE & ~1):
1016 return 0x00;
1017 case MUSB_HDRC_FIFOSIZE:
1018 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
1019 case MUSB_HDRC_RXCOUNT:
1020 return s->ep[ep].rxcount;
1021
1022 default:
1023 TRACE("unknown register 0x%02x", addr);
1024 return 0x00;
1025 };
1026 }
1027
1028 static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1029 {
1030 MUSBState *s = (MUSBState *) opaque;
1031
1032 switch (addr) {
1033 case MUSB_HDRC_TXTYPE:
1034 s->ep[ep].type[0] = value;
1035 break;
1036 case MUSB_HDRC_TXINTERVAL:
1037 s->ep[ep].interval[0] = value;
1038 musb_ep_frame_cancel(&s->ep[ep], 0);
1039 break;
1040 case MUSB_HDRC_RXTYPE:
1041 s->ep[ep].type[1] = value;
1042 break;
1043 case MUSB_HDRC_RXINTERVAL:
1044 s->ep[ep].interval[1] = value;
1045 musb_ep_frame_cancel(&s->ep[ep], 1);
1046 break;
1047 case (MUSB_HDRC_FIFOSIZE & ~1):
1048 break;
1049 case MUSB_HDRC_FIFOSIZE:
1050 TRACE("somebody messes with fifosize (now %i bytes)", value);
1051 s->ep[ep].fifosize = value;
1052 break;
1053 default:
1054 TRACE("unknown register 0x%02x", addr);
1055 break;
1056 };
1057 }
1058
1059 static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1060 {
1061 MUSBState *s = (MUSBState *) opaque;
1062 uint16_t ret;
1063
1064 switch (addr) {
1065 case MUSB_HDRC_TXMAXP:
1066 return s->ep[ep].maxp[0];
1067 case MUSB_HDRC_TXCSR:
1068 return s->ep[ep].csr[0];
1069 case MUSB_HDRC_RXMAXP:
1070 return s->ep[ep].maxp[1];
1071 case MUSB_HDRC_RXCSR:
1072 ret = s->ep[ep].csr[1];
1073
1074 /* TODO: This and other bits probably depend on
1075 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1076 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1077 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1078
1079 return ret;
1080 case MUSB_HDRC_RXCOUNT:
1081 return s->ep[ep].rxcount;
1082
1083 default:
1084 return musb_ep_readb(s, ep, addr) |
1085 (musb_ep_readb(s, ep, addr | 1) << 8);
1086 };
1087 }
1088
1089 static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1090 {
1091 MUSBState *s = (MUSBState *) opaque;
1092
1093 switch (addr) {
1094 case MUSB_HDRC_TXMAXP:
1095 s->ep[ep].maxp[0] = value;
1096 break;
1097 case MUSB_HDRC_TXCSR:
1098 if (ep) {
1099 s->ep[ep].csr[0] &= value & 0xa6;
1100 s->ep[ep].csr[0] |= value & 0xff59;
1101 } else {
1102 s->ep[ep].csr[0] &= value & 0x85;
1103 s->ep[ep].csr[0] |= value & 0xf7a;
1104 }
1105
1106 musb_ep_frame_cancel(&s->ep[ep], 0);
1107
1108 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1109 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1110 s->ep[ep].fifolen[0] = 0;
1111 s->ep[ep].fifostart[0] = 0;
1112 if (ep)
1113 s->ep[ep].csr[0] &=
1114 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1115 else
1116 s->ep[ep].csr[0] &=
1117 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1118 }
1119 if (
1120 (ep &&
1121 #ifdef CLEAR_NAK
1122 (value & MGC_M_TXCSR_TXPKTRDY) &&
1123 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1124 #else
1125 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1126 #endif
1127 (!ep &&
1128 #ifdef CLEAR_NAK
1129 (value & MGC_M_CSR0_TXPKTRDY) &&
1130 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1131 #else
1132 (value & MGC_M_CSR0_TXPKTRDY)))
1133 #endif
1134 musb_tx_rdy(s, ep);
1135 if (!ep &&
1136 (value & MGC_M_CSR0_H_REQPKT) &&
1137 #ifdef CLEAR_NAK
1138 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1139 MGC_M_CSR0_RXPKTRDY)))
1140 #else
1141 !(value & MGC_M_CSR0_RXPKTRDY))
1142 #endif
1143 musb_rx_req(s, ep);
1144 break;
1145
1146 case MUSB_HDRC_RXMAXP:
1147 s->ep[ep].maxp[1] = value;
1148 break;
1149 case MUSB_HDRC_RXCSR:
1150 /* (DMA mode only) */
1151 if (
1152 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1153 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1154 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1155 value |= MGC_M_RXCSR_H_REQPKT;
1156
1157 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1158 s->ep[ep].csr[1] |= value & 0xfeb0;
1159
1160 musb_ep_frame_cancel(&s->ep[ep], 1);
1161
1162 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1163 s->ep[ep].fifolen[1] = 0;
1164 s->ep[ep].fifostart[1] = 0;
1165 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1166 /* If double buffering and we have two packets ready, flush
1167 * only the first one and set up the fifo at the second packet. */
1168 }
1169 #ifdef CLEAR_NAK
1170 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1171 #else
1172 if (value & MGC_M_RXCSR_H_REQPKT)
1173 #endif
1174 musb_rx_req(s, ep);
1175 break;
1176 case MUSB_HDRC_RXCOUNT:
1177 s->ep[ep].rxcount = value;
1178 break;
1179
1180 default:
1181 musb_ep_writeb(s, ep, addr, value & 0xff);
1182 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1183 };
1184 }
1185
1186 /* Generic control */
1187 static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
1188 {
1189 MUSBState *s = (MUSBState *) opaque;
1190 int ep, i;
1191 uint8_t ret;
1192
1193 switch (addr) {
1194 case MUSB_HDRC_FADDR:
1195 return s->faddr;
1196 case MUSB_HDRC_POWER:
1197 return s->power;
1198 case MUSB_HDRC_INTRUSB:
1199 ret = s->intr;
1200 for (i = 0; i < sizeof(ret) * 8; i ++)
1201 if (ret & (1 << i))
1202 musb_intr_set(s, i, 0);
1203 return ret;
1204 case MUSB_HDRC_INTRUSBE:
1205 return s->mask;
1206 case MUSB_HDRC_INDEX:
1207 return s->idx;
1208 case MUSB_HDRC_TESTMODE:
1209 return 0x00;
1210
1211 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1212 return musb_ep_readb(s, s->idx, addr & 0xf);
1213
1214 case MUSB_HDRC_DEVCTL:
1215 return s->devctl;
1216
1217 case MUSB_HDRC_TXFIFOSZ:
1218 case MUSB_HDRC_RXFIFOSZ:
1219 case MUSB_HDRC_VCTRL:
1220 /* TODO */
1221 return 0x00;
1222
1223 case MUSB_HDRC_HWVERS:
1224 return (1 << 10) | 400;
1225
1226 case (MUSB_HDRC_VCTRL | 1):
1227 case (MUSB_HDRC_HWVERS | 1):
1228 case (MUSB_HDRC_DEVCTL | 1):
1229 return 0x00;
1230
1231 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1232 ep = (addr >> 3) & 0xf;
1233 return musb_busctl_readb(s, ep, addr & 0x7);
1234
1235 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1236 ep = (addr >> 4) & 0xf;
1237 return musb_ep_readb(s, ep, addr & 0xf);
1238
1239 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1240 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1241 return musb_read_fifo(s->ep + ep);
1242
1243 default:
1244 TRACE("unknown register 0x%02x", (int) addr);
1245 return 0x00;
1246 };
1247 }
1248
1249 static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1250 {
1251 MUSBState *s = (MUSBState *) opaque;
1252 int ep;
1253
1254 switch (addr) {
1255 case MUSB_HDRC_FADDR:
1256 s->faddr = value & 0x7f;
1257 break;
1258 case MUSB_HDRC_POWER:
1259 s->power = (value & 0xef) | (s->power & 0x10);
1260 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1261 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1262 usb_send_msg(s->port.dev, USB_MSG_RESET);
1263 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1264 if ((value & MGC_M_POWER_HSENAB) &&
1265 s->port.dev->speed == USB_SPEED_HIGH)
1266 s->power |= MGC_M_POWER_HSMODE; /* Success */
1267 /* Restart frame counting. */
1268 }
1269 if (value & MGC_M_POWER_SUSPENDM) {
1270 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1271 * is set, also go into low power mode. Frame counting stops. */
1272 /* XXX: Cleared when the interrupt register is read */
1273 }
1274 if (value & MGC_M_POWER_RESUME) {
1275 /* Wait 20ms and signal resuming on the bus. Frame counting
1276 * restarts. */
1277 }
1278 break;
1279 case MUSB_HDRC_INTRUSB:
1280 break;
1281 case MUSB_HDRC_INTRUSBE:
1282 s->mask = value & 0xff;
1283 break;
1284 case MUSB_HDRC_INDEX:
1285 s->idx = value & 0xf;
1286 break;
1287 case MUSB_HDRC_TESTMODE:
1288 break;
1289
1290 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1291 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1292 break;
1293
1294 case MUSB_HDRC_DEVCTL:
1295 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1296 musb_session_update(s,
1297 !!s->port.dev,
1298 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1299
1300 /* It seems this is the only R/W bit in this register? */
1301 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1302 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1303 break;
1304
1305 case MUSB_HDRC_TXFIFOSZ:
1306 case MUSB_HDRC_RXFIFOSZ:
1307 case MUSB_HDRC_VCTRL:
1308 /* TODO */
1309 break;
1310
1311 case (MUSB_HDRC_VCTRL | 1):
1312 case (MUSB_HDRC_DEVCTL | 1):
1313 break;
1314
1315 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1316 ep = (addr >> 3) & 0xf;
1317 musb_busctl_writeb(s, ep, addr & 0x7, value);
1318 break;
1319
1320 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1321 ep = (addr >> 4) & 0xf;
1322 musb_ep_writeb(s, ep, addr & 0xf, value);
1323 break;
1324
1325 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1326 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1327 musb_write_fifo(s->ep + ep, value & 0xff);
1328 break;
1329
1330 default:
1331 TRACE("unknown register 0x%02x", (int) addr);
1332 break;
1333 };
1334 }
1335
1336 static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
1337 {
1338 MUSBState *s = (MUSBState *) opaque;
1339 int ep, i;
1340 uint16_t ret;
1341
1342 switch (addr) {
1343 case MUSB_HDRC_INTRTX:
1344 ret = s->tx_intr;
1345 /* Auto clear */
1346 for (i = 0; i < sizeof(ret) * 8; i ++)
1347 if (ret & (1 << i))
1348 musb_tx_intr_set(s, i, 0);
1349 return ret;
1350 case MUSB_HDRC_INTRRX:
1351 ret = s->rx_intr;
1352 /* Auto clear */
1353 for (i = 0; i < sizeof(ret) * 8; i ++)
1354 if (ret & (1 << i))
1355 musb_rx_intr_set(s, i, 0);
1356 return ret;
1357 case MUSB_HDRC_INTRTXE:
1358 return s->tx_mask;
1359 case MUSB_HDRC_INTRRXE:
1360 return s->rx_mask;
1361
1362 case MUSB_HDRC_FRAME:
1363 /* TODO */
1364 return 0x0000;
1365 case MUSB_HDRC_TXFIFOADDR:
1366 return s->ep[s->idx].fifoaddr[0];
1367 case MUSB_HDRC_RXFIFOADDR:
1368 return s->ep[s->idx].fifoaddr[1];
1369
1370 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1371 return musb_ep_readh(s, s->idx, addr & 0xf);
1372
1373 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1374 ep = (addr >> 3) & 0xf;
1375 return musb_busctl_readh(s, ep, addr & 0x7);
1376
1377 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1378 ep = (addr >> 4) & 0xf;
1379 return musb_ep_readh(s, ep, addr & 0xf);
1380
1381 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1382 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1383 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1384
1385 default:
1386 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1387 };
1388 }
1389
1390 static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1391 {
1392 MUSBState *s = (MUSBState *) opaque;
1393 int ep;
1394
1395 switch (addr) {
1396 case MUSB_HDRC_INTRTXE:
1397 s->tx_mask = value;
1398 /* XXX: the masks seem to apply on the raising edge like with
1399 * edge-triggered interrupts, thus no need to update. I may be
1400 * wrong though. */
1401 break;
1402 case MUSB_HDRC_INTRRXE:
1403 s->rx_mask = value;
1404 break;
1405
1406 case MUSB_HDRC_FRAME:
1407 /* TODO */
1408 break;
1409 case MUSB_HDRC_TXFIFOADDR:
1410 s->ep[s->idx].fifoaddr[0] = value;
1411 s->ep[s->idx].buf[0] =
1412 s->buf + ((value << 3) & 0x7ff );
1413 break;
1414 case MUSB_HDRC_RXFIFOADDR:
1415 s->ep[s->idx].fifoaddr[1] = value;
1416 s->ep[s->idx].buf[1] =
1417 s->buf + ((value << 3) & 0x7ff);
1418 break;
1419
1420 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1421 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1422 break;
1423
1424 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1425 ep = (addr >> 3) & 0xf;
1426 musb_busctl_writeh(s, ep, addr & 0x7, value);
1427 break;
1428
1429 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1430 ep = (addr >> 4) & 0xf;
1431 musb_ep_writeh(s, ep, addr & 0xf, value);
1432 break;
1433
1434 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1435 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1436 musb_write_fifo(s->ep + ep, value & 0xff);
1437 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1438 break;
1439
1440 default:
1441 musb_writeb(s, addr, value & 0xff);
1442 musb_writeb(s, addr | 1, value >> 8);
1443 };
1444 }
1445
1446 static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
1447 {
1448 MUSBState *s = (MUSBState *) opaque;
1449 int ep;
1450
1451 switch (addr) {
1452 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1453 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1454 return ( musb_read_fifo(s->ep + ep) |
1455 musb_read_fifo(s->ep + ep) << 8 |
1456 musb_read_fifo(s->ep + ep) << 16 |
1457 musb_read_fifo(s->ep + ep) << 24 );
1458 default:
1459 TRACE("unknown register 0x%02x", (int) addr);
1460 return 0x00000000;
1461 };
1462 }
1463
1464 static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1465 {
1466 MUSBState *s = (MUSBState *) opaque;
1467 int ep;
1468
1469 switch (addr) {
1470 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1471 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1472 musb_write_fifo(s->ep + ep, value & 0xff);
1473 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1474 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1475 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
1476 break;
1477 default:
1478 TRACE("unknown register 0x%02x", (int) addr);
1479 break;
1480 };
1481 }
1482
1483 CPUReadMemoryFunc * const musb_read[] = {
1484 musb_readb,
1485 musb_readh,
1486 musb_readw,
1487 };
1488
1489 CPUWriteMemoryFunc * const musb_write[] = {
1490 musb_writeb,
1491 musb_writeh,
1492 musb_writew,
1493 };
Qemu copy for testing