2 * QEMU VMware-SVGA "chipset".
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
33 #define HW_MOUSE_ACCEL
39 struct vmsvga_state_s
{
63 target_phys_addr_t vram_base
;
80 struct __attribute__((__packed__
)) {
85 /* Add registers here when adding capabilities. */
90 #define REDRAW_FIFO_LEN 512
91 struct vmsvga_rect_s
{
93 } redraw_fifo
[REDRAW_FIFO_LEN
];
94 int redraw_fifo_first
, redraw_fifo_last
;
97 struct pci_vmsvga_state_s
{
99 struct vmsvga_state_s chip
;
102 #define SVGA_MAGIC 0x900000UL
103 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
104 #define SVGA_ID_0 SVGA_MAKE_ID(0)
105 #define SVGA_ID_1 SVGA_MAKE_ID(1)
106 #define SVGA_ID_2 SVGA_MAKE_ID(2)
108 #define SVGA_LEGACY_BASE_PORT 0x4560
109 #define SVGA_INDEX_PORT 0x0
110 #define SVGA_VALUE_PORT 0x1
111 #define SVGA_BIOS_PORT 0x2
113 #define SVGA_VERSION_2
115 #ifdef SVGA_VERSION_2
116 # define SVGA_ID SVGA_ID_2
117 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
118 # define SVGA_IO_MUL 1
119 # define SVGA_FIFO_SIZE 0x10000
120 # define SVGA_MEM_BASE 0xe0000000
121 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
123 # define SVGA_ID SVGA_ID_1
124 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
125 # define SVGA_IO_MUL 4
126 # define SVGA_FIFO_SIZE 0x10000
127 # define SVGA_MEM_BASE 0xe0000000
128 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
132 /* ID 0, 1 and 2 registers */
137 SVGA_REG_MAX_WIDTH
= 4,
138 SVGA_REG_MAX_HEIGHT
= 5,
140 SVGA_REG_BITS_PER_PIXEL
= 7, /* Current bpp in the guest */
141 SVGA_REG_PSEUDOCOLOR
= 8,
142 SVGA_REG_RED_MASK
= 9,
143 SVGA_REG_GREEN_MASK
= 10,
144 SVGA_REG_BLUE_MASK
= 11,
145 SVGA_REG_BYTES_PER_LINE
= 12,
146 SVGA_REG_FB_START
= 13,
147 SVGA_REG_FB_OFFSET
= 14,
148 SVGA_REG_VRAM_SIZE
= 15,
149 SVGA_REG_FB_SIZE
= 16,
151 /* ID 1 and 2 registers */
152 SVGA_REG_CAPABILITIES
= 17,
153 SVGA_REG_MEM_START
= 18, /* Memory for command FIFO */
154 SVGA_REG_MEM_SIZE
= 19,
155 SVGA_REG_CONFIG_DONE
= 20, /* Set when memory area configured */
156 SVGA_REG_SYNC
= 21, /* Write to force synchronization */
157 SVGA_REG_BUSY
= 22, /* Read to check if sync is done */
158 SVGA_REG_GUEST_ID
= 23, /* Set guest OS identifier */
159 SVGA_REG_CURSOR_ID
= 24, /* ID of cursor */
160 SVGA_REG_CURSOR_X
= 25, /* Set cursor X position */
161 SVGA_REG_CURSOR_Y
= 26, /* Set cursor Y position */
162 SVGA_REG_CURSOR_ON
= 27, /* Turn cursor on/off */
163 SVGA_REG_HOST_BITS_PER_PIXEL
= 28, /* Current bpp in the host */
164 SVGA_REG_SCRATCH_SIZE
= 29, /* Number of scratch registers */
165 SVGA_REG_MEM_REGS
= 30, /* Number of FIFO registers */
166 SVGA_REG_NUM_DISPLAYS
= 31, /* Number of guest displays */
167 SVGA_REG_PITCHLOCK
= 32, /* Fixed pitch for all modes */
169 SVGA_PALETTE_BASE
= 1024, /* Base of SVGA color map */
170 SVGA_PALETTE_END
= SVGA_PALETTE_BASE
+ 767,
171 SVGA_SCRATCH_BASE
= SVGA_PALETTE_BASE
+ 768,
174 #define SVGA_CAP_NONE 0
175 #define SVGA_CAP_RECT_FILL (1 << 0)
176 #define SVGA_CAP_RECT_COPY (1 << 1)
177 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
178 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
179 #define SVGA_CAP_RASTER_OP (1 << 4)
180 #define SVGA_CAP_CURSOR (1 << 5)
181 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
182 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
183 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
184 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
185 #define SVGA_CAP_GLYPH (1 << 10)
186 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
187 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
188 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
189 #define SVGA_CAP_3D (1 << 14)
190 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
191 #define SVGA_CAP_MULTIMON (1 << 16)
192 #define SVGA_CAP_PITCHLOCK (1 << 17)
195 * FIFO offsets (seen as an array of 32-bit words)
199 * The original defined FIFO offsets
202 SVGA_FIFO_MAX
, /* The distance from MIN to MAX must be at least 10K */
207 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
209 SVGA_FIFO_CAPABILITIES
= 4,
212 SVGA_FIFO_3D_HWVERSION
,
216 #define SVGA_FIFO_CAP_NONE 0
217 #define SVGA_FIFO_CAP_FENCE (1 << 0)
218 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
219 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
221 #define SVGA_FIFO_FLAG_NONE 0
222 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
224 /* These values can probably be changed arbitrarily. */
225 #define SVGA_SCRATCH_SIZE 0x8000
226 #define SVGA_MAX_WIDTH 2360
227 #define SVGA_MAX_HEIGHT 1770
230 # define GUEST_OS_BASE 0x5001
231 static const char *vmsvga_guest_id
[] = {
232 [0x00 ... 0x15] = "an unknown OS",
234 [0x01] = "Windows 3.1",
235 [0x02] = "Windows 95",
236 [0x03] = "Windows 98",
237 [0x04] = "Windows ME",
238 [0x05] = "Windows NT",
239 [0x06] = "Windows 2000",
244 [0x15] = "Windows 2003",
249 SVGA_CMD_INVALID_CMD
= 0,
251 SVGA_CMD_RECT_FILL
= 2,
252 SVGA_CMD_RECT_COPY
= 3,
253 SVGA_CMD_DEFINE_BITMAP
= 4,
254 SVGA_CMD_DEFINE_BITMAP_SCANLINE
= 5,
255 SVGA_CMD_DEFINE_PIXMAP
= 6,
256 SVGA_CMD_DEFINE_PIXMAP_SCANLINE
= 7,
257 SVGA_CMD_RECT_BITMAP_FILL
= 8,
258 SVGA_CMD_RECT_PIXMAP_FILL
= 9,
259 SVGA_CMD_RECT_BITMAP_COPY
= 10,
260 SVGA_CMD_RECT_PIXMAP_COPY
= 11,
261 SVGA_CMD_FREE_OBJECT
= 12,
262 SVGA_CMD_RECT_ROP_FILL
= 13,
263 SVGA_CMD_RECT_ROP_COPY
= 14,
264 SVGA_CMD_RECT_ROP_BITMAP_FILL
= 15,
265 SVGA_CMD_RECT_ROP_PIXMAP_FILL
= 16,
266 SVGA_CMD_RECT_ROP_BITMAP_COPY
= 17,
267 SVGA_CMD_RECT_ROP_PIXMAP_COPY
= 18,
268 SVGA_CMD_DEFINE_CURSOR
= 19,
269 SVGA_CMD_DISPLAY_CURSOR
= 20,
270 SVGA_CMD_MOVE_CURSOR
= 21,
271 SVGA_CMD_DEFINE_ALPHA_CURSOR
= 22,
272 SVGA_CMD_DRAW_GLYPH
= 23,
273 SVGA_CMD_DRAW_GLYPH_CLIPPED
= 24,
274 SVGA_CMD_UPDATE_VERBOSE
= 25,
275 SVGA_CMD_SURFACE_FILL
= 26,
276 SVGA_CMD_SURFACE_COPY
= 27,
277 SVGA_CMD_SURFACE_ALPHA_BLEND
= 28,
278 SVGA_CMD_FRONT_ROP_FILL
= 29,
282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
284 SVGA_CURSOR_ON_HIDE
= 0,
285 SVGA_CURSOR_ON_SHOW
= 1,
286 SVGA_CURSOR_ON_REMOVE_FROM_FB
= 2,
287 SVGA_CURSOR_ON_RESTORE_TO_FB
= 3,
290 static inline void vmsvga_update_rect(struct vmsvga_state_s
*s
,
291 int x
, int y
, int w
, int h
)
301 if (x
+ w
> s
->width
) {
302 fprintf(stderr
, "%s: update width too large x: %d, w: %d\n",
304 x
= MIN(x
, s
->width
);
308 if (y
+ h
> s
->height
) {
309 fprintf(stderr
, "%s: update height too large y: %d, h: %d\n",
311 y
= MIN(y
, s
->height
);
316 bypl
= s
->bypp
* s
->width
;
318 start
= s
->bypp
* x
+ bypl
* y
;
319 src
= s
->vram
+ start
;
320 dst
= s
->ds
->data
+ start
;
322 for (; line
> 0; line
--, src
+= bypl
, dst
+= bypl
)
323 memcpy(dst
, src
, width
);
326 dpy_update(s
->ds
, x
, y
, w
, h
);
329 static inline void vmsvga_update_screen(struct vmsvga_state_s
*s
)
332 memcpy(s
->ds
->data
, s
->vram
, s
->bypp
* s
->width
* s
->height
);
335 dpy_update(s
->ds
, 0, 0, s
->width
, s
->height
);
339 # define vmsvga_update_rect_delayed vmsvga_update_rect
341 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s
*s
,
342 int x
, int y
, int w
, int h
)
344 struct vmsvga_rect_s
*rect
= &s
->redraw_fifo
[s
->redraw_fifo_last
++];
345 s
->redraw_fifo_last
&= REDRAW_FIFO_LEN
- 1;
353 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s
*s
)
355 struct vmsvga_rect_s
*rect
;
356 if (s
->invalidated
) {
357 s
->redraw_fifo_first
= s
->redraw_fifo_last
;
360 /* Overlapping region updates can be optimised out here - if someone
361 * knows a smart algorithm to do that, please share. */
362 while (s
->redraw_fifo_first
!= s
->redraw_fifo_last
) {
363 rect
= &s
->redraw_fifo
[s
->redraw_fifo_first
++];
364 s
->redraw_fifo_first
&= REDRAW_FIFO_LEN
- 1;
365 vmsvga_update_rect(s
, rect
->x
, rect
->y
, rect
->w
, rect
->h
);
370 static inline void vmsvga_copy_rect(struct vmsvga_state_s
*s
,
371 int x0
, int y0
, int x1
, int y1
, int w
, int h
)
374 uint8_t *vram
= s
->ds
->data
;
376 uint8_t *vram
= s
->vram
;
378 int bypl
= s
->bypp
* s
->width
;
379 int width
= s
->bypp
* w
;
385 s
->ds
->dpy_copy(s
->ds
, x0
, y0
, x1
, y1
, w
, h
);
390 ptr
[0] = vram
+ s
->bypp
* x0
+ bypl
* (y0
+ h
- 1);
391 ptr
[1] = vram
+ s
->bypp
* x1
+ bypl
* (y1
+ h
- 1);
392 for (; line
> 0; line
--, ptr
[0] -= bypl
, ptr
[1] -= bypl
)
393 memmove(ptr
[1], ptr
[0], width
);
395 ptr
[0] = vram
+ s
->bypp
* x0
+ bypl
* y0
;
396 ptr
[1] = vram
+ s
->bypp
* x1
+ bypl
* y1
;
397 for (; line
> 0; line
--, ptr
[0] += bypl
, ptr
[1] += bypl
)
398 memmove(ptr
[1], ptr
[0], width
);
402 vmsvga_update_rect_delayed(s
, x1
, y1
, w
, h
);
407 static inline void vmsvga_fill_rect(struct vmsvga_state_s
*s
,
408 uint32_t c
, int x
, int y
, int w
, int h
)
411 uint8_t *vram
= s
->ds
->data
;
413 uint8_t *vram
= s
->vram
;
416 int bypl
= bypp
* s
->width
;
417 int width
= bypp
* w
;
420 uint8_t *fst
= vram
+ bypp
* x
+ bypl
* y
;
427 s
->ds
->dpy_fill(s
->ds
, x
, y
, w
, h
, c
);
439 for (column
= width
; column
> 0; column
--) {
440 *(dst
++) = *(src
++);
441 if (src
- col
== bypp
)
445 for (; line
> 0; line
--) {
447 memcpy(dst
, fst
, width
);
452 vmsvga_update_rect_delayed(s
, x
, y
, w
, h
);
456 struct vmsvga_cursor_definition_s
{
464 uint32_t image
[1024];
467 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
468 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
470 #ifdef HW_MOUSE_ACCEL
471 static inline void vmsvga_cursor_define(struct vmsvga_state_s
*s
,
472 struct vmsvga_cursor_definition_s
*c
)
475 for (i
= SVGA_BITMAP_SIZE(c
->width
, c
->height
) - 1; i
>= 0; i
--)
476 c
->mask
[i
] = ~c
->mask
[i
];
478 if (s
->ds
->cursor_define
)
479 s
->ds
->cursor_define(c
->width
, c
->height
, c
->bpp
, c
->hot_x
, c
->hot_y
,
480 (uint8_t *) c
->image
, (uint8_t *) c
->mask
);
484 static inline int vmsvga_fifo_empty(struct vmsvga_state_s
*s
)
486 if (!s
->config
|| !s
->enable
)
488 return (s
->cmd
->next_cmd
== s
->cmd
->stop
);
491 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s
*s
)
493 uint32_t cmd
= s
->fifo
[s
->cmd
->stop
>> 2];
495 if (s
->cmd
->stop
>= s
->cmd
->max
)
496 s
->cmd
->stop
= s
->cmd
->min
;
500 static void vmsvga_fifo_run(struct vmsvga_state_s
*s
)
502 uint32_t cmd
, colour
;
504 int x
, y
, dx
, dy
, width
, height
;
505 struct vmsvga_cursor_definition_s cursor
;
506 while (!vmsvga_fifo_empty(s
))
507 switch (cmd
= vmsvga_fifo_read(s
)) {
508 case SVGA_CMD_UPDATE
:
509 case SVGA_CMD_UPDATE_VERBOSE
:
510 x
= vmsvga_fifo_read(s
);
511 y
= vmsvga_fifo_read(s
);
512 width
= vmsvga_fifo_read(s
);
513 height
= vmsvga_fifo_read(s
);
514 vmsvga_update_rect_delayed(s
, x
, y
, width
, height
);
517 case SVGA_CMD_RECT_FILL
:
518 colour
= vmsvga_fifo_read(s
);
519 x
= vmsvga_fifo_read(s
);
520 y
= vmsvga_fifo_read(s
);
521 width
= vmsvga_fifo_read(s
);
522 height
= vmsvga_fifo_read(s
);
524 vmsvga_fill_rect(s
, colour
, x
, y
, width
, height
);
530 case SVGA_CMD_RECT_COPY
:
531 x
= vmsvga_fifo_read(s
);
532 y
= vmsvga_fifo_read(s
);
533 dx
= vmsvga_fifo_read(s
);
534 dy
= vmsvga_fifo_read(s
);
535 width
= vmsvga_fifo_read(s
);
536 height
= vmsvga_fifo_read(s
);
538 vmsvga_copy_rect(s
, x
, y
, dx
, dy
, width
, height
);
544 case SVGA_CMD_DEFINE_CURSOR
:
545 cursor
.id
= vmsvga_fifo_read(s
);
546 cursor
.hot_x
= vmsvga_fifo_read(s
);
547 cursor
.hot_y
= vmsvga_fifo_read(s
);
548 cursor
.width
= x
= vmsvga_fifo_read(s
);
549 cursor
.height
= y
= vmsvga_fifo_read(s
);
551 cursor
.bpp
= vmsvga_fifo_read(s
);
552 for (args
= 0; args
< SVGA_BITMAP_SIZE(x
, y
); args
++)
553 cursor
.mask
[args
] = vmsvga_fifo_read(s
);
554 for (args
= 0; args
< SVGA_PIXMAP_SIZE(x
, y
, cursor
.bpp
); args
++)
555 cursor
.image
[args
] = vmsvga_fifo_read(s
);
556 #ifdef HW_MOUSE_ACCEL
557 vmsvga_cursor_define(s
, &cursor
);
565 * Other commands that we at least know the number of arguments
566 * for so we can avoid FIFO desync if driver uses them illegally.
568 case SVGA_CMD_DEFINE_ALPHA_CURSOR
:
572 x
= vmsvga_fifo_read(s
);
573 y
= vmsvga_fifo_read(s
);
576 case SVGA_CMD_RECT_ROP_FILL
:
579 case SVGA_CMD_RECT_ROP_COPY
:
582 case SVGA_CMD_DRAW_GLYPH_CLIPPED
:
585 args
= 7 + (vmsvga_fifo_read(s
) >> 2);
587 case SVGA_CMD_SURFACE_ALPHA_BLEND
:
592 * Other commands that are not listed as depending on any
593 * CAPABILITIES bits, but are not described in the README either.
595 case SVGA_CMD_SURFACE_FILL
:
596 case SVGA_CMD_SURFACE_COPY
:
597 case SVGA_CMD_FRONT_ROP_FILL
:
599 case SVGA_CMD_INVALID_CMD
:
606 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
614 static uint32_t vmsvga_index_read(void *opaque
, uint32_t address
)
616 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
620 static void vmsvga_index_write(void *opaque
, uint32_t address
, uint32_t index
)
622 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
626 static uint32_t vmsvga_value_read(void *opaque
, uint32_t address
)
629 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
634 case SVGA_REG_ENABLE
:
640 case SVGA_REG_HEIGHT
:
643 case SVGA_REG_MAX_WIDTH
:
644 return SVGA_MAX_WIDTH
;
646 case SVGA_REG_MAX_HEIGHT
:
647 return SVGA_MAX_HEIGHT
;
652 case SVGA_REG_BITS_PER_PIXEL
:
653 return (s
->depth
+ 7) & ~7;
655 case SVGA_REG_PSEUDOCOLOR
:
658 case SVGA_REG_RED_MASK
:
660 case SVGA_REG_GREEN_MASK
:
662 case SVGA_REG_BLUE_MASK
:
665 case SVGA_REG_BYTES_PER_LINE
:
666 return ((s
->depth
+ 7) >> 3) * s
->new_width
;
668 case SVGA_REG_FB_START
:
671 case SVGA_REG_FB_OFFSET
:
674 case SVGA_REG_VRAM_SIZE
:
675 return s
->vram_size
- SVGA_FIFO_SIZE
;
677 case SVGA_REG_FB_SIZE
:
680 case SVGA_REG_CAPABILITIES
:
681 caps
= SVGA_CAP_NONE
;
683 caps
|= SVGA_CAP_RECT_COPY
;
686 caps
|= SVGA_CAP_RECT_FILL
;
688 #ifdef HW_MOUSE_ACCEL
689 if (s
->ds
->mouse_set
)
690 caps
|= SVGA_CAP_CURSOR
| SVGA_CAP_CURSOR_BYPASS_2
|
691 SVGA_CAP_CURSOR_BYPASS
;
695 case SVGA_REG_MEM_START
:
696 return s
->vram_base
+ s
->vram_size
- SVGA_FIFO_SIZE
;
698 case SVGA_REG_MEM_SIZE
:
699 return SVGA_FIFO_SIZE
;
701 case SVGA_REG_CONFIG_DONE
:
708 case SVGA_REG_GUEST_ID
:
711 case SVGA_REG_CURSOR_ID
:
714 case SVGA_REG_CURSOR_X
:
717 case SVGA_REG_CURSOR_Y
:
720 case SVGA_REG_CURSOR_ON
:
723 case SVGA_REG_HOST_BITS_PER_PIXEL
:
724 return (s
->depth
+ 7) & ~7;
726 case SVGA_REG_SCRATCH_SIZE
:
727 return s
->scratch_size
;
729 case SVGA_REG_MEM_REGS
:
730 case SVGA_REG_NUM_DISPLAYS
:
731 case SVGA_REG_PITCHLOCK
:
732 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
736 if (s
->index
>= SVGA_SCRATCH_BASE
&&
737 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
)
738 return s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
];
739 printf("%s: Bad register %02x\n", __FUNCTION__
, s
->index
);
745 static void vmsvga_value_write(void *opaque
, uint32_t address
, uint32_t value
)
747 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
750 if (value
== SVGA_ID_2
|| value
== SVGA_ID_1
|| value
== SVGA_ID_0
)
754 case SVGA_REG_ENABLE
:
756 s
->config
&= !!value
;
761 s
->invalidate(opaque
);
764 s
->fb_size
= ((s
->depth
+ 7) >> 3) * s
->new_width
* s
->new_height
;
768 s
->new_width
= value
;
772 case SVGA_REG_HEIGHT
:
773 s
->new_height
= value
;
778 case SVGA_REG_BITS_PER_PIXEL
:
779 if (value
!= s
->depth
) {
780 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__
, value
);
785 case SVGA_REG_CONFIG_DONE
:
787 s
->fifo
= (uint32_t *) &s
->vram
[s
->vram_size
- SVGA_FIFO_SIZE
];
788 /* Check range and alignment. */
789 if ((s
->cmd
->min
| s
->cmd
->max
|
790 s
->cmd
->next_cmd
| s
->cmd
->stop
) & 3)
792 if (s
->cmd
->min
< (uint8_t *) s
->cmd
->fifo
- (uint8_t *) s
->fifo
)
794 if (s
->cmd
->max
> SVGA_FIFO_SIZE
)
796 if (s
->cmd
->max
< s
->cmd
->min
+ 10 * 1024)
804 vmsvga_fifo_run(s
); /* Or should we just wait for update_display? */
807 case SVGA_REG_GUEST_ID
:
810 if (value
>= GUEST_OS_BASE
&& value
< GUEST_OS_BASE
+
811 sizeof(vmsvga_guest_id
) / sizeof(*vmsvga_guest_id
))
812 printf("%s: guest runs %s.\n", __FUNCTION__
,
813 vmsvga_guest_id
[value
- GUEST_OS_BASE
]);
817 case SVGA_REG_CURSOR_ID
:
818 s
->cursor
.id
= value
;
821 case SVGA_REG_CURSOR_X
:
825 case SVGA_REG_CURSOR_Y
:
829 case SVGA_REG_CURSOR_ON
:
830 s
->cursor
.on
|= (value
== SVGA_CURSOR_ON_SHOW
);
831 s
->cursor
.on
&= (value
!= SVGA_CURSOR_ON_HIDE
);
832 #ifdef HW_MOUSE_ACCEL
833 if (s
->ds
->mouse_set
&& value
<= SVGA_CURSOR_ON_SHOW
)
834 s
->ds
->mouse_set(s
->cursor
.x
, s
->cursor
.y
, s
->cursor
.on
);
838 case SVGA_REG_MEM_REGS
:
839 case SVGA_REG_NUM_DISPLAYS
:
840 case SVGA_REG_PITCHLOCK
:
841 case SVGA_PALETTE_BASE
... SVGA_PALETTE_END
:
845 if (s
->index
>= SVGA_SCRATCH_BASE
&&
846 s
->index
< SVGA_SCRATCH_BASE
+ s
->scratch_size
) {
847 s
->scratch
[s
->index
- SVGA_SCRATCH_BASE
] = value
;
850 printf("%s: Bad register %02x\n", __FUNCTION__
, s
->index
);
854 static uint32_t vmsvga_bios_read(void *opaque
, uint32_t address
)
856 printf("%s: what are we supposed to return?\n", __FUNCTION__
);
860 static void vmsvga_bios_write(void *opaque
, uint32_t address
, uint32_t data
)
862 printf("%s: what are we supposed to do with (%08x)?\n",
866 static inline void vmsvga_size(struct vmsvga_state_s
*s
)
868 if (s
->new_width
!= s
->width
|| s
->new_height
!= s
->height
) {
869 s
->width
= s
->new_width
;
870 s
->height
= s
->new_height
;
871 dpy_resize(s
->ds
, s
->width
, s
->height
);
876 static void vmsvga_update_display(void *opaque
)
878 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
889 vmsvga_update_rect_flush(s
);
892 * Is it more efficient to look at vram VGA-dirty bits or wait
893 * for the driver to issue SVGA_CMD_UPDATE?
895 if (s
->invalidated
) {
897 vmsvga_update_screen(s
);
901 static void vmsvga_reset(struct vmsvga_state_s
*s
)
909 s
->depth
= s
->ds
->depth
? s
->ds
->depth
: 24;
910 s
->bypp
= (s
->depth
+ 7) >> 3;
912 s
->redraw_fifo_first
= 0;
913 s
->redraw_fifo_last
= 0;
916 s
->wred
= 0x00000007;
917 s
->wgreen
= 0x00000038;
918 s
->wblue
= 0x000000c0;
921 s
->wred
= 0x0000001f;
922 s
->wgreen
= 0x000003e0;
923 s
->wblue
= 0x00007c00;
926 s
->wred
= 0x0000001f;
927 s
->wgreen
= 0x000007e0;
928 s
->wblue
= 0x0000f800;
931 s
->wred
= 0x00ff0000;
932 s
->wgreen
= 0x0000ff00;
933 s
->wblue
= 0x000000ff;
936 s
->wred
= 0x00ff0000;
937 s
->wgreen
= 0x0000ff00;
938 s
->wblue
= 0x000000ff;
944 static void vmsvga_invalidate_display(void *opaque
)
946 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
949 s
->invalidate(opaque
);
957 /* save the vga display in a PPM image even if no display is
959 static void vmsvga_screen_dump(void *opaque
, const char *filename
)
961 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
964 s
->screen_dump(opaque
, filename
);
969 if (s
->depth
== 32) {
970 ppm_save(filename
, s
->vram
, s
->width
, s
->height
, s
->ds
->linesize
);
974 static void vmsvga_text_update(void *opaque
, console_ch_t
*chardata
)
976 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
979 s
->text_update(opaque
, chardata
);
983 static uint32_t vmsvga_vram_readb(void *opaque
, target_phys_addr_t addr
)
985 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
986 addr
-= s
->vram_base
;
987 if (addr
< s
->fb_size
)
988 return *(uint8_t *) (s
->ds
->data
+ addr
);
990 return *(uint8_t *) (s
->vram
+ addr
);
993 static uint32_t vmsvga_vram_readw(void *opaque
, target_phys_addr_t addr
)
995 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
996 addr
-= s
->vram_base
;
997 if (addr
< s
->fb_size
)
998 return *(uint16_t *) (s
->ds
->data
+ addr
);
1000 return *(uint16_t *) (s
->vram
+ addr
);
1003 static uint32_t vmsvga_vram_readl(void *opaque
, target_phys_addr_t addr
)
1005 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1006 addr
-= s
->vram_base
;
1007 if (addr
< s
->fb_size
)
1008 return *(uint32_t *) (s
->ds
->data
+ addr
);
1010 return *(uint32_t *) (s
->vram
+ addr
);
1013 static void vmsvga_vram_writeb(void *opaque
, target_phys_addr_t addr
,
1016 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1017 addr
-= s
->vram_base
;
1018 if (addr
< s
->fb_size
)
1019 *(uint8_t *) (s
->ds
->data
+ addr
) = value
;
1021 *(uint8_t *) (s
->vram
+ addr
) = value
;
1024 static void vmsvga_vram_writew(void *opaque
, target_phys_addr_t addr
,
1027 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1028 addr
-= s
->vram_base
;
1029 if (addr
< s
->fb_size
)
1030 *(uint16_t *) (s
->ds
->data
+ addr
) = value
;
1032 *(uint16_t *) (s
->vram
+ addr
) = value
;
1035 static void vmsvga_vram_writel(void *opaque
, target_phys_addr_t addr
,
1038 struct vmsvga_state_s
*s
= (struct vmsvga_state_s
*) opaque
;
1039 addr
-= s
->vram_base
;
1040 if (addr
< s
->fb_size
)
1041 *(uint32_t *) (s
->ds
->data
+ addr
) = value
;
1043 *(uint32_t *) (s
->vram
+ addr
) = value
;
1046 static CPUReadMemoryFunc
*vmsvga_vram_read
[] = {
1052 static CPUWriteMemoryFunc
*vmsvga_vram_write
[] = {
1059 static void vmsvga_save(struct vmsvga_state_s
*s
, QEMUFile
*f
)
1061 qemu_put_be32(f
, s
->depth
);
1062 qemu_put_be32(f
, s
->enable
);
1063 qemu_put_be32(f
, s
->config
);
1064 qemu_put_be32(f
, s
->cursor
.id
);
1065 qemu_put_be32(f
, s
->cursor
.x
);
1066 qemu_put_be32(f
, s
->cursor
.y
);
1067 qemu_put_be32(f
, s
->cursor
.on
);
1068 qemu_put_be32(f
, s
->index
);
1069 qemu_put_buffer(f
, (uint8_t *) s
->scratch
, s
->scratch_size
* 4);
1070 qemu_put_be32(f
, s
->new_width
);
1071 qemu_put_be32(f
, s
->new_height
);
1072 qemu_put_be32s(f
, &s
->guest
);
1073 qemu_put_be32s(f
, &s
->svgaid
);
1074 qemu_put_be32(f
, s
->syncing
);
1075 qemu_put_be32(f
, s
->fb_size
);
1078 static int vmsvga_load(struct vmsvga_state_s
*s
, QEMUFile
*f
)
1081 depth
=qemu_get_be32(f
);
1082 s
->enable
=qemu_get_be32(f
);
1083 s
->config
=qemu_get_be32(f
);
1084 s
->cursor
.id
=qemu_get_be32(f
);
1085 s
->cursor
.x
=qemu_get_be32(f
);
1086 s
->cursor
.y
=qemu_get_be32(f
);
1087 s
->cursor
.on
=qemu_get_be32(f
);
1088 s
->index
=qemu_get_be32(f
);
1089 qemu_get_buffer(f
, (uint8_t *) s
->scratch
, s
->scratch_size
* 4);
1090 s
->new_width
=qemu_get_be32(f
);
1091 s
->new_height
=qemu_get_be32(f
);
1092 qemu_get_be32s(f
, &s
->guest
);
1093 qemu_get_be32s(f
, &s
->svgaid
);
1094 s
->syncing
=qemu_get_be32(f
);
1095 s
->fb_size
=qemu_get_be32(f
);
1097 if (s
->enable
&& depth
!= s
->depth
) {
1098 printf("%s: need colour depth of %i bits to resume operation.\n",
1099 __FUNCTION__
, depth
);
1105 s
->fifo
= (uint32_t *) &s
->vram
[s
->vram_size
- SVGA_FIFO_SIZE
];
1110 static void vmsvga_init(struct vmsvga_state_s
*s
, DisplayState
*ds
,
1111 uint8_t *vga_ram_base
, unsigned long vga_ram_offset
,
1115 s
->vram
= vga_ram_base
;
1116 s
->vram_size
= vga_ram_size
;
1118 s
->scratch_size
= SVGA_SCRATCH_SIZE
;
1119 s
->scratch
= (uint32_t *) qemu_malloc(s
->scratch_size
* 4);
1123 graphic_console_init(ds
, vmsvga_update_display
,
1124 vmsvga_invalidate_display
, vmsvga_screen_dump
,
1125 vmsvga_text_update
, s
);
1128 vga_common_init((VGAState
*) s
, ds
,
1129 vga_ram_base
, vga_ram_offset
, vga_ram_size
);
1130 vga_init((VGAState
*) s
);
1134 static void pci_vmsvga_save(QEMUFile
*f
, void *opaque
)
1136 struct pci_vmsvga_state_s
*s
= (struct pci_vmsvga_state_s
*) opaque
;
1137 pci_device_save(&s
->card
, f
);
1138 vmsvga_save(&s
->chip
, f
);
1141 static int pci_vmsvga_load(QEMUFile
*f
, void *opaque
, int version_id
)
1143 struct pci_vmsvga_state_s
*s
= (struct pci_vmsvga_state_s
*) opaque
;
1146 ret
= pci_device_load(&s
->card
, f
);
1150 ret
= vmsvga_load(&s
->chip
, f
);
1157 static void pci_vmsvga_map_ioport(PCIDevice
*pci_dev
, int region_num
,
1158 uint32_t addr
, uint32_t size
, int type
)
1160 struct pci_vmsvga_state_s
*d
= (struct pci_vmsvga_state_s
*) pci_dev
;
1161 struct vmsvga_state_s
*s
= &d
->chip
;
1163 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_INDEX_PORT
,
1164 1, 4, vmsvga_index_read
, s
);
1165 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_INDEX_PORT
,
1166 1, 4, vmsvga_index_write
, s
);
1167 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_VALUE_PORT
,
1168 1, 4, vmsvga_value_read
, s
);
1169 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_VALUE_PORT
,
1170 1, 4, vmsvga_value_write
, s
);
1171 register_ioport_read(addr
+ SVGA_IO_MUL
* SVGA_BIOS_PORT
,
1172 1, 4, vmsvga_bios_read
, s
);
1173 register_ioport_write(addr
+ SVGA_IO_MUL
* SVGA_BIOS_PORT
,
1174 1, 4, vmsvga_bios_write
, s
);
1177 static void pci_vmsvga_map_mem(PCIDevice
*pci_dev
, int region_num
,
1178 uint32_t addr
, uint32_t size
, int type
)
1180 struct pci_vmsvga_state_s
*d
= (struct pci_vmsvga_state_s
*) pci_dev
;
1181 struct vmsvga_state_s
*s
= &d
->chip
;
1184 s
->vram_base
= addr
;
1186 iomemtype
= cpu_register_io_memory(0, vmsvga_vram_read
,
1187 vmsvga_vram_write
, s
);
1189 iomemtype
= 0 | IO_MEM_RAM
;
1191 cpu_register_physical_memory(s
->vram_base
, s
->vram_size
,
1195 #define PCI_VENDOR_ID_VMWARE 0x15ad
1196 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
1197 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
1198 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
1199 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
1200 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
1201 #define PCI_CLASS_BASE_DISPLAY 0x03
1202 #define PCI_CLASS_SUB_VGA 0x00
1203 #define PCI_CLASS_HEADERTYPE_00h 0x00
1205 void pci_vmsvga_init(PCIBus
*bus
, DisplayState
*ds
, uint8_t *vga_ram_base
,
1206 unsigned long vga_ram_offset
, int vga_ram_size
)
1208 struct pci_vmsvga_state_s
*s
;
1210 /* Setup PCI configuration */
1211 s
= (struct pci_vmsvga_state_s
*)
1212 pci_register_device(bus
, "QEMUware SVGA",
1213 sizeof(struct pci_vmsvga_state_s
), -1, 0, 0);
1214 s
->card
.config
[PCI_VENDOR_ID
] = PCI_VENDOR_ID_VMWARE
& 0xff;
1215 s
->card
.config
[PCI_VENDOR_ID
+ 1] = PCI_VENDOR_ID_VMWARE
>> 8;
1216 s
->card
.config
[PCI_DEVICE_ID
] = SVGA_PCI_DEVICE_ID
& 0xff;
1217 s
->card
.config
[PCI_DEVICE_ID
+ 1] = SVGA_PCI_DEVICE_ID
>> 8;
1218 s
->card
.config
[PCI_COMMAND
] = 0x07; /* I/O + Memory */
1219 s
->card
.config
[PCI_CLASS_DEVICE
] = PCI_CLASS_SUB_VGA
;
1220 s
->card
.config
[0x0b] = PCI_CLASS_BASE_DISPLAY
;
1221 s
->card
.config
[0x0c] = 0x08; /* Cache line size */
1222 s
->card
.config
[0x0d] = 0x40; /* Latency timer */
1223 s
->card
.config
[0x0e] = PCI_CLASS_HEADERTYPE_00h
;
1224 s
->card
.config
[0x10] = ((SVGA_IO_BASE
>> 0) & 0xff) | 1;
1225 s
->card
.config
[0x11] = (SVGA_IO_BASE
>> 8) & 0xff;
1226 s
->card
.config
[0x12] = (SVGA_IO_BASE
>> 16) & 0xff;
1227 s
->card
.config
[0x13] = (SVGA_IO_BASE
>> 24) & 0xff;
1228 s
->card
.config
[0x18] = (SVGA_MEM_BASE
>> 0) & 0xff;
1229 s
->card
.config
[0x19] = (SVGA_MEM_BASE
>> 8) & 0xff;
1230 s
->card
.config
[0x1a] = (SVGA_MEM_BASE
>> 16) & 0xff;
1231 s
->card
.config
[0x1b] = (SVGA_MEM_BASE
>> 24) & 0xff;
1232 s
->card
.config
[0x2c] = PCI_VENDOR_ID_VMWARE
& 0xff;
1233 s
->card
.config
[0x2d] = PCI_VENDOR_ID_VMWARE
>> 8;
1234 s
->card
.config
[0x2e] = SVGA_PCI_DEVICE_ID
& 0xff;
1235 s
->card
.config
[0x2f] = SVGA_PCI_DEVICE_ID
>> 8;
1236 s
->card
.config
[0x3c] = 0xff; /* End */
1238 pci_register_io_region(&s
->card
, 0, 0x10,
1239 PCI_ADDRESS_SPACE_IO
, pci_vmsvga_map_ioport
);
1240 pci_register_io_region(&s
->card
, 0, vga_ram_size
,
1241 PCI_ADDRESS_SPACE_MEM_PREFETCH
, pci_vmsvga_map_mem
);
1243 vmsvga_init(&s
->chip
, ds
, vga_ram_base
, vga_ram_offset
, vga_ram_size
);
1245 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save
, pci_vmsvga_load
, s
);