hw/xtensa/xtfpga.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "sysemu/sysemu.h"
  30 #include "hw/boards.h"
  31 #include "hw/loader.h"
  32 #include "elf.h"
  33 #include "exec/memory.h"
  34 #include "exec/address-spaces.h"
  35 #include "hw/char/serial.h"
  36 #include "net/net.h"
  37 #include "hw/sysbus.h"
  38 #include "hw/block/flash.h"
  39 #include "sysemu/block-backend.h"
  40 #include "sysemu/char.h"
  41 #include "sysemu/device_tree.h"
  42 #include "qemu/error-report.h"
  43 #include "bootparam.h"
  44
  45 typedef struct LxBoardDesc {
  46     hwaddr flash_base;
  47     size_t flash_size;
  48     size_t flash_boot_base;
  49     size_t flash_sector_size;
  50     size_t sram_size;
  51 } LxBoardDesc;
  52
  53 typedef struct Lx60FpgaState {
  54     MemoryRegion iomem;
  55     uint32_t leds;
  56     uint32_t switches;
  57 } Lx60FpgaState;
  58
  59 static void lx60_fpga_reset(void *opaque)
  60 {
  61     Lx60FpgaState *s = opaque;
  62
  63     s->leds = 0;
  64     s->switches = 0;
  65 }
  66
  67 static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
  68         unsigned size)
  69 {
  70     Lx60FpgaState *s = opaque;
  71
  72     switch (addr) {
  73     case 0x0: /*build date code*/
  74         return 0x09272011;
  75
  76     case 0x4: /*processor clock frequency, Hz*/
  77         return 10000000;
  78
  79     case 0x8: /*LEDs (off = 0, on = 1)*/
  80         return s->leds;
  81
  82     case 0xc: /*DIP switches (off = 0, on = 1)*/
  83         return s->switches;
  84     }
  85     return 0;
  86 }
  87
  88 static void lx60_fpga_write(void *opaque, hwaddr addr,
  89         uint64_t val, unsigned size)
  90 {
  91     Lx60FpgaState *s = opaque;
  92
  93     switch (addr) {
  94     case 0x8: /*LEDs (off = 0, on = 1)*/
  95         s->leds = val;
  96         break;
  97
  98     case 0x10: /*board reset*/
  99         if (val == 0xdead) {
 100             qemu_system_reset_request();
 101         }
 102         break;
 103     }
 104 }
 105
 106 static const MemoryRegionOps lx60_fpga_ops = {
 107     .read = lx60_fpga_read,
 108     .write = lx60_fpga_write,
 109     .endianness = DEVICE_NATIVE_ENDIAN,
 110 };
 111
 112 static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
 113         hwaddr base)
 114 {
 115     Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
 116
 117     memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
 118             "lx60.fpga", 0x10000);
 119     memory_region_add_subregion(address_space, base, &s->iomem);
 120     lx60_fpga_reset(s);
 121     qemu_register_reset(lx60_fpga_reset, s);
 122     return s;
 123 }
 124
 125 static void lx60_net_init(MemoryRegion *address_space,
 126         hwaddr base,
 127         hwaddr descriptors,
 128         hwaddr buffers,
 129         qemu_irq irq, NICInfo *nd)
 130 {
 131     DeviceState *dev;
 132     SysBusDevice *s;
 133     MemoryRegion *ram;
 134
 135     dev = qdev_create(NULL, "open_eth");
 136     qdev_set_nic_properties(dev, nd);
 137     qdev_init_nofail(dev);
 138
 139     s = SYS_BUS_DEVICE(dev);
 140     sysbus_connect_irq(s, 0, irq);
 141     memory_region_add_subregion(address_space, base,
 142             sysbus_mmio_get_region(s, 0));
 143     memory_region_add_subregion(address_space, descriptors,
 144             sysbus_mmio_get_region(s, 1));
 145
 146     ram = g_malloc(sizeof(*ram));
 147     memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384,
 148                            &error_fatal);
 149     vmstate_register_ram_global(ram);
 150     memory_region_add_subregion(address_space, buffers, ram);
 151 }
 152
 153 static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
 154                                    const LxBoardDesc *board,
 155                                    DriveInfo *dinfo, int be)
 156 {
 157     SysBusDevice *s;
 158     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 159
 160     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
 161                         &error_abort);
 162     qdev_prop_set_uint32(dev, "num-blocks",
 163                          board->flash_size / board->flash_sector_size);
 164     qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
 165     qdev_prop_set_uint8(dev, "width", 4);
 166     qdev_prop_set_bit(dev, "big-endian", be);
 167     qdev_prop_set_string(dev, "name", "lx60.io.flash");
 168     qdev_init_nofail(dev);
 169     s = SYS_BUS_DEVICE(dev);
 170     memory_region_add_subregion(address_space, board->flash_base,
 171                                 sysbus_mmio_get_region(s, 0));
 172     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 173 }
 174
 175 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
 176 {
 177     XtensaCPU *cpu = opaque;
 178
 179     return cpu_get_phys_page_debug(CPU(cpu), addr);
 180 }
 181
 182 static void lx60_reset(void *opaque)
 183 {
 184     XtensaCPU *cpu = opaque;
 185
 186     cpu_reset(CPU(cpu));
 187 }
 188
 189 static uint64_t lx60_io_read(void *opaque, hwaddr addr,
 190         unsigned size)
 191 {
 192     return 0;
 193 }
 194
 195 static void lx60_io_write(void *opaque, hwaddr addr,
 196         uint64_t val, unsigned size)
 197 {
 198 }
 199
 200 static const MemoryRegionOps lx60_io_ops = {
 201     .read = lx60_io_read,
 202     .write = lx60_io_write,
 203     .endianness = DEVICE_NATIVE_ENDIAN,
 204 };
 205
 206 static void lx_init(const LxBoardDesc *board, MachineState *machine)
 207 {
 208 #ifdef TARGET_WORDS_BIGENDIAN
 209     int be = 1;
 210 #else
 211     int be = 0;
 212 #endif
 213     MemoryRegion *system_memory = get_system_memory();
 214     XtensaCPU *cpu = NULL;
 215     CPUXtensaState *env = NULL;
 216     MemoryRegion *ram, *rom, *system_io;
 217     DriveInfo *dinfo;
 218     pflash_t *flash = NULL;
 219     QemuOpts *machine_opts = qemu_get_machine_opts();
 220     const char *cpu_model = machine->cpu_model;
 221     const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
 222     const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
 223     const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
 224     const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
 225     int n;
 226
 227     if (!cpu_model) {
 228         cpu_model = XTENSA_DEFAULT_CPU_MODEL;
 229     }
 230
 231     for (n = 0; n < smp_cpus; n++) {
 232         cpu = cpu_xtensa_init(cpu_model);
 233         if (cpu == NULL) {
 234             error_report("unable to find CPU definition '%s'",
 235                          cpu_model);
 236             exit(EXIT_FAILURE);
 237         }
 238         env = &cpu->env;
 239
 240         env->sregs[PRID] = n;
 241         qemu_register_reset(lx60_reset, cpu);
 242         /* Need MMU initialized prior to ELF loading,
 243          * so that ELF gets loaded into virtual addresses
 244          */
 245         cpu_reset(CPU(cpu));
 246     }
 247
 248     ram = g_malloc(sizeof(*ram));
 249     memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
 250                            &error_fatal);
 251     vmstate_register_ram_global(ram);
 252     memory_region_add_subregion(system_memory, 0, ram);
 253
 254     system_io = g_malloc(sizeof(*system_io));
 255     memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io",
 256                           224 * 1024 * 1024);
 257     memory_region_add_subregion(system_memory, 0xf0000000, system_io);
 258     lx60_fpga_init(system_io, 0x0d020000);
 259     if (nd_table[0].used) {
 260         lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
 261                 xtensa_get_extint(env, 1), nd_table);
 262     }
 263
 264     if (!serial_hds[0]) {
 265         serial_hds[0] = qemu_chr_new("serial0", "null", NULL);
 266     }
 267
 268     serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
 269             115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
 270
 271     dinfo = drive_get(IF_PFLASH, 0, 0);
 272     if (dinfo) {
 273         flash = xtfpga_flash_init(system_io, board, dinfo, be);
 274     }
 275
 276     /* Use presence of kernel file name as 'boot from SRAM' switch. */
 277     if (kernel_filename) {
 278         uint32_t entry_point = env->pc;
 279         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
 280         uint32_t tagptr = 0xfe000000 + board->sram_size;
 281         uint32_t cur_tagptr;
 282         BpMemInfo memory_location = {
 283             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
 284             .start = tswap32(0),
 285             .end = tswap32(machine->ram_size),
 286         };
 287         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
 288             machine->ram_size : 0x08000000;
 289         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
 290
 291         rom = g_malloc(sizeof(*rom));
 292         memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
 293                                &error_fatal);
 294         vmstate_register_ram_global(rom);
 295         memory_region_add_subregion(system_memory, 0xfe000000, rom);
 296
 297         if (kernel_cmdline) {
 298             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
 299         }
 300         if (dtb_filename) {
 301             bp_size += get_tag_size(sizeof(uint32_t));
 302         }
 303         if (initrd_filename) {
 304             bp_size += get_tag_size(sizeof(BpMemInfo));
 305         }
 306
 307         /* Put kernel bootparameters to the end of that SRAM */
 308         tagptr = (tagptr - bp_size) & ~0xff;
 309         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
 310         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
 311                              sizeof(memory_location), &memory_location);
 312
 313         if (kernel_cmdline) {
 314             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
 315                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
 316         }
 317         if (dtb_filename) {
 318             int fdt_size;
 319             void *fdt = load_device_tree(dtb_filename, &fdt_size);
 320             uint32_t dtb_addr = tswap32(cur_lowmem);
 321
 322             if (!fdt) {
 323                 error_report("could not load DTB '%s'", dtb_filename);
 324                 exit(EXIT_FAILURE);
 325             }
 326
 327             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
 328             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
 329                                  sizeof(dtb_addr), &dtb_addr);
 330             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
 331         }
 332         if (initrd_filename) {
 333             BpMemInfo initrd_location = { 0 };
 334             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
 335                                            lowmem_end - cur_lowmem);
 336
 337             if (initrd_size < 0) {
 338                 initrd_size = load_image_targphys(initrd_filename,
 339                                                   cur_lowmem,
 340                                                   lowmem_end - cur_lowmem);
 341             }
 342             if (initrd_size < 0) {
 343                 error_report("could not load initrd '%s'", initrd_filename);
 344                 exit(EXIT_FAILURE);
 345             }
 346             initrd_location.start = tswap32(cur_lowmem);
 347             initrd_location.end = tswap32(cur_lowmem + initrd_size);
 348             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
 349                                  sizeof(initrd_location), &initrd_location);
 350             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
 351         }
 352         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
 353         env->regs[2] = tagptr;
 354
 355         uint64_t elf_entry;
 356         uint64_t elf_lowaddr;
 357         int success = load_elf(kernel_filename, translate_phys_addr, cpu,
 358                 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0);
 359         if (success > 0) {
 360             entry_point = elf_entry;
 361         } else {
 362             hwaddr ep;
 363             int is_linux;
 364             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
 365                                   translate_phys_addr, cpu);
 366             if (success > 0 && is_linux) {
 367                 entry_point = ep;
 368             } else {
 369                 error_report("could not load kernel '%s'",
 370                              kernel_filename);
 371                 exit(EXIT_FAILURE);
 372             }
 373         }
 374         if (entry_point != env->pc) {
 375             static const uint8_t jx_a0[] = {
 376 #ifdef TARGET_WORDS_BIGENDIAN
 377                 0x0a, 0, 0,
 378 #else
 379                 0xa0, 0, 0,
 380 #endif
 381             };
 382             env->regs[0] = entry_point;
 383             cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
 384         }
 385     } else {
 386         if (flash) {
 387             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
 388             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
 389
 390             memory_region_init_alias(flash_io, NULL, "lx60.flash",
 391                     flash_mr, board->flash_boot_base,
 392                     board->flash_size - board->flash_boot_base < 0x02000000 ?
 393                     board->flash_size - board->flash_boot_base : 0x02000000);
 394             memory_region_add_subregion(system_memory, 0xfe000000,
 395                     flash_io);
 396         }
 397     }
 398 }
 399
 400 static void xtensa_lx60_init(MachineState *machine)
 401 {
 402     static const LxBoardDesc lx60_board = {
 403         .flash_base = 0x08000000,
 404         .flash_size = 0x00400000,
 405         .flash_sector_size = 0x10000,
 406         .sram_size = 0x20000,
 407     };
 408     lx_init(&lx60_board, machine);
 409 }
 410
 411 static void xtensa_lx200_init(MachineState *machine)
 412 {
 413     static const LxBoardDesc lx200_board = {
 414         .flash_base = 0x08000000,
 415         .flash_size = 0x01000000,
 416         .flash_sector_size = 0x20000,
 417         .sram_size = 0x2000000,
 418     };
 419     lx_init(&lx200_board, machine);
 420 }
 421
 422 static void xtensa_ml605_init(MachineState *machine)
 423 {
 424     static const LxBoardDesc ml605_board = {
 425         .flash_base = 0x08000000,
 426         .flash_size = 0x01000000,
 427         .flash_sector_size = 0x20000,
 428         .sram_size = 0x2000000,
 429     };
 430     lx_init(&ml605_board, machine);
 431 }
 432
 433 static void xtensa_kc705_init(MachineState *machine)
 434 {
 435     static const LxBoardDesc kc705_board = {
 436         .flash_base = 0x00000000,
 437         .flash_size = 0x08000000,
 438         .flash_boot_base = 0x06000000,
 439         .flash_sector_size = 0x20000,
 440         .sram_size = 0x2000000,
 441     };
 442     lx_init(&kc705_board, machine);
 443 }
 444
 445 static void xtensa_lx60_class_init(ObjectClass *oc, void *data)
 446 {
 447     MachineClass *mc = MACHINE_CLASS(oc);
 448
 449     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 450     mc->init = xtensa_lx60_init;
 451     mc->max_cpus = 4;
 452 }
 453
 454 static const TypeInfo xtensa_lx60_type = {
 455     .name = MACHINE_TYPE_NAME("lx60"),
 456     .parent = TYPE_MACHINE,
 457     .class_init = xtensa_lx60_class_init,
 458 };
 459
 460 static void xtensa_lx200_class_init(ObjectClass *oc, void *data)
 461 {
 462     MachineClass *mc = MACHINE_CLASS(oc);
 463
 464     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 465     mc->init = xtensa_lx200_init;
 466     mc->max_cpus = 4;
 467 }
 468
 469 static const TypeInfo xtensa_lx200_type = {
 470     .name = MACHINE_TYPE_NAME("lx200"),
 471     .parent = TYPE_MACHINE,
 472     .class_init = xtensa_lx200_class_init,
 473 };
 474
 475 static void xtensa_ml605_class_init(ObjectClass *oc, void *data)
 476 {
 477     MachineClass *mc = MACHINE_CLASS(oc);
 478
 479     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 480     mc->init = xtensa_ml605_init;
 481     mc->max_cpus = 4;
 482 }
 483
 484 static const TypeInfo xtensa_ml605_type = {
 485     .name = MACHINE_TYPE_NAME("ml605"),
 486     .parent = TYPE_MACHINE,
 487     .class_init = xtensa_ml605_class_init,
 488 };
 489
 490 static void xtensa_kc705_class_init(ObjectClass *oc, void *data)
 491 {
 492     MachineClass *mc = MACHINE_CLASS(oc);
 493
 494     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 495     mc->init = xtensa_kc705_init;
 496     mc->max_cpus = 4;
 497 }
 498
 499 static const TypeInfo xtensa_kc705_type = {
 500     .name = MACHINE_TYPE_NAME("kc705"),
 501     .parent = TYPE_MACHINE,
 502     .class_init = xtensa_kc705_class_init,
 503 };
 504
 505 static void xtensa_lx_machines_init(void)
 506 {
 507     type_register_static(&xtensa_lx60_type);
 508     type_register_static(&xtensa_lx200_type);
 509     type_register_static(&xtensa_ml605_type);
 510     type_register_static(&xtensa_kc705_type);
 511 }
 512
 513 machine_init(xtensa_lx_machines_init)