include/dt-bindings/clock/jz4740-cgu.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
   4  *
   5  * They are roughly ordered as:
   6  *   - external clocks
   7  *   - PLLs
   8  *   - muxes/dividers in the order they appear in the jz4740 programmers manual
   9  *   - gates in order of their bit in the CLKGR* registers
  10  */
  11
  12 #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
  13 #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
  14
  15 #define JZ4740_CLK_EXT          0
  16 #define JZ4740_CLK_RTC          1
  17 #define JZ4740_CLK_PLL          2
  18 #define JZ4740_CLK_PLL_HALF     3
  19 #define JZ4740_CLK_CCLK         4
  20 #define JZ4740_CLK_HCLK         5
  21 #define JZ4740_CLK_PCLK         6
  22 #define JZ4740_CLK_MCLK         7
  23 #define JZ4740_CLK_LCD          8
  24 #define JZ4740_CLK_LCD_PCLK     9
  25 #define JZ4740_CLK_I2S          10
  26 #define JZ4740_CLK_SPI          11
  27 #define JZ4740_CLK_MMC          12
  28 #define JZ4740_CLK_UHC          13
  29 #define JZ4740_CLK_UDC          14
  30 #define JZ4740_CLK_UART0        15
  31 #define JZ4740_CLK_UART1        16
  32 #define JZ4740_CLK_DMA          17
  33 #define JZ4740_CLK_IPU          18
  34 #define JZ4740_CLK_ADC          19
  35 #define JZ4740_CLK_I2C          20
  36 #define JZ4740_CLK_AIC          21
  37
  38 #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */