include/hw/core/tcg-cpu-ops.h

   1 /*
   2  * TCG CPU-specific operations
   3  *
   4  * Copyright 2021 SUSE LLC
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef TCG_CPU_OPS_H
  11 #define TCG_CPU_OPS_H
  12
  13 #include "hw/core/cpu.h"
  14
  15 struct TCGCPUOps {
  16     /**
  17      * @initialize: Initalize TCG state
  18      *
  19      * Called when the first CPU is realized.
  20      */
  21     void (*initialize)(void);
  22     /**
  23      * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
  24      *
  25      * This is called when we abandon execution of a TB before starting it,
  26      * and must set all parts of the CPU state which the previous TB in the
  27      * chain may not have updated.
  28      * By default, when this is NULL, a call is made to @set_pc(tb->pc).
  29      *
  30      * If more state needs to be restored, the target must implement a
  31      * function to restore all the state, and register it here.
  32      */
  33     void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
  34     /**
  35      * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn
  36      *
  37      * This is called when we unwind state in the middle of a TB,
  38      * usually before raising an exception.  Set all part of the CPU
  39      * state which are tracked insn-by-insn in the target-specific
  40      * arguments to start_insn, passed as @data.
  41      */
  42     void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb,
  43                                  const uint64_t *data);
  44
  45     /** @cpu_exec_enter: Callback for cpu_exec preparation */
  46     void (*cpu_exec_enter)(CPUState *cpu);
  47     /** @cpu_exec_exit: Callback for cpu_exec cleanup */
  48     void (*cpu_exec_exit)(CPUState *cpu);
  49     /** @debug_excp_handler: Callback for handling debug exceptions */
  50     void (*debug_excp_handler)(CPUState *cpu);
  51
  52 #ifdef NEED_CPU_H
  53 #if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
  54     /**
  55      * @fake_user_interrupt: Callback for 'fake exception' handling.
  56      *
  57      * Simulate 'fake exception' which will be handled outside the
  58      * cpu execution loop (hack for x86 user mode).
  59      */
  60     void (*fake_user_interrupt)(CPUState *cpu);
  61 #else
  62     /**
  63      * @do_interrupt: Callback for interrupt handling.
  64      */
  65     void (*do_interrupt)(CPUState *cpu);
  66 #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
  67 #ifdef CONFIG_SOFTMMU
  68     /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
  69     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
  70     /**
  71      * @tlb_fill: Handle a softmmu tlb miss
  72      *
  73      * If the access is valid, call tlb_set_page and return true;
  74      * if the access is invalid and probe is true, return false;
  75      * otherwise raise an exception and do not return.
  76      */
  77     bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
  78                      MMUAccessType access_type, int mmu_idx,
  79                      bool probe, uintptr_t retaddr);
  80     /**
  81      * @do_transaction_failed: Callback for handling failed memory transactions
  82      * (ie bus faults or external aborts; not MMU faults)
  83      */
  84     void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
  85                                   unsigned size, MMUAccessType access_type,
  86                                   int mmu_idx, MemTxAttrs attrs,
  87                                   MemTxResult response, uintptr_t retaddr);
  88     /**
  89      * @do_unaligned_access: Callback for unaligned access handling
  90      * The callback must exit via raising an exception.
  91      */
  92     G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
  93                                            MMUAccessType access_type,
  94                                            int mmu_idx, uintptr_t retaddr);
  95
  96     /**
  97      * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
  98      */
  99     vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
 100
 101     /**
 102      * @debug_check_watchpoint: return true if the architectural
 103      * watchpoint whose address has matched should really fire, used by ARM
 104      * and RISC-V
 105      */
 106     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
 107
 108     /**
 109      * @debug_check_breakpoint: return true if the architectural
 110      * breakpoint whose PC has matched should really fire.
 111      */
 112     bool (*debug_check_breakpoint)(CPUState *cpu);
 113
 114     /**
 115      * @io_recompile_replay_branch: Callback for cpu_io_recompile.
 116      *
 117      * The cpu has been stopped, and cpu_restore_state_from_tb has been
 118      * called.  If the faulting instruction is in a delay slot, and the
 119      * target architecture requires re-execution of the branch, then
 120      * adjust the cpu state as required and return true.
 121      */
 122     bool (*io_recompile_replay_branch)(CPUState *cpu,
 123                                        const TranslationBlock *tb);
 124 #else
 125     /**
 126      * record_sigsegv:
 127      * @cpu: cpu context
 128      * @addr: faulting guest address
 129      * @access_type: access was read/write/execute
 130      * @maperr: true for invalid page, false for permission fault
 131      * @ra: host pc for unwinding
 132      *
 133      * We are about to raise SIGSEGV with si_code set for @maperr,
 134      * and si_addr set for @addr.  Record anything further needed
 135      * for the signal ucontext_t.
 136      *
 137      * If the emulated kernel does not provide anything to the signal
 138      * handler with anything besides the user context registers, and
 139      * the siginfo_t, then this hook need do nothing and may be omitted.
 140      * Otherwise, record the data and return; the caller will raise
 141      * the signal, unwind the cpu state, and return to the main loop.
 142      *
 143      * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
 144      * so that a "normal" cpu exception can be raised.  In this case,
 145      * the signal must be raised by the architecture cpu_loop.
 146      */
 147     void (*record_sigsegv)(CPUState *cpu, vaddr addr,
 148                            MMUAccessType access_type,
 149                            bool maperr, uintptr_t ra);
 150     /**
 151      * record_sigbus:
 152      * @cpu: cpu context
 153      * @addr: misaligned guest address
 154      * @access_type: access was read/write/execute
 155      * @ra: host pc for unwinding
 156      *
 157      * We are about to raise SIGBUS with si_code BUS_ADRALN,
 158      * and si_addr set for @addr.  Record anything further needed
 159      * for the signal ucontext_t.
 160      *
 161      * If the emulated kernel does not provide the signal handler with
 162      * anything besides the user context registers, and the siginfo_t,
 163      * then this hook need do nothing and may be omitted.
 164      * Otherwise, record the data and return; the caller will raise
 165      * the signal, unwind the cpu state, and return to the main loop.
 166      *
 167      * If it is simpler to re-use the sysemu do_unaligned_access code,
 168      * @ra is provided so that a "normal" cpu exception can be raised.
 169      * In this case, the signal must be raised by the architecture cpu_loop.
 170      */
 171     void (*record_sigbus)(CPUState *cpu, vaddr addr,
 172                           MMUAccessType access_type, uintptr_t ra);
 173 #endif /* CONFIG_SOFTMMU */
 174 #endif /* NEED_CPU_H */
 175
 176 };
 177
 178 #endif /* TCG_CPU_OPS_H */