2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/scatterlist.h>
27 #include <linux/bitmap.h>
28 #include <linux/types.h>
32 * typedef dma_cookie_t - an opaque DMA cookie
34 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
36 typedef s32 dma_cookie_t
;
37 #define DMA_MIN_COOKIE 1
38 #define DMA_MAX_COOKIE INT_MAX
40 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
43 * enum dma_status - DMA transaction status
44 * @DMA_SUCCESS: transaction completed successfully
45 * @DMA_IN_PROGRESS: transaction not yet processed
46 * @DMA_PAUSED: transaction is paused
47 * @DMA_ERROR: transaction failed
57 * enum dma_transaction_type - DMA transaction types/indexes
59 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
60 * automatically set as dma devices are registered.
62 enum dma_transaction_type
{
76 /* last transaction type for creation of the capabilities mask */
81 * enum dma_transfer_direction - dma transfer mode and direction indicator
82 * @DMA_MEM_TO_MEM: Async/Memcpy mode
83 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
84 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
85 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
87 enum dma_transfer_direction
{
96 * Interleaved Transfer Request
97 * ----------------------------
98 * A chunk is collection of contiguous bytes to be transfered.
99 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
100 * ICGs may or maynot change between chunks.
101 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
102 * that when repeated an integral number of times, specifies the transfer.
103 * A transfer template is specification of a Frame, the number of times
104 * it is to be repeated and other per-transfer attributes.
106 * Practically, a client driver would have ready a template for each
107 * type of transfer it is going to need during its lifetime and
108 * set only 'src_start' and 'dst_start' before submitting the requests.
111 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
112 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
119 * struct data_chunk - Element of scatter-gather list that makes a frame.
120 * @size: Number of bytes to read from source.
121 * size_dst := fn(op, size_src), so doesn't mean much for destination.
122 * @icg: Number of bytes to jump after last src/dst address of this
123 * chunk and before first src/dst address for next chunk.
124 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
125 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
135 * @src_start: Bus address of source for the first chunk.
136 * @dst_start: Bus address of destination for the first chunk.
137 * @dir: Specifies the type of Source and Destination.
138 * @src_inc: If the source address increments after reading from it.
139 * @dst_inc: If the destination address increments after writing to it.
140 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
141 * Otherwise, source is read contiguously (icg ignored).
142 * Ignored if src_inc is false.
143 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
144 * Otherwise, destination is filled contiguously (icg ignored).
145 * Ignored if dst_inc is false.
146 * @numf: Number of frames in this template.
147 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
148 * @sgl: Array of {chunk,icg} pairs that make up a frame.
150 struct dma_interleaved_template
{
151 dma_addr_t src_start
;
152 dma_addr_t dst_start
;
153 enum dma_transfer_direction dir
;
160 struct data_chunk sgl
[0];
164 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
165 * control completion, and communicate status.
166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
169 * acknowledges receipt, i.e. has has a chance to establish any dependency
171 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
172 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
173 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
174 * (if not set, do the source dma-unmapping as page)
175 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
176 * (if not set, do the destination dma-unmapping as page)
177 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
178 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
179 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
180 * sources that were the result of a previous operation, in the case of a PQ
181 * operation it continues the calculation with new sources
182 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
183 * on the result of this operation
185 enum dma_ctrl_flags
{
186 DMA_PREP_INTERRUPT
= (1 << 0),
187 DMA_CTRL_ACK
= (1 << 1),
188 DMA_COMPL_SKIP_SRC_UNMAP
= (1 << 2),
189 DMA_COMPL_SKIP_DEST_UNMAP
= (1 << 3),
190 DMA_COMPL_SRC_UNMAP_SINGLE
= (1 << 4),
191 DMA_COMPL_DEST_UNMAP_SINGLE
= (1 << 5),
192 DMA_PREP_PQ_DISABLE_P
= (1 << 6),
193 DMA_PREP_PQ_DISABLE_Q
= (1 << 7),
194 DMA_PREP_CONTINUE
= (1 << 8),
195 DMA_PREP_FENCE
= (1 << 9),
199 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
200 * on a running channel.
201 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
202 * @DMA_PAUSE: pause ongoing transfers
203 * @DMA_RESUME: resume paused transfer
204 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
205 * that need to runtime reconfigure the slave channels (as opposed to passing
206 * configuration data in statically from the platform). An additional
207 * argument of struct dma_slave_config must be passed in with this
209 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
210 * into external start mode.
217 FSLDMA_EXTERNAL_START
,
221 * enum sum_check_bits - bit position of pq_check_flags
223 enum sum_check_bits
{
229 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
230 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
231 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
233 enum sum_check_flags
{
234 SUM_CHECK_P_RESULT
= (1 << SUM_CHECK_P
),
235 SUM_CHECK_Q_RESULT
= (1 << SUM_CHECK_Q
),
240 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
241 * See linux/cpumask.h
243 typedef struct { DECLARE_BITMAP(bits
, DMA_TX_TYPE_END
); } dma_cap_mask_t
;
246 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
247 * @memcpy_count: transaction counter
248 * @bytes_transferred: byte counter
251 struct dma_chan_percpu
{
253 unsigned long memcpy_count
;
254 unsigned long bytes_transferred
;
258 * struct dma_chan - devices supply DMA channels, clients use them
259 * @device: ptr to the dma device who supplies this channel, always !%NULL
260 * @cookie: last cookie value returned to client
261 * @chan_id: channel ID for sysfs
262 * @dev: class device for sysfs
263 * @device_node: used to add this to the device chan list
264 * @local: per-cpu pointer to a struct dma_chan_percpu
265 * @client-count: how many clients are using this channel
266 * @table_count: number of appearances in the mem-to-mem allocation table
267 * @private: private data for certain client-channel associations
270 struct dma_device
*device
;
275 struct dma_chan_dev
*dev
;
277 struct list_head device_node
;
278 struct dma_chan_percpu __percpu
*local
;
285 * struct dma_chan_dev - relate sysfs device node to backing channel device
286 * @chan - driver channel device
287 * @device - sysfs device
288 * @dev_id - parent dma_device dev_id
289 * @idr_ref - reference count to gate release of dma_device dev_id
291 struct dma_chan_dev
{
292 struct dma_chan
*chan
;
293 struct device device
;
299 * enum dma_slave_buswidth - defines bus with of the DMA slave
300 * device, source or target buses
302 enum dma_slave_buswidth
{
303 DMA_SLAVE_BUSWIDTH_UNDEFINED
= 0,
304 DMA_SLAVE_BUSWIDTH_1_BYTE
= 1,
305 DMA_SLAVE_BUSWIDTH_2_BYTES
= 2,
306 DMA_SLAVE_BUSWIDTH_4_BYTES
= 4,
307 DMA_SLAVE_BUSWIDTH_8_BYTES
= 8,
311 * struct dma_slave_config - dma slave channel runtime config
312 * @direction: whether the data shall go in or out on this slave
313 * channel, right now. DMA_TO_DEVICE and DMA_FROM_DEVICE are
314 * legal values, DMA_BIDIRECTIONAL is not acceptable since we
315 * need to differentiate source and target addresses.
316 * @src_addr: this is the physical address where DMA slave data
317 * should be read (RX), if the source is memory this argument is
319 * @dst_addr: this is the physical address where DMA slave data
320 * should be written (TX), if the source is memory this argument
322 * @src_addr_width: this is the width in bytes of the source (RX)
323 * register where DMA data shall be read. If the source
324 * is memory this may be ignored depending on architecture.
325 * Legal values: 1, 2, 4, 8.
326 * @dst_addr_width: same as src_addr_width but for destination
327 * target (TX) mutatis mutandis.
328 * @src_maxburst: the maximum number of words (note: words, as in
329 * units of the src_addr_width member, not bytes) that can be sent
330 * in one burst to the device. Typically something like half the
331 * FIFO depth on I/O peripherals so you don't overflow it. This
332 * may or may not be applicable on memory sources.
333 * @dst_maxburst: same as src_maxburst but for destination target
335 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
336 * with 'true' if peripheral should be flow controller. Direction will be
337 * selected at Runtime.
339 * This struct is passed in as configuration data to a DMA engine
340 * in order to set up a certain channel for DMA transport at runtime.
341 * The DMA device/engine has to provide support for an additional
342 * command in the channel config interface, DMA_SLAVE_CONFIG
343 * and this struct will then be passed in as an argument to the
344 * DMA engine device_control() function.
346 * The rationale for adding configuration information to this struct
347 * is as follows: if it is likely that most DMA slave controllers in
348 * the world will support the configuration option, then make it
349 * generic. If not: if it is fixed so that it be sent in static from
350 * the platform data, then prefer to do that. Else, if it is neither
351 * fixed at runtime, nor generic enough (such as bus mastership on
352 * some CPU family and whatnot) then create a custom slave config
353 * struct and pass that, then make this config a member of that
354 * struct, if applicable.
356 struct dma_slave_config
{
357 enum dma_transfer_direction direction
;
360 enum dma_slave_buswidth src_addr_width
;
361 enum dma_slave_buswidth dst_addr_width
;
367 static inline const char *dma_chan_name(struct dma_chan
*chan
)
369 return dev_name(&chan
->dev
->device
);
372 void dma_chan_cleanup(struct kref
*kref
);
375 * typedef dma_filter_fn - callback filter for dma_request_channel
376 * @chan: channel to be reviewed
377 * @filter_param: opaque parameter passed through dma_request_channel
379 * When this optional parameter is specified in a call to dma_request_channel a
380 * suitable channel is passed to this routine for further dispositioning before
381 * being returned. Where 'suitable' indicates a non-busy channel that
382 * satisfies the given capability mask. It returns 'true' to indicate that the
383 * channel is suitable.
385 typedef bool (*dma_filter_fn
)(struct dma_chan
*chan
, void *filter_param
);
387 typedef void (*dma_async_tx_callback
)(void *dma_async_param
);
389 * struct dma_async_tx_descriptor - async transaction descriptor
390 * ---dma generic offload fields---
391 * @cookie: tracking cookie for this transaction, set to -EBUSY if
392 * this tx is sitting on a dependency list
393 * @flags: flags to augment operation preparation, control completion, and
395 * @phys: physical address of the descriptor
396 * @chan: target channel for this operation
397 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
398 * @callback: routine to call after this operation is complete
399 * @callback_param: general parameter to pass to the callback routine
400 * ---async_tx api specific fields---
401 * @next: at completion submit this descriptor
402 * @parent: pointer to the next level up in the dependency chain
403 * @lock: protect the parent and next pointers
405 struct dma_async_tx_descriptor
{
407 enum dma_ctrl_flags flags
; /* not a 'long' to pack with cookie */
409 struct dma_chan
*chan
;
410 dma_cookie_t (*tx_submit
)(struct dma_async_tx_descriptor
*tx
);
411 dma_async_tx_callback callback
;
412 void *callback_param
;
413 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
414 struct dma_async_tx_descriptor
*next
;
415 struct dma_async_tx_descriptor
*parent
;
420 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
421 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
424 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
427 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
431 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
434 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
437 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
441 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
447 static inline void txd_lock(struct dma_async_tx_descriptor
*txd
)
449 spin_lock_bh(&txd
->lock
);
451 static inline void txd_unlock(struct dma_async_tx_descriptor
*txd
)
453 spin_unlock_bh(&txd
->lock
);
455 static inline void txd_chain(struct dma_async_tx_descriptor
*txd
, struct dma_async_tx_descriptor
*next
)
460 static inline void txd_clear_parent(struct dma_async_tx_descriptor
*txd
)
464 static inline void txd_clear_next(struct dma_async_tx_descriptor
*txd
)
468 static inline struct dma_async_tx_descriptor
*txd_parent(struct dma_async_tx_descriptor
*txd
)
472 static inline struct dma_async_tx_descriptor
*txd_next(struct dma_async_tx_descriptor
*txd
)
479 * struct dma_tx_state - filled in to report the status of
481 * @last: last completed DMA cookie
482 * @used: last issued DMA cookie (i.e. the one in progress)
483 * @residue: the remaining number of bytes left to transmit
484 * on the selected transfer for states DMA_IN_PROGRESS and
485 * DMA_PAUSED if this is implemented in the driver, else 0
487 struct dma_tx_state
{
494 * struct dma_device - info on the entity supplying DMA services
495 * @chancnt: how many DMA channels are supported
496 * @privatecnt: how many DMA channels are requested by dma_request_channel
497 * @channels: the list of struct dma_chan
498 * @global_node: list_head for global dma_device_list
499 * @cap_mask: one or more dma_capability flags
500 * @max_xor: maximum number of xor sources, 0 if no capability
501 * @max_pq: maximum number of PQ sources and PQ-continue capability
502 * @copy_align: alignment shift for memcpy operations
503 * @xor_align: alignment shift for xor operations
504 * @pq_align: alignment shift for pq operations
505 * @fill_align: alignment shift for memset operations
506 * @dev_id: unique device ID
507 * @dev: struct device reference for dma mapping api
508 * @device_alloc_chan_resources: allocate resources and return the
509 * number of allocated descriptors
510 * @device_free_chan_resources: release DMA channel's resources
511 * @device_prep_dma_memcpy: prepares a memcpy operation
512 * @device_prep_dma_xor: prepares a xor operation
513 * @device_prep_dma_xor_val: prepares a xor validation operation
514 * @device_prep_dma_pq: prepares a pq operation
515 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
516 * @device_prep_dma_memset: prepares a memset operation
517 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
518 * @device_prep_slave_sg: prepares a slave dma operation
519 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
520 * The function takes a buffer of size buf_len. The callback function will
521 * be called after period_len bytes have been transferred.
522 * @device_prep_interleaved_dma: Transfer expression in a generic way.
523 * @device_control: manipulate all pending operations on a channel, returns
525 * @device_tx_status: poll for transaction completion, the optional
526 * txstate parameter can be supplied with a pointer to get a
527 * struct with auxiliary transfer status information, otherwise the call
528 * will just return a simple status code
529 * @device_issue_pending: push pending transactions to hardware
533 unsigned int chancnt
;
534 unsigned int privatecnt
;
535 struct list_head channels
;
536 struct list_head global_node
;
537 dma_cap_mask_t cap_mask
;
538 unsigned short max_xor
;
539 unsigned short max_pq
;
544 #define DMA_HAS_PQ_CONTINUE (1 << 15)
549 int (*device_alloc_chan_resources
)(struct dma_chan
*chan
);
550 void (*device_free_chan_resources
)(struct dma_chan
*chan
);
552 struct dma_async_tx_descriptor
*(*device_prep_dma_memcpy
)(
553 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
554 size_t len
, unsigned long flags
);
555 struct dma_async_tx_descriptor
*(*device_prep_dma_xor
)(
556 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
557 unsigned int src_cnt
, size_t len
, unsigned long flags
);
558 struct dma_async_tx_descriptor
*(*device_prep_dma_xor_val
)(
559 struct dma_chan
*chan
, dma_addr_t
*src
, unsigned int src_cnt
,
560 size_t len
, enum sum_check_flags
*result
, unsigned long flags
);
561 struct dma_async_tx_descriptor
*(*device_prep_dma_pq
)(
562 struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
563 unsigned int src_cnt
, const unsigned char *scf
,
564 size_t len
, unsigned long flags
);
565 struct dma_async_tx_descriptor
*(*device_prep_dma_pq_val
)(
566 struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
567 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
568 enum sum_check_flags
*pqres
, unsigned long flags
);
569 struct dma_async_tx_descriptor
*(*device_prep_dma_memset
)(
570 struct dma_chan
*chan
, dma_addr_t dest
, int value
, size_t len
,
571 unsigned long flags
);
572 struct dma_async_tx_descriptor
*(*device_prep_dma_interrupt
)(
573 struct dma_chan
*chan
, unsigned long flags
);
574 struct dma_async_tx_descriptor
*(*device_prep_dma_sg
)(
575 struct dma_chan
*chan
,
576 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
577 struct scatterlist
*src_sg
, unsigned int src_nents
,
578 unsigned long flags
);
580 struct dma_async_tx_descriptor
*(*device_prep_slave_sg
)(
581 struct dma_chan
*chan
, struct scatterlist
*sgl
,
582 unsigned int sg_len
, enum dma_transfer_direction direction
,
583 unsigned long flags
);
584 struct dma_async_tx_descriptor
*(*device_prep_dma_cyclic
)(
585 struct dma_chan
*chan
, dma_addr_t buf_addr
, size_t buf_len
,
586 size_t period_len
, enum dma_transfer_direction direction
);
587 struct dma_async_tx_descriptor
*(*device_prep_interleaved_dma
)(
588 struct dma_chan
*chan
, struct dma_interleaved_template
*xt
,
589 unsigned long flags
);
590 int (*device_control
)(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
593 enum dma_status (*device_tx_status
)(struct dma_chan
*chan
,
595 struct dma_tx_state
*txstate
);
596 void (*device_issue_pending
)(struct dma_chan
*chan
);
599 static inline int dmaengine_device_control(struct dma_chan
*chan
,
600 enum dma_ctrl_cmd cmd
,
603 return chan
->device
->device_control(chan
, cmd
, arg
);
606 static inline int dmaengine_slave_config(struct dma_chan
*chan
,
607 struct dma_slave_config
*config
)
609 return dmaengine_device_control(chan
, DMA_SLAVE_CONFIG
,
610 (unsigned long)config
);
613 static inline struct dma_async_tx_descriptor
*dmaengine_prep_slave_single(
614 struct dma_chan
*chan
, void *buf
, size_t len
,
615 enum dma_transfer_direction dir
, unsigned long flags
)
617 struct scatterlist sg
;
618 sg_init_one(&sg
, buf
, len
);
620 return chan
->device
->device_prep_slave_sg(chan
, &sg
, 1, dir
, flags
);
623 static inline int dmaengine_terminate_all(struct dma_chan
*chan
)
625 return dmaengine_device_control(chan
, DMA_TERMINATE_ALL
, 0);
628 static inline int dmaengine_pause(struct dma_chan
*chan
)
630 return dmaengine_device_control(chan
, DMA_PAUSE
, 0);
633 static inline int dmaengine_resume(struct dma_chan
*chan
)
635 return dmaengine_device_control(chan
, DMA_RESUME
, 0);
638 static inline dma_cookie_t
dmaengine_submit(struct dma_async_tx_descriptor
*desc
)
640 return desc
->tx_submit(desc
);
643 static inline bool dmaengine_check_align(u8 align
, size_t off1
, size_t off2
, size_t len
)
649 mask
= (1 << align
) - 1;
650 if (mask
& (off1
| off2
| len
))
655 static inline bool is_dma_copy_aligned(struct dma_device
*dev
, size_t off1
,
656 size_t off2
, size_t len
)
658 return dmaengine_check_align(dev
->copy_align
, off1
, off2
, len
);
661 static inline bool is_dma_xor_aligned(struct dma_device
*dev
, size_t off1
,
662 size_t off2
, size_t len
)
664 return dmaengine_check_align(dev
->xor_align
, off1
, off2
, len
);
667 static inline bool is_dma_pq_aligned(struct dma_device
*dev
, size_t off1
,
668 size_t off2
, size_t len
)
670 return dmaengine_check_align(dev
->pq_align
, off1
, off2
, len
);
673 static inline bool is_dma_fill_aligned(struct dma_device
*dev
, size_t off1
,
674 size_t off2
, size_t len
)
676 return dmaengine_check_align(dev
->fill_align
, off1
, off2
, len
);
680 dma_set_maxpq(struct dma_device
*dma
, int maxpq
, int has_pq_continue
)
684 dma
->max_pq
|= DMA_HAS_PQ_CONTINUE
;
687 static inline bool dmaf_continue(enum dma_ctrl_flags flags
)
689 return (flags
& DMA_PREP_CONTINUE
) == DMA_PREP_CONTINUE
;
692 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags
)
694 enum dma_ctrl_flags mask
= DMA_PREP_CONTINUE
| DMA_PREP_PQ_DISABLE_P
;
696 return (flags
& mask
) == mask
;
699 static inline bool dma_dev_has_pq_continue(struct dma_device
*dma
)
701 return (dma
->max_pq
& DMA_HAS_PQ_CONTINUE
) == DMA_HAS_PQ_CONTINUE
;
704 static inline unsigned short dma_dev_to_maxpq(struct dma_device
*dma
)
706 return dma
->max_pq
& ~DMA_HAS_PQ_CONTINUE
;
709 /* dma_maxpq - reduce maxpq in the face of continued operations
710 * @dma - dma device with PQ capability
711 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
713 * When an engine does not support native continuation we need 3 extra
714 * source slots to reuse P and Q with the following coefficients:
715 * 1/ {00} * P : remove P from Q', but use it as a source for P'
716 * 2/ {01} * Q : use Q to continue Q' calculation
717 * 3/ {00} * Q : subtract Q from P' to cancel (2)
719 * In the case where P is disabled we only need 1 extra source:
720 * 1/ {01} * Q : use Q to continue Q' calculation
722 static inline int dma_maxpq(struct dma_device
*dma
, enum dma_ctrl_flags flags
)
724 if (dma_dev_has_pq_continue(dma
) || !dmaf_continue(flags
))
725 return dma_dev_to_maxpq(dma
);
726 else if (dmaf_p_disabled_continue(flags
))
727 return dma_dev_to_maxpq(dma
) - 1;
728 else if (dmaf_continue(flags
))
729 return dma_dev_to_maxpq(dma
) - 3;
733 /* --- public DMA engine API --- */
735 #ifdef CONFIG_DMA_ENGINE
736 void dmaengine_get(void);
737 void dmaengine_put(void);
739 static inline void dmaengine_get(void)
742 static inline void dmaengine_put(void)
747 #ifdef CONFIG_NET_DMA
748 #define net_dmaengine_get() dmaengine_get()
749 #define net_dmaengine_put() dmaengine_put()
751 static inline void net_dmaengine_get(void)
754 static inline void net_dmaengine_put(void)
759 #ifdef CONFIG_ASYNC_TX_DMA
760 #define async_dmaengine_get() dmaengine_get()
761 #define async_dmaengine_put() dmaengine_put()
762 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
763 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
765 #define async_dma_find_channel(type) dma_find_channel(type)
766 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
768 static inline void async_dmaengine_get(void)
771 static inline void async_dmaengine_put(void)
774 static inline struct dma_chan
*
775 async_dma_find_channel(enum dma_transaction_type type
)
779 #endif /* CONFIG_ASYNC_TX_DMA */
781 dma_cookie_t
dma_async_memcpy_buf_to_buf(struct dma_chan
*chan
,
782 void *dest
, void *src
, size_t len
);
783 dma_cookie_t
dma_async_memcpy_buf_to_pg(struct dma_chan
*chan
,
784 struct page
*page
, unsigned int offset
, void *kdata
, size_t len
);
785 dma_cookie_t
dma_async_memcpy_pg_to_pg(struct dma_chan
*chan
,
786 struct page
*dest_pg
, unsigned int dest_off
, struct page
*src_pg
,
787 unsigned int src_off
, size_t len
);
788 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor
*tx
,
789 struct dma_chan
*chan
);
791 static inline void async_tx_ack(struct dma_async_tx_descriptor
*tx
)
793 tx
->flags
|= DMA_CTRL_ACK
;
796 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor
*tx
)
798 tx
->flags
&= ~DMA_CTRL_ACK
;
801 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor
*tx
)
803 return (tx
->flags
& DMA_CTRL_ACK
) == DMA_CTRL_ACK
;
806 #define first_dma_cap(mask) __first_dma_cap(&(mask))
807 static inline int __first_dma_cap(const dma_cap_mask_t
*srcp
)
809 return min_t(int, DMA_TX_TYPE_END
,
810 find_first_bit(srcp
->bits
, DMA_TX_TYPE_END
));
813 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
814 static inline int __next_dma_cap(int n
, const dma_cap_mask_t
*srcp
)
816 return min_t(int, DMA_TX_TYPE_END
,
817 find_next_bit(srcp
->bits
, DMA_TX_TYPE_END
, n
+1));
820 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
822 __dma_cap_set(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
824 set_bit(tx_type
, dstp
->bits
);
827 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
829 __dma_cap_clear(enum dma_transaction_type tx_type
, dma_cap_mask_t
*dstp
)
831 clear_bit(tx_type
, dstp
->bits
);
834 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
835 static inline void __dma_cap_zero(dma_cap_mask_t
*dstp
)
837 bitmap_zero(dstp
->bits
, DMA_TX_TYPE_END
);
840 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
842 __dma_has_cap(enum dma_transaction_type tx_type
, dma_cap_mask_t
*srcp
)
844 return test_bit(tx_type
, srcp
->bits
);
847 #define for_each_dma_cap_mask(cap, mask) \
848 for ((cap) = first_dma_cap(mask); \
849 (cap) < DMA_TX_TYPE_END; \
850 (cap) = next_dma_cap((cap), (mask)))
853 * dma_async_issue_pending - flush pending transactions to HW
854 * @chan: target DMA channel
856 * This allows drivers to push copies to HW in batches,
857 * reducing MMIO writes where possible.
859 static inline void dma_async_issue_pending(struct dma_chan
*chan
)
861 chan
->device
->device_issue_pending(chan
);
864 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
867 * dma_async_is_tx_complete - poll for transaction completion
869 * @cookie: transaction identifier to check status of
870 * @last: returns last completed cookie, can be NULL
871 * @used: returns last issued cookie, can be NULL
873 * If @last and @used are passed in, upon return they reflect the driver
874 * internal state and can be used with dma_async_is_complete() to check
875 * the status of multiple cookies without re-checking hardware state.
877 static inline enum dma_status
dma_async_is_tx_complete(struct dma_chan
*chan
,
878 dma_cookie_t cookie
, dma_cookie_t
*last
, dma_cookie_t
*used
)
880 struct dma_tx_state state
;
881 enum dma_status status
;
883 status
= chan
->device
->device_tx_status(chan
, cookie
, &state
);
891 #define dma_async_memcpy_complete(chan, cookie, last, used)\
892 dma_async_is_tx_complete(chan, cookie, last, used)
895 * dma_async_is_complete - test a cookie against chan state
896 * @cookie: transaction identifier to test status of
897 * @last_complete: last know completed transaction
898 * @last_used: last cookie value handed out
900 * dma_async_is_complete() is used in dma_async_memcpy_complete()
901 * the test logic is separated for lightweight testing of multiple cookies
903 static inline enum dma_status
dma_async_is_complete(dma_cookie_t cookie
,
904 dma_cookie_t last_complete
, dma_cookie_t last_used
)
906 if (last_complete
<= last_used
) {
907 if ((cookie
<= last_complete
) || (cookie
> last_used
))
910 if ((cookie
<= last_complete
) && (cookie
> last_used
))
913 return DMA_IN_PROGRESS
;
917 dma_set_tx_state(struct dma_tx_state
*st
, dma_cookie_t last
, dma_cookie_t used
, u32 residue
)
922 st
->residue
= residue
;
926 enum dma_status
dma_sync_wait(struct dma_chan
*chan
, dma_cookie_t cookie
);
927 #ifdef CONFIG_DMA_ENGINE
928 enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
);
929 void dma_issue_pending_all(void);
930 struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
, dma_filter_fn fn
, void *fn_param
);
931 void dma_release_channel(struct dma_chan
*chan
);
933 static inline enum dma_status
dma_wait_for_async_tx(struct dma_async_tx_descriptor
*tx
)
937 static inline void dma_issue_pending_all(void)
940 static inline struct dma_chan
*__dma_request_channel(dma_cap_mask_t
*mask
,
941 dma_filter_fn fn
, void *fn_param
)
945 static inline void dma_release_channel(struct dma_chan
*chan
)
950 /* --- DMA device --- */
952 int dma_async_device_register(struct dma_device
*device
);
953 void dma_async_device_unregister(struct dma_device
*device
);
954 void dma_run_dependencies(struct dma_async_tx_descriptor
*tx
);
955 struct dma_chan
*dma_find_channel(enum dma_transaction_type tx_type
);
956 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
958 /* --- Helper iov-locking functions --- */
960 struct dma_page_list
{
961 char __user
*base_address
;
966 struct dma_pinned_list
{
968 struct dma_page_list page_list
[0];
971 struct dma_pinned_list
*dma_pin_iovec_pages(struct iovec
*iov
, size_t len
);
972 void dma_unpin_iovec_pages(struct dma_pinned_list
* pinned_list
);
974 dma_cookie_t
dma_memcpy_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
975 struct dma_pinned_list
*pinned_list
, unsigned char *kdata
, size_t len
);
976 dma_cookie_t
dma_memcpy_pg_to_iovec(struct dma_chan
*chan
, struct iovec
*iov
,
977 struct dma_pinned_list
*pinned_list
, struct page
*page
,
978 unsigned int offset
, size_t len
);
980 #endif /* DMAENGINE_H */