2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/types.h>
25 __u64 cap
; /* Controller Capabilities */
26 __u32 vs
; /* Version */
27 __u32 intms
; /* Interrupt Mask Set */
28 __u32 intmc
; /* Interrupt Mask Clear */
29 __u32 cc
; /* Controller Configuration */
30 __u32 rsvd1
; /* Reserved */
31 __u32 csts
; /* Controller Status */
32 __u32 rsvd2
; /* Reserved */
33 __u32 aqa
; /* Admin Queue Attributes */
34 __u64 asq
; /* Admin SQ Base Address */
35 __u64 acq
; /* Admin CQ Base Address */
38 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
39 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
40 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
41 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
44 NVME_CC_ENABLE
= 1 << 0,
45 NVME_CC_CSS_NVM
= 0 << 4,
46 NVME_CC_MPS_SHIFT
= 7,
47 NVME_CC_ARB_RR
= 0 << 11,
48 NVME_CC_ARB_WRRU
= 1 << 11,
49 NVME_CC_ARB_VS
= 7 << 11,
50 NVME_CC_SHN_NONE
= 0 << 14,
51 NVME_CC_SHN_NORMAL
= 1 << 14,
52 NVME_CC_SHN_ABRUPT
= 2 << 14,
53 NVME_CC_IOSQES
= 6 << 16,
54 NVME_CC_IOCQES
= 4 << 20,
55 NVME_CSTS_RDY
= 1 << 0,
56 NVME_CSTS_CFS
= 1 << 1,
57 NVME_CSTS_SHST_NORMAL
= 0 << 2,
58 NVME_CSTS_SHST_OCCUR
= 1 << 2,
59 NVME_CSTS_SHST_CMPLT
= 2 << 2,
62 struct nvme_id_power_state
{
63 __le16 max_power
; /* centiwatts */
65 __le32 entry_lat
; /* microseconds */
66 __le32 exit_lat
; /* microseconds */
74 #define NVME_VS(major, minor) (major << 16 | minor)
106 struct nvme_id_power_state psd
[32];
127 struct nvme_lbaf lbaf
[16];
133 NVME_NS_FEAT_THIN
= 1 << 0,
134 NVME_LBAF_RP_BEST
= 0,
135 NVME_LBAF_RP_BETTER
= 1,
136 NVME_LBAF_RP_GOOD
= 2,
137 NVME_LBAF_RP_DEGRADED
= 3,
140 struct nvme_smart_log
{
141 __u8 critical_warning
;
147 __u8 data_units_read
[16];
148 __u8 data_units_written
[16];
150 __u8 host_writes
[16];
151 __u8 ctrl_busy_time
[16];
152 __u8 power_cycles
[16];
153 __u8 power_on_hours
[16];
154 __u8 unsafe_shutdowns
[16];
155 __u8 media_errors
[16];
156 __u8 num_err_log_entries
[16];
161 NVME_SMART_CRIT_SPARE
= 1 << 0,
162 NVME_SMART_CRIT_TEMPERATURE
= 1 << 1,
163 NVME_SMART_CRIT_RELIABILITY
= 1 << 2,
164 NVME_SMART_CRIT_MEDIA
= 1 << 3,
165 NVME_SMART_CRIT_VOLATILE_MEMORY
= 1 << 4,
168 struct nvme_lba_range_type
{
179 NVME_LBART_TYPE_FS
= 0x01,
180 NVME_LBART_TYPE_RAID
= 0x02,
181 NVME_LBART_TYPE_CACHE
= 0x03,
182 NVME_LBART_TYPE_SWAP
= 0x04,
184 NVME_LBART_ATTRIB_TEMP
= 1 << 0,
185 NVME_LBART_ATTRIB_HIDE
= 1 << 1,
191 nvme_cmd_flush
= 0x00,
192 nvme_cmd_write
= 0x01,
193 nvme_cmd_read
= 0x02,
194 nvme_cmd_write_uncor
= 0x04,
195 nvme_cmd_compare
= 0x05,
199 struct nvme_common_command
{
211 struct nvme_rw_command
{
230 NVME_RW_LR
= 1 << 15,
231 NVME_RW_FUA
= 1 << 14,
232 NVME_RW_DSM_FREQ_UNSPEC
= 0,
233 NVME_RW_DSM_FREQ_TYPICAL
= 1,
234 NVME_RW_DSM_FREQ_RARE
= 2,
235 NVME_RW_DSM_FREQ_READS
= 3,
236 NVME_RW_DSM_FREQ_WRITES
= 4,
237 NVME_RW_DSM_FREQ_RW
= 5,
238 NVME_RW_DSM_FREQ_ONCE
= 6,
239 NVME_RW_DSM_FREQ_PREFETCH
= 7,
240 NVME_RW_DSM_FREQ_TEMP
= 8,
241 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
242 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
243 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
244 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
245 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
246 NVME_RW_DSM_COMPRESSED
= 1 << 7,
251 enum nvme_admin_opcode
{
252 nvme_admin_delete_sq
= 0x00,
253 nvme_admin_create_sq
= 0x01,
254 nvme_admin_get_log_page
= 0x02,
255 nvme_admin_delete_cq
= 0x04,
256 nvme_admin_create_cq
= 0x05,
257 nvme_admin_identify
= 0x06,
258 nvme_admin_abort_cmd
= 0x08,
259 nvme_admin_set_features
= 0x09,
260 nvme_admin_get_features
= 0x0a,
261 nvme_admin_async_event
= 0x0c,
262 nvme_admin_activate_fw
= 0x10,
263 nvme_admin_download_fw
= 0x11,
264 nvme_admin_format_nvm
= 0x80,
265 nvme_admin_security_send
= 0x81,
266 nvme_admin_security_recv
= 0x82,
270 NVME_QUEUE_PHYS_CONTIG
= (1 << 0),
271 NVME_CQ_IRQ_ENABLED
= (1 << 1),
272 NVME_SQ_PRIO_URGENT
= (0 << 1),
273 NVME_SQ_PRIO_HIGH
= (1 << 1),
274 NVME_SQ_PRIO_MEDIUM
= (2 << 1),
275 NVME_SQ_PRIO_LOW
= (3 << 1),
276 NVME_FEAT_ARBITRATION
= 0x01,
277 NVME_FEAT_POWER_MGMT
= 0x02,
278 NVME_FEAT_LBA_RANGE
= 0x03,
279 NVME_FEAT_TEMP_THRESH
= 0x04,
280 NVME_FEAT_ERR_RECOVERY
= 0x05,
281 NVME_FEAT_VOLATILE_WC
= 0x06,
282 NVME_FEAT_NUM_QUEUES
= 0x07,
283 NVME_FEAT_IRQ_COALESCE
= 0x08,
284 NVME_FEAT_IRQ_CONFIG
= 0x09,
285 NVME_FEAT_WRITE_ATOMIC
= 0x0a,
286 NVME_FEAT_ASYNC_EVENT
= 0x0b,
287 NVME_FEAT_SW_PROGRESS
= 0x0c,
290 struct nvme_identify
{
302 struct nvme_features
{
315 struct nvme_create_cq
{
329 struct nvme_create_sq
{
343 struct nvme_delete_queue
{
353 struct nvme_download_firmware
{
365 struct nvme_command
{
367 struct nvme_common_command common
;
368 struct nvme_rw_command rw
;
369 struct nvme_identify identify
;
370 struct nvme_features features
;
371 struct nvme_create_cq create_cq
;
372 struct nvme_create_sq create_sq
;
373 struct nvme_delete_queue delete_queue
;
374 struct nvme_download_firmware dlfw
;
379 NVME_SC_SUCCESS
= 0x0,
380 NVME_SC_INVALID_OPCODE
= 0x1,
381 NVME_SC_INVALID_FIELD
= 0x2,
382 NVME_SC_CMDID_CONFLICT
= 0x3,
383 NVME_SC_DATA_XFER_ERROR
= 0x4,
384 NVME_SC_POWER_LOSS
= 0x5,
385 NVME_SC_INTERNAL
= 0x6,
386 NVME_SC_ABORT_REQ
= 0x7,
387 NVME_SC_ABORT_QUEUE
= 0x8,
388 NVME_SC_FUSED_FAIL
= 0x9,
389 NVME_SC_FUSED_MISSING
= 0xa,
390 NVME_SC_INVALID_NS
= 0xb,
391 NVME_SC_LBA_RANGE
= 0x80,
392 NVME_SC_CAP_EXCEEDED
= 0x81,
393 NVME_SC_NS_NOT_READY
= 0x82,
394 NVME_SC_CQ_INVALID
= 0x100,
395 NVME_SC_QID_INVALID
= 0x101,
396 NVME_SC_QUEUE_SIZE
= 0x102,
397 NVME_SC_ABORT_LIMIT
= 0x103,
398 NVME_SC_ABORT_MISSING
= 0x104,
399 NVME_SC_ASYNC_LIMIT
= 0x105,
400 NVME_SC_FIRMWARE_SLOT
= 0x106,
401 NVME_SC_FIRMWARE_IMAGE
= 0x107,
402 NVME_SC_INVALID_VECTOR
= 0x108,
403 NVME_SC_INVALID_LOG_PAGE
= 0x109,
404 NVME_SC_INVALID_FORMAT
= 0x10a,
405 NVME_SC_BAD_ATTRIBUTES
= 0x180,
406 NVME_SC_WRITE_FAULT
= 0x280,
407 NVME_SC_READ_ERROR
= 0x281,
408 NVME_SC_GUARD_CHECK
= 0x282,
409 NVME_SC_APPTAG_CHECK
= 0x283,
410 NVME_SC_REFTAG_CHECK
= 0x284,
411 NVME_SC_COMPARE_FAILED
= 0x285,
412 NVME_SC_ACCESS_DENIED
= 0x286,
415 struct nvme_completion
{
416 __le32 result
; /* Used by admin commands to return data */
418 __le16 sq_head
; /* how much of this queue may be reclaimed */
419 __le16 sq_id
; /* submission queue that generated this entry */
420 __u16 command_id
; /* of the command which completed */
421 __le16 status
; /* did the command fail, and if so, why? */
424 struct nvme_user_io
{
439 struct nvme_admin_cmd
{
460 #define NVME_IOCTL_ID _IO('N', 0x40)
461 #define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
462 #define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
464 #endif /* _LINUX_NVME_H */