1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #ifndef __FCOE_COMMON__
10 #define __FCOE_COMMON__
11 /*********************/
12 /* FCOE FW CONSTANTS */
13 /*********************/
15 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
17 struct fcoe_abts_pkt
{
18 __le32 abts_rsp_fc_payload_lo
;
19 __le16 abts_rsp_rx_id
;
24 /* FCoE additional WQE (Sq/XferQ) information */
25 union fcoe_additional_info_union
{
29 __le32 seq_rec_updated_offset
;
37 union fcoe_cleanup_addr_exp_ro_union
{
38 struct regpair abts_rsp_fc_payload_hi
;
39 struct fcoe_exp_ro exp_ro
;
42 /* FCoE Ramrod Command IDs */
43 enum fcoe_completion_status
{
44 FCOE_COMPLETION_STATUS_SUCCESS
,
45 FCOE_COMPLETION_STATUS_FCOE_VER_ERR
,
46 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR
,
47 MAX_FCOE_COMPLETION_STATUS
56 /* FCoE connection offload */
57 struct fcoe_conn_offload_ramrod_data
{
58 struct regpair sq_pbl_addr
;
59 struct regpair sq_curr_page_addr
;
60 struct regpair sq_next_page_addr
;
61 struct regpair xferq_pbl_addr
;
62 struct regpair xferq_curr_page_addr
;
63 struct regpair xferq_next_page_addr
;
64 struct regpair respq_pbl_addr
;
65 struct regpair respq_curr_page_addr
;
66 struct regpair respq_next_page_addr
;
67 __le16 dst_mac_addr_lo
;
68 __le16 dst_mac_addr_mid
;
69 __le16 dst_mac_addr_hi
;
70 __le16 src_mac_addr_lo
;
71 __le16 src_mac_addr_mid
;
72 __le16 src_mac_addr_hi
;
73 __le16 tx_max_fc_pay_len
;
74 __le16 e_d_tov_timer_val
;
75 __le16 rx_max_fc_pay_len
;
77 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
78 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
79 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
80 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
81 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
82 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
84 __le16 rec_rr_tov_timer_val
;
85 struct fc_addr_nw s_id
;
87 struct fc_addr_nw d_id
;
89 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
90 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
91 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
92 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
93 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
94 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
95 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
96 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
97 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
98 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
99 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
100 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
106 /* FCoE terminate connection request */
107 struct fcoe_conn_terminate_ramrod_data
{
108 struct regpair terminate_params_addr
;
111 struct fcoe_slow_sgl_ctx
{
112 struct regpair base_sgl_addr
;
114 __le16 remainder_num_sges
;
115 __le16 curr_sgl_index
;
119 union fcoe_dix_desc_ctx
{
120 struct fcoe_slow_sgl_ctx dix_sgl
;
121 struct scsi_sge cached_dix_sge
;
124 struct fcoe_fast_sgl_ctx
{
125 struct regpair sgl_start_addr
;
126 __le32 sgl_byte_offset
;
127 __le16 task_reuse_cnt
;
128 __le16 init_offset_in_first_sge
;
131 struct fcoe_fcp_cmd_payload
{
135 struct fcoe_fcp_rsp_payload
{
139 struct fcoe_fcp_xfer_payload
{
143 /* FCoE firmware function init */
144 struct fcoe_init_func_ramrod_data
{
145 struct scsi_init_func_params func_params
;
146 struct scsi_init_func_queues q_params
;
148 __le16 sq_num_pages_in_pbl
;
152 /* FCoE: Mode of the connection: Target or Initiator or both */
153 enum fcoe_mode_type
{
154 FCOE_INITIATOR_MODE
= 0x0,
155 FCOE_TARGET_MODE
= 0x1,
156 FCOE_BOTH_OR_NOT_CHOSEN
= 0x3,
160 struct fcoe_rx_stat
{
161 struct regpair fcoe_rx_byte_cnt
;
162 struct regpair fcoe_rx_data_pkt_cnt
;
163 struct regpair fcoe_rx_xfer_pkt_cnt
;
164 struct regpair fcoe_rx_other_pkt_cnt
;
165 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt
;
166 __le32 fcoe_silent_drop_pkt_rq_full_cnt
;
167 __le32 fcoe_silent_drop_pkt_crc_error_cnt
;
168 __le32 fcoe_silent_drop_pkt_task_invalid_cnt
;
169 __le32 fcoe_silent_drop_total_pkt_cnt
;
173 struct fcoe_stat_ramrod_data
{
174 struct regpair stat_params_addr
;
177 struct protection_info_ctx
{
179 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
180 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
181 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
182 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
183 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
184 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
185 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
186 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
187 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
188 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
189 #define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
190 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
195 union protection_info_union_ctx
{
196 struct protection_info_ctx info
;
200 struct fcp_rsp_payload_padded
{
201 struct fcoe_fcp_rsp_payload rsp_payload
;
205 struct fcp_xfer_payload_padded
{
206 struct fcoe_fcp_xfer_payload xfer_payload
;
210 struct fcoe_tx_data_params
{
214 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
215 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
216 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
217 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
218 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
219 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
220 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
221 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
224 __le16 single_sge_saved_offset
;
225 __le16 next_dif_offset
;
230 struct fcoe_tx_mid_path_params
{
240 struct fcoe_tx_params
{
241 struct fcoe_tx_data_params data
;
242 struct fcoe_tx_mid_path_params mid_path
;
245 union fcoe_tx_info_union_ctx
{
246 struct fcoe_fcp_cmd_payload fcp_cmd_payload
;
247 struct fcp_rsp_payload_padded fcp_rsp_payload
;
248 struct fcp_xfer_payload_padded fcp_xfer_payload
;
249 struct fcoe_tx_params tx_params
;
252 struct ystorm_fcoe_task_st_ctx
{
255 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
256 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
257 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
258 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
260 u8 expect_first_xfer
;
261 __le32 num_pbf_zero_write
;
262 union protection_info_union_ctx protection_info_union
;
263 __le32 data_2_trns_rem
;
264 struct scsi_sgl_params sgl_params
;
266 union fcoe_tx_info_union_ctx tx_info_union
;
267 union fcoe_dix_desc_ctx dix_desc
;
268 struct scsi_cached_sges data_desc
;
271 __le32 task_rety_identifier
;
275 struct ystorm_fcoe_task_ag_ctx
{
280 #define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
281 #define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
282 #define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
283 #define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
284 #define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
285 #define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
286 #define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
287 #define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
288 #define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
289 #define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
291 #define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
292 #define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
293 #define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
294 #define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
295 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
296 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
297 #define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
298 #define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
299 #define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
300 #define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
302 #define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
303 #define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
304 #define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
305 #define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
306 #define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
307 #define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
308 #define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
309 #define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
310 #define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
311 #define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
312 #define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
313 #define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
314 #define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
315 #define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
316 #define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
317 #define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
331 struct tstorm_fcoe_task_ag_ctx
{
336 #define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
337 #define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
338 #define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
339 #define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
340 #define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
341 #define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
342 #define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
343 #define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
344 #define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
345 #define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
347 #define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
348 #define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
349 #define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
350 #define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
351 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
352 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
353 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
354 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
355 #define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
356 #define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
358 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
359 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
360 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
361 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
362 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
363 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
364 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
365 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
367 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
368 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
369 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
370 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
371 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
372 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
373 #define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
374 #define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
375 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
376 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
377 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
378 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
379 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
380 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
382 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
383 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
384 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
385 #define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
386 #define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
387 #define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
388 #define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
389 #define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
390 #define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
391 #define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
392 #define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
393 #define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
394 #define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
395 #define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
396 #define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
397 #define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
399 __le16 last_sent_tid
;
400 __le32 rec_rr_tov_exp_timeout
;
406 __le32 data_offset_end_of_seq
;
407 __le32 data_offset_next
;
410 struct fcoe_tstorm_fcoe_task_st_ctx_read_write
{
411 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union
;
413 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
414 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
415 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
416 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
417 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
418 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
419 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
420 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
421 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
422 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
423 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
424 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
425 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
426 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
427 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
428 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
433 struct fcoe_abts_pkt abts_data
;
434 __le32 e_d_tov_exp_timeout_val
;
435 __le16 ooo_rx_seq_cnt
;
439 struct fcoe_tstorm_fcoe_task_st_ctx_read_only
{
445 __le32 fcp_cmd_trns_size
;
449 struct tstorm_fcoe_task_st_ctx
{
450 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write
;
451 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only
;
454 struct mstorm_fcoe_task_ag_ctx
{
459 #define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
460 #define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
461 #define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
462 #define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
463 #define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
464 #define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
465 #define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
466 #define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
467 #define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
468 #define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
470 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
471 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
472 #define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
473 #define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
474 #define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
475 #define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
476 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
477 #define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
478 #define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
479 #define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
481 #define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
482 #define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
483 #define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
484 #define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
485 #define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
486 #define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
487 #define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
488 #define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
489 #define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
490 #define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
491 #define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
492 #define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
493 #define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
494 #define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
495 #define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
496 #define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
498 __le32 received_bytes
;
506 __le32 expected_bytes
;
510 struct mstorm_fcoe_task_st_ctx
{
511 struct regpair rsp_buf_addr
;
513 struct scsi_sgl_params sgl_params
;
514 __le32 data_2_trns_rem
;
515 __le32 data_buffer_offset
;
518 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
519 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
520 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
521 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
522 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
523 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
524 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
525 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
526 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
527 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
528 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
529 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
530 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
531 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
532 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
533 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
534 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
535 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
536 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
537 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
538 struct scsi_cached_sges data_desc
;
541 struct ustorm_fcoe_task_ag_ctx
{
546 #define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
547 #define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
548 #define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
549 #define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
550 #define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
551 #define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
552 #define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
553 #define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
555 #define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
556 #define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
557 #define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
558 #define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
559 #define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
560 #define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
561 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
562 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
564 #define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
565 #define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
566 #define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
567 #define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
568 #define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
569 #define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
570 #define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
571 #define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
572 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
573 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
574 #define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
575 #define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
576 #define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
577 #define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
578 #define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
579 #define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
581 #define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
582 #define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
583 #define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
584 #define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
585 #define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
586 #define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
587 #define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
588 #define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
589 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
590 #define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
591 __le32 dif_err_intervals
;
592 __le32 dif_error_1st_interval
;
593 __le32 global_cq_num
;
599 struct fcoe_task_context
{
600 struct ystorm_fcoe_task_st_ctx ystorm_st_context
;
601 struct regpair ystorm_st_padding
[2];
602 struct tdif_task_context tdif_context
;
603 struct ystorm_fcoe_task_ag_ctx ystorm_ag_context
;
604 struct tstorm_fcoe_task_ag_ctx tstorm_ag_context
;
605 struct timers_context timer_context
;
606 struct tstorm_fcoe_task_st_ctx tstorm_st_context
;
607 struct regpair tstorm_st_padding
[2];
608 struct mstorm_fcoe_task_ag_ctx mstorm_ag_context
;
609 struct mstorm_fcoe_task_st_ctx mstorm_st_context
;
610 struct ustorm_fcoe_task_ag_ctx ustorm_ag_context
;
611 struct rdif_task_context rdif_context
;
614 struct fcoe_tx_stat
{
615 struct regpair fcoe_tx_byte_cnt
;
616 struct regpair fcoe_tx_data_pkt_cnt
;
617 struct regpair fcoe_tx_xfer_pkt_cnt
;
618 struct regpair fcoe_tx_other_pkt_cnt
;
624 #define FCOE_WQE_REQ_TYPE_MASK 0xF
625 #define FCOE_WQE_REQ_TYPE_SHIFT 0
626 #define FCOE_WQE_SGL_MODE_MASK 0x1
627 #define FCOE_WQE_SGL_MODE_SHIFT 4
628 #define FCOE_WQE_CONTINUATION_MASK 0x1
629 #define FCOE_WQE_CONTINUATION_SHIFT 5
630 #define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
631 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
632 #define FCOE_WQE_RESERVED_MASK 0x1
633 #define FCOE_WQE_RESERVED_SHIFT 7
634 #define FCOE_WQE_NUM_SGES_MASK 0xF
635 #define FCOE_WQE_NUM_SGES_SHIFT 8
636 #define FCOE_WQE_RESERVED1_MASK 0xF
637 #define FCOE_WQE_RESERVED1_SHIFT 12
638 union fcoe_additional_info_union additional_info_union
;
641 struct xfrqe_prot_flags
{
643 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
644 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
645 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
646 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
647 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
648 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
649 #define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
650 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
653 struct fcoe_db_data
{
655 #define FCOE_DB_DATA_DEST_MASK 0x3
656 #define FCOE_DB_DATA_DEST_SHIFT 0
657 #define FCOE_DB_DATA_AGG_CMD_MASK 0x3
658 #define FCOE_DB_DATA_AGG_CMD_SHIFT 2
659 #define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
660 #define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
661 #define FCOE_DB_DATA_RESERVED_MASK 0x1
662 #define FCOE_DB_DATA_RESERVED_SHIFT 5
663 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
664 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
668 #endif /* __FCOE_COMMON__ */