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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - include/linux/sh_clk.h
4 #include <linux/list.h>
5 #include <linux/seq_file.h>
6 #include <linux/cpufreq.h>
7 #include <linux/types.h>
8 #include <linux/kref.h>
10 #include <linux/err.h>
23 #ifdef CONFIG_SH_CLK_CPG_LEGACY
24 void (*init
)(struct clk
*clk
);
26 int (*enable
)(struct clk
*clk
);
27 void (*disable
)(struct clk
*clk
);
28 unsigned long (*recalc
)(struct clk
*clk
);
29 int (*set_rate
)(struct clk
*clk
, unsigned long rate
);
30 int (*set_parent
)(struct clk
*clk
, struct clk
*parent
);
31 long (*round_rate
)(struct clk
*clk
, unsigned long rate
);
35 struct list_head node
;
37 struct clk
**parent_table
; /* list of parents to */
38 unsigned short parent_num
; /* choose between */
39 unsigned char src_shift
; /* source clock field in the */
40 unsigned char src_width
; /* configuration register */
41 struct sh_clk_ops
*ops
;
43 struct list_head children
;
44 struct list_head sibling
; /* node for children */
51 void __iomem
*enable_reg
;
52 unsigned int enable_bit
;
53 void __iomem
*mapped_reg
;
55 unsigned long arch_flags
;
57 struct clk_mapping
*mapping
;
58 struct cpufreq_frequency_table
*freq_table
;
59 unsigned int nr_freqs
;
62 #define CLK_ENABLE_ON_INIT BIT(0)
64 #define CLK_ENABLE_REG_32BIT BIT(1) /* default access size */
65 #define CLK_ENABLE_REG_16BIT BIT(2)
66 #define CLK_ENABLE_REG_8BIT BIT(3)
68 #define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
69 CLK_ENABLE_REG_16BIT | \
72 /* drivers/sh/clk.c */
73 unsigned long followparent_recalc(struct clk
*);
74 void recalculate_root_clocks(void);
75 void propagate_rate(struct clk
*);
76 int clk_reparent(struct clk
*child
, struct clk
*parent
);
77 int clk_register(struct clk
*);
78 void clk_unregister(struct clk
*);
79 void clk_enable_init_clocks(void);
81 struct clk_div_mult_table
{
82 unsigned int *divisors
;
83 unsigned int nr_divisors
;
84 unsigned int *multipliers
;
85 unsigned int nr_multipliers
;
88 struct cpufreq_frequency_table
;
89 void clk_rate_table_build(struct clk
*clk
,
90 struct cpufreq_frequency_table
*freq_table
,
92 struct clk_div_mult_table
*src_table
,
93 unsigned long *bitmap
);
95 long clk_rate_table_round(struct clk
*clk
,
96 struct cpufreq_frequency_table
*freq_table
,
99 int clk_rate_table_find(struct clk
*clk
,
100 struct cpufreq_frequency_table
*freq_table
,
103 long clk_rate_div_range_round(struct clk
*clk
, unsigned int div_min
,
104 unsigned int div_max
, unsigned long rate
);
106 long clk_rate_mult_range_round(struct clk
*clk
, unsigned int mult_min
,
107 unsigned int mult_max
, unsigned long rate
);
109 long clk_round_parent(struct clk
*clk
, unsigned long target
,
110 unsigned long *best_freq
, unsigned long *parent_freq
,
111 unsigned int div_min
, unsigned int div_max
);
113 #define SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) \
116 .enable_reg = (void __iomem *)_enable_reg, \
117 .enable_bit = _enable_bit, \
121 #define SH_CLK_MSTP32(_p, _r, _b, _f) \
122 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT)
124 #define SH_CLK_MSTP16(_p, _r, _b, _f) \
125 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT)
127 #define SH_CLK_MSTP8(_p, _r, _b, _f) \
128 SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT)
130 int sh_clk_mstp_register(struct clk
*clks
, int nr
);
133 * MSTP registration never really cared about access size, despite the
134 * original enable/disable pairs assuming a 32-bit access. Clocks are
135 * responsible for defining their access sizes either directly or via the
136 * clock definition wrappers.
138 static inline int __deprecated
sh_clk_mstp32_register(struct clk
*clks
, int nr
)
140 return sh_clk_mstp_register(clks
, nr
);
143 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
146 .enable_reg = (void __iomem *)_reg, \
147 .enable_bit = _shift, \
148 .arch_flags = _div_bitmap, \
152 struct clk_div4_table
{
153 struct clk_div_mult_table
*div_mult_table
;
154 void (*kick
)(struct clk
*clk
);
157 int sh_clk_div4_register(struct clk
*clks
, int nr
,
158 struct clk_div4_table
*table
);
159 int sh_clk_div4_enable_register(struct clk
*clks
, int nr
,
160 struct clk_div4_table
*table
);
161 int sh_clk_div4_reparent_register(struct clk
*clks
, int nr
,
162 struct clk_div4_table
*table
);
164 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
165 _num_parents, _src_shift, _src_width) \
167 .enable_reg = (void __iomem *)_reg, \
169 .parent_table = _parents, \
170 .parent_num = _num_parents, \
171 .src_shift = _src_shift, \
172 .src_width = _src_width, \
175 #define SH_CLK_DIV6(_parent, _reg, _flags) \
178 .enable_reg = (void __iomem *)_reg, \
182 int sh_clk_div6_register(struct clk
*clks
, int nr
);
183 int sh_clk_div6_reparent_register(struct clk
*clks
, int nr
);
185 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
186 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
187 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
189 #endif /* __SH_CLOCK_H */