4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
24 #include "qapi/error.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
31 #include "exec/exec-all.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
37 #include "trace/control.h"
38 #include "glib-compat.h"
43 static const char *filename
;
44 static const char *argv0
;
45 static int gdbstub_port
;
46 static envlist_t
*envlist
;
47 static const char *cpu_model
;
48 unsigned long mmap_min_addr
;
49 unsigned long guest_base
;
52 #define EXCP_DUMP(env, fmt, ...) \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
72 /* MIPS only supports 31 bits of virtual address space for user space */
73 unsigned long reserved_va
= 0x77000000;
75 unsigned long reserved_va
= 0xf7000000;
78 unsigned long reserved_va
;
81 static void usage(int exitcode
);
83 static const char *interp_prefix
= CONFIG_QEMU_INTERP_PREFIX
;
84 const char *qemu_uname_release
;
86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
89 unsigned long guest_stack_size
= 8 * 1024 * 1024UL;
91 void gemu_log(const char *fmt
, ...)
96 vfprintf(stderr
, fmt
, ap
);
100 #if defined(TARGET_I386)
101 int cpu_get_pic_interrupt(CPUX86State
*env
)
107 /***********************************************************/
108 /* Helper routines for implementing atomic operations. */
110 /* Make sure everything is in a consistent state for calling fork(). */
111 void fork_start(void)
114 qemu_mutex_lock(&tcg_ctx
.tb_ctx
.tb_lock
);
118 void fork_end(int child
)
120 mmap_fork_end(child
);
122 CPUState
*cpu
, *next_cpu
;
123 /* Child processes created by fork() only have a single thread.
124 Discard information about the parent threads. */
125 CPU_FOREACH_SAFE(cpu
, next_cpu
) {
126 if (cpu
!= thread_cpu
) {
127 QTAILQ_REMOVE(&cpus
, cpu
, node
);
130 qemu_mutex_init(&tcg_ctx
.tb_ctx
.tb_lock
);
131 qemu_init_cpu_list();
132 gdbserver_fork(thread_cpu
);
134 qemu_mutex_unlock(&tcg_ctx
.tb_ctx
.tb_lock
);
140 /***********************************************************/
141 /* CPUX86 core interface */
143 uint64_t cpu_get_tsc(CPUX86State
*env
)
145 return cpu_get_host_ticks();
148 static void write_dt(void *ptr
, unsigned long addr
, unsigned long limit
,
153 e1
= (addr
<< 16) | (limit
& 0xffff);
154 e2
= ((addr
>> 16) & 0xff) | (addr
& 0xff000000) | (limit
& 0x000f0000);
161 static uint64_t *idt_table
;
163 static void set_gate64(void *ptr
, unsigned int type
, unsigned int dpl
,
164 uint64_t addr
, unsigned int sel
)
167 e1
= (addr
& 0xffff) | (sel
<< 16);
168 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
172 p
[2] = tswap32(addr
>> 32);
175 /* only dpl matters as we do only user space emulation */
176 static void set_idt(int n
, unsigned int dpl
)
178 set_gate64(idt_table
+ n
* 2, 0, dpl
, 0, 0);
181 static void set_gate(void *ptr
, unsigned int type
, unsigned int dpl
,
182 uint32_t addr
, unsigned int sel
)
185 e1
= (addr
& 0xffff) | (sel
<< 16);
186 e2
= (addr
& 0xffff0000) | 0x8000 | (dpl
<< 13) | (type
<< 8);
192 /* only dpl matters as we do only user space emulation */
193 static void set_idt(int n
, unsigned int dpl
)
195 set_gate(idt_table
+ n
, 0, dpl
, 0, 0);
199 void cpu_loop(CPUX86State
*env
)
201 CPUState
*cs
= CPU(x86_env_get_cpu(env
));
205 target_siginfo_t info
;
209 trapnr
= cpu_exec(cs
);
211 process_queued_cpu_work(cs
);
215 /* linux syscall from int $0x80 */
216 ret
= do_syscall(env
,
225 if (ret
== -TARGET_ERESTARTSYS
) {
227 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
228 env
->regs
[R_EAX
] = ret
;
233 /* linux syscall from syscall instruction */
234 ret
= do_syscall(env
,
243 if (ret
== -TARGET_ERESTARTSYS
) {
245 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
246 env
->regs
[R_EAX
] = ret
;
252 info
.si_signo
= TARGET_SIGBUS
;
254 info
.si_code
= TARGET_SI_KERNEL
;
255 info
._sifields
._sigfault
._addr
= 0;
256 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
259 /* XXX: potential problem if ABI32 */
260 #ifndef TARGET_X86_64
261 if (env
->eflags
& VM_MASK
) {
262 handle_vm86_fault(env
);
266 info
.si_signo
= TARGET_SIGSEGV
;
268 info
.si_code
= TARGET_SI_KERNEL
;
269 info
._sifields
._sigfault
._addr
= 0;
270 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
274 info
.si_signo
= TARGET_SIGSEGV
;
276 if (!(env
->error_code
& 1))
277 info
.si_code
= TARGET_SEGV_MAPERR
;
279 info
.si_code
= TARGET_SEGV_ACCERR
;
280 info
._sifields
._sigfault
._addr
= env
->cr
[2];
281 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
284 #ifndef TARGET_X86_64
285 if (env
->eflags
& VM_MASK
) {
286 handle_vm86_trap(env
, trapnr
);
290 /* division by zero */
291 info
.si_signo
= TARGET_SIGFPE
;
293 info
.si_code
= TARGET_FPE_INTDIV
;
294 info
._sifields
._sigfault
._addr
= env
->eip
;
295 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
300 #ifndef TARGET_X86_64
301 if (env
->eflags
& VM_MASK
) {
302 handle_vm86_trap(env
, trapnr
);
306 info
.si_signo
= TARGET_SIGTRAP
;
308 if (trapnr
== EXCP01_DB
) {
309 info
.si_code
= TARGET_TRAP_BRKPT
;
310 info
._sifields
._sigfault
._addr
= env
->eip
;
312 info
.si_code
= TARGET_SI_KERNEL
;
313 info
._sifields
._sigfault
._addr
= 0;
315 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
320 #ifndef TARGET_X86_64
321 if (env
->eflags
& VM_MASK
) {
322 handle_vm86_trap(env
, trapnr
);
326 info
.si_signo
= TARGET_SIGSEGV
;
328 info
.si_code
= TARGET_SI_KERNEL
;
329 info
._sifields
._sigfault
._addr
= 0;
330 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
334 info
.si_signo
= TARGET_SIGILL
;
336 info
.si_code
= TARGET_ILL_ILLOPN
;
337 info
._sifields
._sigfault
._addr
= env
->eip
;
338 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
341 /* just indicate that signals should be handled asap */
347 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
352 info
.si_code
= TARGET_TRAP_BRKPT
;
353 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
358 pc
= env
->segs
[R_CS
].base
+ env
->eip
;
359 EXCP_DUMP(env
, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
363 process_pending_signals(env
);
370 #define get_user_code_u32(x, gaddr, env) \
371 ({ abi_long __r = get_user_u32((x), (gaddr)); \
372 if (!__r && bswap_code(arm_sctlr_b(env))) { \
378 #define get_user_code_u16(x, gaddr, env) \
379 ({ abi_long __r = get_user_u16((x), (gaddr)); \
380 if (!__r && bswap_code(arm_sctlr_b(env))) { \
386 #define get_user_data_u32(x, gaddr, env) \
387 ({ abi_long __r = get_user_u32((x), (gaddr)); \
388 if (!__r && arm_cpu_bswap_data(env)) { \
394 #define get_user_data_u16(x, gaddr, env) \
395 ({ abi_long __r = get_user_u16((x), (gaddr)); \
396 if (!__r && arm_cpu_bswap_data(env)) { \
402 #define put_user_data_u32(x, gaddr, env) \
403 ({ typeof(x) __x = (x); \
404 if (arm_cpu_bswap_data(env)) { \
405 __x = bswap32(__x); \
407 put_user_u32(__x, (gaddr)); \
410 #define put_user_data_u16(x, gaddr, env) \
411 ({ typeof(x) __x = (x); \
412 if (arm_cpu_bswap_data(env)) { \
413 __x = bswap16(__x); \
415 put_user_u16(__x, (gaddr)); \
419 /* Commpage handling -- there is no commpage for AArch64 */
422 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
424 * r0 = pointer to oldval
425 * r1 = pointer to newval
426 * r2 = pointer to target value
429 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
430 * C set if *ptr was changed, clear if no exchange happened
432 * Note segv's in kernel helpers are a bit tricky, we can set the
433 * data address sensibly but the PC address is just the entry point.
435 static void arm_kernel_cmpxchg64_helper(CPUARMState
*env
)
437 uint64_t oldval
, newval
, val
;
439 target_siginfo_t info
;
441 /* Based on the 32 bit code in do_kernel_trap */
443 /* XXX: This only works between threads, not between processes.
444 It's probably possible to implement this with native host
445 operations. However things like ldrex/strex are much harder so
446 there's not much point trying. */
448 cpsr
= cpsr_read(env
);
451 if (get_user_u64(oldval
, env
->regs
[0])) {
452 env
->exception
.vaddress
= env
->regs
[0];
456 if (get_user_u64(newval
, env
->regs
[1])) {
457 env
->exception
.vaddress
= env
->regs
[1];
461 if (get_user_u64(val
, addr
)) {
462 env
->exception
.vaddress
= addr
;
469 if (put_user_u64(val
, addr
)) {
470 env
->exception
.vaddress
= addr
;
480 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
486 /* We get the PC of the entry address - which is as good as anything,
487 on a real kernel what you get depends on which mode it uses. */
488 info
.si_signo
= TARGET_SIGSEGV
;
490 /* XXX: check env->error_code */
491 info
.si_code
= TARGET_SEGV_MAPERR
;
492 info
._sifields
._sigfault
._addr
= env
->exception
.vaddress
;
493 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
496 /* Handle a jump to the kernel code page. */
498 do_kernel_trap(CPUARMState
*env
)
504 switch (env
->regs
[15]) {
505 case 0xffff0fa0: /* __kernel_memory_barrier */
506 /* ??? No-op. Will need to do better for SMP. */
508 case 0xffff0fc0: /* __kernel_cmpxchg */
509 /* XXX: This only works between threads, not between processes.
510 It's probably possible to implement this with native host
511 operations. However things like ldrex/strex are much harder so
512 there's not much point trying. */
514 cpsr
= cpsr_read(env
);
516 /* FIXME: This should SEGV if the access fails. */
517 if (get_user_u32(val
, addr
))
519 if (val
== env
->regs
[0]) {
521 /* FIXME: Check for segfaults. */
522 put_user_u32(val
, addr
);
529 cpsr_write(env
, cpsr
, CPSR_C
, CPSRWriteByInstr
);
532 case 0xffff0fe0: /* __kernel_get_tls */
533 env
->regs
[0] = cpu_get_tls(env
);
535 case 0xffff0f60: /* __kernel_cmpxchg64 */
536 arm_kernel_cmpxchg64_helper(env
);
542 /* Jump back to the caller. */
543 addr
= env
->regs
[14];
548 env
->regs
[15] = addr
;
553 /* Store exclusive handling for AArch32 */
554 static int do_strex(CPUARMState
*env
)
562 if (env
->exclusive_addr
!= env
->exclusive_test
) {
565 /* We know we're always AArch32 so the address is in uint32_t range
566 * unless it was the -1 exclusive-monitor-lost value (which won't
567 * match exclusive_test above).
569 assert(extract64(env
->exclusive_addr
, 32, 32) == 0);
570 addr
= env
->exclusive_addr
;
571 size
= env
->exclusive_info
& 0xf;
574 segv
= get_user_u8(val
, addr
);
577 segv
= get_user_data_u16(val
, addr
, env
);
581 segv
= get_user_data_u32(val
, addr
, env
);
587 env
->exception
.vaddress
= addr
;
592 segv
= get_user_data_u32(valhi
, addr
+ 4, env
);
594 env
->exception
.vaddress
= addr
+ 4;
597 if (arm_cpu_bswap_data(env
)) {
598 val
= deposit64((uint64_t)valhi
, 32, 32, val
);
600 val
= deposit64(val
, 32, 32, valhi
);
603 if (val
!= env
->exclusive_val
) {
607 val
= env
->regs
[(env
->exclusive_info
>> 8) & 0xf];
610 segv
= put_user_u8(val
, addr
);
613 segv
= put_user_data_u16(val
, addr
, env
);
617 segv
= put_user_data_u32(val
, addr
, env
);
621 env
->exception
.vaddress
= addr
;
625 val
= env
->regs
[(env
->exclusive_info
>> 12) & 0xf];
626 segv
= put_user_data_u32(val
, addr
+ 4, env
);
628 env
->exception
.vaddress
= addr
+ 4;
635 env
->regs
[(env
->exclusive_info
>> 4) & 0xf] = rc
;
641 void cpu_loop(CPUARMState
*env
)
643 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
645 unsigned int n
, insn
;
646 target_siginfo_t info
;
652 trapnr
= cpu_exec(cs
);
654 process_queued_cpu_work(cs
);
659 TaskState
*ts
= cs
->opaque
;
663 /* we handle the FPU emulation here, as Linux */
664 /* we get the opcode */
665 /* FIXME - what to do if get_user() fails? */
666 get_user_code_u32(opcode
, env
->regs
[15], env
);
668 rc
= EmulateAll(opcode
, &ts
->fpa
, env
);
669 if (rc
== 0) { /* illegal instruction */
670 info
.si_signo
= TARGET_SIGILL
;
672 info
.si_code
= TARGET_ILL_ILLOPN
;
673 info
._sifields
._sigfault
._addr
= env
->regs
[15];
674 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
675 } else if (rc
< 0) { /* FP exception */
678 /* translate softfloat flags to FPSR flags */
679 if (-rc
& float_flag_invalid
)
681 if (-rc
& float_flag_divbyzero
)
683 if (-rc
& float_flag_overflow
)
685 if (-rc
& float_flag_underflow
)
687 if (-rc
& float_flag_inexact
)
690 FPSR fpsr
= ts
->fpa
.fpsr
;
691 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
693 if (fpsr
& (arm_fpe
<< 16)) { /* exception enabled? */
694 info
.si_signo
= TARGET_SIGFPE
;
697 /* ordered by priority, least first */
698 if (arm_fpe
& BIT_IXC
) info
.si_code
= TARGET_FPE_FLTRES
;
699 if (arm_fpe
& BIT_UFC
) info
.si_code
= TARGET_FPE_FLTUND
;
700 if (arm_fpe
& BIT_OFC
) info
.si_code
= TARGET_FPE_FLTOVF
;
701 if (arm_fpe
& BIT_DZC
) info
.si_code
= TARGET_FPE_FLTDIV
;
702 if (arm_fpe
& BIT_IOC
) info
.si_code
= TARGET_FPE_FLTINV
;
704 info
._sifields
._sigfault
._addr
= env
->regs
[15];
705 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
710 /* accumulate unenabled exceptions */
711 if ((!(fpsr
& BIT_IXE
)) && (arm_fpe
& BIT_IXC
))
713 if ((!(fpsr
& BIT_UFE
)) && (arm_fpe
& BIT_UFC
))
715 if ((!(fpsr
& BIT_OFE
)) && (arm_fpe
& BIT_OFC
))
717 if ((!(fpsr
& BIT_DZE
)) && (arm_fpe
& BIT_DZC
))
719 if ((!(fpsr
& BIT_IOE
)) && (arm_fpe
& BIT_IOC
))
722 } else { /* everything OK */
733 if (trapnr
== EXCP_BKPT
) {
735 /* FIXME - what to do if get_user() fails? */
736 get_user_code_u16(insn
, env
->regs
[15], env
);
740 /* FIXME - what to do if get_user() fails? */
741 get_user_code_u32(insn
, env
->regs
[15], env
);
742 n
= (insn
& 0xf) | ((insn
>> 4) & 0xff0);
747 /* FIXME - what to do if get_user() fails? */
748 get_user_code_u16(insn
, env
->regs
[15] - 2, env
);
751 /* FIXME - what to do if get_user() fails? */
752 get_user_code_u32(insn
, env
->regs
[15] - 4, env
);
757 if (n
== ARM_NR_cacheflush
) {
759 } else if (n
== ARM_NR_semihosting
760 || n
== ARM_NR_thumb_semihosting
) {
761 env
->regs
[0] = do_arm_semihosting (env
);
762 } else if (n
== 0 || n
>= ARM_SYSCALL_BASE
|| env
->thumb
) {
764 if (env
->thumb
|| n
== 0) {
767 n
-= ARM_SYSCALL_BASE
;
770 if ( n
> ARM_NR_BASE
) {
772 case ARM_NR_cacheflush
:
776 cpu_set_tls(env
, env
->regs
[0]);
779 case ARM_NR_breakpoint
:
780 env
->regs
[15] -= env
->thumb
? 2 : 4;
783 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
785 env
->regs
[0] = -TARGET_ENOSYS
;
789 ret
= do_syscall(env
,
798 if (ret
== -TARGET_ERESTARTSYS
) {
799 env
->regs
[15] -= env
->thumb
? 2 : 4;
800 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
810 /* just indicate that signals should be handled asap */
813 if (!do_strex(env
)) {
816 /* fall through for segv */
817 case EXCP_PREFETCH_ABORT
:
818 case EXCP_DATA_ABORT
:
819 addr
= env
->exception
.vaddress
;
821 info
.si_signo
= TARGET_SIGSEGV
;
823 /* XXX: check env->error_code */
824 info
.si_code
= TARGET_SEGV_MAPERR
;
825 info
._sifields
._sigfault
._addr
= addr
;
826 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
834 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
839 info
.si_code
= TARGET_TRAP_BRKPT
;
840 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
844 case EXCP_KERNEL_TRAP
:
845 if (do_kernel_trap(env
))
849 /* nothing to do here for user-mode, just resume guest code */
853 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
856 process_pending_signals(env
);
863 * Handle AArch64 store-release exclusive
865 * rs = gets the status result of store exclusive
866 * rt = is the register that is stored
867 * rt2 = is the second register store (in STP)
870 static int do_strex_a64(CPUARMState
*env
)
881 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
882 size
= extract32(env
->exclusive_info
, 0, 2);
883 is_pair
= extract32(env
->exclusive_info
, 2, 1);
884 rs
= extract32(env
->exclusive_info
, 4, 5);
885 rt
= extract32(env
->exclusive_info
, 9, 5);
886 rt2
= extract32(env
->exclusive_info
, 14, 5);
888 addr
= env
->exclusive_addr
;
890 if (addr
!= env
->exclusive_test
) {
896 segv
= get_user_u8(val
, addr
);
899 segv
= get_user_u16(val
, addr
);
902 segv
= get_user_u32(val
, addr
);
905 segv
= get_user_u64(val
, addr
);
911 env
->exception
.vaddress
= addr
;
914 if (val
!= env
->exclusive_val
) {
919 segv
= get_user_u32(val
, addr
+ 4);
921 segv
= get_user_u64(val
, addr
+ 8);
924 env
->exception
.vaddress
= addr
+ (size
== 2 ? 4 : 8);
927 if (val
!= env
->exclusive_high
) {
931 /* handle the zero register */
932 val
= rt
== 31 ? 0 : env
->xregs
[rt
];
935 segv
= put_user_u8(val
, addr
);
938 segv
= put_user_u16(val
, addr
);
941 segv
= put_user_u32(val
, addr
);
944 segv
= put_user_u64(val
, addr
);
951 /* handle the zero register */
952 val
= rt2
== 31 ? 0 : env
->xregs
[rt2
];
954 segv
= put_user_u32(val
, addr
+ 4);
956 segv
= put_user_u64(val
, addr
+ 8);
959 env
->exception
.vaddress
= addr
+ (size
== 2 ? 4 : 8);
966 /* rs == 31 encodes a write to the ZR, thus throwing away
967 * the status return. This is rather silly but valid.
973 /* instruction faulted, PC does not advance */
974 /* either way a strex releases any exclusive lock we have */
975 env
->exclusive_addr
= -1;
980 /* AArch64 main loop */
981 void cpu_loop(CPUARMState
*env
)
983 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
986 target_siginfo_t info
;
990 trapnr
= cpu_exec(cs
);
992 process_queued_cpu_work(cs
);
996 ret
= do_syscall(env
,
1005 if (ret
== -TARGET_ERESTARTSYS
) {
1007 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
1008 env
->xregs
[0] = ret
;
1011 case EXCP_INTERRUPT
:
1012 /* just indicate that signals should be handled asap */
1015 info
.si_signo
= TARGET_SIGILL
;
1017 info
.si_code
= TARGET_ILL_ILLOPN
;
1018 info
._sifields
._sigfault
._addr
= env
->pc
;
1019 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1022 if (!do_strex_a64(env
)) {
1025 /* fall through for segv */
1026 case EXCP_PREFETCH_ABORT
:
1027 case EXCP_DATA_ABORT
:
1028 info
.si_signo
= TARGET_SIGSEGV
;
1030 /* XXX: check env->error_code */
1031 info
.si_code
= TARGET_SEGV_MAPERR
;
1032 info
._sifields
._sigfault
._addr
= env
->exception
.vaddress
;
1033 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1037 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1039 info
.si_signo
= sig
;
1041 info
.si_code
= TARGET_TRAP_BRKPT
;
1042 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1046 env
->xregs
[0] = do_arm_semihosting(env
);
1049 /* nothing to do here for user-mode, just resume guest code */
1052 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
1055 process_pending_signals(env
);
1056 /* Exception return on AArch64 always clears the exclusive monitor,
1057 * so any return to running guest code implies this.
1058 * A strex (successful or otherwise) also clears the monitor, so
1059 * we don't need to specialcase EXCP_STREX.
1061 env
->exclusive_addr
= -1;
1064 #endif /* ndef TARGET_ABI32 */
1068 #ifdef TARGET_UNICORE32
1070 void cpu_loop(CPUUniCore32State
*env
)
1072 CPUState
*cs
= CPU(uc32_env_get_cpu(env
));
1074 unsigned int n
, insn
;
1075 target_siginfo_t info
;
1079 trapnr
= cpu_exec(cs
);
1081 process_queued_cpu_work(cs
);
1084 case UC32_EXCP_PRIV
:
1087 get_user_u32(insn
, env
->regs
[31] - 4);
1088 n
= insn
& 0xffffff;
1090 if (n
>= UC32_SYSCALL_BASE
) {
1092 n
-= UC32_SYSCALL_BASE
;
1093 if (n
== UC32_SYSCALL_NR_set_tls
) {
1094 cpu_set_tls(env
, env
->regs
[0]);
1097 abi_long ret
= do_syscall(env
,
1106 if (ret
== -TARGET_ERESTARTSYS
) {
1108 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
1117 case UC32_EXCP_DTRAP
:
1118 case UC32_EXCP_ITRAP
:
1119 info
.si_signo
= TARGET_SIGSEGV
;
1121 /* XXX: check env->error_code */
1122 info
.si_code
= TARGET_SEGV_MAPERR
;
1123 info
._sifields
._sigfault
._addr
= env
->cp0
.c4_faultaddr
;
1124 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1126 case EXCP_INTERRUPT
:
1127 /* just indicate that signals should be handled asap */
1133 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1135 info
.si_signo
= sig
;
1137 info
.si_code
= TARGET_TRAP_BRKPT
;
1138 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1145 process_pending_signals(env
);
1149 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
1155 #define SPARC64_STACK_BIAS 2047
1159 /* WARNING: dealing with register windows _is_ complicated. More info
1160 can be found at http://www.sics.se/~psm/sparcstack.html */
1161 static inline int get_reg_index(CPUSPARCState
*env
, int cwp
, int index
)
1163 index
= (index
+ cwp
* 16) % (16 * env
->nwindows
);
1164 /* wrap handling : if cwp is on the last window, then we use the
1165 registers 'after' the end */
1166 if (index
< 8 && env
->cwp
== env
->nwindows
- 1)
1167 index
+= 16 * env
->nwindows
;
1171 /* save the register window 'cwp1' */
1172 static inline void save_window_offset(CPUSPARCState
*env
, int cwp1
)
1177 sp_ptr
= env
->regbase
[get_reg_index(env
, cwp1
, 6)];
1178 #ifdef TARGET_SPARC64
1180 sp_ptr
+= SPARC64_STACK_BIAS
;
1182 #if defined(DEBUG_WIN)
1183 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx
" save_cwp=%d\n",
1186 for(i
= 0; i
< 16; i
++) {
1187 /* FIXME - what to do if put_user() fails? */
1188 put_user_ual(env
->regbase
[get_reg_index(env
, cwp1
, 8 + i
)], sp_ptr
);
1189 sp_ptr
+= sizeof(abi_ulong
);
1193 static void save_window(CPUSPARCState
*env
)
1195 #ifndef TARGET_SPARC64
1196 unsigned int new_wim
;
1197 new_wim
= ((env
->wim
>> 1) | (env
->wim
<< (env
->nwindows
- 1))) &
1198 ((1LL << env
->nwindows
) - 1);
1199 save_window_offset(env
, cpu_cwp_dec(env
, env
->cwp
- 2));
1202 save_window_offset(env
, cpu_cwp_dec(env
, env
->cwp
- 2));
1208 static void restore_window(CPUSPARCState
*env
)
1210 #ifndef TARGET_SPARC64
1211 unsigned int new_wim
;
1213 unsigned int i
, cwp1
;
1216 #ifndef TARGET_SPARC64
1217 new_wim
= ((env
->wim
<< 1) | (env
->wim
>> (env
->nwindows
- 1))) &
1218 ((1LL << env
->nwindows
) - 1);
1221 /* restore the invalid window */
1222 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ 1);
1223 sp_ptr
= env
->regbase
[get_reg_index(env
, cwp1
, 6)];
1224 #ifdef TARGET_SPARC64
1226 sp_ptr
+= SPARC64_STACK_BIAS
;
1228 #if defined(DEBUG_WIN)
1229 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx
" load_cwp=%d\n",
1232 for(i
= 0; i
< 16; i
++) {
1233 /* FIXME - what to do if get_user() fails? */
1234 get_user_ual(env
->regbase
[get_reg_index(env
, cwp1
, 8 + i
)], sp_ptr
);
1235 sp_ptr
+= sizeof(abi_ulong
);
1237 #ifdef TARGET_SPARC64
1239 if (env
->cleanwin
< env
->nwindows
- 1)
1247 static void flush_windows(CPUSPARCState
*env
)
1253 /* if restore would invoke restore_window(), then we can stop */
1254 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ offset
);
1255 #ifndef TARGET_SPARC64
1256 if (env
->wim
& (1 << cwp1
))
1259 if (env
->canrestore
== 0)
1264 save_window_offset(env
, cwp1
);
1267 cwp1
= cpu_cwp_inc(env
, env
->cwp
+ 1);
1268 #ifndef TARGET_SPARC64
1269 /* set wim so that restore will reload the registers */
1270 env
->wim
= 1 << cwp1
;
1272 #if defined(DEBUG_WIN)
1273 printf("flush_windows: nb=%d\n", offset
- 1);
1277 void cpu_loop (CPUSPARCState
*env
)
1279 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
1282 target_siginfo_t info
;
1286 trapnr
= cpu_exec(cs
);
1288 process_queued_cpu_work(cs
);
1290 /* Compute PSR before exposing state. */
1291 if (env
->cc_op
!= CC_OP_FLAGS
) {
1296 #ifndef TARGET_SPARC64
1303 ret
= do_syscall (env
, env
->gregs
[1],
1304 env
->regwptr
[0], env
->regwptr
[1],
1305 env
->regwptr
[2], env
->regwptr
[3],
1306 env
->regwptr
[4], env
->regwptr
[5],
1308 if (ret
== -TARGET_ERESTARTSYS
|| ret
== -TARGET_QEMU_ESIGRETURN
) {
1311 if ((abi_ulong
)ret
>= (abi_ulong
)(-515)) {
1312 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1313 env
->xcc
|= PSR_CARRY
;
1315 env
->psr
|= PSR_CARRY
;
1319 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1320 env
->xcc
&= ~PSR_CARRY
;
1322 env
->psr
&= ~PSR_CARRY
;
1325 env
->regwptr
[0] = ret
;
1326 /* next instruction */
1328 env
->npc
= env
->npc
+ 4;
1330 case 0x83: /* flush windows */
1335 /* next instruction */
1337 env
->npc
= env
->npc
+ 4;
1339 #ifndef TARGET_SPARC64
1340 case TT_WIN_OVF
: /* window overflow */
1343 case TT_WIN_UNF
: /* window underflow */
1344 restore_window(env
);
1349 info
.si_signo
= TARGET_SIGSEGV
;
1351 /* XXX: check env->error_code */
1352 info
.si_code
= TARGET_SEGV_MAPERR
;
1353 info
._sifields
._sigfault
._addr
= env
->mmuregs
[4];
1354 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1358 case TT_SPILL
: /* window overflow */
1361 case TT_FILL
: /* window underflow */
1362 restore_window(env
);
1367 info
.si_signo
= TARGET_SIGSEGV
;
1369 /* XXX: check env->error_code */
1370 info
.si_code
= TARGET_SEGV_MAPERR
;
1371 if (trapnr
== TT_DFAULT
)
1372 info
._sifields
._sigfault
._addr
= env
->dmmuregs
[4];
1374 info
._sifields
._sigfault
._addr
= cpu_tsptr(env
)->tpc
;
1375 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1378 #ifndef TARGET_ABI32
1381 sparc64_get_context(env
);
1385 sparc64_set_context(env
);
1389 case EXCP_INTERRUPT
:
1390 /* just indicate that signals should be handled asap */
1394 info
.si_signo
= TARGET_SIGILL
;
1396 info
.si_code
= TARGET_ILL_ILLOPC
;
1397 info
._sifields
._sigfault
._addr
= env
->pc
;
1398 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1405 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1408 info
.si_signo
= sig
;
1410 info
.si_code
= TARGET_TRAP_BRKPT
;
1411 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1416 printf ("Unhandled trap: 0x%x\n", trapnr
);
1417 cpu_dump_state(cs
, stderr
, fprintf
, 0);
1420 process_pending_signals (env
);
1427 static inline uint64_t cpu_ppc_get_tb(CPUPPCState
*env
)
1429 return cpu_get_host_ticks();
1432 uint64_t cpu_ppc_load_tbl(CPUPPCState
*env
)
1434 return cpu_ppc_get_tb(env
);
1437 uint32_t cpu_ppc_load_tbu(CPUPPCState
*env
)
1439 return cpu_ppc_get_tb(env
) >> 32;
1442 uint64_t cpu_ppc_load_atbl(CPUPPCState
*env
)
1444 return cpu_ppc_get_tb(env
);
1447 uint32_t cpu_ppc_load_atbu(CPUPPCState
*env
)
1449 return cpu_ppc_get_tb(env
) >> 32;
1452 uint32_t cpu_ppc601_load_rtcu(CPUPPCState
*env
)
1453 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1455 uint32_t cpu_ppc601_load_rtcl(CPUPPCState
*env
)
1457 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
1460 /* XXX: to be fixed */
1461 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
)
1466 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
)
1471 static int do_store_exclusive(CPUPPCState
*env
)
1474 target_ulong page_addr
;
1475 target_ulong val
, val2
__attribute__((unused
)) = 0;
1479 addr
= env
->reserve_ea
;
1480 page_addr
= addr
& TARGET_PAGE_MASK
;
1483 flags
= page_get_flags(page_addr
);
1484 if ((flags
& PAGE_READ
) == 0) {
1487 int reg
= env
->reserve_info
& 0x1f;
1488 int size
= env
->reserve_info
>> 5;
1491 if (addr
== env
->reserve_addr
) {
1493 case 1: segv
= get_user_u8(val
, addr
); break;
1494 case 2: segv
= get_user_u16(val
, addr
); break;
1495 case 4: segv
= get_user_u32(val
, addr
); break;
1496 #if defined(TARGET_PPC64)
1497 case 8: segv
= get_user_u64(val
, addr
); break;
1499 segv
= get_user_u64(val
, addr
);
1501 segv
= get_user_u64(val2
, addr
+ 8);
1508 if (!segv
&& val
== env
->reserve_val
) {
1509 val
= env
->gpr
[reg
];
1511 case 1: segv
= put_user_u8(val
, addr
); break;
1512 case 2: segv
= put_user_u16(val
, addr
); break;
1513 case 4: segv
= put_user_u32(val
, addr
); break;
1514 #if defined(TARGET_PPC64)
1515 case 8: segv
= put_user_u64(val
, addr
); break;
1517 if (val2
== env
->reserve_val2
) {
1520 val
= env
->gpr
[reg
+1];
1522 val2
= env
->gpr
[reg
+1];
1524 segv
= put_user_u64(val
, addr
);
1526 segv
= put_user_u64(val2
, addr
+ 8);
1539 env
->crf
[0] = (stored
<< 1) | xer_so
;
1540 env
->reserve_addr
= (target_ulong
)-1;
1550 void cpu_loop(CPUPPCState
*env
)
1552 CPUState
*cs
= CPU(ppc_env_get_cpu(env
));
1553 target_siginfo_t info
;
1559 trapnr
= cpu_exec(cs
);
1561 process_queued_cpu_work(cs
);
1564 case POWERPC_EXCP_NONE
:
1567 case POWERPC_EXCP_CRITICAL
: /* Critical input */
1568 cpu_abort(cs
, "Critical interrupt while in user mode. "
1571 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
1572 cpu_abort(cs
, "Machine check exception while in user mode. "
1575 case POWERPC_EXCP_DSI
: /* Data storage exception */
1576 /* XXX: check this. Seems bugged */
1577 switch (env
->error_code
& 0xFF000000) {
1580 info
.si_signo
= TARGET_SIGSEGV
;
1582 info
.si_code
= TARGET_SEGV_MAPERR
;
1585 info
.si_signo
= TARGET_SIGILL
;
1587 info
.si_code
= TARGET_ILL_ILLADR
;
1590 info
.si_signo
= TARGET_SIGSEGV
;
1592 info
.si_code
= TARGET_SEGV_ACCERR
;
1595 /* Let's send a regular segfault... */
1596 EXCP_DUMP(env
, "Invalid segfault errno (%02x)\n",
1598 info
.si_signo
= TARGET_SIGSEGV
;
1600 info
.si_code
= TARGET_SEGV_MAPERR
;
1603 info
._sifields
._sigfault
._addr
= env
->nip
;
1604 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1606 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
1607 /* XXX: check this */
1608 switch (env
->error_code
& 0xFF000000) {
1610 info
.si_signo
= TARGET_SIGSEGV
;
1612 info
.si_code
= TARGET_SEGV_MAPERR
;
1616 info
.si_signo
= TARGET_SIGSEGV
;
1618 info
.si_code
= TARGET_SEGV_ACCERR
;
1621 /* Let's send a regular segfault... */
1622 EXCP_DUMP(env
, "Invalid segfault errno (%02x)\n",
1624 info
.si_signo
= TARGET_SIGSEGV
;
1626 info
.si_code
= TARGET_SEGV_MAPERR
;
1629 info
._sifields
._sigfault
._addr
= env
->nip
- 4;
1630 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1632 case POWERPC_EXCP_EXTERNAL
: /* External input */
1633 cpu_abort(cs
, "External interrupt while in user mode. "
1636 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
1637 /* XXX: check this */
1638 info
.si_signo
= TARGET_SIGBUS
;
1640 info
.si_code
= TARGET_BUS_ADRALN
;
1641 info
._sifields
._sigfault
._addr
= env
->nip
;
1642 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1644 case POWERPC_EXCP_PROGRAM
: /* Program exception */
1645 case POWERPC_EXCP_HV_EMU
: /* HV emulation */
1646 /* XXX: check this */
1647 switch (env
->error_code
& ~0xF) {
1648 case POWERPC_EXCP_FP
:
1649 info
.si_signo
= TARGET_SIGFPE
;
1651 switch (env
->error_code
& 0xF) {
1652 case POWERPC_EXCP_FP_OX
:
1653 info
.si_code
= TARGET_FPE_FLTOVF
;
1655 case POWERPC_EXCP_FP_UX
:
1656 info
.si_code
= TARGET_FPE_FLTUND
;
1658 case POWERPC_EXCP_FP_ZX
:
1659 case POWERPC_EXCP_FP_VXZDZ
:
1660 info
.si_code
= TARGET_FPE_FLTDIV
;
1662 case POWERPC_EXCP_FP_XX
:
1663 info
.si_code
= TARGET_FPE_FLTRES
;
1665 case POWERPC_EXCP_FP_VXSOFT
:
1666 info
.si_code
= TARGET_FPE_FLTINV
;
1668 case POWERPC_EXCP_FP_VXSNAN
:
1669 case POWERPC_EXCP_FP_VXISI
:
1670 case POWERPC_EXCP_FP_VXIDI
:
1671 case POWERPC_EXCP_FP_VXIMZ
:
1672 case POWERPC_EXCP_FP_VXVC
:
1673 case POWERPC_EXCP_FP_VXSQRT
:
1674 case POWERPC_EXCP_FP_VXCVI
:
1675 info
.si_code
= TARGET_FPE_FLTSUB
;
1678 EXCP_DUMP(env
, "Unknown floating point exception (%02x)\n",
1683 case POWERPC_EXCP_INVAL
:
1684 info
.si_signo
= TARGET_SIGILL
;
1686 switch (env
->error_code
& 0xF) {
1687 case POWERPC_EXCP_INVAL_INVAL
:
1688 info
.si_code
= TARGET_ILL_ILLOPC
;
1690 case POWERPC_EXCP_INVAL_LSWX
:
1691 info
.si_code
= TARGET_ILL_ILLOPN
;
1693 case POWERPC_EXCP_INVAL_SPR
:
1694 info
.si_code
= TARGET_ILL_PRVREG
;
1696 case POWERPC_EXCP_INVAL_FP
:
1697 info
.si_code
= TARGET_ILL_COPROC
;
1700 EXCP_DUMP(env
, "Unknown invalid operation (%02x)\n",
1701 env
->error_code
& 0xF);
1702 info
.si_code
= TARGET_ILL_ILLADR
;
1706 case POWERPC_EXCP_PRIV
:
1707 info
.si_signo
= TARGET_SIGILL
;
1709 switch (env
->error_code
& 0xF) {
1710 case POWERPC_EXCP_PRIV_OPC
:
1711 info
.si_code
= TARGET_ILL_PRVOPC
;
1713 case POWERPC_EXCP_PRIV_REG
:
1714 info
.si_code
= TARGET_ILL_PRVREG
;
1717 EXCP_DUMP(env
, "Unknown privilege violation (%02x)\n",
1718 env
->error_code
& 0xF);
1719 info
.si_code
= TARGET_ILL_PRVOPC
;
1723 case POWERPC_EXCP_TRAP
:
1724 cpu_abort(cs
, "Tried to call a TRAP\n");
1727 /* Should not happen ! */
1728 cpu_abort(cs
, "Unknown program exception (%02x)\n",
1732 info
._sifields
._sigfault
._addr
= env
->nip
;
1733 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1735 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1736 info
.si_signo
= TARGET_SIGILL
;
1738 info
.si_code
= TARGET_ILL_COPROC
;
1739 info
._sifields
._sigfault
._addr
= env
->nip
;
1740 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1742 case POWERPC_EXCP_SYSCALL
: /* System call exception */
1743 cpu_abort(cs
, "Syscall exception while in user mode. "
1746 case POWERPC_EXCP_APU
: /* Auxiliary processor unavailable */
1747 info
.si_signo
= TARGET_SIGILL
;
1749 info
.si_code
= TARGET_ILL_COPROC
;
1750 info
._sifields
._sigfault
._addr
= env
->nip
;
1751 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1753 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1754 cpu_abort(cs
, "Decrementer interrupt while in user mode. "
1757 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
1758 cpu_abort(cs
, "Fix interval timer interrupt while in user mode. "
1761 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
1762 cpu_abort(cs
, "Watchdog timer interrupt while in user mode. "
1765 case POWERPC_EXCP_DTLB
: /* Data TLB error */
1766 cpu_abort(cs
, "Data TLB exception while in user mode. "
1769 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
1770 cpu_abort(cs
, "Instruction TLB exception while in user mode. "
1773 case POWERPC_EXCP_SPEU
: /* SPE/embedded floating-point unavail. */
1774 info
.si_signo
= TARGET_SIGILL
;
1776 info
.si_code
= TARGET_ILL_COPROC
;
1777 info
._sifields
._sigfault
._addr
= env
->nip
;
1778 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1780 case POWERPC_EXCP_EFPDI
: /* Embedded floating-point data IRQ */
1781 cpu_abort(cs
, "Embedded floating-point data IRQ not handled\n");
1783 case POWERPC_EXCP_EFPRI
: /* Embedded floating-point round IRQ */
1784 cpu_abort(cs
, "Embedded floating-point round IRQ not handled\n");
1786 case POWERPC_EXCP_EPERFM
: /* Embedded performance monitor IRQ */
1787 cpu_abort(cs
, "Performance monitor exception not handled\n");
1789 case POWERPC_EXCP_DOORI
: /* Embedded doorbell interrupt */
1790 cpu_abort(cs
, "Doorbell interrupt while in user mode. "
1793 case POWERPC_EXCP_DOORCI
: /* Embedded doorbell critical interrupt */
1794 cpu_abort(cs
, "Doorbell critical interrupt while in user mode. "
1797 case POWERPC_EXCP_RESET
: /* System reset exception */
1798 cpu_abort(cs
, "Reset interrupt while in user mode. "
1801 case POWERPC_EXCP_DSEG
: /* Data segment exception */
1802 cpu_abort(cs
, "Data segment exception while in user mode. "
1805 case POWERPC_EXCP_ISEG
: /* Instruction segment exception */
1806 cpu_abort(cs
, "Instruction segment exception "
1807 "while in user mode. Aborting\n");
1809 /* PowerPC 64 with hypervisor mode support */
1810 case POWERPC_EXCP_HDECR
: /* Hypervisor decrementer exception */
1811 cpu_abort(cs
, "Hypervisor decrementer interrupt "
1812 "while in user mode. Aborting\n");
1814 case POWERPC_EXCP_TRACE
: /* Trace exception */
1816 * we use this exception to emulate step-by-step execution mode.
1819 /* PowerPC 64 with hypervisor mode support */
1820 case POWERPC_EXCP_HDSI
: /* Hypervisor data storage exception */
1821 cpu_abort(cs
, "Hypervisor data storage exception "
1822 "while in user mode. Aborting\n");
1824 case POWERPC_EXCP_HISI
: /* Hypervisor instruction storage excp */
1825 cpu_abort(cs
, "Hypervisor instruction storage exception "
1826 "while in user mode. Aborting\n");
1828 case POWERPC_EXCP_HDSEG
: /* Hypervisor data segment exception */
1829 cpu_abort(cs
, "Hypervisor data segment exception "
1830 "while in user mode. Aborting\n");
1832 case POWERPC_EXCP_HISEG
: /* Hypervisor instruction segment excp */
1833 cpu_abort(cs
, "Hypervisor instruction segment exception "
1834 "while in user mode. Aborting\n");
1836 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
1837 info
.si_signo
= TARGET_SIGILL
;
1839 info
.si_code
= TARGET_ILL_COPROC
;
1840 info
._sifields
._sigfault
._addr
= env
->nip
;
1841 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1843 case POWERPC_EXCP_PIT
: /* Programmable interval timer IRQ */
1844 cpu_abort(cs
, "Programmable interval timer interrupt "
1845 "while in user mode. Aborting\n");
1847 case POWERPC_EXCP_IO
: /* IO error exception */
1848 cpu_abort(cs
, "IO error exception while in user mode. "
1851 case POWERPC_EXCP_RUNM
: /* Run mode exception */
1852 cpu_abort(cs
, "Run mode exception while in user mode. "
1855 case POWERPC_EXCP_EMUL
: /* Emulation trap exception */
1856 cpu_abort(cs
, "Emulation trap exception not handled\n");
1858 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
1859 cpu_abort(cs
, "Instruction fetch TLB exception "
1860 "while in user-mode. Aborting");
1862 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
1863 cpu_abort(cs
, "Data load TLB exception while in user-mode. "
1866 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
1867 cpu_abort(cs
, "Data store TLB exception while in user-mode. "
1870 case POWERPC_EXCP_FPA
: /* Floating-point assist exception */
1871 cpu_abort(cs
, "Floating-point assist exception not handled\n");
1873 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
1874 cpu_abort(cs
, "Instruction address breakpoint exception "
1877 case POWERPC_EXCP_SMI
: /* System management interrupt */
1878 cpu_abort(cs
, "System management interrupt while in user mode. "
1881 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
1882 cpu_abort(cs
, "Thermal interrupt interrupt while in user mode. "
1885 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor IRQ */
1886 cpu_abort(cs
, "Performance monitor exception not handled\n");
1888 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
1889 cpu_abort(cs
, "Vector assist exception not handled\n");
1891 case POWERPC_EXCP_SOFTP
: /* Soft patch exception */
1892 cpu_abort(cs
, "Soft patch exception not handled\n");
1894 case POWERPC_EXCP_MAINT
: /* Maintenance exception */
1895 cpu_abort(cs
, "Maintenance exception while in user mode. "
1898 case POWERPC_EXCP_STOP
: /* stop translation */
1899 /* We did invalidate the instruction cache. Go on */
1901 case POWERPC_EXCP_BRANCH
: /* branch instruction: */
1902 /* We just stopped because of a branch. Go on */
1904 case POWERPC_EXCP_SYSCALL_USER
:
1905 /* system call in user-mode emulation */
1907 * PPC ABI uses overflow flag in cr0 to signal an error
1910 env
->crf
[0] &= ~0x1;
1911 ret
= do_syscall(env
, env
->gpr
[0], env
->gpr
[3], env
->gpr
[4],
1912 env
->gpr
[5], env
->gpr
[6], env
->gpr
[7],
1914 if (ret
== -TARGET_ERESTARTSYS
) {
1917 if (ret
== (target_ulong
)(-TARGET_QEMU_ESIGRETURN
)) {
1918 /* Returning from a successful sigreturn syscall.
1919 Avoid corrupting register state. */
1923 if (ret
> (target_ulong
)(-515)) {
1929 case POWERPC_EXCP_STCX
:
1930 if (do_store_exclusive(env
)) {
1931 info
.si_signo
= TARGET_SIGSEGV
;
1933 info
.si_code
= TARGET_SEGV_MAPERR
;
1934 info
._sifields
._sigfault
._addr
= env
->nip
;
1935 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1942 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
1944 info
.si_signo
= sig
;
1946 info
.si_code
= TARGET_TRAP_BRKPT
;
1947 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
1951 case EXCP_INTERRUPT
:
1952 /* just indicate that signals should be handled asap */
1955 cpu_abort(cs
, "Unknown exception 0x%x. Aborting\n", trapnr
);
1958 process_pending_signals(env
);
1965 # ifdef TARGET_ABI_MIPSO32
1966 # define MIPS_SYS(name, args) args,
1967 static const uint8_t mips_syscall_args
[] = {
1968 MIPS_SYS(sys_syscall
, 8) /* 4000 */
1969 MIPS_SYS(sys_exit
, 1)
1970 MIPS_SYS(sys_fork
, 0)
1971 MIPS_SYS(sys_read
, 3)
1972 MIPS_SYS(sys_write
, 3)
1973 MIPS_SYS(sys_open
, 3) /* 4005 */
1974 MIPS_SYS(sys_close
, 1)
1975 MIPS_SYS(sys_waitpid
, 3)
1976 MIPS_SYS(sys_creat
, 2)
1977 MIPS_SYS(sys_link
, 2)
1978 MIPS_SYS(sys_unlink
, 1) /* 4010 */
1979 MIPS_SYS(sys_execve
, 0)
1980 MIPS_SYS(sys_chdir
, 1)
1981 MIPS_SYS(sys_time
, 1)
1982 MIPS_SYS(sys_mknod
, 3)
1983 MIPS_SYS(sys_chmod
, 2) /* 4015 */
1984 MIPS_SYS(sys_lchown
, 3)
1985 MIPS_SYS(sys_ni_syscall
, 0)
1986 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_stat */
1987 MIPS_SYS(sys_lseek
, 3)
1988 MIPS_SYS(sys_getpid
, 0) /* 4020 */
1989 MIPS_SYS(sys_mount
, 5)
1990 MIPS_SYS(sys_umount
, 1)
1991 MIPS_SYS(sys_setuid
, 1)
1992 MIPS_SYS(sys_getuid
, 0)
1993 MIPS_SYS(sys_stime
, 1) /* 4025 */
1994 MIPS_SYS(sys_ptrace
, 4)
1995 MIPS_SYS(sys_alarm
, 1)
1996 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_fstat */
1997 MIPS_SYS(sys_pause
, 0)
1998 MIPS_SYS(sys_utime
, 2) /* 4030 */
1999 MIPS_SYS(sys_ni_syscall
, 0)
2000 MIPS_SYS(sys_ni_syscall
, 0)
2001 MIPS_SYS(sys_access
, 2)
2002 MIPS_SYS(sys_nice
, 1)
2003 MIPS_SYS(sys_ni_syscall
, 0) /* 4035 */
2004 MIPS_SYS(sys_sync
, 0)
2005 MIPS_SYS(sys_kill
, 2)
2006 MIPS_SYS(sys_rename
, 2)
2007 MIPS_SYS(sys_mkdir
, 2)
2008 MIPS_SYS(sys_rmdir
, 1) /* 4040 */
2009 MIPS_SYS(sys_dup
, 1)
2010 MIPS_SYS(sys_pipe
, 0)
2011 MIPS_SYS(sys_times
, 1)
2012 MIPS_SYS(sys_ni_syscall
, 0)
2013 MIPS_SYS(sys_brk
, 1) /* 4045 */
2014 MIPS_SYS(sys_setgid
, 1)
2015 MIPS_SYS(sys_getgid
, 0)
2016 MIPS_SYS(sys_ni_syscall
, 0) /* was signal(2) */
2017 MIPS_SYS(sys_geteuid
, 0)
2018 MIPS_SYS(sys_getegid
, 0) /* 4050 */
2019 MIPS_SYS(sys_acct
, 0)
2020 MIPS_SYS(sys_umount2
, 2)
2021 MIPS_SYS(sys_ni_syscall
, 0)
2022 MIPS_SYS(sys_ioctl
, 3)
2023 MIPS_SYS(sys_fcntl
, 3) /* 4055 */
2024 MIPS_SYS(sys_ni_syscall
, 2)
2025 MIPS_SYS(sys_setpgid
, 2)
2026 MIPS_SYS(sys_ni_syscall
, 0)
2027 MIPS_SYS(sys_olduname
, 1)
2028 MIPS_SYS(sys_umask
, 1) /* 4060 */
2029 MIPS_SYS(sys_chroot
, 1)
2030 MIPS_SYS(sys_ustat
, 2)
2031 MIPS_SYS(sys_dup2
, 2)
2032 MIPS_SYS(sys_getppid
, 0)
2033 MIPS_SYS(sys_getpgrp
, 0) /* 4065 */
2034 MIPS_SYS(sys_setsid
, 0)
2035 MIPS_SYS(sys_sigaction
, 3)
2036 MIPS_SYS(sys_sgetmask
, 0)
2037 MIPS_SYS(sys_ssetmask
, 1)
2038 MIPS_SYS(sys_setreuid
, 2) /* 4070 */
2039 MIPS_SYS(sys_setregid
, 2)
2040 MIPS_SYS(sys_sigsuspend
, 0)
2041 MIPS_SYS(sys_sigpending
, 1)
2042 MIPS_SYS(sys_sethostname
, 2)
2043 MIPS_SYS(sys_setrlimit
, 2) /* 4075 */
2044 MIPS_SYS(sys_getrlimit
, 2)
2045 MIPS_SYS(sys_getrusage
, 2)
2046 MIPS_SYS(sys_gettimeofday
, 2)
2047 MIPS_SYS(sys_settimeofday
, 2)
2048 MIPS_SYS(sys_getgroups
, 2) /* 4080 */
2049 MIPS_SYS(sys_setgroups
, 2)
2050 MIPS_SYS(sys_ni_syscall
, 0) /* old_select */
2051 MIPS_SYS(sys_symlink
, 2)
2052 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_lstat */
2053 MIPS_SYS(sys_readlink
, 3) /* 4085 */
2054 MIPS_SYS(sys_uselib
, 1)
2055 MIPS_SYS(sys_swapon
, 2)
2056 MIPS_SYS(sys_reboot
, 3)
2057 MIPS_SYS(old_readdir
, 3)
2058 MIPS_SYS(old_mmap
, 6) /* 4090 */
2059 MIPS_SYS(sys_munmap
, 2)
2060 MIPS_SYS(sys_truncate
, 2)
2061 MIPS_SYS(sys_ftruncate
, 2)
2062 MIPS_SYS(sys_fchmod
, 2)
2063 MIPS_SYS(sys_fchown
, 3) /* 4095 */
2064 MIPS_SYS(sys_getpriority
, 2)
2065 MIPS_SYS(sys_setpriority
, 3)
2066 MIPS_SYS(sys_ni_syscall
, 0)
2067 MIPS_SYS(sys_statfs
, 2)
2068 MIPS_SYS(sys_fstatfs
, 2) /* 4100 */
2069 MIPS_SYS(sys_ni_syscall
, 0) /* was ioperm(2) */
2070 MIPS_SYS(sys_socketcall
, 2)
2071 MIPS_SYS(sys_syslog
, 3)
2072 MIPS_SYS(sys_setitimer
, 3)
2073 MIPS_SYS(sys_getitimer
, 2) /* 4105 */
2074 MIPS_SYS(sys_newstat
, 2)
2075 MIPS_SYS(sys_newlstat
, 2)
2076 MIPS_SYS(sys_newfstat
, 2)
2077 MIPS_SYS(sys_uname
, 1)
2078 MIPS_SYS(sys_ni_syscall
, 0) /* 4110 was iopl(2) */
2079 MIPS_SYS(sys_vhangup
, 0)
2080 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_idle() */
2081 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_vm86 */
2082 MIPS_SYS(sys_wait4
, 4)
2083 MIPS_SYS(sys_swapoff
, 1) /* 4115 */
2084 MIPS_SYS(sys_sysinfo
, 1)
2085 MIPS_SYS(sys_ipc
, 6)
2086 MIPS_SYS(sys_fsync
, 1)
2087 MIPS_SYS(sys_sigreturn
, 0)
2088 MIPS_SYS(sys_clone
, 6) /* 4120 */
2089 MIPS_SYS(sys_setdomainname
, 2)
2090 MIPS_SYS(sys_newuname
, 1)
2091 MIPS_SYS(sys_ni_syscall
, 0) /* sys_modify_ldt */
2092 MIPS_SYS(sys_adjtimex
, 1)
2093 MIPS_SYS(sys_mprotect
, 3) /* 4125 */
2094 MIPS_SYS(sys_sigprocmask
, 3)
2095 MIPS_SYS(sys_ni_syscall
, 0) /* was create_module */
2096 MIPS_SYS(sys_init_module
, 5)
2097 MIPS_SYS(sys_delete_module
, 1)
2098 MIPS_SYS(sys_ni_syscall
, 0) /* 4130 was get_kernel_syms */
2099 MIPS_SYS(sys_quotactl
, 0)
2100 MIPS_SYS(sys_getpgid
, 1)
2101 MIPS_SYS(sys_fchdir
, 1)
2102 MIPS_SYS(sys_bdflush
, 2)
2103 MIPS_SYS(sys_sysfs
, 3) /* 4135 */
2104 MIPS_SYS(sys_personality
, 1)
2105 MIPS_SYS(sys_ni_syscall
, 0) /* for afs_syscall */
2106 MIPS_SYS(sys_setfsuid
, 1)
2107 MIPS_SYS(sys_setfsgid
, 1)
2108 MIPS_SYS(sys_llseek
, 5) /* 4140 */
2109 MIPS_SYS(sys_getdents
, 3)
2110 MIPS_SYS(sys_select
, 5)
2111 MIPS_SYS(sys_flock
, 2)
2112 MIPS_SYS(sys_msync
, 3)
2113 MIPS_SYS(sys_readv
, 3) /* 4145 */
2114 MIPS_SYS(sys_writev
, 3)
2115 MIPS_SYS(sys_cacheflush
, 3)
2116 MIPS_SYS(sys_cachectl
, 3)
2117 MIPS_SYS(sys_sysmips
, 4)
2118 MIPS_SYS(sys_ni_syscall
, 0) /* 4150 */
2119 MIPS_SYS(sys_getsid
, 1)
2120 MIPS_SYS(sys_fdatasync
, 0)
2121 MIPS_SYS(sys_sysctl
, 1)
2122 MIPS_SYS(sys_mlock
, 2)
2123 MIPS_SYS(sys_munlock
, 2) /* 4155 */
2124 MIPS_SYS(sys_mlockall
, 1)
2125 MIPS_SYS(sys_munlockall
, 0)
2126 MIPS_SYS(sys_sched_setparam
, 2)
2127 MIPS_SYS(sys_sched_getparam
, 2)
2128 MIPS_SYS(sys_sched_setscheduler
, 3) /* 4160 */
2129 MIPS_SYS(sys_sched_getscheduler
, 1)
2130 MIPS_SYS(sys_sched_yield
, 0)
2131 MIPS_SYS(sys_sched_get_priority_max
, 1)
2132 MIPS_SYS(sys_sched_get_priority_min
, 1)
2133 MIPS_SYS(sys_sched_rr_get_interval
, 2) /* 4165 */
2134 MIPS_SYS(sys_nanosleep
, 2)
2135 MIPS_SYS(sys_mremap
, 5)
2136 MIPS_SYS(sys_accept
, 3)
2137 MIPS_SYS(sys_bind
, 3)
2138 MIPS_SYS(sys_connect
, 3) /* 4170 */
2139 MIPS_SYS(sys_getpeername
, 3)
2140 MIPS_SYS(sys_getsockname
, 3)
2141 MIPS_SYS(sys_getsockopt
, 5)
2142 MIPS_SYS(sys_listen
, 2)
2143 MIPS_SYS(sys_recv
, 4) /* 4175 */
2144 MIPS_SYS(sys_recvfrom
, 6)
2145 MIPS_SYS(sys_recvmsg
, 3)
2146 MIPS_SYS(sys_send
, 4)
2147 MIPS_SYS(sys_sendmsg
, 3)
2148 MIPS_SYS(sys_sendto
, 6) /* 4180 */
2149 MIPS_SYS(sys_setsockopt
, 5)
2150 MIPS_SYS(sys_shutdown
, 2)
2151 MIPS_SYS(sys_socket
, 3)
2152 MIPS_SYS(sys_socketpair
, 4)
2153 MIPS_SYS(sys_setresuid
, 3) /* 4185 */
2154 MIPS_SYS(sys_getresuid
, 3)
2155 MIPS_SYS(sys_ni_syscall
, 0) /* was sys_query_module */
2156 MIPS_SYS(sys_poll
, 3)
2157 MIPS_SYS(sys_nfsservctl
, 3)
2158 MIPS_SYS(sys_setresgid
, 3) /* 4190 */
2159 MIPS_SYS(sys_getresgid
, 3)
2160 MIPS_SYS(sys_prctl
, 5)
2161 MIPS_SYS(sys_rt_sigreturn
, 0)
2162 MIPS_SYS(sys_rt_sigaction
, 4)
2163 MIPS_SYS(sys_rt_sigprocmask
, 4) /* 4195 */
2164 MIPS_SYS(sys_rt_sigpending
, 2)
2165 MIPS_SYS(sys_rt_sigtimedwait
, 4)
2166 MIPS_SYS(sys_rt_sigqueueinfo
, 3)
2167 MIPS_SYS(sys_rt_sigsuspend
, 0)
2168 MIPS_SYS(sys_pread64
, 6) /* 4200 */
2169 MIPS_SYS(sys_pwrite64
, 6)
2170 MIPS_SYS(sys_chown
, 3)
2171 MIPS_SYS(sys_getcwd
, 2)
2172 MIPS_SYS(sys_capget
, 2)
2173 MIPS_SYS(sys_capset
, 2) /* 4205 */
2174 MIPS_SYS(sys_sigaltstack
, 2)
2175 MIPS_SYS(sys_sendfile
, 4)
2176 MIPS_SYS(sys_ni_syscall
, 0)
2177 MIPS_SYS(sys_ni_syscall
, 0)
2178 MIPS_SYS(sys_mmap2
, 6) /* 4210 */
2179 MIPS_SYS(sys_truncate64
, 4)
2180 MIPS_SYS(sys_ftruncate64
, 4)
2181 MIPS_SYS(sys_stat64
, 2)
2182 MIPS_SYS(sys_lstat64
, 2)
2183 MIPS_SYS(sys_fstat64
, 2) /* 4215 */
2184 MIPS_SYS(sys_pivot_root
, 2)
2185 MIPS_SYS(sys_mincore
, 3)
2186 MIPS_SYS(sys_madvise
, 3)
2187 MIPS_SYS(sys_getdents64
, 3)
2188 MIPS_SYS(sys_fcntl64
, 3) /* 4220 */
2189 MIPS_SYS(sys_ni_syscall
, 0)
2190 MIPS_SYS(sys_gettid
, 0)
2191 MIPS_SYS(sys_readahead
, 5)
2192 MIPS_SYS(sys_setxattr
, 5)
2193 MIPS_SYS(sys_lsetxattr
, 5) /* 4225 */
2194 MIPS_SYS(sys_fsetxattr
, 5)
2195 MIPS_SYS(sys_getxattr
, 4)
2196 MIPS_SYS(sys_lgetxattr
, 4)
2197 MIPS_SYS(sys_fgetxattr
, 4)
2198 MIPS_SYS(sys_listxattr
, 3) /* 4230 */
2199 MIPS_SYS(sys_llistxattr
, 3)
2200 MIPS_SYS(sys_flistxattr
, 3)
2201 MIPS_SYS(sys_removexattr
, 2)
2202 MIPS_SYS(sys_lremovexattr
, 2)
2203 MIPS_SYS(sys_fremovexattr
, 2) /* 4235 */
2204 MIPS_SYS(sys_tkill
, 2)
2205 MIPS_SYS(sys_sendfile64
, 5)
2206 MIPS_SYS(sys_futex
, 6)
2207 MIPS_SYS(sys_sched_setaffinity
, 3)
2208 MIPS_SYS(sys_sched_getaffinity
, 3) /* 4240 */
2209 MIPS_SYS(sys_io_setup
, 2)
2210 MIPS_SYS(sys_io_destroy
, 1)
2211 MIPS_SYS(sys_io_getevents
, 5)
2212 MIPS_SYS(sys_io_submit
, 3)
2213 MIPS_SYS(sys_io_cancel
, 3) /* 4245 */
2214 MIPS_SYS(sys_exit_group
, 1)
2215 MIPS_SYS(sys_lookup_dcookie
, 3)
2216 MIPS_SYS(sys_epoll_create
, 1)
2217 MIPS_SYS(sys_epoll_ctl
, 4)
2218 MIPS_SYS(sys_epoll_wait
, 3) /* 4250 */
2219 MIPS_SYS(sys_remap_file_pages
, 5)
2220 MIPS_SYS(sys_set_tid_address
, 1)
2221 MIPS_SYS(sys_restart_syscall
, 0)
2222 MIPS_SYS(sys_fadvise64_64
, 7)
2223 MIPS_SYS(sys_statfs64
, 3) /* 4255 */
2224 MIPS_SYS(sys_fstatfs64
, 2)
2225 MIPS_SYS(sys_timer_create
, 3)
2226 MIPS_SYS(sys_timer_settime
, 4)
2227 MIPS_SYS(sys_timer_gettime
, 2)
2228 MIPS_SYS(sys_timer_getoverrun
, 1) /* 4260 */
2229 MIPS_SYS(sys_timer_delete
, 1)
2230 MIPS_SYS(sys_clock_settime
, 2)
2231 MIPS_SYS(sys_clock_gettime
, 2)
2232 MIPS_SYS(sys_clock_getres
, 2)
2233 MIPS_SYS(sys_clock_nanosleep
, 4) /* 4265 */
2234 MIPS_SYS(sys_tgkill
, 3)
2235 MIPS_SYS(sys_utimes
, 2)
2236 MIPS_SYS(sys_mbind
, 4)
2237 MIPS_SYS(sys_ni_syscall
, 0) /* sys_get_mempolicy */
2238 MIPS_SYS(sys_ni_syscall
, 0) /* 4270 sys_set_mempolicy */
2239 MIPS_SYS(sys_mq_open
, 4)
2240 MIPS_SYS(sys_mq_unlink
, 1)
2241 MIPS_SYS(sys_mq_timedsend
, 5)
2242 MIPS_SYS(sys_mq_timedreceive
, 5)
2243 MIPS_SYS(sys_mq_notify
, 2) /* 4275 */
2244 MIPS_SYS(sys_mq_getsetattr
, 3)
2245 MIPS_SYS(sys_ni_syscall
, 0) /* sys_vserver */
2246 MIPS_SYS(sys_waitid
, 4)
2247 MIPS_SYS(sys_ni_syscall
, 0) /* available, was setaltroot */
2248 MIPS_SYS(sys_add_key
, 5)
2249 MIPS_SYS(sys_request_key
, 4)
2250 MIPS_SYS(sys_keyctl
, 5)
2251 MIPS_SYS(sys_set_thread_area
, 1)
2252 MIPS_SYS(sys_inotify_init
, 0)
2253 MIPS_SYS(sys_inotify_add_watch
, 3) /* 4285 */
2254 MIPS_SYS(sys_inotify_rm_watch
, 2)
2255 MIPS_SYS(sys_migrate_pages
, 4)
2256 MIPS_SYS(sys_openat
, 4)
2257 MIPS_SYS(sys_mkdirat
, 3)
2258 MIPS_SYS(sys_mknodat
, 4) /* 4290 */
2259 MIPS_SYS(sys_fchownat
, 5)
2260 MIPS_SYS(sys_futimesat
, 3)
2261 MIPS_SYS(sys_fstatat64
, 4)
2262 MIPS_SYS(sys_unlinkat
, 3)
2263 MIPS_SYS(sys_renameat
, 4) /* 4295 */
2264 MIPS_SYS(sys_linkat
, 5)
2265 MIPS_SYS(sys_symlinkat
, 3)
2266 MIPS_SYS(sys_readlinkat
, 4)
2267 MIPS_SYS(sys_fchmodat
, 3)
2268 MIPS_SYS(sys_faccessat
, 3) /* 4300 */
2269 MIPS_SYS(sys_pselect6
, 6)
2270 MIPS_SYS(sys_ppoll
, 5)
2271 MIPS_SYS(sys_unshare
, 1)
2272 MIPS_SYS(sys_splice
, 6)
2273 MIPS_SYS(sys_sync_file_range
, 7) /* 4305 */
2274 MIPS_SYS(sys_tee
, 4)
2275 MIPS_SYS(sys_vmsplice
, 4)
2276 MIPS_SYS(sys_move_pages
, 6)
2277 MIPS_SYS(sys_set_robust_list
, 2)
2278 MIPS_SYS(sys_get_robust_list
, 3) /* 4310 */
2279 MIPS_SYS(sys_kexec_load
, 4)
2280 MIPS_SYS(sys_getcpu
, 3)
2281 MIPS_SYS(sys_epoll_pwait
, 6)
2282 MIPS_SYS(sys_ioprio_set
, 3)
2283 MIPS_SYS(sys_ioprio_get
, 2)
2284 MIPS_SYS(sys_utimensat
, 4)
2285 MIPS_SYS(sys_signalfd
, 3)
2286 MIPS_SYS(sys_ni_syscall
, 0) /* was timerfd */
2287 MIPS_SYS(sys_eventfd
, 1)
2288 MIPS_SYS(sys_fallocate
, 6) /* 4320 */
2289 MIPS_SYS(sys_timerfd_create
, 2)
2290 MIPS_SYS(sys_timerfd_gettime
, 2)
2291 MIPS_SYS(sys_timerfd_settime
, 4)
2292 MIPS_SYS(sys_signalfd4
, 4)
2293 MIPS_SYS(sys_eventfd2
, 2) /* 4325 */
2294 MIPS_SYS(sys_epoll_create1
, 1)
2295 MIPS_SYS(sys_dup3
, 3)
2296 MIPS_SYS(sys_pipe2
, 2)
2297 MIPS_SYS(sys_inotify_init1
, 1)
2298 MIPS_SYS(sys_preadv
, 5) /* 4330 */
2299 MIPS_SYS(sys_pwritev
, 5)
2300 MIPS_SYS(sys_rt_tgsigqueueinfo
, 4)
2301 MIPS_SYS(sys_perf_event_open
, 5)
2302 MIPS_SYS(sys_accept4
, 4)
2303 MIPS_SYS(sys_recvmmsg
, 5) /* 4335 */
2304 MIPS_SYS(sys_fanotify_init
, 2)
2305 MIPS_SYS(sys_fanotify_mark
, 6)
2306 MIPS_SYS(sys_prlimit64
, 4)
2307 MIPS_SYS(sys_name_to_handle_at
, 5)
2308 MIPS_SYS(sys_open_by_handle_at
, 3) /* 4340 */
2309 MIPS_SYS(sys_clock_adjtime
, 2)
2310 MIPS_SYS(sys_syncfs
, 1)
2311 MIPS_SYS(sys_sendmmsg
, 4)
2312 MIPS_SYS(sys_setns
, 2)
2313 MIPS_SYS(sys_process_vm_readv
, 6) /* 345 */
2314 MIPS_SYS(sys_process_vm_writev
, 6)
2315 MIPS_SYS(sys_kcmp
, 5)
2316 MIPS_SYS(sys_finit_module
, 3)
2317 MIPS_SYS(sys_sched_setattr
, 2)
2318 MIPS_SYS(sys_sched_getattr
, 3) /* 350 */
2319 MIPS_SYS(sys_renameat2
, 5)
2320 MIPS_SYS(sys_seccomp
, 3)
2321 MIPS_SYS(sys_getrandom
, 3)
2322 MIPS_SYS(sys_memfd_create
, 2)
2323 MIPS_SYS(sys_bpf
, 3) /* 355 */
2324 MIPS_SYS(sys_execveat
, 5)
2325 MIPS_SYS(sys_userfaultfd
, 1)
2326 MIPS_SYS(sys_membarrier
, 2)
2327 MIPS_SYS(sys_mlock2
, 3)
2328 MIPS_SYS(sys_copy_file_range
, 6) /* 360 */
2329 MIPS_SYS(sys_preadv2
, 6)
2330 MIPS_SYS(sys_pwritev2
, 6)
2335 static int do_store_exclusive(CPUMIPSState
*env
)
2338 target_ulong page_addr
;
2346 page_addr
= addr
& TARGET_PAGE_MASK
;
2349 flags
= page_get_flags(page_addr
);
2350 if ((flags
& PAGE_READ
) == 0) {
2353 reg
= env
->llreg
& 0x1f;
2354 d
= (env
->llreg
& 0x20) != 0;
2356 segv
= get_user_s64(val
, addr
);
2358 segv
= get_user_s32(val
, addr
);
2361 if (val
!= env
->llval
) {
2362 env
->active_tc
.gpr
[reg
] = 0;
2365 segv
= put_user_u64(env
->llnewval
, addr
);
2367 segv
= put_user_u32(env
->llnewval
, addr
);
2370 env
->active_tc
.gpr
[reg
] = 1;
2377 env
->active_tc
.PC
+= 4;
2390 static int do_break(CPUMIPSState
*env
, target_siginfo_t
*info
,
2398 info
->si_signo
= TARGET_SIGFPE
;
2400 info
->si_code
= (code
== BRK_OVERFLOW
) ? FPE_INTOVF
: FPE_INTDIV
;
2401 queue_signal(env
, info
->si_signo
, QEMU_SI_FAULT
, &*info
);
2405 info
->si_signo
= TARGET_SIGTRAP
;
2407 queue_signal(env
, info
->si_signo
, QEMU_SI_FAULT
, &*info
);
2415 void cpu_loop(CPUMIPSState
*env
)
2417 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2418 target_siginfo_t info
;
2421 # ifdef TARGET_ABI_MIPSO32
2422 unsigned int syscall_num
;
2427 trapnr
= cpu_exec(cs
);
2429 process_queued_cpu_work(cs
);
2433 env
->active_tc
.PC
+= 4;
2434 # ifdef TARGET_ABI_MIPSO32
2435 syscall_num
= env
->active_tc
.gpr
[2] - 4000;
2436 if (syscall_num
>= sizeof(mips_syscall_args
)) {
2437 ret
= -TARGET_ENOSYS
;
2441 abi_ulong arg5
= 0, arg6
= 0, arg7
= 0, arg8
= 0;
2443 nb_args
= mips_syscall_args
[syscall_num
];
2444 sp_reg
= env
->active_tc
.gpr
[29];
2446 /* these arguments are taken from the stack */
2448 if ((ret
= get_user_ual(arg8
, sp_reg
+ 28)) != 0) {
2452 if ((ret
= get_user_ual(arg7
, sp_reg
+ 24)) != 0) {
2456 if ((ret
= get_user_ual(arg6
, sp_reg
+ 20)) != 0) {
2460 if ((ret
= get_user_ual(arg5
, sp_reg
+ 16)) != 0) {
2466 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
2467 env
->active_tc
.gpr
[4],
2468 env
->active_tc
.gpr
[5],
2469 env
->active_tc
.gpr
[6],
2470 env
->active_tc
.gpr
[7],
2471 arg5
, arg6
, arg7
, arg8
);
2475 ret
= do_syscall(env
, env
->active_tc
.gpr
[2],
2476 env
->active_tc
.gpr
[4], env
->active_tc
.gpr
[5],
2477 env
->active_tc
.gpr
[6], env
->active_tc
.gpr
[7],
2478 env
->active_tc
.gpr
[8], env
->active_tc
.gpr
[9],
2479 env
->active_tc
.gpr
[10], env
->active_tc
.gpr
[11]);
2481 if (ret
== -TARGET_ERESTARTSYS
) {
2482 env
->active_tc
.PC
-= 4;
2485 if (ret
== -TARGET_QEMU_ESIGRETURN
) {
2486 /* Returning from a successful sigreturn syscall.
2487 Avoid clobbering register state. */
2490 if ((abi_ulong
)ret
>= (abi_ulong
)-1133) {
2491 env
->active_tc
.gpr
[7] = 1; /* error flag */
2494 env
->active_tc
.gpr
[7] = 0; /* error flag */
2496 env
->active_tc
.gpr
[2] = ret
;
2502 info
.si_signo
= TARGET_SIGSEGV
;
2504 /* XXX: check env->error_code */
2505 info
.si_code
= TARGET_SEGV_MAPERR
;
2506 info
._sifields
._sigfault
._addr
= env
->CP0_BadVAddr
;
2507 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2511 info
.si_signo
= TARGET_SIGILL
;
2514 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2516 case EXCP_INTERRUPT
:
2517 /* just indicate that signals should be handled asap */
2523 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2526 info
.si_signo
= sig
;
2528 info
.si_code
= TARGET_TRAP_BRKPT
;
2529 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2534 if (do_store_exclusive(env
)) {
2535 info
.si_signo
= TARGET_SIGSEGV
;
2537 info
.si_code
= TARGET_SEGV_MAPERR
;
2538 info
._sifields
._sigfault
._addr
= env
->active_tc
.PC
;
2539 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2543 info
.si_signo
= TARGET_SIGILL
;
2545 info
.si_code
= TARGET_ILL_ILLOPC
;
2546 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2548 /* The code below was inspired by the MIPS Linux kernel trap
2549 * handling code in arch/mips/kernel/traps.c.
2553 abi_ulong trap_instr
;
2556 if (env
->hflags
& MIPS_HFLAG_M16
) {
2557 if (env
->insn_flags
& ASE_MICROMIPS
) {
2558 /* microMIPS mode */
2559 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
2564 if ((trap_instr
>> 10) == 0x11) {
2565 /* 16-bit instruction */
2566 code
= trap_instr
& 0xf;
2568 /* 32-bit instruction */
2571 ret
= get_user_u16(instr_lo
,
2572 env
->active_tc
.PC
+ 2);
2576 trap_instr
= (trap_instr
<< 16) | instr_lo
;
2577 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
2578 /* Unfortunately, microMIPS also suffers from
2579 the old assembler bug... */
2580 if (code
>= (1 << 10)) {
2586 ret
= get_user_u16(trap_instr
, env
->active_tc
.PC
);
2590 code
= (trap_instr
>> 6) & 0x3f;
2593 ret
= get_user_u32(trap_instr
, env
->active_tc
.PC
);
2598 /* As described in the original Linux kernel code, the
2599 * below checks on 'code' are to work around an old
2602 code
= ((trap_instr
>> 6) & ((1 << 20) - 1));
2603 if (code
>= (1 << 10)) {
2608 if (do_break(env
, &info
, code
) != 0) {
2615 abi_ulong trap_instr
;
2616 unsigned int code
= 0;
2618 if (env
->hflags
& MIPS_HFLAG_M16
) {
2619 /* microMIPS mode */
2622 ret
= get_user_u16(instr
[0], env
->active_tc
.PC
) ||
2623 get_user_u16(instr
[1], env
->active_tc
.PC
+ 2);
2625 trap_instr
= (instr
[0] << 16) | instr
[1];
2627 ret
= get_user_u32(trap_instr
, env
->active_tc
.PC
);
2634 /* The immediate versions don't provide a code. */
2635 if (!(trap_instr
& 0xFC000000)) {
2636 if (env
->hflags
& MIPS_HFLAG_M16
) {
2637 /* microMIPS mode */
2638 code
= ((trap_instr
>> 12) & ((1 << 4) - 1));
2640 code
= ((trap_instr
>> 6) & ((1 << 10) - 1));
2644 if (do_break(env
, &info
, code
) != 0) {
2651 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
2654 process_pending_signals(env
);
2659 #ifdef TARGET_OPENRISC
2661 void cpu_loop(CPUOpenRISCState
*env
)
2663 CPUState
*cs
= CPU(openrisc_env_get_cpu(env
));
2669 trapnr
= cpu_exec(cs
);
2671 process_queued_cpu_work(cs
);
2676 qemu_log_mask(CPU_LOG_INT
, "\nReset request, exit, pc is %#x\n", env
->pc
);
2680 qemu_log_mask(CPU_LOG_INT
, "\nBus error, exit, pc is %#x\n", env
->pc
);
2681 gdbsig
= TARGET_SIGBUS
;
2685 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2686 gdbsig
= TARGET_SIGSEGV
;
2689 qemu_log_mask(CPU_LOG_INT
, "\nTick time interrupt pc is %#x\n", env
->pc
);
2692 qemu_log_mask(CPU_LOG_INT
, "\nAlignment pc is %#x\n", env
->pc
);
2693 gdbsig
= TARGET_SIGBUS
;
2696 qemu_log_mask(CPU_LOG_INT
, "\nIllegal instructionpc is %#x\n", env
->pc
);
2697 gdbsig
= TARGET_SIGILL
;
2700 qemu_log_mask(CPU_LOG_INT
, "\nExternal interruptpc is %#x\n", env
->pc
);
2704 qemu_log_mask(CPU_LOG_INT
, "\nTLB miss\n");
2707 qemu_log_mask(CPU_LOG_INT
, "\nRange\n");
2708 gdbsig
= TARGET_SIGSEGV
;
2711 env
->pc
+= 4; /* 0xc00; */
2712 ret
= do_syscall(env
,
2713 env
->gpr
[11], /* return value */
2714 env
->gpr
[3], /* r3 - r7 are params */
2720 if (ret
== -TARGET_ERESTARTSYS
) {
2722 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
2727 qemu_log_mask(CPU_LOG_INT
, "\nFloating point error\n");
2730 qemu_log_mask(CPU_LOG_INT
, "\nTrap\n");
2731 gdbsig
= TARGET_SIGTRAP
;
2734 qemu_log_mask(CPU_LOG_INT
, "\nNR\n");
2737 EXCP_DUMP(env
, "\nqemu: unhandled CPU exception %#x - aborting\n",
2739 gdbsig
= TARGET_SIGILL
;
2743 gdb_handlesig(cs
, gdbsig
);
2744 if (gdbsig
!= TARGET_SIGTRAP
) {
2749 process_pending_signals(env
);
2753 #endif /* TARGET_OPENRISC */
2756 void cpu_loop(CPUSH4State
*env
)
2758 CPUState
*cs
= CPU(sh_env_get_cpu(env
));
2760 target_siginfo_t info
;
2764 trapnr
= cpu_exec(cs
);
2766 process_queued_cpu_work(cs
);
2771 ret
= do_syscall(env
,
2780 if (ret
== -TARGET_ERESTARTSYS
) {
2782 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
2783 env
->gregs
[0] = ret
;
2786 case EXCP_INTERRUPT
:
2787 /* just indicate that signals should be handled asap */
2793 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2796 info
.si_signo
= sig
;
2798 info
.si_code
= TARGET_TRAP_BRKPT
;
2799 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2805 info
.si_signo
= TARGET_SIGSEGV
;
2807 info
.si_code
= TARGET_SEGV_MAPERR
;
2808 info
._sifields
._sigfault
._addr
= env
->tea
;
2809 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2813 printf ("Unhandled trap: 0x%x\n", trapnr
);
2814 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2817 process_pending_signals (env
);
2823 void cpu_loop(CPUCRISState
*env
)
2825 CPUState
*cs
= CPU(cris_env_get_cpu(env
));
2827 target_siginfo_t info
;
2831 trapnr
= cpu_exec(cs
);
2833 process_queued_cpu_work(cs
);
2838 info
.si_signo
= TARGET_SIGSEGV
;
2840 /* XXX: check env->error_code */
2841 info
.si_code
= TARGET_SEGV_MAPERR
;
2842 info
._sifields
._sigfault
._addr
= env
->pregs
[PR_EDA
];
2843 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2846 case EXCP_INTERRUPT
:
2847 /* just indicate that signals should be handled asap */
2850 ret
= do_syscall(env
,
2859 if (ret
== -TARGET_ERESTARTSYS
) {
2861 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
2862 env
->regs
[10] = ret
;
2869 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2872 info
.si_signo
= sig
;
2874 info
.si_code
= TARGET_TRAP_BRKPT
;
2875 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2880 printf ("Unhandled trap: 0x%x\n", trapnr
);
2881 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2884 process_pending_signals (env
);
2889 #ifdef TARGET_MICROBLAZE
2890 void cpu_loop(CPUMBState
*env
)
2892 CPUState
*cs
= CPU(mb_env_get_cpu(env
));
2894 target_siginfo_t info
;
2898 trapnr
= cpu_exec(cs
);
2900 process_queued_cpu_work(cs
);
2905 info
.si_signo
= TARGET_SIGSEGV
;
2907 /* XXX: check env->error_code */
2908 info
.si_code
= TARGET_SEGV_MAPERR
;
2909 info
._sifields
._sigfault
._addr
= 0;
2910 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2913 case EXCP_INTERRUPT
:
2914 /* just indicate that signals should be handled asap */
2917 /* Return address is 4 bytes after the call. */
2919 env
->sregs
[SR_PC
] = env
->regs
[14];
2920 ret
= do_syscall(env
,
2929 if (ret
== -TARGET_ERESTARTSYS
) {
2930 /* Wind back to before the syscall. */
2931 env
->sregs
[SR_PC
] -= 4;
2932 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
2935 /* All syscall exits result in guest r14 being equal to the
2936 * PC we return to, because the kernel syscall exit "rtbd" does
2937 * this. (This is true even for sigreturn(); note that r14 is
2938 * not a userspace-usable register, as the kernel may clobber it
2941 env
->regs
[14] = env
->sregs
[SR_PC
];
2944 env
->regs
[17] = env
->sregs
[SR_PC
] + 4;
2945 if (env
->iflags
& D_FLAG
) {
2946 env
->sregs
[SR_ESR
] |= 1 << 12;
2947 env
->sregs
[SR_PC
] -= 4;
2948 /* FIXME: if branch was immed, replay the imm as well. */
2951 env
->iflags
&= ~(IMM_FLAG
| D_FLAG
);
2953 switch (env
->sregs
[SR_ESR
] & 31) {
2954 case ESR_EC_DIVZERO
:
2955 info
.si_signo
= TARGET_SIGFPE
;
2957 info
.si_code
= TARGET_FPE_FLTDIV
;
2958 info
._sifields
._sigfault
._addr
= 0;
2959 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2962 info
.si_signo
= TARGET_SIGFPE
;
2964 if (env
->sregs
[SR_FSR
] & FSR_IO
) {
2965 info
.si_code
= TARGET_FPE_FLTINV
;
2967 if (env
->sregs
[SR_FSR
] & FSR_DZ
) {
2968 info
.si_code
= TARGET_FPE_FLTDIV
;
2970 info
._sifields
._sigfault
._addr
= 0;
2971 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2974 printf ("Unhandled hw-exception: 0x%x\n",
2975 env
->sregs
[SR_ESR
] & ESR_EC_MASK
);
2976 cpu_dump_state(cs
, stderr
, fprintf
, 0);
2985 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
2988 info
.si_signo
= sig
;
2990 info
.si_code
= TARGET_TRAP_BRKPT
;
2991 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
2996 printf ("Unhandled trap: 0x%x\n", trapnr
);
2997 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3000 process_pending_signals (env
);
3007 void cpu_loop(CPUM68KState
*env
)
3009 CPUState
*cs
= CPU(m68k_env_get_cpu(env
));
3012 target_siginfo_t info
;
3013 TaskState
*ts
= cs
->opaque
;
3017 trapnr
= cpu_exec(cs
);
3019 process_queued_cpu_work(cs
);
3024 if (ts
->sim_syscalls
) {
3026 get_user_u16(nr
, env
->pc
+ 2);
3028 do_m68k_simcall(env
, nr
);
3034 case EXCP_HALT_INSN
:
3035 /* Semihosing syscall. */
3037 do_m68k_semihosting(env
, env
->dregs
[0]);
3041 case EXCP_UNSUPPORTED
:
3043 info
.si_signo
= TARGET_SIGILL
;
3045 info
.si_code
= TARGET_ILL_ILLOPN
;
3046 info
._sifields
._sigfault
._addr
= env
->pc
;
3047 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3052 ts
->sim_syscalls
= 0;
3055 ret
= do_syscall(env
,
3064 if (ret
== -TARGET_ERESTARTSYS
) {
3066 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
3067 env
->dregs
[0] = ret
;
3071 case EXCP_INTERRUPT
:
3072 /* just indicate that signals should be handled asap */
3076 info
.si_signo
= TARGET_SIGSEGV
;
3078 /* XXX: check env->error_code */
3079 info
.si_code
= TARGET_SEGV_MAPERR
;
3080 info
._sifields
._sigfault
._addr
= env
->mmu
.ar
;
3081 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3088 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3091 info
.si_signo
= sig
;
3093 info
.si_code
= TARGET_TRAP_BRKPT
;
3094 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3099 EXCP_DUMP(env
, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr
);
3102 process_pending_signals(env
);
3105 #endif /* TARGET_M68K */
3108 static void do_store_exclusive(CPUAlphaState
*env
, int reg
, int quad
)
3110 target_ulong addr
, val
, tmp
;
3111 target_siginfo_t info
;
3114 addr
= env
->lock_addr
;
3115 tmp
= env
->lock_st_addr
;
3116 env
->lock_addr
= -1;
3117 env
->lock_st_addr
= 0;
3123 if (quad
? get_user_s64(val
, addr
) : get_user_s32(val
, addr
)) {
3127 if (val
== env
->lock_value
) {
3129 if (quad
? put_user_u64(tmp
, addr
) : put_user_u32(tmp
, addr
)) {
3146 info
.si_signo
= TARGET_SIGSEGV
;
3148 info
.si_code
= TARGET_SEGV_MAPERR
;
3149 info
._sifields
._sigfault
._addr
= addr
;
3150 queue_signal(env
, TARGET_SIGSEGV
, QEMU_SI_FAULT
, &info
);
3153 void cpu_loop(CPUAlphaState
*env
)
3155 CPUState
*cs
= CPU(alpha_env_get_cpu(env
));
3157 target_siginfo_t info
;
3162 trapnr
= cpu_exec(cs
);
3164 process_queued_cpu_work(cs
);
3166 /* All of the traps imply a transition through PALcode, which
3167 implies an REI instruction has been executed. Which means
3168 that the intr_flag should be cleared. */
3173 fprintf(stderr
, "Reset requested. Exit\n");
3177 fprintf(stderr
, "Machine check exception. Exit\n");
3180 case EXCP_SMP_INTERRUPT
:
3181 case EXCP_CLK_INTERRUPT
:
3182 case EXCP_DEV_INTERRUPT
:
3183 fprintf(stderr
, "External interrupt. Exit\n");
3187 env
->lock_addr
= -1;
3188 info
.si_signo
= TARGET_SIGSEGV
;
3190 info
.si_code
= (page_get_flags(env
->trap_arg0
) & PAGE_VALID
3191 ? TARGET_SEGV_ACCERR
: TARGET_SEGV_MAPERR
);
3192 info
._sifields
._sigfault
._addr
= env
->trap_arg0
;
3193 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3196 env
->lock_addr
= -1;
3197 info
.si_signo
= TARGET_SIGBUS
;
3199 info
.si_code
= TARGET_BUS_ADRALN
;
3200 info
._sifields
._sigfault
._addr
= env
->trap_arg0
;
3201 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3205 env
->lock_addr
= -1;
3206 info
.si_signo
= TARGET_SIGILL
;
3208 info
.si_code
= TARGET_ILL_ILLOPC
;
3209 info
._sifields
._sigfault
._addr
= env
->pc
;
3210 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3213 env
->lock_addr
= -1;
3214 info
.si_signo
= TARGET_SIGFPE
;
3216 info
.si_code
= TARGET_FPE_FLTINV
;
3217 info
._sifields
._sigfault
._addr
= env
->pc
;
3218 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3221 /* No-op. Linux simply re-enables the FPU. */
3224 env
->lock_addr
= -1;
3225 switch (env
->error_code
) {
3228 info
.si_signo
= TARGET_SIGTRAP
;
3230 info
.si_code
= TARGET_TRAP_BRKPT
;
3231 info
._sifields
._sigfault
._addr
= env
->pc
;
3232 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3236 info
.si_signo
= TARGET_SIGTRAP
;
3239 info
._sifields
._sigfault
._addr
= env
->pc
;
3240 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3244 trapnr
= env
->ir
[IR_V0
];
3245 sysret
= do_syscall(env
, trapnr
,
3246 env
->ir
[IR_A0
], env
->ir
[IR_A1
],
3247 env
->ir
[IR_A2
], env
->ir
[IR_A3
],
3248 env
->ir
[IR_A4
], env
->ir
[IR_A5
],
3250 if (sysret
== -TARGET_ERESTARTSYS
) {
3254 if (sysret
== -TARGET_QEMU_ESIGRETURN
) {
3257 /* Syscall writes 0 to V0 to bypass error check, similar
3258 to how this is handled internal to Linux kernel.
3259 (Ab)use trapnr temporarily as boolean indicating error. */
3260 trapnr
= (env
->ir
[IR_V0
] != 0 && sysret
< 0);
3261 env
->ir
[IR_V0
] = (trapnr
? -sysret
: sysret
);
3262 env
->ir
[IR_A3
] = trapnr
;
3266 /* ??? We can probably elide the code using page_unprotect
3267 that is checking for self-modifying code. Instead we
3268 could simply call tb_flush here. Until we work out the
3269 changes required to turn off the extra write protection,
3270 this can be a no-op. */
3274 /* Handled in the translator for usermode. */
3278 /* Handled in the translator for usermode. */
3282 info
.si_signo
= TARGET_SIGFPE
;
3283 switch (env
->ir
[IR_A0
]) {
3284 case TARGET_GEN_INTOVF
:
3285 info
.si_code
= TARGET_FPE_INTOVF
;
3287 case TARGET_GEN_INTDIV
:
3288 info
.si_code
= TARGET_FPE_INTDIV
;
3290 case TARGET_GEN_FLTOVF
:
3291 info
.si_code
= TARGET_FPE_FLTOVF
;
3293 case TARGET_GEN_FLTUND
:
3294 info
.si_code
= TARGET_FPE_FLTUND
;
3296 case TARGET_GEN_FLTINV
:
3297 info
.si_code
= TARGET_FPE_FLTINV
;
3299 case TARGET_GEN_FLTINE
:
3300 info
.si_code
= TARGET_FPE_FLTRES
;
3302 case TARGET_GEN_ROPRAND
:
3306 info
.si_signo
= TARGET_SIGTRAP
;
3311 info
._sifields
._sigfault
._addr
= env
->pc
;
3312 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3319 info
.si_signo
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3320 if (info
.si_signo
) {
3321 env
->lock_addr
= -1;
3323 info
.si_code
= TARGET_TRAP_BRKPT
;
3324 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3329 do_store_exclusive(env
, env
->error_code
, trapnr
- EXCP_STL_C
);
3331 case EXCP_INTERRUPT
:
3332 /* Just indicate that signals should be handled asap. */
3335 printf ("Unhandled trap: 0x%x\n", trapnr
);
3336 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3339 process_pending_signals (env
);
3342 #endif /* TARGET_ALPHA */
3345 void cpu_loop(CPUS390XState
*env
)
3347 CPUState
*cs
= CPU(s390_env_get_cpu(env
));
3349 target_siginfo_t info
;
3355 trapnr
= cpu_exec(cs
);
3357 process_queued_cpu_work(cs
);
3360 case EXCP_INTERRUPT
:
3361 /* Just indicate that signals should be handled asap. */
3365 n
= env
->int_svc_code
;
3367 /* syscalls > 255 */
3370 env
->psw
.addr
+= env
->int_svc_ilen
;
3371 ret
= do_syscall(env
, n
, env
->regs
[2], env
->regs
[3],
3372 env
->regs
[4], env
->regs
[5],
3373 env
->regs
[6], env
->regs
[7], 0, 0);
3374 if (ret
== -TARGET_ERESTARTSYS
) {
3375 env
->psw
.addr
-= env
->int_svc_ilen
;
3376 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
3382 sig
= gdb_handlesig(cs
, TARGET_SIGTRAP
);
3384 n
= TARGET_TRAP_BRKPT
;
3389 n
= env
->int_pgm_code
;
3392 case PGM_PRIVILEGED
:
3393 sig
= TARGET_SIGILL
;
3394 n
= TARGET_ILL_ILLOPC
;
3396 case PGM_PROTECTION
:
3397 case PGM_ADDRESSING
:
3398 sig
= TARGET_SIGSEGV
;
3399 /* XXX: check env->error_code */
3400 n
= TARGET_SEGV_MAPERR
;
3401 addr
= env
->__excp_addr
;
3404 case PGM_SPECIFICATION
:
3405 case PGM_SPECIAL_OP
:
3408 sig
= TARGET_SIGILL
;
3409 n
= TARGET_ILL_ILLOPN
;
3412 case PGM_FIXPT_OVERFLOW
:
3413 sig
= TARGET_SIGFPE
;
3414 n
= TARGET_FPE_INTOVF
;
3416 case PGM_FIXPT_DIVIDE
:
3417 sig
= TARGET_SIGFPE
;
3418 n
= TARGET_FPE_INTDIV
;
3422 n
= (env
->fpc
>> 8) & 0xff;
3424 /* compare-and-trap */
3427 /* An IEEE exception, simulated or otherwise. */
3429 n
= TARGET_FPE_FLTINV
;
3430 } else if (n
& 0x40) {
3431 n
= TARGET_FPE_FLTDIV
;
3432 } else if (n
& 0x20) {
3433 n
= TARGET_FPE_FLTOVF
;
3434 } else if (n
& 0x10) {
3435 n
= TARGET_FPE_FLTUND
;
3436 } else if (n
& 0x08) {
3437 n
= TARGET_FPE_FLTRES
;
3439 /* ??? Quantum exception; BFP, DFP error. */
3442 sig
= TARGET_SIGFPE
;
3447 fprintf(stderr
, "Unhandled program exception: %#x\n", n
);
3448 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3454 addr
= env
->psw
.addr
;
3456 info
.si_signo
= sig
;
3459 info
._sifields
._sigfault
._addr
= addr
;
3460 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3464 fprintf(stderr
, "Unhandled trap: 0x%x\n", trapnr
);
3465 cpu_dump_state(cs
, stderr
, fprintf
, 0);
3468 process_pending_signals (env
);
3472 #endif /* TARGET_S390X */
3474 #ifdef TARGET_TILEGX
3476 static void gen_sigill_reg(CPUTLGState
*env
)
3478 target_siginfo_t info
;
3480 info
.si_signo
= TARGET_SIGILL
;
3482 info
.si_code
= TARGET_ILL_PRVREG
;
3483 info
._sifields
._sigfault
._addr
= env
->pc
;
3484 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3487 static void do_signal(CPUTLGState
*env
, int signo
, int sigcode
)
3489 target_siginfo_t info
;
3491 info
.si_signo
= signo
;
3493 info
._sifields
._sigfault
._addr
= env
->pc
;
3495 if (signo
== TARGET_SIGSEGV
) {
3496 /* The passed in sigcode is a dummy; check for a page mapping
3497 and pass either MAPERR or ACCERR. */
3498 target_ulong addr
= env
->excaddr
;
3499 info
._sifields
._sigfault
._addr
= addr
;
3500 if (page_check_range(addr
, 1, PAGE_VALID
) < 0) {
3501 sigcode
= TARGET_SEGV_MAPERR
;
3503 sigcode
= TARGET_SEGV_ACCERR
;
3506 info
.si_code
= sigcode
;
3508 queue_signal(env
, info
.si_signo
, QEMU_SI_FAULT
, &info
);
3511 static void gen_sigsegv_maperr(CPUTLGState
*env
, target_ulong addr
)
3513 env
->excaddr
= addr
;
3514 do_signal(env
, TARGET_SIGSEGV
, 0);
3517 static void set_regval(CPUTLGState
*env
, uint8_t reg
, uint64_t val
)
3519 if (unlikely(reg
>= TILEGX_R_COUNT
)) {
3530 gen_sigill_reg(env
);
3533 g_assert_not_reached();
3536 env
->regs
[reg
] = val
;
3540 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3541 * memory at the address held in the first source register. If the values are
3542 * not equal, then no memory operation is performed. If the values are equal,
3543 * the 8-byte quantity from the second source register is written into memory
3544 * at the address held in the first source register. In either case, the result
3545 * of the instruction is the value read from memory. The compare and write to
3546 * memory are atomic and thus can be used for synchronization purposes. This
3547 * instruction only operates for addresses aligned to a 8-byte boundary.
3548 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3550 * Functional Description (64-bit)
3551 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3552 * rf[Dest] = memVal;
3553 * if (memVal == SPR[CmpValueSPR])
3554 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3556 * Functional Description (32-bit)
3557 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3558 * rf[Dest] = memVal;
3559 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3560 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3563 * This function also processes exch and exch4 which need not process SPR.
3565 static void do_exch(CPUTLGState
*env
, bool quad
, bool cmp
)
3568 target_long val
, sprval
;
3572 addr
= env
->atomic_srca
;
3573 if (quad
? get_user_s64(val
, addr
) : get_user_s32(val
, addr
)) {
3574 goto sigsegv_maperr
;
3579 sprval
= env
->spregs
[TILEGX_SPR_CMPEXCH
];
3581 sprval
= sextract64(env
->spregs
[TILEGX_SPR_CMPEXCH
], 0, 32);
3585 if (!cmp
|| val
== sprval
) {
3586 target_long valb
= env
->atomic_srcb
;
3587 if (quad
? put_user_u64(valb
, addr
) : put_user_u32(valb
, addr
)) {
3588 goto sigsegv_maperr
;
3592 set_regval(env
, env
->atomic_dstr
, val
);
3598 gen_sigsegv_maperr(env
, addr
);
3601 static void do_fetch(CPUTLGState
*env
, int trapnr
, bool quad
)
3605 target_long val
, valb
;
3609 addr
= env
->atomic_srca
;
3610 valb
= env
->atomic_srcb
;
3611 if (quad
? get_user_s64(val
, addr
) : get_user_s32(val
, addr
)) {
3612 goto sigsegv_maperr
;
3616 case TILEGX_EXCP_OPCODE_FETCHADD
:
3617 case TILEGX_EXCP_OPCODE_FETCHADD4
:
3620 case TILEGX_EXCP_OPCODE_FETCHADDGEZ
:
3626 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4
:
3628 if ((int32_t)valb
< 0) {
3632 case TILEGX_EXCP_OPCODE_FETCHAND
:
3633 case TILEGX_EXCP_OPCODE_FETCHAND4
:
3636 case TILEGX_EXCP_OPCODE_FETCHOR
:
3637 case TILEGX_EXCP_OPCODE_FETCHOR4
:
3641 g_assert_not_reached();
3645 if (quad
? put_user_u64(valb
, addr
) : put_user_u32(valb
, addr
)) {
3646 goto sigsegv_maperr
;
3650 set_regval(env
, env
->atomic_dstr
, val
);
3656 gen_sigsegv_maperr(env
, addr
);
3659 void cpu_loop(CPUTLGState
*env
)
3661 CPUState
*cs
= CPU(tilegx_env_get_cpu(env
));
3666 trapnr
= cpu_exec(cs
);
3668 process_queued_cpu_work(cs
);
3671 case TILEGX_EXCP_SYSCALL
:
3673 abi_ulong ret
= do_syscall(env
, env
->regs
[TILEGX_R_NR
],
3674 env
->regs
[0], env
->regs
[1],
3675 env
->regs
[2], env
->regs
[3],
3676 env
->regs
[4], env
->regs
[5],
3677 env
->regs
[6], env
->regs
[7]);
3678 if (ret
== -TARGET_ERESTARTSYS
) {
3680 } else if (ret
!= -TARGET_QEMU_ESIGRETURN
) {
3681 env
->regs
[TILEGX_R_RE
] = ret
;
3682 env
->regs
[TILEGX_R_ERR
] = TILEGX_IS_ERRNO(ret
) ? -ret
: 0;
3686 case TILEGX_EXCP_OPCODE_EXCH
:
3687 do_exch(env
, true, false);
3689 case TILEGX_EXCP_OPCODE_EXCH4
:
3690 do_exch(env
, false, false);
3692 case TILEGX_EXCP_OPCODE_CMPEXCH
:
3693 do_exch(env
, true, true);
3695 case TILEGX_EXCP_OPCODE_CMPEXCH4
:
3696 do_exch(env
, false, true);
3698 case TILEGX_EXCP_OPCODE_FETCHADD
:
3699 case TILEGX_EXCP_OPCODE_FETCHADDGEZ
:
3700 case TILEGX_EXCP_OPCODE_FETCHAND
:
3701 case TILEGX_EXCP_OPCODE_FETCHOR
:
3702 do_fetch(env
, trapnr
, true);
3704 case TILEGX_EXCP_OPCODE_FETCHADD4
:
3705 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4
:
3706 case TILEGX_EXCP_OPCODE_FETCHAND4
:
3707 case TILEGX_EXCP_OPCODE_FETCHOR4
:
3708 do_fetch(env
, trapnr
, false);
3710 case TILEGX_EXCP_SIGNAL
:
3711 do_signal(env
, env
->signo
, env
->sigcode
);
3713 case TILEGX_EXCP_REG_IDN_ACCESS
:
3714 case TILEGX_EXCP_REG_UDN_ACCESS
:
3715 gen_sigill_reg(env
);
3718 fprintf(stderr
, "trapnr is %d[0x%x].\n", trapnr
, trapnr
);
3719 g_assert_not_reached();
3721 process_pending_signals(env
);
3727 THREAD CPUState
*thread_cpu
;
3729 bool qemu_cpu_is_self(CPUState
*cpu
)
3731 return thread_cpu
== cpu
;
3734 void qemu_cpu_kick(CPUState
*cpu
)
3739 void task_settid(TaskState
*ts
)
3741 if (ts
->ts_tid
== 0) {
3742 ts
->ts_tid
= (pid_t
)syscall(SYS_gettid
);
3746 void stop_all_tasks(void)
3749 * We trust that when using NPTL, start_exclusive()
3750 * handles thread stopping correctly.
3755 /* Assumes contents are already zeroed. */
3756 void init_task_state(TaskState
*ts
)
3761 CPUArchState
*cpu_copy(CPUArchState
*env
)
3763 CPUState
*cpu
= ENV_GET_CPU(env
);
3764 CPUState
*new_cpu
= cpu_init(cpu_model
);
3765 CPUArchState
*new_env
= new_cpu
->env_ptr
;
3769 /* Reset non arch specific state */
3772 memcpy(new_env
, env
, sizeof(CPUArchState
));
3774 /* Clone all break/watchpoints.
3775 Note: Once we support ptrace with hw-debug register access, make sure
3776 BP_CPU break/watchpoints are handled correctly on clone. */
3777 QTAILQ_INIT(&new_cpu
->breakpoints
);
3778 QTAILQ_INIT(&new_cpu
->watchpoints
);
3779 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
3780 cpu_breakpoint_insert(new_cpu
, bp
->pc
, bp
->flags
, NULL
);
3782 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
3783 cpu_watchpoint_insert(new_cpu
, wp
->vaddr
, wp
->len
, wp
->flags
, NULL
);
3789 static void handle_arg_help(const char *arg
)
3791 usage(EXIT_SUCCESS
);
3794 static void handle_arg_log(const char *arg
)
3798 mask
= qemu_str_to_log_mask(arg
);
3800 qemu_print_log_usage(stdout
);
3803 qemu_log_needs_buffers();
3807 static void handle_arg_log_filename(const char *arg
)
3809 qemu_set_log_filename(arg
, &error_fatal
);
3812 static void handle_arg_set_env(const char *arg
)
3814 char *r
, *p
, *token
;
3815 r
= p
= strdup(arg
);
3816 while ((token
= strsep(&p
, ",")) != NULL
) {
3817 if (envlist_setenv(envlist
, token
) != 0) {
3818 usage(EXIT_FAILURE
);
3824 static void handle_arg_unset_env(const char *arg
)
3826 char *r
, *p
, *token
;
3827 r
= p
= strdup(arg
);
3828 while ((token
= strsep(&p
, ",")) != NULL
) {
3829 if (envlist_unsetenv(envlist
, token
) != 0) {
3830 usage(EXIT_FAILURE
);
3836 static void handle_arg_argv0(const char *arg
)
3838 argv0
= strdup(arg
);
3841 static void handle_arg_stack_size(const char *arg
)
3844 guest_stack_size
= strtoul(arg
, &p
, 0);
3845 if (guest_stack_size
== 0) {
3846 usage(EXIT_FAILURE
);
3850 guest_stack_size
*= 1024 * 1024;
3851 } else if (*p
== 'k' || *p
== 'K') {
3852 guest_stack_size
*= 1024;
3856 static void handle_arg_ld_prefix(const char *arg
)
3858 interp_prefix
= strdup(arg
);
3861 static void handle_arg_pagesize(const char *arg
)
3863 qemu_host_page_size
= atoi(arg
);
3864 if (qemu_host_page_size
== 0 ||
3865 (qemu_host_page_size
& (qemu_host_page_size
- 1)) != 0) {
3866 fprintf(stderr
, "page size must be a power of two\n");
3871 static void handle_arg_randseed(const char *arg
)
3873 unsigned long long seed
;
3875 if (parse_uint_full(arg
, &seed
, 0) != 0 || seed
> UINT_MAX
) {
3876 fprintf(stderr
, "Invalid seed number: %s\n", arg
);
3882 static void handle_arg_gdb(const char *arg
)
3884 gdbstub_port
= atoi(arg
);
3887 static void handle_arg_uname(const char *arg
)
3889 qemu_uname_release
= strdup(arg
);
3892 static void handle_arg_cpu(const char *arg
)
3894 cpu_model
= strdup(arg
);
3895 if (cpu_model
== NULL
|| is_help_option(cpu_model
)) {
3896 /* XXX: implement xxx_cpu_list for targets that still miss it */
3897 #if defined(cpu_list)
3898 cpu_list(stdout
, &fprintf
);
3904 static void handle_arg_guest_base(const char *arg
)
3906 guest_base
= strtol(arg
, NULL
, 0);
3907 have_guest_base
= 1;
3910 static void handle_arg_reserved_va(const char *arg
)
3914 reserved_va
= strtoul(arg
, &p
, 0);
3928 unsigned long unshifted
= reserved_va
;
3930 reserved_va
<<= shift
;
3931 if (((reserved_va
>> shift
) != unshifted
)
3932 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3933 || (reserved_va
> (1ul << TARGET_VIRT_ADDR_SPACE_BITS
))
3936 fprintf(stderr
, "Reserved virtual address too big\n");
3941 fprintf(stderr
, "Unrecognised -R size suffix '%s'\n", p
);
3946 static void handle_arg_singlestep(const char *arg
)
3951 static void handle_arg_strace(const char *arg
)
3956 static void handle_arg_version(const char *arg
)
3958 printf("qemu-" TARGET_NAME
" version " QEMU_VERSION QEMU_PKGVERSION
3959 "\n" QEMU_COPYRIGHT
"\n");
3963 static char *trace_file
;
3964 static void handle_arg_trace(const char *arg
)
3967 trace_file
= trace_opt_parse(arg
);
3970 struct qemu_argument
{
3974 void (*handle_opt
)(const char *arg
);
3975 const char *example
;
3979 static const struct qemu_argument arg_table
[] = {
3980 {"h", "", false, handle_arg_help
,
3981 "", "print this help"},
3982 {"help", "", false, handle_arg_help
,
3984 {"g", "QEMU_GDB", true, handle_arg_gdb
,
3985 "port", "wait gdb connection to 'port'"},
3986 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix
,
3987 "path", "set the elf interpreter prefix to 'path'"},
3988 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size
,
3989 "size", "set the stack size to 'size' bytes"},
3990 {"cpu", "QEMU_CPU", true, handle_arg_cpu
,
3991 "model", "select CPU (-cpu help for list)"},
3992 {"E", "QEMU_SET_ENV", true, handle_arg_set_env
,
3993 "var=value", "sets targets environment variable (see below)"},
3994 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env
,
3995 "var", "unsets targets environment variable (see below)"},
3996 {"0", "QEMU_ARGV0", true, handle_arg_argv0
,
3997 "argv0", "forces target process argv[0] to be 'argv0'"},
3998 {"r", "QEMU_UNAME", true, handle_arg_uname
,
3999 "uname", "set qemu uname release string to 'uname'"},
4000 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base
,
4001 "address", "set guest_base address to 'address'"},
4002 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va
,
4003 "size", "reserve 'size' bytes for guest virtual address space"},
4004 {"d", "QEMU_LOG", true, handle_arg_log
,
4005 "item[,...]", "enable logging of specified items "
4006 "(use '-d help' for a list of items)"},
4007 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename
,
4008 "logfile", "write logs to 'logfile' (default stderr)"},
4009 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize
,
4010 "pagesize", "set the host page size to 'pagesize'"},
4011 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep
,
4012 "", "run in singlestep mode"},
4013 {"strace", "QEMU_STRACE", false, handle_arg_strace
,
4014 "", "log system calls"},
4015 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed
,
4016 "", "Seed for pseudo-random number generator"},
4017 {"trace", "QEMU_TRACE", true, handle_arg_trace
,
4018 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
4019 {"version", "QEMU_VERSION", false, handle_arg_version
,
4020 "", "display version information and exit"},
4021 {NULL
, NULL
, false, NULL
, NULL
, NULL
}
4024 static void usage(int exitcode
)
4026 const struct qemu_argument
*arginfo
;
4030 printf("usage: qemu-" TARGET_NAME
" [options] program [arguments...]\n"
4031 "Linux CPU emulator (compiled for " TARGET_NAME
" emulation)\n"
4033 "Options and associated environment variables:\n"
4036 /* Calculate column widths. We must always have at least enough space
4037 * for the column header.
4039 maxarglen
= strlen("Argument");
4040 maxenvlen
= strlen("Env-variable");
4042 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
4043 int arglen
= strlen(arginfo
->argv
);
4044 if (arginfo
->has_arg
) {
4045 arglen
+= strlen(arginfo
->example
) + 1;
4047 if (strlen(arginfo
->env
) > maxenvlen
) {
4048 maxenvlen
= strlen(arginfo
->env
);
4050 if (arglen
> maxarglen
) {
4055 printf("%-*s %-*s Description\n", maxarglen
+1, "Argument",
4056 maxenvlen
, "Env-variable");
4058 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
4059 if (arginfo
->has_arg
) {
4060 printf("-%s %-*s %-*s %s\n", arginfo
->argv
,
4061 (int)(maxarglen
- strlen(arginfo
->argv
) - 1),
4062 arginfo
->example
, maxenvlen
, arginfo
->env
, arginfo
->help
);
4064 printf("-%-*s %-*s %s\n", maxarglen
, arginfo
->argv
,
4065 maxenvlen
, arginfo
->env
,
4072 "QEMU_LD_PREFIX = %s\n"
4073 "QEMU_STACK_SIZE = %ld byte\n",
4078 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4079 "QEMU_UNSET_ENV environment variables to set and unset\n"
4080 "environment variables for the target process.\n"
4081 "It is possible to provide several variables by separating them\n"
4082 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4083 "provide the -E and -U options multiple times.\n"
4084 "The following lines are equivalent:\n"
4085 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4086 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4087 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4088 "Note that if you provide several changes to a single variable\n"
4089 "the last change will stay in effect.\n");
4094 static int parse_args(int argc
, char **argv
)
4098 const struct qemu_argument
*arginfo
;
4100 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
4101 if (arginfo
->env
== NULL
) {
4105 r
= getenv(arginfo
->env
);
4107 arginfo
->handle_opt(r
);
4113 if (optind
>= argc
) {
4122 if (!strcmp(r
, "-")) {
4125 /* Treat --foo the same as -foo. */
4130 for (arginfo
= arg_table
; arginfo
->handle_opt
!= NULL
; arginfo
++) {
4131 if (!strcmp(r
, arginfo
->argv
)) {
4132 if (arginfo
->has_arg
) {
4133 if (optind
>= argc
) {
4134 (void) fprintf(stderr
,
4135 "qemu: missing argument for option '%s'\n", r
);
4138 arginfo
->handle_opt(argv
[optind
]);
4141 arginfo
->handle_opt(NULL
);
4147 /* no option matched the current argv */
4148 if (arginfo
->handle_opt
== NULL
) {
4149 (void) fprintf(stderr
, "qemu: unknown option '%s'\n", r
);
4154 if (optind
>= argc
) {
4155 (void) fprintf(stderr
, "qemu: no user program specified\n");
4159 filename
= argv
[optind
];
4160 exec_path
= argv
[optind
];
4165 int main(int argc
, char **argv
, char **envp
)
4167 struct target_pt_regs regs1
, *regs
= ®s1
;
4168 struct image_info info1
, *info
= &info1
;
4169 struct linux_binprm bprm
;
4174 char **target_environ
, **wrk
;
4181 module_call_init(MODULE_INIT_TRACE
);
4182 qemu_init_cpu_list();
4183 module_call_init(MODULE_INIT_QOM
);
4185 if ((envlist
= envlist_create()) == NULL
) {
4186 (void) fprintf(stderr
, "Unable to allocate envlist\n");
4190 /* add current environment into the list */
4191 for (wrk
= environ
; *wrk
!= NULL
; wrk
++) {
4192 (void) envlist_setenv(envlist
, *wrk
);
4195 /* Read the stack limit from the kernel. If it's "unlimited",
4196 then we can do little else besides use the default. */
4199 if (getrlimit(RLIMIT_STACK
, &lim
) == 0
4200 && lim
.rlim_cur
!= RLIM_INFINITY
4201 && lim
.rlim_cur
== (target_long
)lim
.rlim_cur
) {
4202 guest_stack_size
= lim
.rlim_cur
;
4210 qemu_add_opts(&qemu_trace_opts
);
4212 optind
= parse_args(argc
, argv
);
4214 if (!trace_init_backends()) {
4217 trace_init_file(trace_file
);
4220 memset(regs
, 0, sizeof(struct target_pt_regs
));
4222 /* Zero out image_info */
4223 memset(info
, 0, sizeof(struct image_info
));
4225 memset(&bprm
, 0, sizeof (bprm
));
4227 /* Scan interp_prefix dir for replacement files. */
4228 init_paths(interp_prefix
);
4230 init_qemu_uname_release();
4232 if (cpu_model
== NULL
) {
4233 #if defined(TARGET_I386)
4234 #ifdef TARGET_X86_64
4235 cpu_model
= "qemu64";
4237 cpu_model
= "qemu32";
4239 #elif defined(TARGET_ARM)
4241 #elif defined(TARGET_UNICORE32)
4243 #elif defined(TARGET_M68K)
4245 #elif defined(TARGET_SPARC)
4246 #ifdef TARGET_SPARC64
4247 cpu_model
= "TI UltraSparc II";
4249 cpu_model
= "Fujitsu MB86904";
4251 #elif defined(TARGET_MIPS)
4252 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4257 #elif defined TARGET_OPENRISC
4258 cpu_model
= "or1200";
4259 #elif defined(TARGET_PPC)
4260 # ifdef TARGET_PPC64
4261 cpu_model
= "POWER8";
4265 #elif defined TARGET_SH4
4266 cpu_model
= TYPE_SH7785_CPU
;
4272 /* NOTE: we need to init the CPU at this stage to get
4273 qemu_host_page_size */
4274 cpu
= cpu_init(cpu_model
);
4276 fprintf(stderr
, "Unable to find CPU definition\n");
4284 if (getenv("QEMU_STRACE")) {
4288 if (getenv("QEMU_RAND_SEED")) {
4289 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4292 target_environ
= envlist_to_environ(envlist
, NULL
);
4293 envlist_free(envlist
);
4296 * Now that page sizes are configured in cpu_init() we can do
4297 * proper page alignment for guest_base.
4299 guest_base
= HOST_PAGE_ALIGN(guest_base
);
4301 if (reserved_va
|| have_guest_base
) {
4302 guest_base
= init_guest_space(guest_base
, reserved_va
, 0,
4304 if (guest_base
== (unsigned long)-1) {
4305 fprintf(stderr
, "Unable to reserve 0x%lx bytes of virtual address "
4306 "space for use as guest address space (check your virtual "
4307 "memory ulimit setting or reserve less using -R option)\n",
4313 mmap_next_start
= reserved_va
;
4318 * Read in mmap_min_addr kernel parameter. This value is used
4319 * When loading the ELF image to determine whether guest_base
4320 * is needed. It is also used in mmap_find_vma.
4325 if ((fp
= fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL
) {
4327 if (fscanf(fp
, "%lu", &tmp
) == 1) {
4328 mmap_min_addr
= tmp
;
4329 qemu_log_mask(CPU_LOG_PAGE
, "host mmap_min_addr=0x%lx\n", mmap_min_addr
);
4336 * Prepare copy of argv vector for target.
4338 target_argc
= argc
- optind
;
4339 target_argv
= calloc(target_argc
+ 1, sizeof (char *));
4340 if (target_argv
== NULL
) {
4341 (void) fprintf(stderr
, "Unable to allocate memory for target_argv\n");
4346 * If argv0 is specified (using '-0' switch) we replace
4347 * argv[0] pointer with the given one.
4350 if (argv0
!= NULL
) {
4351 target_argv
[i
++] = strdup(argv0
);
4353 for (; i
< target_argc
; i
++) {
4354 target_argv
[i
] = strdup(argv
[optind
+ i
]);
4356 target_argv
[target_argc
] = NULL
;
4358 ts
= g_new0(TaskState
, 1);
4359 init_task_state(ts
);
4360 /* build Task State */
4366 execfd
= qemu_getauxval(AT_EXECFD
);
4368 execfd
= open(filename
, O_RDONLY
);
4370 printf("Error while loading %s: %s\n", filename
, strerror(errno
));
4371 _exit(EXIT_FAILURE
);
4375 ret
= loader_exec(execfd
, filename
, target_argv
, target_environ
, regs
,
4378 printf("Error while loading %s: %s\n", filename
, strerror(-ret
));
4379 _exit(EXIT_FAILURE
);
4382 for (wrk
= target_environ
; *wrk
; wrk
++) {
4386 free(target_environ
);
4388 if (qemu_loglevel_mask(CPU_LOG_PAGE
)) {
4389 qemu_log("guest_base 0x%lx\n", guest_base
);
4392 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx
"\n", info
->start_brk
);
4393 qemu_log("end_code 0x" TARGET_ABI_FMT_lx
"\n", info
->end_code
);
4394 qemu_log("start_code 0x" TARGET_ABI_FMT_lx
"\n",
4396 qemu_log("start_data 0x" TARGET_ABI_FMT_lx
"\n",
4398 qemu_log("end_data 0x" TARGET_ABI_FMT_lx
"\n", info
->end_data
);
4399 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx
"\n",
4401 qemu_log("brk 0x" TARGET_ABI_FMT_lx
"\n", info
->brk
);
4402 qemu_log("entry 0x" TARGET_ABI_FMT_lx
"\n", info
->entry
);
4405 target_set_brk(info
->brk
);
4409 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4410 generating the prologue until now so that the prologue can take
4411 the real value of GUEST_BASE into account. */
4412 tcg_prologue_init(&tcg_ctx
);
4414 #if defined(TARGET_I386)
4415 env
->cr
[0] = CR0_PG_MASK
| CR0_WP_MASK
| CR0_PE_MASK
;
4416 env
->hflags
|= HF_PE_MASK
| HF_CPL_MASK
;
4417 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
4418 env
->cr
[4] |= CR4_OSFXSR_MASK
;
4419 env
->hflags
|= HF_OSFXSR_MASK
;
4421 #ifndef TARGET_ABI32
4422 /* enable 64 bit mode if possible */
4423 if (!(env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
)) {
4424 fprintf(stderr
, "The selected x86 CPU does not support 64 bit mode\n");
4427 env
->cr
[4] |= CR4_PAE_MASK
;
4428 env
->efer
|= MSR_EFER_LMA
| MSR_EFER_LME
;
4429 env
->hflags
|= HF_LMA_MASK
;
4432 /* flags setup : we activate the IRQs by default as in user mode */
4433 env
->eflags
|= IF_MASK
;
4435 /* linux register setup */
4436 #ifndef TARGET_ABI32
4437 env
->regs
[R_EAX
] = regs
->rax
;
4438 env
->regs
[R_EBX
] = regs
->rbx
;
4439 env
->regs
[R_ECX
] = regs
->rcx
;
4440 env
->regs
[R_EDX
] = regs
->rdx
;
4441 env
->regs
[R_ESI
] = regs
->rsi
;
4442 env
->regs
[R_EDI
] = regs
->rdi
;
4443 env
->regs
[R_EBP
] = regs
->rbp
;
4444 env
->regs
[R_ESP
] = regs
->rsp
;
4445 env
->eip
= regs
->rip
;
4447 env
->regs
[R_EAX
] = regs
->eax
;
4448 env
->regs
[R_EBX
] = regs
->ebx
;
4449 env
->regs
[R_ECX
] = regs
->ecx
;
4450 env
->regs
[R_EDX
] = regs
->edx
;
4451 env
->regs
[R_ESI
] = regs
->esi
;
4452 env
->regs
[R_EDI
] = regs
->edi
;
4453 env
->regs
[R_EBP
] = regs
->ebp
;
4454 env
->regs
[R_ESP
] = regs
->esp
;
4455 env
->eip
= regs
->eip
;
4458 /* linux interrupt setup */
4459 #ifndef TARGET_ABI32
4460 env
->idt
.limit
= 511;
4462 env
->idt
.limit
= 255;
4464 env
->idt
.base
= target_mmap(0, sizeof(uint64_t) * (env
->idt
.limit
+ 1),
4465 PROT_READ
|PROT_WRITE
,
4466 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
4467 idt_table
= g2h(env
->idt
.base
);
4490 /* linux segment setup */
4492 uint64_t *gdt_table
;
4493 env
->gdt
.base
= target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES
,
4494 PROT_READ
|PROT_WRITE
,
4495 MAP_ANONYMOUS
|MAP_PRIVATE
, -1, 0);
4496 env
->gdt
.limit
= sizeof(uint64_t) * TARGET_GDT_ENTRIES
- 1;
4497 gdt_table
= g2h(env
->gdt
.base
);
4499 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
4500 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4501 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
4503 /* 64 bit code segment */
4504 write_dt(&gdt_table
[__USER_CS
>> 3], 0, 0xfffff,
4505 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4507 (3 << DESC_DPL_SHIFT
) | (0xa << DESC_TYPE_SHIFT
));
4509 write_dt(&gdt_table
[__USER_DS
>> 3], 0, 0xfffff,
4510 DESC_G_MASK
| DESC_B_MASK
| DESC_P_MASK
| DESC_S_MASK
|
4511 (3 << DESC_DPL_SHIFT
) | (0x2 << DESC_TYPE_SHIFT
));
4513 cpu_x86_load_seg(env
, R_CS
, __USER_CS
);
4514 cpu_x86_load_seg(env
, R_SS
, __USER_DS
);
4516 cpu_x86_load_seg(env
, R_DS
, __USER_DS
);
4517 cpu_x86_load_seg(env
, R_ES
, __USER_DS
);
4518 cpu_x86_load_seg(env
, R_FS
, __USER_DS
);
4519 cpu_x86_load_seg(env
, R_GS
, __USER_DS
);
4520 /* This hack makes Wine work... */
4521 env
->segs
[R_FS
].selector
= 0;
4523 cpu_x86_load_seg(env
, R_DS
, 0);
4524 cpu_x86_load_seg(env
, R_ES
, 0);
4525 cpu_x86_load_seg(env
, R_FS
, 0);
4526 cpu_x86_load_seg(env
, R_GS
, 0);
4528 #elif defined(TARGET_AARCH64)
4532 if (!(arm_feature(env
, ARM_FEATURE_AARCH64
))) {
4534 "The selected ARM CPU does not support 64 bit mode\n");
4538 for (i
= 0; i
< 31; i
++) {
4539 env
->xregs
[i
] = regs
->regs
[i
];
4542 env
->xregs
[31] = regs
->sp
;
4544 #elif defined(TARGET_ARM)
4547 cpsr_write(env
, regs
->uregs
[16], CPSR_USER
| CPSR_EXEC
,
4549 for(i
= 0; i
< 16; i
++) {
4550 env
->regs
[i
] = regs
->uregs
[i
];
4552 #ifdef TARGET_WORDS_BIGENDIAN
4554 if (EF_ARM_EABI_VERSION(info
->elf_flags
) >= EF_ARM_EABI_VER4
4555 && (info
->elf_flags
& EF_ARM_BE8
)) {
4556 env
->uncached_cpsr
|= CPSR_E
;
4557 env
->cp15
.sctlr_el
[1] |= SCTLR_E0E
;
4559 env
->cp15
.sctlr_el
[1] |= SCTLR_B
;
4563 #elif defined(TARGET_UNICORE32)
4566 cpu_asr_write(env
, regs
->uregs
[32], 0xffffffff);
4567 for (i
= 0; i
< 32; i
++) {
4568 env
->regs
[i
] = regs
->uregs
[i
];
4571 #elif defined(TARGET_SPARC)
4575 env
->npc
= regs
->npc
;
4577 for(i
= 0; i
< 8; i
++)
4578 env
->gregs
[i
] = regs
->u_regs
[i
];
4579 for(i
= 0; i
< 8; i
++)
4580 env
->regwptr
[i
] = regs
->u_regs
[i
+ 8];
4582 #elif defined(TARGET_PPC)
4586 #if defined(TARGET_PPC64)
4587 int flag
= (env
->insns_flags2
& PPC2_BOOKE206
) ? MSR_CM
: MSR_SF
;
4588 #if defined(TARGET_ABI32)
4589 env
->msr
&= ~((target_ulong
)1 << flag
);
4591 env
->msr
|= (target_ulong
)1 << flag
;
4594 env
->nip
= regs
->nip
;
4595 for(i
= 0; i
< 32; i
++) {
4596 env
->gpr
[i
] = regs
->gpr
[i
];
4599 #elif defined(TARGET_M68K)
4602 env
->dregs
[0] = regs
->d0
;
4603 env
->dregs
[1] = regs
->d1
;
4604 env
->dregs
[2] = regs
->d2
;
4605 env
->dregs
[3] = regs
->d3
;
4606 env
->dregs
[4] = regs
->d4
;
4607 env
->dregs
[5] = regs
->d5
;
4608 env
->dregs
[6] = regs
->d6
;
4609 env
->dregs
[7] = regs
->d7
;
4610 env
->aregs
[0] = regs
->a0
;
4611 env
->aregs
[1] = regs
->a1
;
4612 env
->aregs
[2] = regs
->a2
;
4613 env
->aregs
[3] = regs
->a3
;
4614 env
->aregs
[4] = regs
->a4
;
4615 env
->aregs
[5] = regs
->a5
;
4616 env
->aregs
[6] = regs
->a6
;
4617 env
->aregs
[7] = regs
->usp
;
4619 ts
->sim_syscalls
= 1;
4621 #elif defined(TARGET_MICROBLAZE)
4623 env
->regs
[0] = regs
->r0
;
4624 env
->regs
[1] = regs
->r1
;
4625 env
->regs
[2] = regs
->r2
;
4626 env
->regs
[3] = regs
->r3
;
4627 env
->regs
[4] = regs
->r4
;
4628 env
->regs
[5] = regs
->r5
;
4629 env
->regs
[6] = regs
->r6
;
4630 env
->regs
[7] = regs
->r7
;
4631 env
->regs
[8] = regs
->r8
;
4632 env
->regs
[9] = regs
->r9
;
4633 env
->regs
[10] = regs
->r10
;
4634 env
->regs
[11] = regs
->r11
;
4635 env
->regs
[12] = regs
->r12
;
4636 env
->regs
[13] = regs
->r13
;
4637 env
->regs
[14] = regs
->r14
;
4638 env
->regs
[15] = regs
->r15
;
4639 env
->regs
[16] = regs
->r16
;
4640 env
->regs
[17] = regs
->r17
;
4641 env
->regs
[18] = regs
->r18
;
4642 env
->regs
[19] = regs
->r19
;
4643 env
->regs
[20] = regs
->r20
;
4644 env
->regs
[21] = regs
->r21
;
4645 env
->regs
[22] = regs
->r22
;
4646 env
->regs
[23] = regs
->r23
;
4647 env
->regs
[24] = regs
->r24
;
4648 env
->regs
[25] = regs
->r25
;
4649 env
->regs
[26] = regs
->r26
;
4650 env
->regs
[27] = regs
->r27
;
4651 env
->regs
[28] = regs
->r28
;
4652 env
->regs
[29] = regs
->r29
;
4653 env
->regs
[30] = regs
->r30
;
4654 env
->regs
[31] = regs
->r31
;
4655 env
->sregs
[SR_PC
] = regs
->pc
;
4657 #elif defined(TARGET_MIPS)
4661 for(i
= 0; i
< 32; i
++) {
4662 env
->active_tc
.gpr
[i
] = regs
->regs
[i
];
4664 env
->active_tc
.PC
= regs
->cp0_epc
& ~(target_ulong
)1;
4665 if (regs
->cp0_epc
& 1) {
4666 env
->hflags
|= MIPS_HFLAG_M16
;
4668 if (((info
->elf_flags
& EF_MIPS_NAN2008
) != 0) !=
4669 ((env
->active_fpu
.fcr31
& (1 << FCR31_NAN2008
)) != 0)) {
4670 if ((env
->active_fpu
.fcr31_rw_bitmask
&
4671 (1 << FCR31_NAN2008
)) == 0) {
4672 fprintf(stderr
, "ELF binary's NaN mode not supported by CPU\n");
4675 if ((info
->elf_flags
& EF_MIPS_NAN2008
) != 0) {
4676 env
->active_fpu
.fcr31
|= (1 << FCR31_NAN2008
);
4678 env
->active_fpu
.fcr31
&= ~(1 << FCR31_NAN2008
);
4680 restore_snan_bit_mode(env
);
4683 #elif defined(TARGET_OPENRISC)
4687 for (i
= 0; i
< 32; i
++) {
4688 env
->gpr
[i
] = regs
->gpr
[i
];
4694 #elif defined(TARGET_SH4)
4698 for(i
= 0; i
< 16; i
++) {
4699 env
->gregs
[i
] = regs
->regs
[i
];
4703 #elif defined(TARGET_ALPHA)
4707 for(i
= 0; i
< 28; i
++) {
4708 env
->ir
[i
] = ((abi_ulong
*)regs
)[i
];
4710 env
->ir
[IR_SP
] = regs
->usp
;
4713 #elif defined(TARGET_CRIS)
4715 env
->regs
[0] = regs
->r0
;
4716 env
->regs
[1] = regs
->r1
;
4717 env
->regs
[2] = regs
->r2
;
4718 env
->regs
[3] = regs
->r3
;
4719 env
->regs
[4] = regs
->r4
;
4720 env
->regs
[5] = regs
->r5
;
4721 env
->regs
[6] = regs
->r6
;
4722 env
->regs
[7] = regs
->r7
;
4723 env
->regs
[8] = regs
->r8
;
4724 env
->regs
[9] = regs
->r9
;
4725 env
->regs
[10] = regs
->r10
;
4726 env
->regs
[11] = regs
->r11
;
4727 env
->regs
[12] = regs
->r12
;
4728 env
->regs
[13] = regs
->r13
;
4729 env
->regs
[14] = info
->start_stack
;
4730 env
->regs
[15] = regs
->acr
;
4731 env
->pc
= regs
->erp
;
4733 #elif defined(TARGET_S390X)
4736 for (i
= 0; i
< 16; i
++) {
4737 env
->regs
[i
] = regs
->gprs
[i
];
4739 env
->psw
.mask
= regs
->psw
.mask
;
4740 env
->psw
.addr
= regs
->psw
.addr
;
4742 #elif defined(TARGET_TILEGX)
4745 for (i
= 0; i
< TILEGX_R_COUNT
; i
++) {
4746 env
->regs
[i
] = regs
->regs
[i
];
4748 for (i
= 0; i
< TILEGX_SPR_COUNT
; i
++) {
4754 #error unsupported target CPU
4757 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4758 ts
->stack_base
= info
->start_stack
;
4759 ts
->heap_base
= info
->brk
;
4760 /* This will be filled in on the first SYS_HEAPINFO call. */
4765 if (gdbserver_start(gdbstub_port
) < 0) {
4766 fprintf(stderr
, "qemu: could not open gdbserver on port %d\n",
4770 gdb_handlesig(cpu
, 0);