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linux-user: Add qemu_cpu_is_self() and qemu_cpu_kick()
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1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36 #include "exec/log.h"
37 #include "trace/control.h"
38 #include "glib-compat.h"
39
40 char *exec_path;
41
42 int singlestep;
43 static const char *filename;
44 static const char *argv0;
45 static int gdbstub_port;
46 static envlist_t *envlist;
47 static const char *cpu_model;
48 unsigned long mmap_min_addr;
49 unsigned long guest_base;
50 int have_guest_base;
51
52 #define EXCP_DUMP(env, fmt, ...) \
53 do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61 } while (0)
62
63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64 /*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
71 # ifdef TARGET_MIPS
72 /* MIPS only supports 31 bits of virtual address space for user space */
73 unsigned long reserved_va = 0x77000000;
74 # else
75 unsigned long reserved_va = 0xf7000000;
76 # endif
77 #else
78 unsigned long reserved_va;
79 #endif
80
81 static void usage(int exitcode);
82
83 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
84 const char *qemu_uname_release;
85
86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
89 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
90
91 void gemu_log(const char *fmt, ...)
92 {
93 va_list ap;
94
95 va_start(ap, fmt);
96 vfprintf(stderr, fmt, ap);
97 va_end(ap);
98 }
99
100 #if defined(TARGET_I386)
101 int cpu_get_pic_interrupt(CPUX86State *env)
102 {
103 return -1;
104 }
105 #endif
106
107 /***********************************************************/
108 /* Helper routines for implementing atomic operations. */
109
110 /* To implement exclusive operations we force all cpus to syncronise.
111 We don't require a full sync, only that no cpus are executing guest code.
112 The alternative is to map target atomic ops onto host equivalents,
113 which requires quite a lot of per host/target work. */
114 static QemuMutex cpu_list_lock;
115 static QemuMutex exclusive_lock;
116 static QemuCond exclusive_cond;
117 static QemuCond exclusive_resume;
118 static int pending_cpus;
119
120 void qemu_init_cpu_loop(void)
121 {
122 qemu_mutex_init(&cpu_list_lock);
123 qemu_mutex_init(&exclusive_lock);
124 qemu_cond_init(&exclusive_cond);
125 qemu_cond_init(&exclusive_resume);
126 }
127
128 /* Make sure everything is in a consistent state for calling fork(). */
129 void fork_start(void)
130 {
131 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
132 qemu_mutex_lock(&exclusive_lock);
133 mmap_fork_start();
134 }
135
136 void fork_end(int child)
137 {
138 mmap_fork_end(child);
139 if (child) {
140 CPUState *cpu, *next_cpu;
141 /* Child processes created by fork() only have a single thread.
142 Discard information about the parent threads. */
143 CPU_FOREACH_SAFE(cpu, next_cpu) {
144 if (cpu != thread_cpu) {
145 QTAILQ_REMOVE(&cpus, cpu, node);
146 }
147 }
148 pending_cpus = 0;
149 qemu_mutex_init(&exclusive_lock);
150 qemu_mutex_init(&cpu_list_lock);
151 qemu_cond_init(&exclusive_cond);
152 qemu_cond_init(&exclusive_resume);
153 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
154 gdbserver_fork(thread_cpu);
155 } else {
156 qemu_mutex_unlock(&exclusive_lock);
157 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
158 }
159 }
160
161 /* Wait for pending exclusive operations to complete. The exclusive lock
162 must be held. */
163 static inline void exclusive_idle(void)
164 {
165 while (pending_cpus) {
166 qemu_cond_wait(&exclusive_resume, &exclusive_lock);
167 }
168 }
169
170 /* Start an exclusive operation.
171 Must only be called from outside cpu_exec. */
172 static inline void start_exclusive(void)
173 {
174 CPUState *other_cpu;
175
176 qemu_mutex_lock(&exclusive_lock);
177 exclusive_idle();
178
179 pending_cpus = 1;
180 /* Make all other cpus stop executing. */
181 CPU_FOREACH(other_cpu) {
182 if (other_cpu->running) {
183 pending_cpus++;
184 cpu_exit(other_cpu);
185 }
186 }
187 while (pending_cpus > 1) {
188 qemu_cond_wait(&exclusive_cond, &exclusive_lock);
189 }
190 }
191
192 /* Finish an exclusive operation. */
193 static inline void __attribute__((unused)) end_exclusive(void)
194 {
195 pending_cpus = 0;
196 qemu_cond_broadcast(&exclusive_resume);
197 qemu_mutex_unlock(&exclusive_lock);
198 }
199
200 /* Wait for exclusive ops to finish, and begin cpu execution. */
201 static inline void cpu_exec_start(CPUState *cpu)
202 {
203 qemu_mutex_lock(&exclusive_lock);
204 exclusive_idle();
205 cpu->running = true;
206 qemu_mutex_unlock(&exclusive_lock);
207 }
208
209 /* Mark cpu as not executing, and release pending exclusive ops. */
210 static inline void cpu_exec_end(CPUState *cpu)
211 {
212 qemu_mutex_lock(&exclusive_lock);
213 cpu->running = false;
214 if (pending_cpus > 1) {
215 pending_cpus--;
216 if (pending_cpus == 1) {
217 qemu_cond_signal(&exclusive_cond);
218 }
219 }
220 exclusive_idle();
221 qemu_mutex_unlock(&exclusive_lock);
222 }
223
224 void cpu_list_lock(void)
225 {
226 qemu_mutex_lock(&cpu_list_lock);
227 }
228
229 void cpu_list_unlock(void)
230 {
231 qemu_mutex_unlock(&cpu_list_lock);
232 }
233
234
235 #ifdef TARGET_I386
236 /***********************************************************/
237 /* CPUX86 core interface */
238
239 uint64_t cpu_get_tsc(CPUX86State *env)
240 {
241 return cpu_get_host_ticks();
242 }
243
244 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
245 int flags)
246 {
247 unsigned int e1, e2;
248 uint32_t *p;
249 e1 = (addr << 16) | (limit & 0xffff);
250 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
251 e2 |= flags;
252 p = ptr;
253 p[0] = tswap32(e1);
254 p[1] = tswap32(e2);
255 }
256
257 static uint64_t *idt_table;
258 #ifdef TARGET_X86_64
259 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
260 uint64_t addr, unsigned int sel)
261 {
262 uint32_t *p, e1, e2;
263 e1 = (addr & 0xffff) | (sel << 16);
264 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
265 p = ptr;
266 p[0] = tswap32(e1);
267 p[1] = tswap32(e2);
268 p[2] = tswap32(addr >> 32);
269 p[3] = 0;
270 }
271 /* only dpl matters as we do only user space emulation */
272 static void set_idt(int n, unsigned int dpl)
273 {
274 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
275 }
276 #else
277 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
278 uint32_t addr, unsigned int sel)
279 {
280 uint32_t *p, e1, e2;
281 e1 = (addr & 0xffff) | (sel << 16);
282 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
283 p = ptr;
284 p[0] = tswap32(e1);
285 p[1] = tswap32(e2);
286 }
287
288 /* only dpl matters as we do only user space emulation */
289 static void set_idt(int n, unsigned int dpl)
290 {
291 set_gate(idt_table + n, 0, dpl, 0, 0);
292 }
293 #endif
294
295 void cpu_loop(CPUX86State *env)
296 {
297 CPUState *cs = CPU(x86_env_get_cpu(env));
298 int trapnr;
299 abi_ulong pc;
300 abi_ulong ret;
301 target_siginfo_t info;
302
303 for(;;) {
304 cpu_exec_start(cs);
305 trapnr = cpu_exec(cs);
306 cpu_exec_end(cs);
307 switch(trapnr) {
308 case 0x80:
309 /* linux syscall from int $0x80 */
310 ret = do_syscall(env,
311 env->regs[R_EAX],
312 env->regs[R_EBX],
313 env->regs[R_ECX],
314 env->regs[R_EDX],
315 env->regs[R_ESI],
316 env->regs[R_EDI],
317 env->regs[R_EBP],
318 0, 0);
319 if (ret == -TARGET_ERESTARTSYS) {
320 env->eip -= 2;
321 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
322 env->regs[R_EAX] = ret;
323 }
324 break;
325 #ifndef TARGET_ABI32
326 case EXCP_SYSCALL:
327 /* linux syscall from syscall instruction */
328 ret = do_syscall(env,
329 env->regs[R_EAX],
330 env->regs[R_EDI],
331 env->regs[R_ESI],
332 env->regs[R_EDX],
333 env->regs[10],
334 env->regs[8],
335 env->regs[9],
336 0, 0);
337 if (ret == -TARGET_ERESTARTSYS) {
338 env->eip -= 2;
339 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
340 env->regs[R_EAX] = ret;
341 }
342 break;
343 #endif
344 case EXCP0B_NOSEG:
345 case EXCP0C_STACK:
346 info.si_signo = TARGET_SIGBUS;
347 info.si_errno = 0;
348 info.si_code = TARGET_SI_KERNEL;
349 info._sifields._sigfault._addr = 0;
350 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
351 break;
352 case EXCP0D_GPF:
353 /* XXX: potential problem if ABI32 */
354 #ifndef TARGET_X86_64
355 if (env->eflags & VM_MASK) {
356 handle_vm86_fault(env);
357 } else
358 #endif
359 {
360 info.si_signo = TARGET_SIGSEGV;
361 info.si_errno = 0;
362 info.si_code = TARGET_SI_KERNEL;
363 info._sifields._sigfault._addr = 0;
364 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
365 }
366 break;
367 case EXCP0E_PAGE:
368 info.si_signo = TARGET_SIGSEGV;
369 info.si_errno = 0;
370 if (!(env->error_code & 1))
371 info.si_code = TARGET_SEGV_MAPERR;
372 else
373 info.si_code = TARGET_SEGV_ACCERR;
374 info._sifields._sigfault._addr = env->cr[2];
375 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
376 break;
377 case EXCP00_DIVZ:
378 #ifndef TARGET_X86_64
379 if (env->eflags & VM_MASK) {
380 handle_vm86_trap(env, trapnr);
381 } else
382 #endif
383 {
384 /* division by zero */
385 info.si_signo = TARGET_SIGFPE;
386 info.si_errno = 0;
387 info.si_code = TARGET_FPE_INTDIV;
388 info._sifields._sigfault._addr = env->eip;
389 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
390 }
391 break;
392 case EXCP01_DB:
393 case EXCP03_INT3:
394 #ifndef TARGET_X86_64
395 if (env->eflags & VM_MASK) {
396 handle_vm86_trap(env, trapnr);
397 } else
398 #endif
399 {
400 info.si_signo = TARGET_SIGTRAP;
401 info.si_errno = 0;
402 if (trapnr == EXCP01_DB) {
403 info.si_code = TARGET_TRAP_BRKPT;
404 info._sifields._sigfault._addr = env->eip;
405 } else {
406 info.si_code = TARGET_SI_KERNEL;
407 info._sifields._sigfault._addr = 0;
408 }
409 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
410 }
411 break;
412 case EXCP04_INTO:
413 case EXCP05_BOUND:
414 #ifndef TARGET_X86_64
415 if (env->eflags & VM_MASK) {
416 handle_vm86_trap(env, trapnr);
417 } else
418 #endif
419 {
420 info.si_signo = TARGET_SIGSEGV;
421 info.si_errno = 0;
422 info.si_code = TARGET_SI_KERNEL;
423 info._sifields._sigfault._addr = 0;
424 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
425 }
426 break;
427 case EXCP06_ILLOP:
428 info.si_signo = TARGET_SIGILL;
429 info.si_errno = 0;
430 info.si_code = TARGET_ILL_ILLOPN;
431 info._sifields._sigfault._addr = env->eip;
432 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
433 break;
434 case EXCP_INTERRUPT:
435 /* just indicate that signals should be handled asap */
436 break;
437 case EXCP_DEBUG:
438 {
439 int sig;
440
441 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
442 if (sig)
443 {
444 info.si_signo = sig;
445 info.si_errno = 0;
446 info.si_code = TARGET_TRAP_BRKPT;
447 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
448 }
449 }
450 break;
451 default:
452 pc = env->segs[R_CS].base + env->eip;
453 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
454 (long)pc, trapnr);
455 abort();
456 }
457 process_pending_signals(env);
458 }
459 }
460 #endif
461
462 #ifdef TARGET_ARM
463
464 #define get_user_code_u32(x, gaddr, env) \
465 ({ abi_long __r = get_user_u32((x), (gaddr)); \
466 if (!__r && bswap_code(arm_sctlr_b(env))) { \
467 (x) = bswap32(x); \
468 } \
469 __r; \
470 })
471
472 #define get_user_code_u16(x, gaddr, env) \
473 ({ abi_long __r = get_user_u16((x), (gaddr)); \
474 if (!__r && bswap_code(arm_sctlr_b(env))) { \
475 (x) = bswap16(x); \
476 } \
477 __r; \
478 })
479
480 #define get_user_data_u32(x, gaddr, env) \
481 ({ abi_long __r = get_user_u32((x), (gaddr)); \
482 if (!__r && arm_cpu_bswap_data(env)) { \
483 (x) = bswap32(x); \
484 } \
485 __r; \
486 })
487
488 #define get_user_data_u16(x, gaddr, env) \
489 ({ abi_long __r = get_user_u16((x), (gaddr)); \
490 if (!__r && arm_cpu_bswap_data(env)) { \
491 (x) = bswap16(x); \
492 } \
493 __r; \
494 })
495
496 #define put_user_data_u32(x, gaddr, env) \
497 ({ typeof(x) __x = (x); \
498 if (arm_cpu_bswap_data(env)) { \
499 __x = bswap32(__x); \
500 } \
501 put_user_u32(__x, (gaddr)); \
502 })
503
504 #define put_user_data_u16(x, gaddr, env) \
505 ({ typeof(x) __x = (x); \
506 if (arm_cpu_bswap_data(env)) { \
507 __x = bswap16(__x); \
508 } \
509 put_user_u16(__x, (gaddr)); \
510 })
511
512 #ifdef TARGET_ABI32
513 /* Commpage handling -- there is no commpage for AArch64 */
514
515 /*
516 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
517 * Input:
518 * r0 = pointer to oldval
519 * r1 = pointer to newval
520 * r2 = pointer to target value
521 *
522 * Output:
523 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
524 * C set if *ptr was changed, clear if no exchange happened
525 *
526 * Note segv's in kernel helpers are a bit tricky, we can set the
527 * data address sensibly but the PC address is just the entry point.
528 */
529 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
530 {
531 uint64_t oldval, newval, val;
532 uint32_t addr, cpsr;
533 target_siginfo_t info;
534
535 /* Based on the 32 bit code in do_kernel_trap */
536
537 /* XXX: This only works between threads, not between processes.
538 It's probably possible to implement this with native host
539 operations. However things like ldrex/strex are much harder so
540 there's not much point trying. */
541 start_exclusive();
542 cpsr = cpsr_read(env);
543 addr = env->regs[2];
544
545 if (get_user_u64(oldval, env->regs[0])) {
546 env->exception.vaddress = env->regs[0];
547 goto segv;
548 };
549
550 if (get_user_u64(newval, env->regs[1])) {
551 env->exception.vaddress = env->regs[1];
552 goto segv;
553 };
554
555 if (get_user_u64(val, addr)) {
556 env->exception.vaddress = addr;
557 goto segv;
558 }
559
560 if (val == oldval) {
561 val = newval;
562
563 if (put_user_u64(val, addr)) {
564 env->exception.vaddress = addr;
565 goto segv;
566 };
567
568 env->regs[0] = 0;
569 cpsr |= CPSR_C;
570 } else {
571 env->regs[0] = -1;
572 cpsr &= ~CPSR_C;
573 }
574 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
575 end_exclusive();
576 return;
577
578 segv:
579 end_exclusive();
580 /* We get the PC of the entry address - which is as good as anything,
581 on a real kernel what you get depends on which mode it uses. */
582 info.si_signo = TARGET_SIGSEGV;
583 info.si_errno = 0;
584 /* XXX: check env->error_code */
585 info.si_code = TARGET_SEGV_MAPERR;
586 info._sifields._sigfault._addr = env->exception.vaddress;
587 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
588 }
589
590 /* Handle a jump to the kernel code page. */
591 static int
592 do_kernel_trap(CPUARMState *env)
593 {
594 uint32_t addr;
595 uint32_t cpsr;
596 uint32_t val;
597
598 switch (env->regs[15]) {
599 case 0xffff0fa0: /* __kernel_memory_barrier */
600 /* ??? No-op. Will need to do better for SMP. */
601 break;
602 case 0xffff0fc0: /* __kernel_cmpxchg */
603 /* XXX: This only works between threads, not between processes.
604 It's probably possible to implement this with native host
605 operations. However things like ldrex/strex are much harder so
606 there's not much point trying. */
607 start_exclusive();
608 cpsr = cpsr_read(env);
609 addr = env->regs[2];
610 /* FIXME: This should SEGV if the access fails. */
611 if (get_user_u32(val, addr))
612 val = ~env->regs[0];
613 if (val == env->regs[0]) {
614 val = env->regs[1];
615 /* FIXME: Check for segfaults. */
616 put_user_u32(val, addr);
617 env->regs[0] = 0;
618 cpsr |= CPSR_C;
619 } else {
620 env->regs[0] = -1;
621 cpsr &= ~CPSR_C;
622 }
623 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
624 end_exclusive();
625 break;
626 case 0xffff0fe0: /* __kernel_get_tls */
627 env->regs[0] = cpu_get_tls(env);
628 break;
629 case 0xffff0f60: /* __kernel_cmpxchg64 */
630 arm_kernel_cmpxchg64_helper(env);
631 break;
632
633 default:
634 return 1;
635 }
636 /* Jump back to the caller. */
637 addr = env->regs[14];
638 if (addr & 1) {
639 env->thumb = 1;
640 addr &= ~1;
641 }
642 env->regs[15] = addr;
643
644 return 0;
645 }
646
647 /* Store exclusive handling for AArch32 */
648 static int do_strex(CPUARMState *env)
649 {
650 uint64_t val;
651 int size;
652 int rc = 1;
653 int segv = 0;
654 uint32_t addr;
655 start_exclusive();
656 if (env->exclusive_addr != env->exclusive_test) {
657 goto fail;
658 }
659 /* We know we're always AArch32 so the address is in uint32_t range
660 * unless it was the -1 exclusive-monitor-lost value (which won't
661 * match exclusive_test above).
662 */
663 assert(extract64(env->exclusive_addr, 32, 32) == 0);
664 addr = env->exclusive_addr;
665 size = env->exclusive_info & 0xf;
666 switch (size) {
667 case 0:
668 segv = get_user_u8(val, addr);
669 break;
670 case 1:
671 segv = get_user_data_u16(val, addr, env);
672 break;
673 case 2:
674 case 3:
675 segv = get_user_data_u32(val, addr, env);
676 break;
677 default:
678 abort();
679 }
680 if (segv) {
681 env->exception.vaddress = addr;
682 goto done;
683 }
684 if (size == 3) {
685 uint32_t valhi;
686 segv = get_user_data_u32(valhi, addr + 4, env);
687 if (segv) {
688 env->exception.vaddress = addr + 4;
689 goto done;
690 }
691 if (arm_cpu_bswap_data(env)) {
692 val = deposit64((uint64_t)valhi, 32, 32, val);
693 } else {
694 val = deposit64(val, 32, 32, valhi);
695 }
696 }
697 if (val != env->exclusive_val) {
698 goto fail;
699 }
700
701 val = env->regs[(env->exclusive_info >> 8) & 0xf];
702 switch (size) {
703 case 0:
704 segv = put_user_u8(val, addr);
705 break;
706 case 1:
707 segv = put_user_data_u16(val, addr, env);
708 break;
709 case 2:
710 case 3:
711 segv = put_user_data_u32(val, addr, env);
712 break;
713 }
714 if (segv) {
715 env->exception.vaddress = addr;
716 goto done;
717 }
718 if (size == 3) {
719 val = env->regs[(env->exclusive_info >> 12) & 0xf];
720 segv = put_user_data_u32(val, addr + 4, env);
721 if (segv) {
722 env->exception.vaddress = addr + 4;
723 goto done;
724 }
725 }
726 rc = 0;
727 fail:
728 env->regs[15] += 4;
729 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
730 done:
731 end_exclusive();
732 return segv;
733 }
734
735 void cpu_loop(CPUARMState *env)
736 {
737 CPUState *cs = CPU(arm_env_get_cpu(env));
738 int trapnr;
739 unsigned int n, insn;
740 target_siginfo_t info;
741 uint32_t addr;
742 abi_ulong ret;
743
744 for(;;) {
745 cpu_exec_start(cs);
746 trapnr = cpu_exec(cs);
747 cpu_exec_end(cs);
748 switch(trapnr) {
749 case EXCP_UDEF:
750 {
751 TaskState *ts = cs->opaque;
752 uint32_t opcode;
753 int rc;
754
755 /* we handle the FPU emulation here, as Linux */
756 /* we get the opcode */
757 /* FIXME - what to do if get_user() fails? */
758 get_user_code_u32(opcode, env->regs[15], env);
759
760 rc = EmulateAll(opcode, &ts->fpa, env);
761 if (rc == 0) { /* illegal instruction */
762 info.si_signo = TARGET_SIGILL;
763 info.si_errno = 0;
764 info.si_code = TARGET_ILL_ILLOPN;
765 info._sifields._sigfault._addr = env->regs[15];
766 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
767 } else if (rc < 0) { /* FP exception */
768 int arm_fpe=0;
769
770 /* translate softfloat flags to FPSR flags */
771 if (-rc & float_flag_invalid)
772 arm_fpe |= BIT_IOC;
773 if (-rc & float_flag_divbyzero)
774 arm_fpe |= BIT_DZC;
775 if (-rc & float_flag_overflow)
776 arm_fpe |= BIT_OFC;
777 if (-rc & float_flag_underflow)
778 arm_fpe |= BIT_UFC;
779 if (-rc & float_flag_inexact)
780 arm_fpe |= BIT_IXC;
781
782 FPSR fpsr = ts->fpa.fpsr;
783 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
784
785 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
786 info.si_signo = TARGET_SIGFPE;
787 info.si_errno = 0;
788
789 /* ordered by priority, least first */
790 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
791 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
792 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
793 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
794 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
795
796 info._sifields._sigfault._addr = env->regs[15];
797 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
798 } else {
799 env->regs[15] += 4;
800 }
801
802 /* accumulate unenabled exceptions */
803 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
804 fpsr |= BIT_IXC;
805 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
806 fpsr |= BIT_UFC;
807 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
808 fpsr |= BIT_OFC;
809 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
810 fpsr |= BIT_DZC;
811 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
812 fpsr |= BIT_IOC;
813 ts->fpa.fpsr=fpsr;
814 } else { /* everything OK */
815 /* increment PC */
816 env->regs[15] += 4;
817 }
818 }
819 break;
820 case EXCP_SWI:
821 case EXCP_BKPT:
822 {
823 env->eabi = 1;
824 /* system call */
825 if (trapnr == EXCP_BKPT) {
826 if (env->thumb) {
827 /* FIXME - what to do if get_user() fails? */
828 get_user_code_u16(insn, env->regs[15], env);
829 n = insn & 0xff;
830 env->regs[15] += 2;
831 } else {
832 /* FIXME - what to do if get_user() fails? */
833 get_user_code_u32(insn, env->regs[15], env);
834 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
835 env->regs[15] += 4;
836 }
837 } else {
838 if (env->thumb) {
839 /* FIXME - what to do if get_user() fails? */
840 get_user_code_u16(insn, env->regs[15] - 2, env);
841 n = insn & 0xff;
842 } else {
843 /* FIXME - what to do if get_user() fails? */
844 get_user_code_u32(insn, env->regs[15] - 4, env);
845 n = insn & 0xffffff;
846 }
847 }
848
849 if (n == ARM_NR_cacheflush) {
850 /* nop */
851 } else if (n == ARM_NR_semihosting
852 || n == ARM_NR_thumb_semihosting) {
853 env->regs[0] = do_arm_semihosting (env);
854 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
855 /* linux syscall */
856 if (env->thumb || n == 0) {
857 n = env->regs[7];
858 } else {
859 n -= ARM_SYSCALL_BASE;
860 env->eabi = 0;
861 }
862 if ( n > ARM_NR_BASE) {
863 switch (n) {
864 case ARM_NR_cacheflush:
865 /* nop */
866 break;
867 case ARM_NR_set_tls:
868 cpu_set_tls(env, env->regs[0]);
869 env->regs[0] = 0;
870 break;
871 case ARM_NR_breakpoint:
872 env->regs[15] -= env->thumb ? 2 : 4;
873 goto excp_debug;
874 default:
875 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
876 n);
877 env->regs[0] = -TARGET_ENOSYS;
878 break;
879 }
880 } else {
881 ret = do_syscall(env,
882 n,
883 env->regs[0],
884 env->regs[1],
885 env->regs[2],
886 env->regs[3],
887 env->regs[4],
888 env->regs[5],
889 0, 0);
890 if (ret == -TARGET_ERESTARTSYS) {
891 env->regs[15] -= env->thumb ? 2 : 4;
892 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
893 env->regs[0] = ret;
894 }
895 }
896 } else {
897 goto error;
898 }
899 }
900 break;
901 case EXCP_INTERRUPT:
902 /* just indicate that signals should be handled asap */
903 break;
904 case EXCP_STREX:
905 if (!do_strex(env)) {
906 break;
907 }
908 /* fall through for segv */
909 case EXCP_PREFETCH_ABORT:
910 case EXCP_DATA_ABORT:
911 addr = env->exception.vaddress;
912 {
913 info.si_signo = TARGET_SIGSEGV;
914 info.si_errno = 0;
915 /* XXX: check env->error_code */
916 info.si_code = TARGET_SEGV_MAPERR;
917 info._sifields._sigfault._addr = addr;
918 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
919 }
920 break;
921 case EXCP_DEBUG:
922 excp_debug:
923 {
924 int sig;
925
926 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
927 if (sig)
928 {
929 info.si_signo = sig;
930 info.si_errno = 0;
931 info.si_code = TARGET_TRAP_BRKPT;
932 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
933 }
934 }
935 break;
936 case EXCP_KERNEL_TRAP:
937 if (do_kernel_trap(env))
938 goto error;
939 break;
940 case EXCP_YIELD:
941 /* nothing to do here for user-mode, just resume guest code */
942 break;
943 default:
944 error:
945 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
946 abort();
947 }
948 process_pending_signals(env);
949 }
950 }
951
952 #else
953
954 /*
955 * Handle AArch64 store-release exclusive
956 *
957 * rs = gets the status result of store exclusive
958 * rt = is the register that is stored
959 * rt2 = is the second register store (in STP)
960 *
961 */
962 static int do_strex_a64(CPUARMState *env)
963 {
964 uint64_t val;
965 int size;
966 bool is_pair;
967 int rc = 1;
968 int segv = 0;
969 uint64_t addr;
970 int rs, rt, rt2;
971
972 start_exclusive();
973 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
974 size = extract32(env->exclusive_info, 0, 2);
975 is_pair = extract32(env->exclusive_info, 2, 1);
976 rs = extract32(env->exclusive_info, 4, 5);
977 rt = extract32(env->exclusive_info, 9, 5);
978 rt2 = extract32(env->exclusive_info, 14, 5);
979
980 addr = env->exclusive_addr;
981
982 if (addr != env->exclusive_test) {
983 goto finish;
984 }
985
986 switch (size) {
987 case 0:
988 segv = get_user_u8(val, addr);
989 break;
990 case 1:
991 segv = get_user_u16(val, addr);
992 break;
993 case 2:
994 segv = get_user_u32(val, addr);
995 break;
996 case 3:
997 segv = get_user_u64(val, addr);
998 break;
999 default:
1000 abort();
1001 }
1002 if (segv) {
1003 env->exception.vaddress = addr;
1004 goto error;
1005 }
1006 if (val != env->exclusive_val) {
1007 goto finish;
1008 }
1009 if (is_pair) {
1010 if (size == 2) {
1011 segv = get_user_u32(val, addr + 4);
1012 } else {
1013 segv = get_user_u64(val, addr + 8);
1014 }
1015 if (segv) {
1016 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1017 goto error;
1018 }
1019 if (val != env->exclusive_high) {
1020 goto finish;
1021 }
1022 }
1023 /* handle the zero register */
1024 val = rt == 31 ? 0 : env->xregs[rt];
1025 switch (size) {
1026 case 0:
1027 segv = put_user_u8(val, addr);
1028 break;
1029 case 1:
1030 segv = put_user_u16(val, addr);
1031 break;
1032 case 2:
1033 segv = put_user_u32(val, addr);
1034 break;
1035 case 3:
1036 segv = put_user_u64(val, addr);
1037 break;
1038 }
1039 if (segv) {
1040 goto error;
1041 }
1042 if (is_pair) {
1043 /* handle the zero register */
1044 val = rt2 == 31 ? 0 : env->xregs[rt2];
1045 if (size == 2) {
1046 segv = put_user_u32(val, addr + 4);
1047 } else {
1048 segv = put_user_u64(val, addr + 8);
1049 }
1050 if (segv) {
1051 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1052 goto error;
1053 }
1054 }
1055 rc = 0;
1056 finish:
1057 env->pc += 4;
1058 /* rs == 31 encodes a write to the ZR, thus throwing away
1059 * the status return. This is rather silly but valid.
1060 */
1061 if (rs < 31) {
1062 env->xregs[rs] = rc;
1063 }
1064 error:
1065 /* instruction faulted, PC does not advance */
1066 /* either way a strex releases any exclusive lock we have */
1067 env->exclusive_addr = -1;
1068 end_exclusive();
1069 return segv;
1070 }
1071
1072 /* AArch64 main loop */
1073 void cpu_loop(CPUARMState *env)
1074 {
1075 CPUState *cs = CPU(arm_env_get_cpu(env));
1076 int trapnr, sig;
1077 abi_long ret;
1078 target_siginfo_t info;
1079
1080 for (;;) {
1081 cpu_exec_start(cs);
1082 trapnr = cpu_exec(cs);
1083 cpu_exec_end(cs);
1084
1085 switch (trapnr) {
1086 case EXCP_SWI:
1087 ret = do_syscall(env,
1088 env->xregs[8],
1089 env->xregs[0],
1090 env->xregs[1],
1091 env->xregs[2],
1092 env->xregs[3],
1093 env->xregs[4],
1094 env->xregs[5],
1095 0, 0);
1096 if (ret == -TARGET_ERESTARTSYS) {
1097 env->pc -= 4;
1098 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1099 env->xregs[0] = ret;
1100 }
1101 break;
1102 case EXCP_INTERRUPT:
1103 /* just indicate that signals should be handled asap */
1104 break;
1105 case EXCP_UDEF:
1106 info.si_signo = TARGET_SIGILL;
1107 info.si_errno = 0;
1108 info.si_code = TARGET_ILL_ILLOPN;
1109 info._sifields._sigfault._addr = env->pc;
1110 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1111 break;
1112 case EXCP_STREX:
1113 if (!do_strex_a64(env)) {
1114 break;
1115 }
1116 /* fall through for segv */
1117 case EXCP_PREFETCH_ABORT:
1118 case EXCP_DATA_ABORT:
1119 info.si_signo = TARGET_SIGSEGV;
1120 info.si_errno = 0;
1121 /* XXX: check env->error_code */
1122 info.si_code = TARGET_SEGV_MAPERR;
1123 info._sifields._sigfault._addr = env->exception.vaddress;
1124 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1125 break;
1126 case EXCP_DEBUG:
1127 case EXCP_BKPT:
1128 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1129 if (sig) {
1130 info.si_signo = sig;
1131 info.si_errno = 0;
1132 info.si_code = TARGET_TRAP_BRKPT;
1133 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1134 }
1135 break;
1136 case EXCP_SEMIHOST:
1137 env->xregs[0] = do_arm_semihosting(env);
1138 break;
1139 case EXCP_YIELD:
1140 /* nothing to do here for user-mode, just resume guest code */
1141 break;
1142 default:
1143 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1144 abort();
1145 }
1146 process_pending_signals(env);
1147 /* Exception return on AArch64 always clears the exclusive monitor,
1148 * so any return to running guest code implies this.
1149 * A strex (successful or otherwise) also clears the monitor, so
1150 * we don't need to specialcase EXCP_STREX.
1151 */
1152 env->exclusive_addr = -1;
1153 }
1154 }
1155 #endif /* ndef TARGET_ABI32 */
1156
1157 #endif
1158
1159 #ifdef TARGET_UNICORE32
1160
1161 void cpu_loop(CPUUniCore32State *env)
1162 {
1163 CPUState *cs = CPU(uc32_env_get_cpu(env));
1164 int trapnr;
1165 unsigned int n, insn;
1166 target_siginfo_t info;
1167
1168 for (;;) {
1169 cpu_exec_start(cs);
1170 trapnr = cpu_exec(cs);
1171 cpu_exec_end(cs);
1172 switch (trapnr) {
1173 case UC32_EXCP_PRIV:
1174 {
1175 /* system call */
1176 get_user_u32(insn, env->regs[31] - 4);
1177 n = insn & 0xffffff;
1178
1179 if (n >= UC32_SYSCALL_BASE) {
1180 /* linux syscall */
1181 n -= UC32_SYSCALL_BASE;
1182 if (n == UC32_SYSCALL_NR_set_tls) {
1183 cpu_set_tls(env, env->regs[0]);
1184 env->regs[0] = 0;
1185 } else {
1186 abi_long ret = do_syscall(env,
1187 n,
1188 env->regs[0],
1189 env->regs[1],
1190 env->regs[2],
1191 env->regs[3],
1192 env->regs[4],
1193 env->regs[5],
1194 0, 0);
1195 if (ret == -TARGET_ERESTARTSYS) {
1196 env->regs[31] -= 4;
1197 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1198 env->regs[0] = ret;
1199 }
1200 }
1201 } else {
1202 goto error;
1203 }
1204 }
1205 break;
1206 case UC32_EXCP_DTRAP:
1207 case UC32_EXCP_ITRAP:
1208 info.si_signo = TARGET_SIGSEGV;
1209 info.si_errno = 0;
1210 /* XXX: check env->error_code */
1211 info.si_code = TARGET_SEGV_MAPERR;
1212 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1213 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1214 break;
1215 case EXCP_INTERRUPT:
1216 /* just indicate that signals should be handled asap */
1217 break;
1218 case EXCP_DEBUG:
1219 {
1220 int sig;
1221
1222 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1223 if (sig) {
1224 info.si_signo = sig;
1225 info.si_errno = 0;
1226 info.si_code = TARGET_TRAP_BRKPT;
1227 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1228 }
1229 }
1230 break;
1231 default:
1232 goto error;
1233 }
1234 process_pending_signals(env);
1235 }
1236
1237 error:
1238 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1239 abort();
1240 }
1241 #endif
1242
1243 #ifdef TARGET_SPARC
1244 #define SPARC64_STACK_BIAS 2047
1245
1246 //#define DEBUG_WIN
1247
1248 /* WARNING: dealing with register windows _is_ complicated. More info
1249 can be found at http://www.sics.se/~psm/sparcstack.html */
1250 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1251 {
1252 index = (index + cwp * 16) % (16 * env->nwindows);
1253 /* wrap handling : if cwp is on the last window, then we use the
1254 registers 'after' the end */
1255 if (index < 8 && env->cwp == env->nwindows - 1)
1256 index += 16 * env->nwindows;
1257 return index;
1258 }
1259
1260 /* save the register window 'cwp1' */
1261 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1262 {
1263 unsigned int i;
1264 abi_ulong sp_ptr;
1265
1266 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1267 #ifdef TARGET_SPARC64
1268 if (sp_ptr & 3)
1269 sp_ptr += SPARC64_STACK_BIAS;
1270 #endif
1271 #if defined(DEBUG_WIN)
1272 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1273 sp_ptr, cwp1);
1274 #endif
1275 for(i = 0; i < 16; i++) {
1276 /* FIXME - what to do if put_user() fails? */
1277 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1278 sp_ptr += sizeof(abi_ulong);
1279 }
1280 }
1281
1282 static void save_window(CPUSPARCState *env)
1283 {
1284 #ifndef TARGET_SPARC64
1285 unsigned int new_wim;
1286 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1287 ((1LL << env->nwindows) - 1);
1288 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1289 env->wim = new_wim;
1290 #else
1291 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1292 env->cansave++;
1293 env->canrestore--;
1294 #endif
1295 }
1296
1297 static void restore_window(CPUSPARCState *env)
1298 {
1299 #ifndef TARGET_SPARC64
1300 unsigned int new_wim;
1301 #endif
1302 unsigned int i, cwp1;
1303 abi_ulong sp_ptr;
1304
1305 #ifndef TARGET_SPARC64
1306 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1307 ((1LL << env->nwindows) - 1);
1308 #endif
1309
1310 /* restore the invalid window */
1311 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1312 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1313 #ifdef TARGET_SPARC64
1314 if (sp_ptr & 3)
1315 sp_ptr += SPARC64_STACK_BIAS;
1316 #endif
1317 #if defined(DEBUG_WIN)
1318 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1319 sp_ptr, cwp1);
1320 #endif
1321 for(i = 0; i < 16; i++) {
1322 /* FIXME - what to do if get_user() fails? */
1323 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1324 sp_ptr += sizeof(abi_ulong);
1325 }
1326 #ifdef TARGET_SPARC64
1327 env->canrestore++;
1328 if (env->cleanwin < env->nwindows - 1)
1329 env->cleanwin++;
1330 env->cansave--;
1331 #else
1332 env->wim = new_wim;
1333 #endif
1334 }
1335
1336 static void flush_windows(CPUSPARCState *env)
1337 {
1338 int offset, cwp1;
1339
1340 offset = 1;
1341 for(;;) {
1342 /* if restore would invoke restore_window(), then we can stop */
1343 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1344 #ifndef TARGET_SPARC64
1345 if (env->wim & (1 << cwp1))
1346 break;
1347 #else
1348 if (env->canrestore == 0)
1349 break;
1350 env->cansave++;
1351 env->canrestore--;
1352 #endif
1353 save_window_offset(env, cwp1);
1354 offset++;
1355 }
1356 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1357 #ifndef TARGET_SPARC64
1358 /* set wim so that restore will reload the registers */
1359 env->wim = 1 << cwp1;
1360 #endif
1361 #if defined(DEBUG_WIN)
1362 printf("flush_windows: nb=%d\n", offset - 1);
1363 #endif
1364 }
1365
1366 void cpu_loop (CPUSPARCState *env)
1367 {
1368 CPUState *cs = CPU(sparc_env_get_cpu(env));
1369 int trapnr;
1370 abi_long ret;
1371 target_siginfo_t info;
1372
1373 while (1) {
1374 cpu_exec_start(cs);
1375 trapnr = cpu_exec(cs);
1376 cpu_exec_end(cs);
1377
1378 /* Compute PSR before exposing state. */
1379 if (env->cc_op != CC_OP_FLAGS) {
1380 cpu_get_psr(env);
1381 }
1382
1383 switch (trapnr) {
1384 #ifndef TARGET_SPARC64
1385 case 0x88:
1386 case 0x90:
1387 #else
1388 case 0x110:
1389 case 0x16d:
1390 #endif
1391 ret = do_syscall (env, env->gregs[1],
1392 env->regwptr[0], env->regwptr[1],
1393 env->regwptr[2], env->regwptr[3],
1394 env->regwptr[4], env->regwptr[5],
1395 0, 0);
1396 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1397 break;
1398 }
1399 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1400 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1401 env->xcc |= PSR_CARRY;
1402 #else
1403 env->psr |= PSR_CARRY;
1404 #endif
1405 ret = -ret;
1406 } else {
1407 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1408 env->xcc &= ~PSR_CARRY;
1409 #else
1410 env->psr &= ~PSR_CARRY;
1411 #endif
1412 }
1413 env->regwptr[0] = ret;
1414 /* next instruction */
1415 env->pc = env->npc;
1416 env->npc = env->npc + 4;
1417 break;
1418 case 0x83: /* flush windows */
1419 #ifdef TARGET_ABI32
1420 case 0x103:
1421 #endif
1422 flush_windows(env);
1423 /* next instruction */
1424 env->pc = env->npc;
1425 env->npc = env->npc + 4;
1426 break;
1427 #ifndef TARGET_SPARC64
1428 case TT_WIN_OVF: /* window overflow */
1429 save_window(env);
1430 break;
1431 case TT_WIN_UNF: /* window underflow */
1432 restore_window(env);
1433 break;
1434 case TT_TFAULT:
1435 case TT_DFAULT:
1436 {
1437 info.si_signo = TARGET_SIGSEGV;
1438 info.si_errno = 0;
1439 /* XXX: check env->error_code */
1440 info.si_code = TARGET_SEGV_MAPERR;
1441 info._sifields._sigfault._addr = env->mmuregs[4];
1442 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1443 }
1444 break;
1445 #else
1446 case TT_SPILL: /* window overflow */
1447 save_window(env);
1448 break;
1449 case TT_FILL: /* window underflow */
1450 restore_window(env);
1451 break;
1452 case TT_TFAULT:
1453 case TT_DFAULT:
1454 {
1455 info.si_signo = TARGET_SIGSEGV;
1456 info.si_errno = 0;
1457 /* XXX: check env->error_code */
1458 info.si_code = TARGET_SEGV_MAPERR;
1459 if (trapnr == TT_DFAULT)
1460 info._sifields._sigfault._addr = env->dmmuregs[4];
1461 else
1462 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1463 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1464 }
1465 break;
1466 #ifndef TARGET_ABI32
1467 case 0x16e:
1468 flush_windows(env);
1469 sparc64_get_context(env);
1470 break;
1471 case 0x16f:
1472 flush_windows(env);
1473 sparc64_set_context(env);
1474 break;
1475 #endif
1476 #endif
1477 case EXCP_INTERRUPT:
1478 /* just indicate that signals should be handled asap */
1479 break;
1480 case TT_ILL_INSN:
1481 {
1482 info.si_signo = TARGET_SIGILL;
1483 info.si_errno = 0;
1484 info.si_code = TARGET_ILL_ILLOPC;
1485 info._sifields._sigfault._addr = env->pc;
1486 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1487 }
1488 break;
1489 case EXCP_DEBUG:
1490 {
1491 int sig;
1492
1493 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1494 if (sig)
1495 {
1496 info.si_signo = sig;
1497 info.si_errno = 0;
1498 info.si_code = TARGET_TRAP_BRKPT;
1499 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1500 }
1501 }
1502 break;
1503 default:
1504 printf ("Unhandled trap: 0x%x\n", trapnr);
1505 cpu_dump_state(cs, stderr, fprintf, 0);
1506 exit(EXIT_FAILURE);
1507 }
1508 process_pending_signals (env);
1509 }
1510 }
1511
1512 #endif
1513
1514 #ifdef TARGET_PPC
1515 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1516 {
1517 return cpu_get_host_ticks();
1518 }
1519
1520 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1521 {
1522 return cpu_ppc_get_tb(env);
1523 }
1524
1525 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1526 {
1527 return cpu_ppc_get_tb(env) >> 32;
1528 }
1529
1530 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1531 {
1532 return cpu_ppc_get_tb(env);
1533 }
1534
1535 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1536 {
1537 return cpu_ppc_get_tb(env) >> 32;
1538 }
1539
1540 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1541 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1542
1543 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1544 {
1545 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1546 }
1547
1548 /* XXX: to be fixed */
1549 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1550 {
1551 return -1;
1552 }
1553
1554 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1555 {
1556 return -1;
1557 }
1558
1559 static int do_store_exclusive(CPUPPCState *env)
1560 {
1561 target_ulong addr;
1562 target_ulong page_addr;
1563 target_ulong val, val2 __attribute__((unused)) = 0;
1564 int flags;
1565 int segv = 0;
1566
1567 addr = env->reserve_ea;
1568 page_addr = addr & TARGET_PAGE_MASK;
1569 start_exclusive();
1570 mmap_lock();
1571 flags = page_get_flags(page_addr);
1572 if ((flags & PAGE_READ) == 0) {
1573 segv = 1;
1574 } else {
1575 int reg = env->reserve_info & 0x1f;
1576 int size = env->reserve_info >> 5;
1577 int stored = 0;
1578
1579 if (addr == env->reserve_addr) {
1580 switch (size) {
1581 case 1: segv = get_user_u8(val, addr); break;
1582 case 2: segv = get_user_u16(val, addr); break;
1583 case 4: segv = get_user_u32(val, addr); break;
1584 #if defined(TARGET_PPC64)
1585 case 8: segv = get_user_u64(val, addr); break;
1586 case 16: {
1587 segv = get_user_u64(val, addr);
1588 if (!segv) {
1589 segv = get_user_u64(val2, addr + 8);
1590 }
1591 break;
1592 }
1593 #endif
1594 default: abort();
1595 }
1596 if (!segv && val == env->reserve_val) {
1597 val = env->gpr[reg];
1598 switch (size) {
1599 case 1: segv = put_user_u8(val, addr); break;
1600 case 2: segv = put_user_u16(val, addr); break;
1601 case 4: segv = put_user_u32(val, addr); break;
1602 #if defined(TARGET_PPC64)
1603 case 8: segv = put_user_u64(val, addr); break;
1604 case 16: {
1605 if (val2 == env->reserve_val2) {
1606 if (msr_le) {
1607 val2 = val;
1608 val = env->gpr[reg+1];
1609 } else {
1610 val2 = env->gpr[reg+1];
1611 }
1612 segv = put_user_u64(val, addr);
1613 if (!segv) {
1614 segv = put_user_u64(val2, addr + 8);
1615 }
1616 }
1617 break;
1618 }
1619 #endif
1620 default: abort();
1621 }
1622 if (!segv) {
1623 stored = 1;
1624 }
1625 }
1626 }
1627 env->crf[0] = (stored << 1) | xer_so;
1628 env->reserve_addr = (target_ulong)-1;
1629 }
1630 if (!segv) {
1631 env->nip += 4;
1632 }
1633 mmap_unlock();
1634 end_exclusive();
1635 return segv;
1636 }
1637
1638 void cpu_loop(CPUPPCState *env)
1639 {
1640 CPUState *cs = CPU(ppc_env_get_cpu(env));
1641 target_siginfo_t info;
1642 int trapnr;
1643 target_ulong ret;
1644
1645 for(;;) {
1646 cpu_exec_start(cs);
1647 trapnr = cpu_exec(cs);
1648 cpu_exec_end(cs);
1649 switch(trapnr) {
1650 case POWERPC_EXCP_NONE:
1651 /* Just go on */
1652 break;
1653 case POWERPC_EXCP_CRITICAL: /* Critical input */
1654 cpu_abort(cs, "Critical interrupt while in user mode. "
1655 "Aborting\n");
1656 break;
1657 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1658 cpu_abort(cs, "Machine check exception while in user mode. "
1659 "Aborting\n");
1660 break;
1661 case POWERPC_EXCP_DSI: /* Data storage exception */
1662 /* XXX: check this. Seems bugged */
1663 switch (env->error_code & 0xFF000000) {
1664 case 0x40000000:
1665 case 0x42000000:
1666 info.si_signo = TARGET_SIGSEGV;
1667 info.si_errno = 0;
1668 info.si_code = TARGET_SEGV_MAPERR;
1669 break;
1670 case 0x04000000:
1671 info.si_signo = TARGET_SIGILL;
1672 info.si_errno = 0;
1673 info.si_code = TARGET_ILL_ILLADR;
1674 break;
1675 case 0x08000000:
1676 info.si_signo = TARGET_SIGSEGV;
1677 info.si_errno = 0;
1678 info.si_code = TARGET_SEGV_ACCERR;
1679 break;
1680 default:
1681 /* Let's send a regular segfault... */
1682 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1683 env->error_code);
1684 info.si_signo = TARGET_SIGSEGV;
1685 info.si_errno = 0;
1686 info.si_code = TARGET_SEGV_MAPERR;
1687 break;
1688 }
1689 info._sifields._sigfault._addr = env->nip;
1690 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1691 break;
1692 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1693 /* XXX: check this */
1694 switch (env->error_code & 0xFF000000) {
1695 case 0x40000000:
1696 info.si_signo = TARGET_SIGSEGV;
1697 info.si_errno = 0;
1698 info.si_code = TARGET_SEGV_MAPERR;
1699 break;
1700 case 0x10000000:
1701 case 0x08000000:
1702 info.si_signo = TARGET_SIGSEGV;
1703 info.si_errno = 0;
1704 info.si_code = TARGET_SEGV_ACCERR;
1705 break;
1706 default:
1707 /* Let's send a regular segfault... */
1708 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1709 env->error_code);
1710 info.si_signo = TARGET_SIGSEGV;
1711 info.si_errno = 0;
1712 info.si_code = TARGET_SEGV_MAPERR;
1713 break;
1714 }
1715 info._sifields._sigfault._addr = env->nip - 4;
1716 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1717 break;
1718 case POWERPC_EXCP_EXTERNAL: /* External input */
1719 cpu_abort(cs, "External interrupt while in user mode. "
1720 "Aborting\n");
1721 break;
1722 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1723 /* XXX: check this */
1724 info.si_signo = TARGET_SIGBUS;
1725 info.si_errno = 0;
1726 info.si_code = TARGET_BUS_ADRALN;
1727 info._sifields._sigfault._addr = env->nip;
1728 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1729 break;
1730 case POWERPC_EXCP_PROGRAM: /* Program exception */
1731 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1732 /* XXX: check this */
1733 switch (env->error_code & ~0xF) {
1734 case POWERPC_EXCP_FP:
1735 info.si_signo = TARGET_SIGFPE;
1736 info.si_errno = 0;
1737 switch (env->error_code & 0xF) {
1738 case POWERPC_EXCP_FP_OX:
1739 info.si_code = TARGET_FPE_FLTOVF;
1740 break;
1741 case POWERPC_EXCP_FP_UX:
1742 info.si_code = TARGET_FPE_FLTUND;
1743 break;
1744 case POWERPC_EXCP_FP_ZX:
1745 case POWERPC_EXCP_FP_VXZDZ:
1746 info.si_code = TARGET_FPE_FLTDIV;
1747 break;
1748 case POWERPC_EXCP_FP_XX:
1749 info.si_code = TARGET_FPE_FLTRES;
1750 break;
1751 case POWERPC_EXCP_FP_VXSOFT:
1752 info.si_code = TARGET_FPE_FLTINV;
1753 break;
1754 case POWERPC_EXCP_FP_VXSNAN:
1755 case POWERPC_EXCP_FP_VXISI:
1756 case POWERPC_EXCP_FP_VXIDI:
1757 case POWERPC_EXCP_FP_VXIMZ:
1758 case POWERPC_EXCP_FP_VXVC:
1759 case POWERPC_EXCP_FP_VXSQRT:
1760 case POWERPC_EXCP_FP_VXCVI:
1761 info.si_code = TARGET_FPE_FLTSUB;
1762 break;
1763 default:
1764 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1765 env->error_code);
1766 break;
1767 }
1768 break;
1769 case POWERPC_EXCP_INVAL:
1770 info.si_signo = TARGET_SIGILL;
1771 info.si_errno = 0;
1772 switch (env->error_code & 0xF) {
1773 case POWERPC_EXCP_INVAL_INVAL:
1774 info.si_code = TARGET_ILL_ILLOPC;
1775 break;
1776 case POWERPC_EXCP_INVAL_LSWX:
1777 info.si_code = TARGET_ILL_ILLOPN;
1778 break;
1779 case POWERPC_EXCP_INVAL_SPR:
1780 info.si_code = TARGET_ILL_PRVREG;
1781 break;
1782 case POWERPC_EXCP_INVAL_FP:
1783 info.si_code = TARGET_ILL_COPROC;
1784 break;
1785 default:
1786 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1787 env->error_code & 0xF);
1788 info.si_code = TARGET_ILL_ILLADR;
1789 break;
1790 }
1791 break;
1792 case POWERPC_EXCP_PRIV:
1793 info.si_signo = TARGET_SIGILL;
1794 info.si_errno = 0;
1795 switch (env->error_code & 0xF) {
1796 case POWERPC_EXCP_PRIV_OPC:
1797 info.si_code = TARGET_ILL_PRVOPC;
1798 break;
1799 case POWERPC_EXCP_PRIV_REG:
1800 info.si_code = TARGET_ILL_PRVREG;
1801 break;
1802 default:
1803 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1804 env->error_code & 0xF);
1805 info.si_code = TARGET_ILL_PRVOPC;
1806 break;
1807 }
1808 break;
1809 case POWERPC_EXCP_TRAP:
1810 cpu_abort(cs, "Tried to call a TRAP\n");
1811 break;
1812 default:
1813 /* Should not happen ! */
1814 cpu_abort(cs, "Unknown program exception (%02x)\n",
1815 env->error_code);
1816 break;
1817 }
1818 info._sifields._sigfault._addr = env->nip;
1819 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1820 break;
1821 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1822 info.si_signo = TARGET_SIGILL;
1823 info.si_errno = 0;
1824 info.si_code = TARGET_ILL_COPROC;
1825 info._sifields._sigfault._addr = env->nip;
1826 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1827 break;
1828 case POWERPC_EXCP_SYSCALL: /* System call exception */
1829 cpu_abort(cs, "Syscall exception while in user mode. "
1830 "Aborting\n");
1831 break;
1832 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1833 info.si_signo = TARGET_SIGILL;
1834 info.si_errno = 0;
1835 info.si_code = TARGET_ILL_COPROC;
1836 info._sifields._sigfault._addr = env->nip;
1837 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1838 break;
1839 case POWERPC_EXCP_DECR: /* Decrementer exception */
1840 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1841 "Aborting\n");
1842 break;
1843 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1844 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1845 "Aborting\n");
1846 break;
1847 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1848 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1849 "Aborting\n");
1850 break;
1851 case POWERPC_EXCP_DTLB: /* Data TLB error */
1852 cpu_abort(cs, "Data TLB exception while in user mode. "
1853 "Aborting\n");
1854 break;
1855 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1856 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1857 "Aborting\n");
1858 break;
1859 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1860 info.si_signo = TARGET_SIGILL;
1861 info.si_errno = 0;
1862 info.si_code = TARGET_ILL_COPROC;
1863 info._sifields._sigfault._addr = env->nip;
1864 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1865 break;
1866 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1867 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1868 break;
1869 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1870 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1871 break;
1872 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1873 cpu_abort(cs, "Performance monitor exception not handled\n");
1874 break;
1875 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1876 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1877 "Aborting\n");
1878 break;
1879 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1880 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1881 "Aborting\n");
1882 break;
1883 case POWERPC_EXCP_RESET: /* System reset exception */
1884 cpu_abort(cs, "Reset interrupt while in user mode. "
1885 "Aborting\n");
1886 break;
1887 case POWERPC_EXCP_DSEG: /* Data segment exception */
1888 cpu_abort(cs, "Data segment exception while in user mode. "
1889 "Aborting\n");
1890 break;
1891 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1892 cpu_abort(cs, "Instruction segment exception "
1893 "while in user mode. Aborting\n");
1894 break;
1895 /* PowerPC 64 with hypervisor mode support */
1896 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1897 cpu_abort(cs, "Hypervisor decrementer interrupt "
1898 "while in user mode. Aborting\n");
1899 break;
1900 case POWERPC_EXCP_TRACE: /* Trace exception */
1901 /* Nothing to do:
1902 * we use this exception to emulate step-by-step execution mode.
1903 */
1904 break;
1905 /* PowerPC 64 with hypervisor mode support */
1906 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1907 cpu_abort(cs, "Hypervisor data storage exception "
1908 "while in user mode. Aborting\n");
1909 break;
1910 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1911 cpu_abort(cs, "Hypervisor instruction storage exception "
1912 "while in user mode. Aborting\n");
1913 break;
1914 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1915 cpu_abort(cs, "Hypervisor data segment exception "
1916 "while in user mode. Aborting\n");
1917 break;
1918 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1919 cpu_abort(cs, "Hypervisor instruction segment exception "
1920 "while in user mode. Aborting\n");
1921 break;
1922 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1923 info.si_signo = TARGET_SIGILL;
1924 info.si_errno = 0;
1925 info.si_code = TARGET_ILL_COPROC;
1926 info._sifields._sigfault._addr = env->nip;
1927 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1928 break;
1929 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1930 cpu_abort(cs, "Programmable interval timer interrupt "
1931 "while in user mode. Aborting\n");
1932 break;
1933 case POWERPC_EXCP_IO: /* IO error exception */
1934 cpu_abort(cs, "IO error exception while in user mode. "
1935 "Aborting\n");
1936 break;
1937 case POWERPC_EXCP_RUNM: /* Run mode exception */
1938 cpu_abort(cs, "Run mode exception while in user mode. "
1939 "Aborting\n");
1940 break;
1941 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1942 cpu_abort(cs, "Emulation trap exception not handled\n");
1943 break;
1944 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1945 cpu_abort(cs, "Instruction fetch TLB exception "
1946 "while in user-mode. Aborting");
1947 break;
1948 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1949 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1950 "Aborting");
1951 break;
1952 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1953 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1954 "Aborting");
1955 break;
1956 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1957 cpu_abort(cs, "Floating-point assist exception not handled\n");
1958 break;
1959 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1960 cpu_abort(cs, "Instruction address breakpoint exception "
1961 "not handled\n");
1962 break;
1963 case POWERPC_EXCP_SMI: /* System management interrupt */
1964 cpu_abort(cs, "System management interrupt while in user mode. "
1965 "Aborting\n");
1966 break;
1967 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1968 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1969 "Aborting\n");
1970 break;
1971 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1972 cpu_abort(cs, "Performance monitor exception not handled\n");
1973 break;
1974 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1975 cpu_abort(cs, "Vector assist exception not handled\n");
1976 break;
1977 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1978 cpu_abort(cs, "Soft patch exception not handled\n");
1979 break;
1980 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1981 cpu_abort(cs, "Maintenance exception while in user mode. "
1982 "Aborting\n");
1983 break;
1984 case POWERPC_EXCP_STOP: /* stop translation */
1985 /* We did invalidate the instruction cache. Go on */
1986 break;
1987 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1988 /* We just stopped because of a branch. Go on */
1989 break;
1990 case POWERPC_EXCP_SYSCALL_USER:
1991 /* system call in user-mode emulation */
1992 /* WARNING:
1993 * PPC ABI uses overflow flag in cr0 to signal an error
1994 * in syscalls.
1995 */
1996 env->crf[0] &= ~0x1;
1997 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1998 env->gpr[5], env->gpr[6], env->gpr[7],
1999 env->gpr[8], 0, 0);
2000 if (ret == -TARGET_ERESTARTSYS) {
2001 break;
2002 }
2003 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
2004 /* Returning from a successful sigreturn syscall.
2005 Avoid corrupting register state. */
2006 break;
2007 }
2008 env->nip += 4;
2009 if (ret > (target_ulong)(-515)) {
2010 env->crf[0] |= 0x1;
2011 ret = -ret;
2012 }
2013 env->gpr[3] = ret;
2014 break;
2015 case POWERPC_EXCP_STCX:
2016 if (do_store_exclusive(env)) {
2017 info.si_signo = TARGET_SIGSEGV;
2018 info.si_errno = 0;
2019 info.si_code = TARGET_SEGV_MAPERR;
2020 info._sifields._sigfault._addr = env->nip;
2021 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2022 }
2023 break;
2024 case EXCP_DEBUG:
2025 {
2026 int sig;
2027
2028 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2029 if (sig) {
2030 info.si_signo = sig;
2031 info.si_errno = 0;
2032 info.si_code = TARGET_TRAP_BRKPT;
2033 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2034 }
2035 }
2036 break;
2037 case EXCP_INTERRUPT:
2038 /* just indicate that signals should be handled asap */
2039 break;
2040 default:
2041 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
2042 break;
2043 }
2044 process_pending_signals(env);
2045 }
2046 }
2047 #endif
2048
2049 #ifdef TARGET_MIPS
2050
2051 # ifdef TARGET_ABI_MIPSO32
2052 # define MIPS_SYS(name, args) args,
2053 static const uint8_t mips_syscall_args[] = {
2054 MIPS_SYS(sys_syscall , 8) /* 4000 */
2055 MIPS_SYS(sys_exit , 1)
2056 MIPS_SYS(sys_fork , 0)
2057 MIPS_SYS(sys_read , 3)
2058 MIPS_SYS(sys_write , 3)
2059 MIPS_SYS(sys_open , 3) /* 4005 */
2060 MIPS_SYS(sys_close , 1)
2061 MIPS_SYS(sys_waitpid , 3)
2062 MIPS_SYS(sys_creat , 2)
2063 MIPS_SYS(sys_link , 2)
2064 MIPS_SYS(sys_unlink , 1) /* 4010 */
2065 MIPS_SYS(sys_execve , 0)
2066 MIPS_SYS(sys_chdir , 1)
2067 MIPS_SYS(sys_time , 1)
2068 MIPS_SYS(sys_mknod , 3)
2069 MIPS_SYS(sys_chmod , 2) /* 4015 */
2070 MIPS_SYS(sys_lchown , 3)
2071 MIPS_SYS(sys_ni_syscall , 0)
2072 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2073 MIPS_SYS(sys_lseek , 3)
2074 MIPS_SYS(sys_getpid , 0) /* 4020 */
2075 MIPS_SYS(sys_mount , 5)
2076 MIPS_SYS(sys_umount , 1)
2077 MIPS_SYS(sys_setuid , 1)
2078 MIPS_SYS(sys_getuid , 0)
2079 MIPS_SYS(sys_stime , 1) /* 4025 */
2080 MIPS_SYS(sys_ptrace , 4)
2081 MIPS_SYS(sys_alarm , 1)
2082 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2083 MIPS_SYS(sys_pause , 0)
2084 MIPS_SYS(sys_utime , 2) /* 4030 */
2085 MIPS_SYS(sys_ni_syscall , 0)
2086 MIPS_SYS(sys_ni_syscall , 0)
2087 MIPS_SYS(sys_access , 2)
2088 MIPS_SYS(sys_nice , 1)
2089 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2090 MIPS_SYS(sys_sync , 0)
2091 MIPS_SYS(sys_kill , 2)
2092 MIPS_SYS(sys_rename , 2)
2093 MIPS_SYS(sys_mkdir , 2)
2094 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2095 MIPS_SYS(sys_dup , 1)
2096 MIPS_SYS(sys_pipe , 0)
2097 MIPS_SYS(sys_times , 1)
2098 MIPS_SYS(sys_ni_syscall , 0)
2099 MIPS_SYS(sys_brk , 1) /* 4045 */
2100 MIPS_SYS(sys_setgid , 1)
2101 MIPS_SYS(sys_getgid , 0)
2102 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2103 MIPS_SYS(sys_geteuid , 0)
2104 MIPS_SYS(sys_getegid , 0) /* 4050 */
2105 MIPS_SYS(sys_acct , 0)
2106 MIPS_SYS(sys_umount2 , 2)
2107 MIPS_SYS(sys_ni_syscall , 0)
2108 MIPS_SYS(sys_ioctl , 3)
2109 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2110 MIPS_SYS(sys_ni_syscall , 2)
2111 MIPS_SYS(sys_setpgid , 2)
2112 MIPS_SYS(sys_ni_syscall , 0)
2113 MIPS_SYS(sys_olduname , 1)
2114 MIPS_SYS(sys_umask , 1) /* 4060 */
2115 MIPS_SYS(sys_chroot , 1)
2116 MIPS_SYS(sys_ustat , 2)
2117 MIPS_SYS(sys_dup2 , 2)
2118 MIPS_SYS(sys_getppid , 0)
2119 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2120 MIPS_SYS(sys_setsid , 0)
2121 MIPS_SYS(sys_sigaction , 3)
2122 MIPS_SYS(sys_sgetmask , 0)
2123 MIPS_SYS(sys_ssetmask , 1)
2124 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2125 MIPS_SYS(sys_setregid , 2)
2126 MIPS_SYS(sys_sigsuspend , 0)
2127 MIPS_SYS(sys_sigpending , 1)
2128 MIPS_SYS(sys_sethostname , 2)
2129 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2130 MIPS_SYS(sys_getrlimit , 2)
2131 MIPS_SYS(sys_getrusage , 2)
2132 MIPS_SYS(sys_gettimeofday, 2)
2133 MIPS_SYS(sys_settimeofday, 2)
2134 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2135 MIPS_SYS(sys_setgroups , 2)
2136 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2137 MIPS_SYS(sys_symlink , 2)
2138 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2139 MIPS_SYS(sys_readlink , 3) /* 4085 */
2140 MIPS_SYS(sys_uselib , 1)
2141 MIPS_SYS(sys_swapon , 2)
2142 MIPS_SYS(sys_reboot , 3)
2143 MIPS_SYS(old_readdir , 3)
2144 MIPS_SYS(old_mmap , 6) /* 4090 */
2145 MIPS_SYS(sys_munmap , 2)
2146 MIPS_SYS(sys_truncate , 2)
2147 MIPS_SYS(sys_ftruncate , 2)
2148 MIPS_SYS(sys_fchmod , 2)
2149 MIPS_SYS(sys_fchown , 3) /* 4095 */
2150 MIPS_SYS(sys_getpriority , 2)
2151 MIPS_SYS(sys_setpriority , 3)
2152 MIPS_SYS(sys_ni_syscall , 0)
2153 MIPS_SYS(sys_statfs , 2)
2154 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2155 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2156 MIPS_SYS(sys_socketcall , 2)
2157 MIPS_SYS(sys_syslog , 3)
2158 MIPS_SYS(sys_setitimer , 3)
2159 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2160 MIPS_SYS(sys_newstat , 2)
2161 MIPS_SYS(sys_newlstat , 2)
2162 MIPS_SYS(sys_newfstat , 2)
2163 MIPS_SYS(sys_uname , 1)
2164 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2165 MIPS_SYS(sys_vhangup , 0)
2166 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2167 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2168 MIPS_SYS(sys_wait4 , 4)
2169 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2170 MIPS_SYS(sys_sysinfo , 1)
2171 MIPS_SYS(sys_ipc , 6)
2172 MIPS_SYS(sys_fsync , 1)
2173 MIPS_SYS(sys_sigreturn , 0)
2174 MIPS_SYS(sys_clone , 6) /* 4120 */
2175 MIPS_SYS(sys_setdomainname, 2)
2176 MIPS_SYS(sys_newuname , 1)
2177 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2178 MIPS_SYS(sys_adjtimex , 1)
2179 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2180 MIPS_SYS(sys_sigprocmask , 3)
2181 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2182 MIPS_SYS(sys_init_module , 5)
2183 MIPS_SYS(sys_delete_module, 1)
2184 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2185 MIPS_SYS(sys_quotactl , 0)
2186 MIPS_SYS(sys_getpgid , 1)
2187 MIPS_SYS(sys_fchdir , 1)
2188 MIPS_SYS(sys_bdflush , 2)
2189 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2190 MIPS_SYS(sys_personality , 1)
2191 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2192 MIPS_SYS(sys_setfsuid , 1)
2193 MIPS_SYS(sys_setfsgid , 1)
2194 MIPS_SYS(sys_llseek , 5) /* 4140 */
2195 MIPS_SYS(sys_getdents , 3)
2196 MIPS_SYS(sys_select , 5)
2197 MIPS_SYS(sys_flock , 2)
2198 MIPS_SYS(sys_msync , 3)
2199 MIPS_SYS(sys_readv , 3) /* 4145 */
2200 MIPS_SYS(sys_writev , 3)
2201 MIPS_SYS(sys_cacheflush , 3)
2202 MIPS_SYS(sys_cachectl , 3)
2203 MIPS_SYS(sys_sysmips , 4)
2204 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2205 MIPS_SYS(sys_getsid , 1)
2206 MIPS_SYS(sys_fdatasync , 0)
2207 MIPS_SYS(sys_sysctl , 1)
2208 MIPS_SYS(sys_mlock , 2)
2209 MIPS_SYS(sys_munlock , 2) /* 4155 */
2210 MIPS_SYS(sys_mlockall , 1)
2211 MIPS_SYS(sys_munlockall , 0)
2212 MIPS_SYS(sys_sched_setparam, 2)
2213 MIPS_SYS(sys_sched_getparam, 2)
2214 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2215 MIPS_SYS(sys_sched_getscheduler, 1)
2216 MIPS_SYS(sys_sched_yield , 0)
2217 MIPS_SYS(sys_sched_get_priority_max, 1)
2218 MIPS_SYS(sys_sched_get_priority_min, 1)
2219 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2220 MIPS_SYS(sys_nanosleep, 2)
2221 MIPS_SYS(sys_mremap , 5)
2222 MIPS_SYS(sys_accept , 3)
2223 MIPS_SYS(sys_bind , 3)
2224 MIPS_SYS(sys_connect , 3) /* 4170 */
2225 MIPS_SYS(sys_getpeername , 3)
2226 MIPS_SYS(sys_getsockname , 3)
2227 MIPS_SYS(sys_getsockopt , 5)
2228 MIPS_SYS(sys_listen , 2)
2229 MIPS_SYS(sys_recv , 4) /* 4175 */
2230 MIPS_SYS(sys_recvfrom , 6)
2231 MIPS_SYS(sys_recvmsg , 3)
2232 MIPS_SYS(sys_send , 4)
2233 MIPS_SYS(sys_sendmsg , 3)
2234 MIPS_SYS(sys_sendto , 6) /* 4180 */
2235 MIPS_SYS(sys_setsockopt , 5)
2236 MIPS_SYS(sys_shutdown , 2)
2237 MIPS_SYS(sys_socket , 3)
2238 MIPS_SYS(sys_socketpair , 4)
2239 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2240 MIPS_SYS(sys_getresuid , 3)
2241 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2242 MIPS_SYS(sys_poll , 3)
2243 MIPS_SYS(sys_nfsservctl , 3)
2244 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2245 MIPS_SYS(sys_getresgid , 3)
2246 MIPS_SYS(sys_prctl , 5)
2247 MIPS_SYS(sys_rt_sigreturn, 0)
2248 MIPS_SYS(sys_rt_sigaction, 4)
2249 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2250 MIPS_SYS(sys_rt_sigpending, 2)
2251 MIPS_SYS(sys_rt_sigtimedwait, 4)
2252 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2253 MIPS_SYS(sys_rt_sigsuspend, 0)
2254 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2255 MIPS_SYS(sys_pwrite64 , 6)
2256 MIPS_SYS(sys_chown , 3)
2257 MIPS_SYS(sys_getcwd , 2)
2258 MIPS_SYS(sys_capget , 2)
2259 MIPS_SYS(sys_capset , 2) /* 4205 */
2260 MIPS_SYS(sys_sigaltstack , 2)
2261 MIPS_SYS(sys_sendfile , 4)
2262 MIPS_SYS(sys_ni_syscall , 0)
2263 MIPS_SYS(sys_ni_syscall , 0)
2264 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2265 MIPS_SYS(sys_truncate64 , 4)
2266 MIPS_SYS(sys_ftruncate64 , 4)
2267 MIPS_SYS(sys_stat64 , 2)
2268 MIPS_SYS(sys_lstat64 , 2)
2269 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2270 MIPS_SYS(sys_pivot_root , 2)
2271 MIPS_SYS(sys_mincore , 3)
2272 MIPS_SYS(sys_madvise , 3)
2273 MIPS_SYS(sys_getdents64 , 3)
2274 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2275 MIPS_SYS(sys_ni_syscall , 0)
2276 MIPS_SYS(sys_gettid , 0)
2277 MIPS_SYS(sys_readahead , 5)
2278 MIPS_SYS(sys_setxattr , 5)
2279 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2280 MIPS_SYS(sys_fsetxattr , 5)
2281 MIPS_SYS(sys_getxattr , 4)
2282 MIPS_SYS(sys_lgetxattr , 4)
2283 MIPS_SYS(sys_fgetxattr , 4)
2284 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2285 MIPS_SYS(sys_llistxattr , 3)
2286 MIPS_SYS(sys_flistxattr , 3)
2287 MIPS_SYS(sys_removexattr , 2)
2288 MIPS_SYS(sys_lremovexattr, 2)
2289 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2290 MIPS_SYS(sys_tkill , 2)
2291 MIPS_SYS(sys_sendfile64 , 5)
2292 MIPS_SYS(sys_futex , 6)
2293 MIPS_SYS(sys_sched_setaffinity, 3)
2294 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2295 MIPS_SYS(sys_io_setup , 2)
2296 MIPS_SYS(sys_io_destroy , 1)
2297 MIPS_SYS(sys_io_getevents, 5)
2298 MIPS_SYS(sys_io_submit , 3)
2299 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2300 MIPS_SYS(sys_exit_group , 1)
2301 MIPS_SYS(sys_lookup_dcookie, 3)
2302 MIPS_SYS(sys_epoll_create, 1)
2303 MIPS_SYS(sys_epoll_ctl , 4)
2304 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2305 MIPS_SYS(sys_remap_file_pages, 5)
2306 MIPS_SYS(sys_set_tid_address, 1)
2307 MIPS_SYS(sys_restart_syscall, 0)
2308 MIPS_SYS(sys_fadvise64_64, 7)
2309 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2310 MIPS_SYS(sys_fstatfs64 , 2)
2311 MIPS_SYS(sys_timer_create, 3)
2312 MIPS_SYS(sys_timer_settime, 4)
2313 MIPS_SYS(sys_timer_gettime, 2)
2314 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2315 MIPS_SYS(sys_timer_delete, 1)
2316 MIPS_SYS(sys_clock_settime, 2)
2317 MIPS_SYS(sys_clock_gettime, 2)
2318 MIPS_SYS(sys_clock_getres, 2)
2319 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2320 MIPS_SYS(sys_tgkill , 3)
2321 MIPS_SYS(sys_utimes , 2)
2322 MIPS_SYS(sys_mbind , 4)
2323 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2324 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2325 MIPS_SYS(sys_mq_open , 4)
2326 MIPS_SYS(sys_mq_unlink , 1)
2327 MIPS_SYS(sys_mq_timedsend, 5)
2328 MIPS_SYS(sys_mq_timedreceive, 5)
2329 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2330 MIPS_SYS(sys_mq_getsetattr, 3)
2331 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2332 MIPS_SYS(sys_waitid , 4)
2333 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2334 MIPS_SYS(sys_add_key , 5)
2335 MIPS_SYS(sys_request_key, 4)
2336 MIPS_SYS(sys_keyctl , 5)
2337 MIPS_SYS(sys_set_thread_area, 1)
2338 MIPS_SYS(sys_inotify_init, 0)
2339 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2340 MIPS_SYS(sys_inotify_rm_watch, 2)
2341 MIPS_SYS(sys_migrate_pages, 4)
2342 MIPS_SYS(sys_openat, 4)
2343 MIPS_SYS(sys_mkdirat, 3)
2344 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2345 MIPS_SYS(sys_fchownat, 5)
2346 MIPS_SYS(sys_futimesat, 3)
2347 MIPS_SYS(sys_fstatat64, 4)
2348 MIPS_SYS(sys_unlinkat, 3)
2349 MIPS_SYS(sys_renameat, 4) /* 4295 */
2350 MIPS_SYS(sys_linkat, 5)
2351 MIPS_SYS(sys_symlinkat, 3)
2352 MIPS_SYS(sys_readlinkat, 4)
2353 MIPS_SYS(sys_fchmodat, 3)
2354 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2355 MIPS_SYS(sys_pselect6, 6)
2356 MIPS_SYS(sys_ppoll, 5)
2357 MIPS_SYS(sys_unshare, 1)
2358 MIPS_SYS(sys_splice, 6)
2359 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2360 MIPS_SYS(sys_tee, 4)
2361 MIPS_SYS(sys_vmsplice, 4)
2362 MIPS_SYS(sys_move_pages, 6)
2363 MIPS_SYS(sys_set_robust_list, 2)
2364 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2365 MIPS_SYS(sys_kexec_load, 4)
2366 MIPS_SYS(sys_getcpu, 3)
2367 MIPS_SYS(sys_epoll_pwait, 6)
2368 MIPS_SYS(sys_ioprio_set, 3)
2369 MIPS_SYS(sys_ioprio_get, 2)
2370 MIPS_SYS(sys_utimensat, 4)
2371 MIPS_SYS(sys_signalfd, 3)
2372 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2373 MIPS_SYS(sys_eventfd, 1)
2374 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2375 MIPS_SYS(sys_timerfd_create, 2)
2376 MIPS_SYS(sys_timerfd_gettime, 2)
2377 MIPS_SYS(sys_timerfd_settime, 4)
2378 MIPS_SYS(sys_signalfd4, 4)
2379 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2380 MIPS_SYS(sys_epoll_create1, 1)
2381 MIPS_SYS(sys_dup3, 3)
2382 MIPS_SYS(sys_pipe2, 2)
2383 MIPS_SYS(sys_inotify_init1, 1)
2384 MIPS_SYS(sys_preadv, 6) /* 4330 */
2385 MIPS_SYS(sys_pwritev, 6)
2386 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2387 MIPS_SYS(sys_perf_event_open, 5)
2388 MIPS_SYS(sys_accept4, 4)
2389 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2390 MIPS_SYS(sys_fanotify_init, 2)
2391 MIPS_SYS(sys_fanotify_mark, 6)
2392 MIPS_SYS(sys_prlimit64, 4)
2393 MIPS_SYS(sys_name_to_handle_at, 5)
2394 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2395 MIPS_SYS(sys_clock_adjtime, 2)
2396 MIPS_SYS(sys_syncfs, 1)
2397 };
2398 # undef MIPS_SYS
2399 # endif /* O32 */
2400
2401 static int do_store_exclusive(CPUMIPSState *env)
2402 {
2403 target_ulong addr;
2404 target_ulong page_addr;
2405 target_ulong val;
2406 int flags;
2407 int segv = 0;
2408 int reg;
2409 int d;
2410
2411 addr = env->lladdr;
2412 page_addr = addr & TARGET_PAGE_MASK;
2413 start_exclusive();
2414 mmap_lock();
2415 flags = page_get_flags(page_addr);
2416 if ((flags & PAGE_READ) == 0) {
2417 segv = 1;
2418 } else {
2419 reg = env->llreg & 0x1f;
2420 d = (env->llreg & 0x20) != 0;
2421 if (d) {
2422 segv = get_user_s64(val, addr);
2423 } else {
2424 segv = get_user_s32(val, addr);
2425 }
2426 if (!segv) {
2427 if (val != env->llval) {
2428 env->active_tc.gpr[reg] = 0;
2429 } else {
2430 if (d) {
2431 segv = put_user_u64(env->llnewval, addr);
2432 } else {
2433 segv = put_user_u32(env->llnewval, addr);
2434 }
2435 if (!segv) {
2436 env->active_tc.gpr[reg] = 1;
2437 }
2438 }
2439 }
2440 }
2441 env->lladdr = -1;
2442 if (!segv) {
2443 env->active_tc.PC += 4;
2444 }
2445 mmap_unlock();
2446 end_exclusive();
2447 return segv;
2448 }
2449
2450 /* Break codes */
2451 enum {
2452 BRK_OVERFLOW = 6,
2453 BRK_DIVZERO = 7
2454 };
2455
2456 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2457 unsigned int code)
2458 {
2459 int ret = -1;
2460
2461 switch (code) {
2462 case BRK_OVERFLOW:
2463 case BRK_DIVZERO:
2464 info->si_signo = TARGET_SIGFPE;
2465 info->si_errno = 0;
2466 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2467 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2468 ret = 0;
2469 break;
2470 default:
2471 info->si_signo = TARGET_SIGTRAP;
2472 info->si_errno = 0;
2473 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2474 ret = 0;
2475 break;
2476 }
2477
2478 return ret;
2479 }
2480
2481 void cpu_loop(CPUMIPSState *env)
2482 {
2483 CPUState *cs = CPU(mips_env_get_cpu(env));
2484 target_siginfo_t info;
2485 int trapnr;
2486 abi_long ret;
2487 # ifdef TARGET_ABI_MIPSO32
2488 unsigned int syscall_num;
2489 # endif
2490
2491 for(;;) {
2492 cpu_exec_start(cs);
2493 trapnr = cpu_exec(cs);
2494 cpu_exec_end(cs);
2495 switch(trapnr) {
2496 case EXCP_SYSCALL:
2497 env->active_tc.PC += 4;
2498 # ifdef TARGET_ABI_MIPSO32
2499 syscall_num = env->active_tc.gpr[2] - 4000;
2500 if (syscall_num >= sizeof(mips_syscall_args)) {
2501 ret = -TARGET_ENOSYS;
2502 } else {
2503 int nb_args;
2504 abi_ulong sp_reg;
2505 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2506
2507 nb_args = mips_syscall_args[syscall_num];
2508 sp_reg = env->active_tc.gpr[29];
2509 switch (nb_args) {
2510 /* these arguments are taken from the stack */
2511 case 8:
2512 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2513 goto done_syscall;
2514 }
2515 case 7:
2516 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2517 goto done_syscall;
2518 }
2519 case 6:
2520 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2521 goto done_syscall;
2522 }
2523 case 5:
2524 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2525 goto done_syscall;
2526 }
2527 default:
2528 break;
2529 }
2530 ret = do_syscall(env, env->active_tc.gpr[2],
2531 env->active_tc.gpr[4],
2532 env->active_tc.gpr[5],
2533 env->active_tc.gpr[6],
2534 env->active_tc.gpr[7],
2535 arg5, arg6, arg7, arg8);
2536 }
2537 done_syscall:
2538 # else
2539 ret = do_syscall(env, env->active_tc.gpr[2],
2540 env->active_tc.gpr[4], env->active_tc.gpr[5],
2541 env->active_tc.gpr[6], env->active_tc.gpr[7],
2542 env->active_tc.gpr[8], env->active_tc.gpr[9],
2543 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2544 # endif /* O32 */
2545 if (ret == -TARGET_ERESTARTSYS) {
2546 env->active_tc.PC -= 4;
2547 break;
2548 }
2549 if (ret == -TARGET_QEMU_ESIGRETURN) {
2550 /* Returning from a successful sigreturn syscall.
2551 Avoid clobbering register state. */
2552 break;
2553 }
2554 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2555 env->active_tc.gpr[7] = 1; /* error flag */
2556 ret = -ret;
2557 } else {
2558 env->active_tc.gpr[7] = 0; /* error flag */
2559 }
2560 env->active_tc.gpr[2] = ret;
2561 break;
2562 case EXCP_TLBL:
2563 case EXCP_TLBS:
2564 case EXCP_AdEL:
2565 case EXCP_AdES:
2566 info.si_signo = TARGET_SIGSEGV;
2567 info.si_errno = 0;
2568 /* XXX: check env->error_code */
2569 info.si_code = TARGET_SEGV_MAPERR;
2570 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2571 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2572 break;
2573 case EXCP_CpU:
2574 case EXCP_RI:
2575 info.si_signo = TARGET_SIGILL;
2576 info.si_errno = 0;
2577 info.si_code = 0;
2578 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2579 break;
2580 case EXCP_INTERRUPT:
2581 /* just indicate that signals should be handled asap */
2582 break;
2583 case EXCP_DEBUG:
2584 {
2585 int sig;
2586
2587 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2588 if (sig)
2589 {
2590 info.si_signo = sig;
2591 info.si_errno = 0;
2592 info.si_code = TARGET_TRAP_BRKPT;
2593 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2594 }
2595 }
2596 break;
2597 case EXCP_SC:
2598 if (do_store_exclusive(env)) {
2599 info.si_signo = TARGET_SIGSEGV;
2600 info.si_errno = 0;
2601 info.si_code = TARGET_SEGV_MAPERR;
2602 info._sifields._sigfault._addr = env->active_tc.PC;
2603 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2604 }
2605 break;
2606 case EXCP_DSPDIS:
2607 info.si_signo = TARGET_SIGILL;
2608 info.si_errno = 0;
2609 info.si_code = TARGET_ILL_ILLOPC;
2610 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2611 break;
2612 /* The code below was inspired by the MIPS Linux kernel trap
2613 * handling code in arch/mips/kernel/traps.c.
2614 */
2615 case EXCP_BREAK:
2616 {
2617 abi_ulong trap_instr;
2618 unsigned int code;
2619
2620 if (env->hflags & MIPS_HFLAG_M16) {
2621 if (env->insn_flags & ASE_MICROMIPS) {
2622 /* microMIPS mode */
2623 ret = get_user_u16(trap_instr, env->active_tc.PC);
2624 if (ret != 0) {
2625 goto error;
2626 }
2627
2628 if ((trap_instr >> 10) == 0x11) {
2629 /* 16-bit instruction */
2630 code = trap_instr & 0xf;
2631 } else {
2632 /* 32-bit instruction */
2633 abi_ulong instr_lo;
2634
2635 ret = get_user_u16(instr_lo,
2636 env->active_tc.PC + 2);
2637 if (ret != 0) {
2638 goto error;
2639 }
2640 trap_instr = (trap_instr << 16) | instr_lo;
2641 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2642 /* Unfortunately, microMIPS also suffers from
2643 the old assembler bug... */
2644 if (code >= (1 << 10)) {
2645 code >>= 10;
2646 }
2647 }
2648 } else {
2649 /* MIPS16e mode */
2650 ret = get_user_u16(trap_instr, env->active_tc.PC);
2651 if (ret != 0) {
2652 goto error;
2653 }
2654 code = (trap_instr >> 6) & 0x3f;
2655 }
2656 } else {
2657 ret = get_user_u32(trap_instr, env->active_tc.PC);
2658 if (ret != 0) {
2659 goto error;
2660 }
2661
2662 /* As described in the original Linux kernel code, the
2663 * below checks on 'code' are to work around an old
2664 * assembly bug.
2665 */
2666 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2667 if (code >= (1 << 10)) {
2668 code >>= 10;
2669 }
2670 }
2671
2672 if (do_break(env, &info, code) != 0) {
2673 goto error;
2674 }
2675 }
2676 break;
2677 case EXCP_TRAP:
2678 {
2679 abi_ulong trap_instr;
2680 unsigned int code = 0;
2681
2682 if (env->hflags & MIPS_HFLAG_M16) {
2683 /* microMIPS mode */
2684 abi_ulong instr[2];
2685
2686 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2687 get_user_u16(instr[1], env->active_tc.PC + 2);
2688
2689 trap_instr = (instr[0] << 16) | instr[1];
2690 } else {
2691 ret = get_user_u32(trap_instr, env->active_tc.PC);
2692 }
2693
2694 if (ret != 0) {
2695 goto error;
2696 }
2697
2698 /* The immediate versions don't provide a code. */
2699 if (!(trap_instr & 0xFC000000)) {
2700 if (env->hflags & MIPS_HFLAG_M16) {
2701 /* microMIPS mode */
2702 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2703 } else {
2704 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2705 }
2706 }
2707
2708 if (do_break(env, &info, code) != 0) {
2709 goto error;
2710 }
2711 }
2712 break;
2713 default:
2714 error:
2715 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2716 abort();
2717 }
2718 process_pending_signals(env);
2719 }
2720 }
2721 #endif
2722
2723 #ifdef TARGET_OPENRISC
2724
2725 void cpu_loop(CPUOpenRISCState *env)
2726 {
2727 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2728 int trapnr, gdbsig;
2729 abi_long ret;
2730
2731 for (;;) {
2732 cpu_exec_start(cs);
2733 trapnr = cpu_exec(cs);
2734 cpu_exec_end(cs);
2735 gdbsig = 0;
2736
2737 switch (trapnr) {
2738 case EXCP_RESET:
2739 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2740 exit(EXIT_FAILURE);
2741 break;
2742 case EXCP_BUSERR:
2743 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2744 gdbsig = TARGET_SIGBUS;
2745 break;
2746 case EXCP_DPF:
2747 case EXCP_IPF:
2748 cpu_dump_state(cs, stderr, fprintf, 0);
2749 gdbsig = TARGET_SIGSEGV;
2750 break;
2751 case EXCP_TICK:
2752 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2753 break;
2754 case EXCP_ALIGN:
2755 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2756 gdbsig = TARGET_SIGBUS;
2757 break;
2758 case EXCP_ILLEGAL:
2759 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2760 gdbsig = TARGET_SIGILL;
2761 break;
2762 case EXCP_INT:
2763 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2764 break;
2765 case EXCP_DTLBMISS:
2766 case EXCP_ITLBMISS:
2767 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2768 break;
2769 case EXCP_RANGE:
2770 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2771 gdbsig = TARGET_SIGSEGV;
2772 break;
2773 case EXCP_SYSCALL:
2774 env->pc += 4; /* 0xc00; */
2775 ret = do_syscall(env,
2776 env->gpr[11], /* return value */
2777 env->gpr[3], /* r3 - r7 are params */
2778 env->gpr[4],
2779 env->gpr[5],
2780 env->gpr[6],
2781 env->gpr[7],
2782 env->gpr[8], 0, 0);
2783 if (ret == -TARGET_ERESTARTSYS) {
2784 env->pc -= 4;
2785 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2786 env->gpr[11] = ret;
2787 }
2788 break;
2789 case EXCP_FPE:
2790 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2791 break;
2792 case EXCP_TRAP:
2793 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2794 gdbsig = TARGET_SIGTRAP;
2795 break;
2796 case EXCP_NR:
2797 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2798 break;
2799 default:
2800 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2801 trapnr);
2802 gdbsig = TARGET_SIGILL;
2803 break;
2804 }
2805 if (gdbsig) {
2806 gdb_handlesig(cs, gdbsig);
2807 if (gdbsig != TARGET_SIGTRAP) {
2808 exit(EXIT_FAILURE);
2809 }
2810 }
2811
2812 process_pending_signals(env);
2813 }
2814 }
2815
2816 #endif /* TARGET_OPENRISC */
2817
2818 #ifdef TARGET_SH4
2819 void cpu_loop(CPUSH4State *env)
2820 {
2821 CPUState *cs = CPU(sh_env_get_cpu(env));
2822 int trapnr, ret;
2823 target_siginfo_t info;
2824
2825 while (1) {
2826 cpu_exec_start(cs);
2827 trapnr = cpu_exec(cs);
2828 cpu_exec_end(cs);
2829
2830 switch (trapnr) {
2831 case 0x160:
2832 env->pc += 2;
2833 ret = do_syscall(env,
2834 env->gregs[3],
2835 env->gregs[4],
2836 env->gregs[5],
2837 env->gregs[6],
2838 env->gregs[7],
2839 env->gregs[0],
2840 env->gregs[1],
2841 0, 0);
2842 if (ret == -TARGET_ERESTARTSYS) {
2843 env->pc -= 2;
2844 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2845 env->gregs[0] = ret;
2846 }
2847 break;
2848 case EXCP_INTERRUPT:
2849 /* just indicate that signals should be handled asap */
2850 break;
2851 case EXCP_DEBUG:
2852 {
2853 int sig;
2854
2855 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2856 if (sig)
2857 {
2858 info.si_signo = sig;
2859 info.si_errno = 0;
2860 info.si_code = TARGET_TRAP_BRKPT;
2861 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2862 }
2863 }
2864 break;
2865 case 0xa0:
2866 case 0xc0:
2867 info.si_signo = TARGET_SIGSEGV;
2868 info.si_errno = 0;
2869 info.si_code = TARGET_SEGV_MAPERR;
2870 info._sifields._sigfault._addr = env->tea;
2871 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2872 break;
2873
2874 default:
2875 printf ("Unhandled trap: 0x%x\n", trapnr);
2876 cpu_dump_state(cs, stderr, fprintf, 0);
2877 exit(EXIT_FAILURE);
2878 }
2879 process_pending_signals (env);
2880 }
2881 }
2882 #endif
2883
2884 #ifdef TARGET_CRIS
2885 void cpu_loop(CPUCRISState *env)
2886 {
2887 CPUState *cs = CPU(cris_env_get_cpu(env));
2888 int trapnr, ret;
2889 target_siginfo_t info;
2890
2891 while (1) {
2892 cpu_exec_start(cs);
2893 trapnr = cpu_exec(cs);
2894 cpu_exec_end(cs);
2895 switch (trapnr) {
2896 case 0xaa:
2897 {
2898 info.si_signo = TARGET_SIGSEGV;
2899 info.si_errno = 0;
2900 /* XXX: check env->error_code */
2901 info.si_code = TARGET_SEGV_MAPERR;
2902 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2903 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2904 }
2905 break;
2906 case EXCP_INTERRUPT:
2907 /* just indicate that signals should be handled asap */
2908 break;
2909 case EXCP_BREAK:
2910 ret = do_syscall(env,
2911 env->regs[9],
2912 env->regs[10],
2913 env->regs[11],
2914 env->regs[12],
2915 env->regs[13],
2916 env->pregs[7],
2917 env->pregs[11],
2918 0, 0);
2919 if (ret == -TARGET_ERESTARTSYS) {
2920 env->pc -= 2;
2921 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2922 env->regs[10] = ret;
2923 }
2924 break;
2925 case EXCP_DEBUG:
2926 {
2927 int sig;
2928
2929 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2930 if (sig)
2931 {
2932 info.si_signo = sig;
2933 info.si_errno = 0;
2934 info.si_code = TARGET_TRAP_BRKPT;
2935 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2936 }
2937 }
2938 break;
2939 default:
2940 printf ("Unhandled trap: 0x%x\n", trapnr);
2941 cpu_dump_state(cs, stderr, fprintf, 0);
2942 exit(EXIT_FAILURE);
2943 }
2944 process_pending_signals (env);
2945 }
2946 }
2947 #endif
2948
2949 #ifdef TARGET_MICROBLAZE
2950 void cpu_loop(CPUMBState *env)
2951 {
2952 CPUState *cs = CPU(mb_env_get_cpu(env));
2953 int trapnr, ret;
2954 target_siginfo_t info;
2955
2956 while (1) {
2957 cpu_exec_start(cs);
2958 trapnr = cpu_exec(cs);
2959 cpu_exec_end(cs);
2960 switch (trapnr) {
2961 case 0xaa:
2962 {
2963 info.si_signo = TARGET_SIGSEGV;
2964 info.si_errno = 0;
2965 /* XXX: check env->error_code */
2966 info.si_code = TARGET_SEGV_MAPERR;
2967 info._sifields._sigfault._addr = 0;
2968 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2969 }
2970 break;
2971 case EXCP_INTERRUPT:
2972 /* just indicate that signals should be handled asap */
2973 break;
2974 case EXCP_BREAK:
2975 /* Return address is 4 bytes after the call. */
2976 env->regs[14] += 4;
2977 env->sregs[SR_PC] = env->regs[14];
2978 ret = do_syscall(env,
2979 env->regs[12],
2980 env->regs[5],
2981 env->regs[6],
2982 env->regs[7],
2983 env->regs[8],
2984 env->regs[9],
2985 env->regs[10],
2986 0, 0);
2987 if (ret == -TARGET_ERESTARTSYS) {
2988 /* Wind back to before the syscall. */
2989 env->sregs[SR_PC] -= 4;
2990 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2991 env->regs[3] = ret;
2992 }
2993 /* All syscall exits result in guest r14 being equal to the
2994 * PC we return to, because the kernel syscall exit "rtbd" does
2995 * this. (This is true even for sigreturn(); note that r14 is
2996 * not a userspace-usable register, as the kernel may clobber it
2997 * at any point.)
2998 */
2999 env->regs[14] = env->sregs[SR_PC];
3000 break;
3001 case EXCP_HW_EXCP:
3002 env->regs[17] = env->sregs[SR_PC] + 4;
3003 if (env->iflags & D_FLAG) {
3004 env->sregs[SR_ESR] |= 1 << 12;
3005 env->sregs[SR_PC] -= 4;
3006 /* FIXME: if branch was immed, replay the imm as well. */
3007 }
3008
3009 env->iflags &= ~(IMM_FLAG | D_FLAG);
3010
3011 switch (env->sregs[SR_ESR] & 31) {
3012 case ESR_EC_DIVZERO:
3013 info.si_signo = TARGET_SIGFPE;
3014 info.si_errno = 0;
3015 info.si_code = TARGET_FPE_FLTDIV;
3016 info._sifields._sigfault._addr = 0;
3017 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3018 break;
3019 case ESR_EC_FPU:
3020 info.si_signo = TARGET_SIGFPE;
3021 info.si_errno = 0;
3022 if (env->sregs[SR_FSR] & FSR_IO) {
3023 info.si_code = TARGET_FPE_FLTINV;
3024 }
3025 if (env->sregs[SR_FSR] & FSR_DZ) {
3026 info.si_code = TARGET_FPE_FLTDIV;
3027 }
3028 info._sifields._sigfault._addr = 0;
3029 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3030 break;
3031 default:
3032 printf ("Unhandled hw-exception: 0x%x\n",
3033 env->sregs[SR_ESR] & ESR_EC_MASK);
3034 cpu_dump_state(cs, stderr, fprintf, 0);
3035 exit(EXIT_FAILURE);
3036 break;
3037 }
3038 break;
3039 case EXCP_DEBUG:
3040 {
3041 int sig;
3042
3043 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3044 if (sig)
3045 {
3046 info.si_signo = sig;
3047 info.si_errno = 0;
3048 info.si_code = TARGET_TRAP_BRKPT;
3049 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3050 }
3051 }
3052 break;
3053 default:
3054 printf ("Unhandled trap: 0x%x\n", trapnr);
3055 cpu_dump_state(cs, stderr, fprintf, 0);
3056 exit(EXIT_FAILURE);
3057 }
3058 process_pending_signals (env);
3059 }
3060 }
3061 #endif
3062
3063 #ifdef TARGET_M68K
3064
3065 void cpu_loop(CPUM68KState *env)
3066 {
3067 CPUState *cs = CPU(m68k_env_get_cpu(env));
3068 int trapnr;
3069 unsigned int n;
3070 target_siginfo_t info;
3071 TaskState *ts = cs->opaque;
3072
3073 for(;;) {
3074 cpu_exec_start(cs);
3075 trapnr = cpu_exec(cs);
3076 cpu_exec_end(cs);
3077 switch(trapnr) {
3078 case EXCP_ILLEGAL:
3079 {
3080 if (ts->sim_syscalls) {
3081 uint16_t nr;
3082 get_user_u16(nr, env->pc + 2);
3083 env->pc += 4;
3084 do_m68k_simcall(env, nr);
3085 } else {
3086 goto do_sigill;
3087 }
3088 }
3089 break;
3090 case EXCP_HALT_INSN:
3091 /* Semihosing syscall. */
3092 env->pc += 4;
3093 do_m68k_semihosting(env, env->dregs[0]);
3094 break;
3095 case EXCP_LINEA:
3096 case EXCP_LINEF:
3097 case EXCP_UNSUPPORTED:
3098 do_sigill:
3099 info.si_signo = TARGET_SIGILL;
3100 info.si_errno = 0;
3101 info.si_code = TARGET_ILL_ILLOPN;
3102 info._sifields._sigfault._addr = env->pc;
3103 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3104 break;
3105 case EXCP_TRAP0:
3106 {
3107 abi_long ret;
3108 ts->sim_syscalls = 0;
3109 n = env->dregs[0];
3110 env->pc += 2;
3111 ret = do_syscall(env,
3112 n,
3113 env->dregs[1],
3114 env->dregs[2],
3115 env->dregs[3],
3116 env->dregs[4],
3117 env->dregs[5],
3118 env->aregs[0],
3119 0, 0);
3120 if (ret == -TARGET_ERESTARTSYS) {
3121 env->pc -= 2;
3122 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3123 env->dregs[0] = ret;
3124 }
3125 }
3126 break;
3127 case EXCP_INTERRUPT:
3128 /* just indicate that signals should be handled asap */
3129 break;
3130 case EXCP_ACCESS:
3131 {
3132 info.si_signo = TARGET_SIGSEGV;
3133 info.si_errno = 0;
3134 /* XXX: check env->error_code */
3135 info.si_code = TARGET_SEGV_MAPERR;
3136 info._sifields._sigfault._addr = env->mmu.ar;
3137 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3138 }
3139 break;
3140 case EXCP_DEBUG:
3141 {
3142 int sig;
3143
3144 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3145 if (sig)
3146 {
3147 info.si_signo = sig;
3148 info.si_errno = 0;
3149 info.si_code = TARGET_TRAP_BRKPT;
3150 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3151 }
3152 }
3153 break;
3154 default:
3155 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3156 abort();
3157 }
3158 process_pending_signals(env);
3159 }
3160 }
3161 #endif /* TARGET_M68K */
3162
3163 #ifdef TARGET_ALPHA
3164 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3165 {
3166 target_ulong addr, val, tmp;
3167 target_siginfo_t info;
3168 int ret = 0;
3169
3170 addr = env->lock_addr;
3171 tmp = env->lock_st_addr;
3172 env->lock_addr = -1;
3173 env->lock_st_addr = 0;
3174
3175 start_exclusive();
3176 mmap_lock();
3177
3178 if (addr == tmp) {
3179 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3180 goto do_sigsegv;
3181 }
3182
3183 if (val == env->lock_value) {
3184 tmp = env->ir[reg];
3185 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3186 goto do_sigsegv;
3187 }
3188 ret = 1;
3189 }
3190 }
3191 env->ir[reg] = ret;
3192 env->pc += 4;
3193
3194 mmap_unlock();
3195 end_exclusive();
3196 return;
3197
3198 do_sigsegv:
3199 mmap_unlock();
3200 end_exclusive();
3201
3202 info.si_signo = TARGET_SIGSEGV;
3203 info.si_errno = 0;
3204 info.si_code = TARGET_SEGV_MAPERR;
3205 info._sifields._sigfault._addr = addr;
3206 queue_signal(env, TARGET_SIGSEGV, QEMU_SI_FAULT, &info);
3207 }
3208
3209 void cpu_loop(CPUAlphaState *env)
3210 {
3211 CPUState *cs = CPU(alpha_env_get_cpu(env));
3212 int trapnr;
3213 target_siginfo_t info;
3214 abi_long sysret;
3215
3216 while (1) {
3217 cpu_exec_start(cs);
3218 trapnr = cpu_exec(cs);
3219 cpu_exec_end(cs);
3220
3221 /* All of the traps imply a transition through PALcode, which
3222 implies an REI instruction has been executed. Which means
3223 that the intr_flag should be cleared. */
3224 env->intr_flag = 0;
3225
3226 switch (trapnr) {
3227 case EXCP_RESET:
3228 fprintf(stderr, "Reset requested. Exit\n");
3229 exit(EXIT_FAILURE);
3230 break;
3231 case EXCP_MCHK:
3232 fprintf(stderr, "Machine check exception. Exit\n");
3233 exit(EXIT_FAILURE);
3234 break;
3235 case EXCP_SMP_INTERRUPT:
3236 case EXCP_CLK_INTERRUPT:
3237 case EXCP_DEV_INTERRUPT:
3238 fprintf(stderr, "External interrupt. Exit\n");
3239 exit(EXIT_FAILURE);
3240 break;
3241 case EXCP_MMFAULT:
3242 env->lock_addr = -1;
3243 info.si_signo = TARGET_SIGSEGV;
3244 info.si_errno = 0;
3245 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3246 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3247 info._sifields._sigfault._addr = env->trap_arg0;
3248 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3249 break;
3250 case EXCP_UNALIGN:
3251 env->lock_addr = -1;
3252 info.si_signo = TARGET_SIGBUS;
3253 info.si_errno = 0;
3254 info.si_code = TARGET_BUS_ADRALN;
3255 info._sifields._sigfault._addr = env->trap_arg0;
3256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3257 break;
3258 case EXCP_OPCDEC:
3259 do_sigill:
3260 env->lock_addr = -1;
3261 info.si_signo = TARGET_SIGILL;
3262 info.si_errno = 0;
3263 info.si_code = TARGET_ILL_ILLOPC;
3264 info._sifields._sigfault._addr = env->pc;
3265 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3266 break;
3267 case EXCP_ARITH:
3268 env->lock_addr = -1;
3269 info.si_signo = TARGET_SIGFPE;
3270 info.si_errno = 0;
3271 info.si_code = TARGET_FPE_FLTINV;
3272 info._sifields._sigfault._addr = env->pc;
3273 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3274 break;
3275 case EXCP_FEN:
3276 /* No-op. Linux simply re-enables the FPU. */
3277 break;
3278 case EXCP_CALL_PAL:
3279 env->lock_addr = -1;
3280 switch (env->error_code) {
3281 case 0x80:
3282 /* BPT */
3283 info.si_signo = TARGET_SIGTRAP;
3284 info.si_errno = 0;
3285 info.si_code = TARGET_TRAP_BRKPT;
3286 info._sifields._sigfault._addr = env->pc;
3287 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3288 break;
3289 case 0x81:
3290 /* BUGCHK */
3291 info.si_signo = TARGET_SIGTRAP;
3292 info.si_errno = 0;
3293 info.si_code = 0;
3294 info._sifields._sigfault._addr = env->pc;
3295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3296 break;
3297 case 0x83:
3298 /* CALLSYS */
3299 trapnr = env->ir[IR_V0];
3300 sysret = do_syscall(env, trapnr,
3301 env->ir[IR_A0], env->ir[IR_A1],
3302 env->ir[IR_A2], env->ir[IR_A3],
3303 env->ir[IR_A4], env->ir[IR_A5],
3304 0, 0);
3305 if (sysret == -TARGET_ERESTARTSYS) {
3306 env->pc -= 4;
3307 break;
3308 }
3309 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3310 break;
3311 }
3312 /* Syscall writes 0 to V0 to bypass error check, similar
3313 to how this is handled internal to Linux kernel.
3314 (Ab)use trapnr temporarily as boolean indicating error. */
3315 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3316 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3317 env->ir[IR_A3] = trapnr;
3318 break;
3319 case 0x86:
3320 /* IMB */
3321 /* ??? We can probably elide the code using page_unprotect
3322 that is checking for self-modifying code. Instead we
3323 could simply call tb_flush here. Until we work out the
3324 changes required to turn off the extra write protection,
3325 this can be a no-op. */
3326 break;
3327 case 0x9E:
3328 /* RDUNIQUE */
3329 /* Handled in the translator for usermode. */
3330 abort();
3331 case 0x9F:
3332 /* WRUNIQUE */
3333 /* Handled in the translator for usermode. */
3334 abort();
3335 case 0xAA:
3336 /* GENTRAP */
3337 info.si_signo = TARGET_SIGFPE;
3338 switch (env->ir[IR_A0]) {
3339 case TARGET_GEN_INTOVF:
3340 info.si_code = TARGET_FPE_INTOVF;
3341 break;
3342 case TARGET_GEN_INTDIV:
3343 info.si_code = TARGET_FPE_INTDIV;
3344 break;
3345 case TARGET_GEN_FLTOVF:
3346 info.si_code = TARGET_FPE_FLTOVF;
3347 break;
3348 case TARGET_GEN_FLTUND:
3349 info.si_code = TARGET_FPE_FLTUND;
3350 break;
3351 case TARGET_GEN_FLTINV:
3352 info.si_code = TARGET_FPE_FLTINV;
3353 break;
3354 case TARGET_GEN_FLTINE:
3355 info.si_code = TARGET_FPE_FLTRES;
3356 break;
3357 case TARGET_GEN_ROPRAND:
3358 info.si_code = 0;
3359 break;
3360 default:
3361 info.si_signo = TARGET_SIGTRAP;
3362 info.si_code = 0;
3363 break;
3364 }
3365 info.si_errno = 0;
3366 info._sifields._sigfault._addr = env->pc;
3367 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3368 break;
3369 default:
3370 goto do_sigill;
3371 }
3372 break;
3373 case EXCP_DEBUG:
3374 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3375 if (info.si_signo) {
3376 env->lock_addr = -1;
3377 info.si_errno = 0;
3378 info.si_code = TARGET_TRAP_BRKPT;
3379 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3380 }
3381 break;
3382 case EXCP_STL_C:
3383 case EXCP_STQ_C:
3384 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3385 break;
3386 case EXCP_INTERRUPT:
3387 /* Just indicate that signals should be handled asap. */
3388 break;
3389 default:
3390 printf ("Unhandled trap: 0x%x\n", trapnr);
3391 cpu_dump_state(cs, stderr, fprintf, 0);
3392 exit(EXIT_FAILURE);
3393 }
3394 process_pending_signals (env);
3395 }
3396 }
3397 #endif /* TARGET_ALPHA */
3398
3399 #ifdef TARGET_S390X
3400 void cpu_loop(CPUS390XState *env)
3401 {
3402 CPUState *cs = CPU(s390_env_get_cpu(env));
3403 int trapnr, n, sig;
3404 target_siginfo_t info;
3405 target_ulong addr;
3406 abi_long ret;
3407
3408 while (1) {
3409 cpu_exec_start(cs);
3410 trapnr = cpu_exec(cs);
3411 cpu_exec_end(cs);
3412 switch (trapnr) {
3413 case EXCP_INTERRUPT:
3414 /* Just indicate that signals should be handled asap. */
3415 break;
3416
3417 case EXCP_SVC:
3418 n = env->int_svc_code;
3419 if (!n) {
3420 /* syscalls > 255 */
3421 n = env->regs[1];
3422 }
3423 env->psw.addr += env->int_svc_ilen;
3424 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3425 env->regs[4], env->regs[5],
3426 env->regs[6], env->regs[7], 0, 0);
3427 if (ret == -TARGET_ERESTARTSYS) {
3428 env->psw.addr -= env->int_svc_ilen;
3429 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3430 env->regs[2] = ret;
3431 }
3432 break;
3433
3434 case EXCP_DEBUG:
3435 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3436 if (sig) {
3437 n = TARGET_TRAP_BRKPT;
3438 goto do_signal_pc;
3439 }
3440 break;
3441 case EXCP_PGM:
3442 n = env->int_pgm_code;
3443 switch (n) {
3444 case PGM_OPERATION:
3445 case PGM_PRIVILEGED:
3446 sig = TARGET_SIGILL;
3447 n = TARGET_ILL_ILLOPC;
3448 goto do_signal_pc;
3449 case PGM_PROTECTION:
3450 case PGM_ADDRESSING:
3451 sig = TARGET_SIGSEGV;
3452 /* XXX: check env->error_code */
3453 n = TARGET_SEGV_MAPERR;
3454 addr = env->__excp_addr;
3455 goto do_signal;
3456 case PGM_EXECUTE:
3457 case PGM_SPECIFICATION:
3458 case PGM_SPECIAL_OP:
3459 case PGM_OPERAND:
3460 do_sigill_opn:
3461 sig = TARGET_SIGILL;
3462 n = TARGET_ILL_ILLOPN;
3463 goto do_signal_pc;
3464
3465 case PGM_FIXPT_OVERFLOW:
3466 sig = TARGET_SIGFPE;
3467 n = TARGET_FPE_INTOVF;
3468 goto do_signal_pc;
3469 case PGM_FIXPT_DIVIDE:
3470 sig = TARGET_SIGFPE;
3471 n = TARGET_FPE_INTDIV;
3472 goto do_signal_pc;
3473
3474 case PGM_DATA:
3475 n = (env->fpc >> 8) & 0xff;
3476 if (n == 0xff) {
3477 /* compare-and-trap */
3478 goto do_sigill_opn;
3479 } else {
3480 /* An IEEE exception, simulated or otherwise. */
3481 if (n & 0x80) {
3482 n = TARGET_FPE_FLTINV;
3483 } else if (n & 0x40) {
3484 n = TARGET_FPE_FLTDIV;
3485 } else if (n & 0x20) {
3486 n = TARGET_FPE_FLTOVF;
3487 } else if (n & 0x10) {
3488 n = TARGET_FPE_FLTUND;
3489 } else if (n & 0x08) {
3490 n = TARGET_FPE_FLTRES;
3491 } else {
3492 /* ??? Quantum exception; BFP, DFP error. */
3493 goto do_sigill_opn;
3494 }
3495 sig = TARGET_SIGFPE;
3496 goto do_signal_pc;
3497 }
3498
3499 default:
3500 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3501 cpu_dump_state(cs, stderr, fprintf, 0);
3502 exit(EXIT_FAILURE);
3503 }
3504 break;
3505
3506 do_signal_pc:
3507 addr = env->psw.addr;
3508 do_signal:
3509 info.si_signo = sig;
3510 info.si_errno = 0;
3511 info.si_code = n;
3512 info._sifields._sigfault._addr = addr;
3513 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3514 break;
3515
3516 default:
3517 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3518 cpu_dump_state(cs, stderr, fprintf, 0);
3519 exit(EXIT_FAILURE);
3520 }
3521 process_pending_signals (env);
3522 }
3523 }
3524
3525 #endif /* TARGET_S390X */
3526
3527 #ifdef TARGET_TILEGX
3528
3529 static void gen_sigill_reg(CPUTLGState *env)
3530 {
3531 target_siginfo_t info;
3532
3533 info.si_signo = TARGET_SIGILL;
3534 info.si_errno = 0;
3535 info.si_code = TARGET_ILL_PRVREG;
3536 info._sifields._sigfault._addr = env->pc;
3537 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3538 }
3539
3540 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3541 {
3542 target_siginfo_t info;
3543
3544 info.si_signo = signo;
3545 info.si_errno = 0;
3546 info._sifields._sigfault._addr = env->pc;
3547
3548 if (signo == TARGET_SIGSEGV) {
3549 /* The passed in sigcode is a dummy; check for a page mapping
3550 and pass either MAPERR or ACCERR. */
3551 target_ulong addr = env->excaddr;
3552 info._sifields._sigfault._addr = addr;
3553 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3554 sigcode = TARGET_SEGV_MAPERR;
3555 } else {
3556 sigcode = TARGET_SEGV_ACCERR;
3557 }
3558 }
3559 info.si_code = sigcode;
3560
3561 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3562 }
3563
3564 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3565 {
3566 env->excaddr = addr;
3567 do_signal(env, TARGET_SIGSEGV, 0);
3568 }
3569
3570 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3571 {
3572 if (unlikely(reg >= TILEGX_R_COUNT)) {
3573 switch (reg) {
3574 case TILEGX_R_SN:
3575 case TILEGX_R_ZERO:
3576 return;
3577 case TILEGX_R_IDN0:
3578 case TILEGX_R_IDN1:
3579 case TILEGX_R_UDN0:
3580 case TILEGX_R_UDN1:
3581 case TILEGX_R_UDN2:
3582 case TILEGX_R_UDN3:
3583 gen_sigill_reg(env);
3584 return;
3585 default:
3586 g_assert_not_reached();
3587 }
3588 }
3589 env->regs[reg] = val;
3590 }
3591
3592 /*
3593 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3594 * memory at the address held in the first source register. If the values are
3595 * not equal, then no memory operation is performed. If the values are equal,
3596 * the 8-byte quantity from the second source register is written into memory
3597 * at the address held in the first source register. In either case, the result
3598 * of the instruction is the value read from memory. The compare and write to
3599 * memory are atomic and thus can be used for synchronization purposes. This
3600 * instruction only operates for addresses aligned to a 8-byte boundary.
3601 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3602 *
3603 * Functional Description (64-bit)
3604 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3605 * rf[Dest] = memVal;
3606 * if (memVal == SPR[CmpValueSPR])
3607 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3608 *
3609 * Functional Description (32-bit)
3610 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3611 * rf[Dest] = memVal;
3612 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3613 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3614 *
3615 *
3616 * This function also processes exch and exch4 which need not process SPR.
3617 */
3618 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3619 {
3620 target_ulong addr;
3621 target_long val, sprval;
3622
3623 start_exclusive();
3624
3625 addr = env->atomic_srca;
3626 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3627 goto sigsegv_maperr;
3628 }
3629
3630 if (cmp) {
3631 if (quad) {
3632 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3633 } else {
3634 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3635 }
3636 }
3637
3638 if (!cmp || val == sprval) {
3639 target_long valb = env->atomic_srcb;
3640 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3641 goto sigsegv_maperr;
3642 }
3643 }
3644
3645 set_regval(env, env->atomic_dstr, val);
3646 end_exclusive();
3647 return;
3648
3649 sigsegv_maperr:
3650 end_exclusive();
3651 gen_sigsegv_maperr(env, addr);
3652 }
3653
3654 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3655 {
3656 int8_t write = 1;
3657 target_ulong addr;
3658 target_long val, valb;
3659
3660 start_exclusive();
3661
3662 addr = env->atomic_srca;
3663 valb = env->atomic_srcb;
3664 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3665 goto sigsegv_maperr;
3666 }
3667
3668 switch (trapnr) {
3669 case TILEGX_EXCP_OPCODE_FETCHADD:
3670 case TILEGX_EXCP_OPCODE_FETCHADD4:
3671 valb += val;
3672 break;
3673 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3674 valb += val;
3675 if (valb < 0) {
3676 write = 0;
3677 }
3678 break;
3679 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3680 valb += val;
3681 if ((int32_t)valb < 0) {
3682 write = 0;
3683 }
3684 break;
3685 case TILEGX_EXCP_OPCODE_FETCHAND:
3686 case TILEGX_EXCP_OPCODE_FETCHAND4:
3687 valb &= val;
3688 break;
3689 case TILEGX_EXCP_OPCODE_FETCHOR:
3690 case TILEGX_EXCP_OPCODE_FETCHOR4:
3691 valb |= val;
3692 break;
3693 default:
3694 g_assert_not_reached();
3695 }
3696
3697 if (write) {
3698 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3699 goto sigsegv_maperr;
3700 }
3701 }
3702
3703 set_regval(env, env->atomic_dstr, val);
3704 end_exclusive();
3705 return;
3706
3707 sigsegv_maperr:
3708 end_exclusive();
3709 gen_sigsegv_maperr(env, addr);
3710 }
3711
3712 void cpu_loop(CPUTLGState *env)
3713 {
3714 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3715 int trapnr;
3716
3717 while (1) {
3718 cpu_exec_start(cs);
3719 trapnr = cpu_exec(cs);
3720 cpu_exec_end(cs);
3721 switch (trapnr) {
3722 case TILEGX_EXCP_SYSCALL:
3723 {
3724 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3725 env->regs[0], env->regs[1],
3726 env->regs[2], env->regs[3],
3727 env->regs[4], env->regs[5],
3728 env->regs[6], env->regs[7]);
3729 if (ret == -TARGET_ERESTARTSYS) {
3730 env->pc -= 8;
3731 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3732 env->regs[TILEGX_R_RE] = ret;
3733 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3734 }
3735 break;
3736 }
3737 case TILEGX_EXCP_OPCODE_EXCH:
3738 do_exch(env, true, false);
3739 break;
3740 case TILEGX_EXCP_OPCODE_EXCH4:
3741 do_exch(env, false, false);
3742 break;
3743 case TILEGX_EXCP_OPCODE_CMPEXCH:
3744 do_exch(env, true, true);
3745 break;
3746 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3747 do_exch(env, false, true);
3748 break;
3749 case TILEGX_EXCP_OPCODE_FETCHADD:
3750 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3751 case TILEGX_EXCP_OPCODE_FETCHAND:
3752 case TILEGX_EXCP_OPCODE_FETCHOR:
3753 do_fetch(env, trapnr, true);
3754 break;
3755 case TILEGX_EXCP_OPCODE_FETCHADD4:
3756 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3757 case TILEGX_EXCP_OPCODE_FETCHAND4:
3758 case TILEGX_EXCP_OPCODE_FETCHOR4:
3759 do_fetch(env, trapnr, false);
3760 break;
3761 case TILEGX_EXCP_SIGNAL:
3762 do_signal(env, env->signo, env->sigcode);
3763 break;
3764 case TILEGX_EXCP_REG_IDN_ACCESS:
3765 case TILEGX_EXCP_REG_UDN_ACCESS:
3766 gen_sigill_reg(env);
3767 break;
3768 default:
3769 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3770 g_assert_not_reached();
3771 }
3772 process_pending_signals(env);
3773 }
3774 }
3775
3776 #endif
3777
3778 THREAD CPUState *thread_cpu;
3779
3780 bool qemu_cpu_is_self(CPUState *cpu)
3781 {
3782 return thread_cpu == cpu;
3783 }
3784
3785 void qemu_cpu_kick(CPUState *cpu)
3786 {
3787 cpu_exit(cpu);
3788 }
3789
3790 void task_settid(TaskState *ts)
3791 {
3792 if (ts->ts_tid == 0) {
3793 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3794 }
3795 }
3796
3797 void stop_all_tasks(void)
3798 {
3799 /*
3800 * We trust that when using NPTL, start_exclusive()
3801 * handles thread stopping correctly.
3802 */
3803 start_exclusive();
3804 }
3805
3806 /* Assumes contents are already zeroed. */
3807 void init_task_state(TaskState *ts)
3808 {
3809 ts->used = 1;
3810 }
3811
3812 CPUArchState *cpu_copy(CPUArchState *env)
3813 {
3814 CPUState *cpu = ENV_GET_CPU(env);
3815 CPUState *new_cpu = cpu_init(cpu_model);
3816 CPUArchState *new_env = new_cpu->env_ptr;
3817 CPUBreakpoint *bp;
3818 CPUWatchpoint *wp;
3819
3820 /* Reset non arch specific state */
3821 cpu_reset(new_cpu);
3822
3823 memcpy(new_env, env, sizeof(CPUArchState));
3824
3825 /* Clone all break/watchpoints.
3826 Note: Once we support ptrace with hw-debug register access, make sure
3827 BP_CPU break/watchpoints are handled correctly on clone. */
3828 QTAILQ_INIT(&new_cpu->breakpoints);
3829 QTAILQ_INIT(&new_cpu->watchpoints);
3830 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3831 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3832 }
3833 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3834 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3835 }
3836
3837 return new_env;
3838 }
3839
3840 static void handle_arg_help(const char *arg)
3841 {
3842 usage(EXIT_SUCCESS);
3843 }
3844
3845 static void handle_arg_log(const char *arg)
3846 {
3847 int mask;
3848
3849 mask = qemu_str_to_log_mask(arg);
3850 if (!mask) {
3851 qemu_print_log_usage(stdout);
3852 exit(EXIT_FAILURE);
3853 }
3854 qemu_log_needs_buffers();
3855 qemu_set_log(mask);
3856 }
3857
3858 static void handle_arg_log_filename(const char *arg)
3859 {
3860 qemu_set_log_filename(arg, &error_fatal);
3861 }
3862
3863 static void handle_arg_set_env(const char *arg)
3864 {
3865 char *r, *p, *token;
3866 r = p = strdup(arg);
3867 while ((token = strsep(&p, ",")) != NULL) {
3868 if (envlist_setenv(envlist, token) != 0) {
3869 usage(EXIT_FAILURE);
3870 }
3871 }
3872 free(r);
3873 }
3874
3875 static void handle_arg_unset_env(const char *arg)
3876 {
3877 char *r, *p, *token;
3878 r = p = strdup(arg);
3879 while ((token = strsep(&p, ",")) != NULL) {
3880 if (envlist_unsetenv(envlist, token) != 0) {
3881 usage(EXIT_FAILURE);
3882 }
3883 }
3884 free(r);
3885 }
3886
3887 static void handle_arg_argv0(const char *arg)
3888 {
3889 argv0 = strdup(arg);
3890 }
3891
3892 static void handle_arg_stack_size(const char *arg)
3893 {
3894 char *p;
3895 guest_stack_size = strtoul(arg, &p, 0);
3896 if (guest_stack_size == 0) {
3897 usage(EXIT_FAILURE);
3898 }
3899
3900 if (*p == 'M') {
3901 guest_stack_size *= 1024 * 1024;
3902 } else if (*p == 'k' || *p == 'K') {
3903 guest_stack_size *= 1024;
3904 }
3905 }
3906
3907 static void handle_arg_ld_prefix(const char *arg)
3908 {
3909 interp_prefix = strdup(arg);
3910 }
3911
3912 static void handle_arg_pagesize(const char *arg)
3913 {
3914 qemu_host_page_size = atoi(arg);
3915 if (qemu_host_page_size == 0 ||
3916 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3917 fprintf(stderr, "page size must be a power of two\n");
3918 exit(EXIT_FAILURE);
3919 }
3920 }
3921
3922 static void handle_arg_randseed(const char *arg)
3923 {
3924 unsigned long long seed;
3925
3926 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3927 fprintf(stderr, "Invalid seed number: %s\n", arg);
3928 exit(EXIT_FAILURE);
3929 }
3930 srand(seed);
3931 }
3932
3933 static void handle_arg_gdb(const char *arg)
3934 {
3935 gdbstub_port = atoi(arg);
3936 }
3937
3938 static void handle_arg_uname(const char *arg)
3939 {
3940 qemu_uname_release = strdup(arg);
3941 }
3942
3943 static void handle_arg_cpu(const char *arg)
3944 {
3945 cpu_model = strdup(arg);
3946 if (cpu_model == NULL || is_help_option(cpu_model)) {
3947 /* XXX: implement xxx_cpu_list for targets that still miss it */
3948 #if defined(cpu_list)
3949 cpu_list(stdout, &fprintf);
3950 #endif
3951 exit(EXIT_FAILURE);
3952 }
3953 }
3954
3955 static void handle_arg_guest_base(const char *arg)
3956 {
3957 guest_base = strtol(arg, NULL, 0);
3958 have_guest_base = 1;
3959 }
3960
3961 static void handle_arg_reserved_va(const char *arg)
3962 {
3963 char *p;
3964 int shift = 0;
3965 reserved_va = strtoul(arg, &p, 0);
3966 switch (*p) {
3967 case 'k':
3968 case 'K':
3969 shift = 10;
3970 break;
3971 case 'M':
3972 shift = 20;
3973 break;
3974 case 'G':
3975 shift = 30;
3976 break;
3977 }
3978 if (shift) {
3979 unsigned long unshifted = reserved_va;
3980 p++;
3981 reserved_va <<= shift;
3982 if (((reserved_va >> shift) != unshifted)
3983 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3984 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3985 #endif
3986 ) {
3987 fprintf(stderr, "Reserved virtual address too big\n");
3988 exit(EXIT_FAILURE);
3989 }
3990 }
3991 if (*p) {
3992 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3993 exit(EXIT_FAILURE);
3994 }
3995 }
3996
3997 static void handle_arg_singlestep(const char *arg)
3998 {
3999 singlestep = 1;
4000 }
4001
4002 static void handle_arg_strace(const char *arg)
4003 {
4004 do_strace = 1;
4005 }
4006
4007 static void handle_arg_version(const char *arg)
4008 {
4009 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
4010 ", " QEMU_COPYRIGHT "\n");
4011 exit(EXIT_SUCCESS);
4012 }
4013
4014 static char *trace_file;
4015 static void handle_arg_trace(const char *arg)
4016 {
4017 g_free(trace_file);
4018 trace_file = trace_opt_parse(arg);
4019 }
4020
4021 struct qemu_argument {
4022 const char *argv;
4023 const char *env;
4024 bool has_arg;
4025 void (*handle_opt)(const char *arg);
4026 const char *example;
4027 const char *help;
4028 };
4029
4030 static const struct qemu_argument arg_table[] = {
4031 {"h", "", false, handle_arg_help,
4032 "", "print this help"},
4033 {"help", "", false, handle_arg_help,
4034 "", ""},
4035 {"g", "QEMU_GDB", true, handle_arg_gdb,
4036 "port", "wait gdb connection to 'port'"},
4037 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4038 "path", "set the elf interpreter prefix to 'path'"},
4039 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4040 "size", "set the stack size to 'size' bytes"},
4041 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
4042 "model", "select CPU (-cpu help for list)"},
4043 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4044 "var=value", "sets targets environment variable (see below)"},
4045 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4046 "var", "unsets targets environment variable (see below)"},
4047 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4048 "argv0", "forces target process argv[0] to be 'argv0'"},
4049 {"r", "QEMU_UNAME", true, handle_arg_uname,
4050 "uname", "set qemu uname release string to 'uname'"},
4051 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4052 "address", "set guest_base address to 'address'"},
4053 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4054 "size", "reserve 'size' bytes for guest virtual address space"},
4055 {"d", "QEMU_LOG", true, handle_arg_log,
4056 "item[,...]", "enable logging of specified items "
4057 "(use '-d help' for a list of items)"},
4058 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
4059 "logfile", "write logs to 'logfile' (default stderr)"},
4060 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4061 "pagesize", "set the host page size to 'pagesize'"},
4062 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4063 "", "run in singlestep mode"},
4064 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4065 "", "log system calls"},
4066 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4067 "", "Seed for pseudo-random number generator"},
4068 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4069 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
4070 {"version", "QEMU_VERSION", false, handle_arg_version,
4071 "", "display version information and exit"},
4072 {NULL, NULL, false, NULL, NULL, NULL}
4073 };
4074
4075 static void usage(int exitcode)
4076 {
4077 const struct qemu_argument *arginfo;
4078 int maxarglen;
4079 int maxenvlen;
4080
4081 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4082 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
4083 "\n"
4084 "Options and associated environment variables:\n"
4085 "\n");
4086
4087 /* Calculate column widths. We must always have at least enough space
4088 * for the column header.
4089 */
4090 maxarglen = strlen("Argument");
4091 maxenvlen = strlen("Env-variable");
4092
4093 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4094 int arglen = strlen(arginfo->argv);
4095 if (arginfo->has_arg) {
4096 arglen += strlen(arginfo->example) + 1;
4097 }
4098 if (strlen(arginfo->env) > maxenvlen) {
4099 maxenvlen = strlen(arginfo->env);
4100 }
4101 if (arglen > maxarglen) {
4102 maxarglen = arglen;
4103 }
4104 }
4105
4106 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4107 maxenvlen, "Env-variable");
4108
4109 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4110 if (arginfo->has_arg) {
4111 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4112 (int)(maxarglen - strlen(arginfo->argv) - 1),
4113 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4114 } else {
4115 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4116 maxenvlen, arginfo->env,
4117 arginfo->help);
4118 }
4119 }
4120
4121 printf("\n"
4122 "Defaults:\n"
4123 "QEMU_LD_PREFIX = %s\n"
4124 "QEMU_STACK_SIZE = %ld byte\n",
4125 interp_prefix,
4126 guest_stack_size);
4127
4128 printf("\n"
4129 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4130 "QEMU_UNSET_ENV environment variables to set and unset\n"
4131 "environment variables for the target process.\n"
4132 "It is possible to provide several variables by separating them\n"
4133 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4134 "provide the -E and -U options multiple times.\n"
4135 "The following lines are equivalent:\n"
4136 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4137 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4138 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4139 "Note that if you provide several changes to a single variable\n"
4140 "the last change will stay in effect.\n");
4141
4142 exit(exitcode);
4143 }
4144
4145 static int parse_args(int argc, char **argv)
4146 {
4147 const char *r;
4148 int optind;
4149 const struct qemu_argument *arginfo;
4150
4151 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4152 if (arginfo->env == NULL) {
4153 continue;
4154 }
4155
4156 r = getenv(arginfo->env);
4157 if (r != NULL) {
4158 arginfo->handle_opt(r);
4159 }
4160 }
4161
4162 optind = 1;
4163 for (;;) {
4164 if (optind >= argc) {
4165 break;
4166 }
4167 r = argv[optind];
4168 if (r[0] != '-') {
4169 break;
4170 }
4171 optind++;
4172 r++;
4173 if (!strcmp(r, "-")) {
4174 break;
4175 }
4176 /* Treat --foo the same as -foo. */
4177 if (r[0] == '-') {
4178 r++;
4179 }
4180
4181 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4182 if (!strcmp(r, arginfo->argv)) {
4183 if (arginfo->has_arg) {
4184 if (optind >= argc) {
4185 (void) fprintf(stderr,
4186 "qemu: missing argument for option '%s'\n", r);
4187 exit(EXIT_FAILURE);
4188 }
4189 arginfo->handle_opt(argv[optind]);
4190 optind++;
4191 } else {
4192 arginfo->handle_opt(NULL);
4193 }
4194 break;
4195 }
4196 }
4197
4198 /* no option matched the current argv */
4199 if (arginfo->handle_opt == NULL) {
4200 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4201 exit(EXIT_FAILURE);
4202 }
4203 }
4204
4205 if (optind >= argc) {
4206 (void) fprintf(stderr, "qemu: no user program specified\n");
4207 exit(EXIT_FAILURE);
4208 }
4209
4210 filename = argv[optind];
4211 exec_path = argv[optind];
4212
4213 return optind;
4214 }
4215
4216 int main(int argc, char **argv, char **envp)
4217 {
4218 struct target_pt_regs regs1, *regs = &regs1;
4219 struct image_info info1, *info = &info1;
4220 struct linux_binprm bprm;
4221 TaskState *ts;
4222 CPUArchState *env;
4223 CPUState *cpu;
4224 int optind;
4225 char **target_environ, **wrk;
4226 char **target_argv;
4227 int target_argc;
4228 int i;
4229 int ret;
4230 int execfd;
4231
4232 qemu_init_cpu_loop();
4233 module_call_init(MODULE_INIT_QOM);
4234
4235 if ((envlist = envlist_create()) == NULL) {
4236 (void) fprintf(stderr, "Unable to allocate envlist\n");
4237 exit(EXIT_FAILURE);
4238 }
4239
4240 /* add current environment into the list */
4241 for (wrk = environ; *wrk != NULL; wrk++) {
4242 (void) envlist_setenv(envlist, *wrk);
4243 }
4244
4245 /* Read the stack limit from the kernel. If it's "unlimited",
4246 then we can do little else besides use the default. */
4247 {
4248 struct rlimit lim;
4249 if (getrlimit(RLIMIT_STACK, &lim) == 0
4250 && lim.rlim_cur != RLIM_INFINITY
4251 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4252 guest_stack_size = lim.rlim_cur;
4253 }
4254 }
4255
4256 cpu_model = NULL;
4257
4258 srand(time(NULL));
4259
4260 qemu_add_opts(&qemu_trace_opts);
4261
4262 optind = parse_args(argc, argv);
4263
4264 if (!trace_init_backends()) {
4265 exit(1);
4266 }
4267 trace_init_file(trace_file);
4268
4269 /* Zero out regs */
4270 memset(regs, 0, sizeof(struct target_pt_regs));
4271
4272 /* Zero out image_info */
4273 memset(info, 0, sizeof(struct image_info));
4274
4275 memset(&bprm, 0, sizeof (bprm));
4276
4277 /* Scan interp_prefix dir for replacement files. */
4278 init_paths(interp_prefix);
4279
4280 init_qemu_uname_release();
4281
4282 if (cpu_model == NULL) {
4283 #if defined(TARGET_I386)
4284 #ifdef TARGET_X86_64
4285 cpu_model = "qemu64";
4286 #else
4287 cpu_model = "qemu32";
4288 #endif
4289 #elif defined(TARGET_ARM)
4290 cpu_model = "any";
4291 #elif defined(TARGET_UNICORE32)
4292 cpu_model = "any";
4293 #elif defined(TARGET_M68K)
4294 cpu_model = "any";
4295 #elif defined(TARGET_SPARC)
4296 #ifdef TARGET_SPARC64
4297 cpu_model = "TI UltraSparc II";
4298 #else
4299 cpu_model = "Fujitsu MB86904";
4300 #endif
4301 #elif defined(TARGET_MIPS)
4302 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4303 cpu_model = "5KEf";
4304 #else
4305 cpu_model = "24Kf";
4306 #endif
4307 #elif defined TARGET_OPENRISC
4308 cpu_model = "or1200";
4309 #elif defined(TARGET_PPC)
4310 # ifdef TARGET_PPC64
4311 cpu_model = "POWER8";
4312 # else
4313 cpu_model = "750";
4314 # endif
4315 #elif defined TARGET_SH4
4316 cpu_model = TYPE_SH7785_CPU;
4317 #else
4318 cpu_model = "any";
4319 #endif
4320 }
4321 tcg_exec_init(0);
4322 /* NOTE: we need to init the CPU at this stage to get
4323 qemu_host_page_size */
4324 cpu = cpu_init(cpu_model);
4325 if (!cpu) {
4326 fprintf(stderr, "Unable to find CPU definition\n");
4327 exit(EXIT_FAILURE);
4328 }
4329 env = cpu->env_ptr;
4330 cpu_reset(cpu);
4331
4332 thread_cpu = cpu;
4333
4334 if (getenv("QEMU_STRACE")) {
4335 do_strace = 1;
4336 }
4337
4338 if (getenv("QEMU_RAND_SEED")) {
4339 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4340 }
4341
4342 target_environ = envlist_to_environ(envlist, NULL);
4343 envlist_free(envlist);
4344
4345 /*
4346 * Now that page sizes are configured in cpu_init() we can do
4347 * proper page alignment for guest_base.
4348 */
4349 guest_base = HOST_PAGE_ALIGN(guest_base);
4350
4351 if (reserved_va || have_guest_base) {
4352 guest_base = init_guest_space(guest_base, reserved_va, 0,
4353 have_guest_base);
4354 if (guest_base == (unsigned long)-1) {
4355 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4356 "space for use as guest address space (check your virtual "
4357 "memory ulimit setting or reserve less using -R option)\n",
4358 reserved_va);
4359 exit(EXIT_FAILURE);
4360 }
4361
4362 if (reserved_va) {
4363 mmap_next_start = reserved_va;
4364 }
4365 }
4366
4367 /*
4368 * Read in mmap_min_addr kernel parameter. This value is used
4369 * When loading the ELF image to determine whether guest_base
4370 * is needed. It is also used in mmap_find_vma.
4371 */
4372 {
4373 FILE *fp;
4374
4375 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4376 unsigned long tmp;
4377 if (fscanf(fp, "%lu", &tmp) == 1) {
4378 mmap_min_addr = tmp;
4379 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4380 }
4381 fclose(fp);
4382 }
4383 }
4384
4385 /*
4386 * Prepare copy of argv vector for target.
4387 */
4388 target_argc = argc - optind;
4389 target_argv = calloc(target_argc + 1, sizeof (char *));
4390 if (target_argv == NULL) {
4391 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4392 exit(EXIT_FAILURE);
4393 }
4394
4395 /*
4396 * If argv0 is specified (using '-0' switch) we replace
4397 * argv[0] pointer with the given one.
4398 */
4399 i = 0;
4400 if (argv0 != NULL) {
4401 target_argv[i++] = strdup(argv0);
4402 }
4403 for (; i < target_argc; i++) {
4404 target_argv[i] = strdup(argv[optind + i]);
4405 }
4406 target_argv[target_argc] = NULL;
4407
4408 ts = g_new0(TaskState, 1);
4409 init_task_state(ts);
4410 /* build Task State */
4411 ts->info = info;
4412 ts->bprm = &bprm;
4413 cpu->opaque = ts;
4414 task_settid(ts);
4415
4416 execfd = qemu_getauxval(AT_EXECFD);
4417 if (execfd == 0) {
4418 execfd = open(filename, O_RDONLY);
4419 if (execfd < 0) {
4420 printf("Error while loading %s: %s\n", filename, strerror(errno));
4421 _exit(EXIT_FAILURE);
4422 }
4423 }
4424
4425 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4426 info, &bprm);
4427 if (ret != 0) {
4428 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4429 _exit(EXIT_FAILURE);
4430 }
4431
4432 for (wrk = target_environ; *wrk; wrk++) {
4433 free(*wrk);
4434 }
4435
4436 free(target_environ);
4437
4438 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4439 qemu_log("guest_base 0x%lx\n", guest_base);
4440 log_page_dump();
4441
4442 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4443 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4444 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4445 info->start_code);
4446 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4447 info->start_data);
4448 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4449 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4450 info->start_stack);
4451 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4452 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4453 }
4454
4455 target_set_brk(info->brk);
4456 syscall_init();
4457 signal_init();
4458
4459 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4460 generating the prologue until now so that the prologue can take
4461 the real value of GUEST_BASE into account. */
4462 tcg_prologue_init(&tcg_ctx);
4463
4464 #if defined(TARGET_I386)
4465 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4466 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4467 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4468 env->cr[4] |= CR4_OSFXSR_MASK;
4469 env->hflags |= HF_OSFXSR_MASK;
4470 }
4471 #ifndef TARGET_ABI32
4472 /* enable 64 bit mode if possible */
4473 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4474 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4475 exit(EXIT_FAILURE);
4476 }
4477 env->cr[4] |= CR4_PAE_MASK;
4478 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4479 env->hflags |= HF_LMA_MASK;
4480 #endif
4481
4482 /* flags setup : we activate the IRQs by default as in user mode */
4483 env->eflags |= IF_MASK;
4484
4485 /* linux register setup */
4486 #ifndef TARGET_ABI32
4487 env->regs[R_EAX] = regs->rax;
4488 env->regs[R_EBX] = regs->rbx;
4489 env->regs[R_ECX] = regs->rcx;
4490 env->regs[R_EDX] = regs->rdx;
4491 env->regs[R_ESI] = regs->rsi;
4492 env->regs[R_EDI] = regs->rdi;
4493 env->regs[R_EBP] = regs->rbp;
4494 env->regs[R_ESP] = regs->rsp;
4495 env->eip = regs->rip;
4496 #else
4497 env->regs[R_EAX] = regs->eax;
4498 env->regs[R_EBX] = regs->ebx;
4499 env->regs[R_ECX] = regs->ecx;
4500 env->regs[R_EDX] = regs->edx;
4501 env->regs[R_ESI] = regs->esi;
4502 env->regs[R_EDI] = regs->edi;
4503 env->regs[R_EBP] = regs->ebp;
4504 env->regs[R_ESP] = regs->esp;
4505 env->eip = regs->eip;
4506 #endif
4507
4508 /* linux interrupt setup */
4509 #ifndef TARGET_ABI32
4510 env->idt.limit = 511;
4511 #else
4512 env->idt.limit = 255;
4513 #endif
4514 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4515 PROT_READ|PROT_WRITE,
4516 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4517 idt_table = g2h(env->idt.base);
4518 set_idt(0, 0);
4519 set_idt(1, 0);
4520 set_idt(2, 0);
4521 set_idt(3, 3);
4522 set_idt(4, 3);
4523 set_idt(5, 0);
4524 set_idt(6, 0);
4525 set_idt(7, 0);
4526 set_idt(8, 0);
4527 set_idt(9, 0);
4528 set_idt(10, 0);
4529 set_idt(11, 0);
4530 set_idt(12, 0);
4531 set_idt(13, 0);
4532 set_idt(14, 0);
4533 set_idt(15, 0);
4534 set_idt(16, 0);
4535 set_idt(17, 0);
4536 set_idt(18, 0);
4537 set_idt(19, 0);
4538 set_idt(0x80, 3);
4539
4540 /* linux segment setup */
4541 {
4542 uint64_t *gdt_table;
4543 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4544 PROT_READ|PROT_WRITE,
4545 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4546 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4547 gdt_table = g2h(env->gdt.base);
4548 #ifdef TARGET_ABI32
4549 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4550 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4551 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4552 #else
4553 /* 64 bit code segment */
4554 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4555 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4556 DESC_L_MASK |
4557 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4558 #endif
4559 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4560 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4561 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4562 }
4563 cpu_x86_load_seg(env, R_CS, __USER_CS);
4564 cpu_x86_load_seg(env, R_SS, __USER_DS);
4565 #ifdef TARGET_ABI32
4566 cpu_x86_load_seg(env, R_DS, __USER_DS);
4567 cpu_x86_load_seg(env, R_ES, __USER_DS);
4568 cpu_x86_load_seg(env, R_FS, __USER_DS);
4569 cpu_x86_load_seg(env, R_GS, __USER_DS);
4570 /* This hack makes Wine work... */
4571 env->segs[R_FS].selector = 0;
4572 #else
4573 cpu_x86_load_seg(env, R_DS, 0);
4574 cpu_x86_load_seg(env, R_ES, 0);
4575 cpu_x86_load_seg(env, R_FS, 0);
4576 cpu_x86_load_seg(env, R_GS, 0);
4577 #endif
4578 #elif defined(TARGET_AARCH64)
4579 {
4580 int i;
4581
4582 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4583 fprintf(stderr,
4584 "The selected ARM CPU does not support 64 bit mode\n");
4585 exit(EXIT_FAILURE);
4586 }
4587
4588 for (i = 0; i < 31; i++) {
4589 env->xregs[i] = regs->regs[i];
4590 }
4591 env->pc = regs->pc;
4592 env->xregs[31] = regs->sp;
4593 }
4594 #elif defined(TARGET_ARM)
4595 {
4596 int i;
4597 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4598 CPSRWriteByInstr);
4599 for(i = 0; i < 16; i++) {
4600 env->regs[i] = regs->uregs[i];
4601 }
4602 #ifdef TARGET_WORDS_BIGENDIAN
4603 /* Enable BE8. */
4604 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4605 && (info->elf_flags & EF_ARM_BE8)) {
4606 env->uncached_cpsr |= CPSR_E;
4607 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4608 } else {
4609 env->cp15.sctlr_el[1] |= SCTLR_B;
4610 }
4611 #endif
4612 }
4613 #elif defined(TARGET_UNICORE32)
4614 {
4615 int i;
4616 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4617 for (i = 0; i < 32; i++) {
4618 env->regs[i] = regs->uregs[i];
4619 }
4620 }
4621 #elif defined(TARGET_SPARC)
4622 {
4623 int i;
4624 env->pc = regs->pc;
4625 env->npc = regs->npc;
4626 env->y = regs->y;
4627 for(i = 0; i < 8; i++)
4628 env->gregs[i] = regs->u_regs[i];
4629 for(i = 0; i < 8; i++)
4630 env->regwptr[i] = regs->u_regs[i + 8];
4631 }
4632 #elif defined(TARGET_PPC)
4633 {
4634 int i;
4635
4636 #if defined(TARGET_PPC64)
4637 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
4638 #if defined(TARGET_ABI32)
4639 env->msr &= ~((target_ulong)1 << flag);
4640 #else
4641 env->msr |= (target_ulong)1 << flag;
4642 #endif
4643 #endif
4644 env->nip = regs->nip;
4645 for(i = 0; i < 32; i++) {
4646 env->gpr[i] = regs->gpr[i];
4647 }
4648 }
4649 #elif defined(TARGET_M68K)
4650 {
4651 env->pc = regs->pc;
4652 env->dregs[0] = regs->d0;
4653 env->dregs[1] = regs->d1;
4654 env->dregs[2] = regs->d2;
4655 env->dregs[3] = regs->d3;
4656 env->dregs[4] = regs->d4;
4657 env->dregs[5] = regs->d5;
4658 env->dregs[6] = regs->d6;
4659 env->dregs[7] = regs->d7;
4660 env->aregs[0] = regs->a0;
4661 env->aregs[1] = regs->a1;
4662 env->aregs[2] = regs->a2;
4663 env->aregs[3] = regs->a3;
4664 env->aregs[4] = regs->a4;
4665 env->aregs[5] = regs->a5;
4666 env->aregs[6] = regs->a6;
4667 env->aregs[7] = regs->usp;
4668 env->sr = regs->sr;
4669 ts->sim_syscalls = 1;
4670 }
4671 #elif defined(TARGET_MICROBLAZE)
4672 {
4673 env->regs[0] = regs->r0;
4674 env->regs[1] = regs->r1;
4675 env->regs[2] = regs->r2;
4676 env->regs[3] = regs->r3;
4677 env->regs[4] = regs->r4;
4678 env->regs[5] = regs->r5;
4679 env->regs[6] = regs->r6;
4680 env->regs[7] = regs->r7;
4681 env->regs[8] = regs->r8;
4682 env->regs[9] = regs->r9;
4683 env->regs[10] = regs->r10;
4684 env->regs[11] = regs->r11;
4685 env->regs[12] = regs->r12;
4686 env->regs[13] = regs->r13;
4687 env->regs[14] = regs->r14;
4688 env->regs[15] = regs->r15;
4689 env->regs[16] = regs->r16;
4690 env->regs[17] = regs->r17;
4691 env->regs[18] = regs->r18;
4692 env->regs[19] = regs->r19;
4693 env->regs[20] = regs->r20;
4694 env->regs[21] = regs->r21;
4695 env->regs[22] = regs->r22;
4696 env->regs[23] = regs->r23;
4697 env->regs[24] = regs->r24;
4698 env->regs[25] = regs->r25;
4699 env->regs[26] = regs->r26;
4700 env->regs[27] = regs->r27;
4701 env->regs[28] = regs->r28;
4702 env->regs[29] = regs->r29;
4703 env->regs[30] = regs->r30;
4704 env->regs[31] = regs->r31;
4705 env->sregs[SR_PC] = regs->pc;
4706 }
4707 #elif defined(TARGET_MIPS)
4708 {
4709 int i;
4710
4711 for(i = 0; i < 32; i++) {
4712 env->active_tc.gpr[i] = regs->regs[i];
4713 }
4714 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4715 if (regs->cp0_epc & 1) {
4716 env->hflags |= MIPS_HFLAG_M16;
4717 }
4718 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4719 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4720 if ((env->active_fpu.fcr31_rw_bitmask &
4721 (1 << FCR31_NAN2008)) == 0) {
4722 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4723 exit(1);
4724 }
4725 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4726 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4727 } else {
4728 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4729 }
4730 restore_snan_bit_mode(env);
4731 }
4732 }
4733 #elif defined(TARGET_OPENRISC)
4734 {
4735 int i;
4736
4737 for (i = 0; i < 32; i++) {
4738 env->gpr[i] = regs->gpr[i];
4739 }
4740
4741 env->sr = regs->sr;
4742 env->pc = regs->pc;
4743 }
4744 #elif defined(TARGET_SH4)
4745 {
4746 int i;
4747
4748 for(i = 0; i < 16; i++) {
4749 env->gregs[i] = regs->regs[i];
4750 }
4751 env->pc = regs->pc;
4752 }
4753 #elif defined(TARGET_ALPHA)
4754 {
4755 int i;
4756
4757 for(i = 0; i < 28; i++) {
4758 env->ir[i] = ((abi_ulong *)regs)[i];
4759 }
4760 env->ir[IR_SP] = regs->usp;
4761 env->pc = regs->pc;
4762 }
4763 #elif defined(TARGET_CRIS)
4764 {
4765 env->regs[0] = regs->r0;
4766 env->regs[1] = regs->r1;
4767 env->regs[2] = regs->r2;
4768 env->regs[3] = regs->r3;
4769 env->regs[4] = regs->r4;
4770 env->regs[5] = regs->r5;
4771 env->regs[6] = regs->r6;
4772 env->regs[7] = regs->r7;
4773 env->regs[8] = regs->r8;
4774 env->regs[9] = regs->r9;
4775 env->regs[10] = regs->r10;
4776 env->regs[11] = regs->r11;
4777 env->regs[12] = regs->r12;
4778 env->regs[13] = regs->r13;
4779 env->regs[14] = info->start_stack;
4780 env->regs[15] = regs->acr;
4781 env->pc = regs->erp;
4782 }
4783 #elif defined(TARGET_S390X)
4784 {
4785 int i;
4786 for (i = 0; i < 16; i++) {
4787 env->regs[i] = regs->gprs[i];
4788 }
4789 env->psw.mask = regs->psw.mask;
4790 env->psw.addr = regs->psw.addr;
4791 }
4792 #elif defined(TARGET_TILEGX)
4793 {
4794 int i;
4795 for (i = 0; i < TILEGX_R_COUNT; i++) {
4796 env->regs[i] = regs->regs[i];
4797 }
4798 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4799 env->spregs[i] = 0;
4800 }
4801 env->pc = regs->pc;
4802 }
4803 #else
4804 #error unsupported target CPU
4805 #endif
4806
4807 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4808 ts->stack_base = info->start_stack;
4809 ts->heap_base = info->brk;
4810 /* This will be filled in on the first SYS_HEAPINFO call. */
4811 ts->heap_limit = 0;
4812 #endif
4813
4814 if (gdbstub_port) {
4815 if (gdbserver_start(gdbstub_port) < 0) {
4816 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4817 gdbstub_port);
4818 exit(EXIT_FAILURE);
4819 }
4820 gdb_handlesig(cpu, 0);
4821 }
4822 trace_init_vcpu_events();
4823 cpu_loop(env);
4824 /* never exits */
4825 return 0;
4826 }
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