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[mirror_ubuntu-zesty-kernel.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64 #include "hda_controller.h"
65 #include "hda_intel.h"
66
67 /* position fix mode */
68 enum {
69 POS_FIX_AUTO,
70 POS_FIX_LPIB,
71 POS_FIX_POSBUF,
72 POS_FIX_VIACOMBO,
73 POS_FIX_COMBO,
74 };
75
76 /* Defines for ATI HD Audio support in SB450 south bridge */
77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
79
80 /* Defines for Nvidia HDA support */
81 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
82 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
83 #define NVIDIA_HDA_ISTRM_COH 0x4d
84 #define NVIDIA_HDA_OSTRM_COH 0x4c
85 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
86
87 /* Defines for Intel SCH HDA snoop control */
88 #define INTEL_SCH_HDA_DEVC 0x78
89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91 /* Define IN stream 0 FIFO size offset in VIA controller */
92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
93 /* Define VIA HD Audio Device ID*/
94 #define VIA_HDAC_DEVICE_ID 0x3288
95
96 /* max number of SDs */
97 /* ICH, ATI and VIA have 4 playback and 4 capture */
98 #define ICH6_NUM_CAPTURE 4
99 #define ICH6_NUM_PLAYBACK 4
100
101 /* ULI has 6 playback and 5 capture */
102 #define ULI_NUM_CAPTURE 5
103 #define ULI_NUM_PLAYBACK 6
104
105 /* ATI HDMI may have up to 8 playbacks and 0 capture */
106 #define ATIHDMI_NUM_CAPTURE 0
107 #define ATIHDMI_NUM_PLAYBACK 8
108
109 /* TERA has 4 playback and 3 capture */
110 #define TERA_NUM_CAPTURE 3
111 #define TERA_NUM_PLAYBACK 4
112
113
114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
117 static char *model[SNDRV_CARDS];
118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
121 static int probe_only[SNDRV_CARDS];
122 static int jackpoll_ms[SNDRV_CARDS];
123 static bool single_cmd;
124 static int enable_msi = -1;
125 #ifdef CONFIG_SND_HDA_PATCH_LOADER
126 static char *patch[SNDRV_CARDS];
127 #endif
128 #ifdef CONFIG_SND_HDA_INPUT_BEEP
129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
130 CONFIG_SND_HDA_INPUT_BEEP_MODE};
131 #endif
132
133 module_param_array(index, int, NULL, 0444);
134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
135 module_param_array(id, charp, NULL, 0444);
136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
137 module_param_array(enable, bool, NULL, 0444);
138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
139 module_param_array(model, charp, NULL, 0444);
140 MODULE_PARM_DESC(model, "Use the given board model.");
141 module_param_array(position_fix, int, NULL, 0444);
142 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
144 module_param_array(bdl_pos_adj, int, NULL, 0644);
145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
146 module_param_array(probe_mask, int, NULL, 0444);
147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
148 module_param_array(probe_only, int, NULL, 0444);
149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
150 module_param_array(jackpoll_ms, int, NULL, 0444);
151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
152 module_param(single_cmd, bool, 0444);
153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
154 "(for debugging only).");
155 module_param(enable_msi, bint, 0444);
156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
158 module_param_array(patch, charp, NULL, 0444);
159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
160 #endif
161 #ifdef CONFIG_SND_HDA_INPUT_BEEP
162 module_param_array(beep_mode, bool, NULL, 0444);
163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
164 "(0=off, 1=on) (default=1).");
165 #endif
166
167 #ifdef CONFIG_PM
168 static int param_set_xint(const char *val, const struct kernel_param *kp);
169 static struct kernel_param_ops param_ops_xint = {
170 .set = param_set_xint,
171 .get = param_get_int,
172 };
173 #define param_check_xint param_check_int
174
175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
176 module_param(power_save, xint, 0644);
177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
178 "(in second, 0 = disable).");
179
180 /* reset the HD-audio controller in power save mode.
181 * this may give more power-saving, but will take longer time to
182 * wake up.
183 */
184 static bool power_save_controller = 1;
185 module_param(power_save_controller, bool, 0644);
186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
187 #else
188 #define power_save 0
189 #endif /* CONFIG_PM */
190
191 static int align_buffer_size = -1;
192 module_param(align_buffer_size, bint, 0644);
193 MODULE_PARM_DESC(align_buffer_size,
194 "Force buffer and period sizes to be multiple of 128 bytes.");
195
196 #ifdef CONFIG_X86
197 static int hda_snoop = -1;
198 module_param_named(snoop, hda_snoop, bint, 0444);
199 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
200 #else
201 #define hda_snoop true
202 #endif
203
204
205 MODULE_LICENSE("GPL");
206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
207 "{Intel, ICH6M},"
208 "{Intel, ICH7},"
209 "{Intel, ESB2},"
210 "{Intel, ICH8},"
211 "{Intel, ICH9},"
212 "{Intel, ICH10},"
213 "{Intel, PCH},"
214 "{Intel, CPT},"
215 "{Intel, PPT},"
216 "{Intel, LPT},"
217 "{Intel, LPT_LP},"
218 "{Intel, WPT_LP},"
219 "{Intel, SPT},"
220 "{Intel, SPT_LP},"
221 "{Intel, HPT},"
222 "{Intel, PBG},"
223 "{Intel, SCH},"
224 "{ATI, SB450},"
225 "{ATI, SB600},"
226 "{ATI, RS600},"
227 "{ATI, RS690},"
228 "{ATI, RS780},"
229 "{ATI, R600},"
230 "{ATI, RV630},"
231 "{ATI, RV610},"
232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
236 "{VIA, VT8251},"
237 "{VIA, VT8237A},"
238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
240 MODULE_DESCRIPTION("Intel HDA driver");
241
242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
244 #define SUPPORT_VGA_SWITCHEROO
245 #endif
246 #endif
247
248
249 /*
250 */
251
252 /* driver types */
253 enum {
254 AZX_DRIVER_ICH,
255 AZX_DRIVER_PCH,
256 AZX_DRIVER_SCH,
257 AZX_DRIVER_HDMI,
258 AZX_DRIVER_ATI,
259 AZX_DRIVER_ATIHDMI,
260 AZX_DRIVER_ATIHDMI_NS,
261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
264 AZX_DRIVER_NVIDIA,
265 AZX_DRIVER_TERA,
266 AZX_DRIVER_CTX,
267 AZX_DRIVER_CTHDA,
268 AZX_DRIVER_CMEDIA,
269 AZX_DRIVER_GENERIC,
270 AZX_NUM_DRIVERS, /* keep this as last entry */
271 };
272
273 #define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
276
277 /* quirks for old Intel chipsets */
278 #define AZX_DCAPS_INTEL_ICH \
279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
280
281 /* quirks for Intel PCH */
282 #define AZX_DCAPS_INTEL_PCH_NOPM \
283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
285
286 #define AZX_DCAPS_INTEL_PCH \
287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
288
289 #define AZX_DCAPS_INTEL_HASWELL \
290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
292 AZX_DCAPS_SNOOP_TYPE(SCH))
293
294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
295 #define AZX_DCAPS_INTEL_BROADWELL \
296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
299
300 #define AZX_DCAPS_INTEL_BRASWELL \
301 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
302
303 #define AZX_DCAPS_INTEL_SKYLAKE \
304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
305 AZX_DCAPS_I915_POWERWELL)
306
307 /* quirks for ATI SB / AMD Hudson */
308 #define AZX_DCAPS_PRESET_ATI_SB \
309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
310 AZX_DCAPS_SNOOP_TYPE(ATI))
311
312 /* quirks for ATI/AMD HDMI */
313 #define AZX_DCAPS_PRESET_ATI_HDMI \
314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
315 AZX_DCAPS_NO_MSI64)
316
317 /* quirks for ATI HDMI with snoop off */
318 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
319 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
320
321 /* quirks for Nvidia */
322 #define AZX_DCAPS_PRESET_NVIDIA \
323 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
324 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
325 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
326
327 #define AZX_DCAPS_PRESET_CTHDA \
328 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
329 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
330
331 /*
332 * VGA-switcher support
333 */
334 #ifdef SUPPORT_VGA_SWITCHEROO
335 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
336 #else
337 #define use_vga_switcheroo(chip) 0
338 #endif
339
340 static char *driver_short_names[] = {
341 [AZX_DRIVER_ICH] = "HDA Intel",
342 [AZX_DRIVER_PCH] = "HDA Intel PCH",
343 [AZX_DRIVER_SCH] = "HDA Intel MID",
344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
345 [AZX_DRIVER_ATI] = "HDA ATI SB",
346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
348 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
349 [AZX_DRIVER_SIS] = "HDA SIS966",
350 [AZX_DRIVER_ULI] = "HDA ULI M5461",
351 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
352 [AZX_DRIVER_TERA] = "HDA Teradici",
353 [AZX_DRIVER_CTX] = "HDA Creative",
354 [AZX_DRIVER_CTHDA] = "HDA Creative",
355 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
356 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
357 };
358
359 #ifdef CONFIG_X86
360 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
361 {
362 int pages;
363
364 if (azx_snoop(chip))
365 return;
366 if (!dmab || !dmab->area || !dmab->bytes)
367 return;
368
369 #ifdef CONFIG_SND_DMA_SGBUF
370 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
371 struct snd_sg_buf *sgbuf = dmab->private_data;
372 if (chip->driver_type == AZX_DRIVER_CMEDIA)
373 return; /* deal with only CORB/RIRB buffers */
374 if (on)
375 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
376 else
377 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
378 return;
379 }
380 #endif
381
382 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
383 if (on)
384 set_memory_wc((unsigned long)dmab->area, pages);
385 else
386 set_memory_wb((unsigned long)dmab->area, pages);
387 }
388
389 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
390 bool on)
391 {
392 __mark_pages_wc(chip, buf, on);
393 }
394 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
395 struct snd_pcm_substream *substream, bool on)
396 {
397 if (azx_dev->wc_marked != on) {
398 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
399 azx_dev->wc_marked = on;
400 }
401 }
402 #else
403 /* NOP for other archs */
404 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
405 bool on)
406 {
407 }
408 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
409 struct snd_pcm_substream *substream, bool on)
410 {
411 }
412 #endif
413
414 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
415
416 /*
417 * initialize the PCI registers
418 */
419 /* update bits in a PCI register byte */
420 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
421 unsigned char mask, unsigned char val)
422 {
423 unsigned char data;
424
425 pci_read_config_byte(pci, reg, &data);
426 data &= ~mask;
427 data |= (val & mask);
428 pci_write_config_byte(pci, reg, data);
429 }
430
431 static void azx_init_pci(struct azx *chip)
432 {
433 int snoop_type = azx_get_snoop_type(chip);
434
435 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
436 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
437 * Ensuring these bits are 0 clears playback static on some HD Audio
438 * codecs.
439 * The PCI register TCSEL is defined in the Intel manuals.
440 */
441 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
442 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
443 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
444 }
445
446 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
447 * we need to enable snoop.
448 */
449 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
450 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
451 azx_snoop(chip));
452 update_pci_byte(chip->pci,
453 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
454 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
455 }
456
457 /* For NVIDIA HDA, enable snoop */
458 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
459 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
460 azx_snoop(chip));
461 update_pci_byte(chip->pci,
462 NVIDIA_HDA_TRANSREG_ADDR,
463 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
464 update_pci_byte(chip->pci,
465 NVIDIA_HDA_ISTRM_COH,
466 0x01, NVIDIA_HDA_ENABLE_COHBIT);
467 update_pci_byte(chip->pci,
468 NVIDIA_HDA_OSTRM_COH,
469 0x01, NVIDIA_HDA_ENABLE_COHBIT);
470 }
471
472 /* Enable SCH/PCH snoop if needed */
473 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
474 unsigned short snoop;
475 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
476 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
477 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
478 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
479 if (!azx_snoop(chip))
480 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
481 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
482 pci_read_config_word(chip->pci,
483 INTEL_SCH_HDA_DEVC, &snoop);
484 }
485 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
486 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
487 "Disabled" : "Enabled");
488 }
489 }
490
491 /* calculate runtime delay from LPIB */
492 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
493 unsigned int pos)
494 {
495 struct snd_pcm_substream *substream = azx_dev->core.substream;
496 int stream = substream->stream;
497 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
498 int delay;
499
500 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
501 delay = pos - lpib_pos;
502 else
503 delay = lpib_pos - pos;
504 if (delay < 0) {
505 if (delay >= azx_dev->core.delay_negative_threshold)
506 delay = 0;
507 else
508 delay += azx_dev->core.bufsize;
509 }
510
511 if (delay >= azx_dev->core.period_bytes) {
512 dev_info(chip->card->dev,
513 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
514 delay, azx_dev->core.period_bytes);
515 delay = 0;
516 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
517 chip->get_delay[stream] = NULL;
518 }
519
520 return bytes_to_frames(substream->runtime, delay);
521 }
522
523 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
524
525 /* called from IRQ */
526 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
527 {
528 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
529 int ok;
530
531 ok = azx_position_ok(chip, azx_dev);
532 if (ok == 1) {
533 azx_dev->irq_pending = 0;
534 return ok;
535 } else if (ok == 0) {
536 /* bogus IRQ, process it later */
537 azx_dev->irq_pending = 1;
538 schedule_work(&hda->irq_pending_work);
539 }
540 return 0;
541 }
542
543 /*
544 * Check whether the current DMA position is acceptable for updating
545 * periods. Returns non-zero if it's OK.
546 *
547 * Many HD-audio controllers appear pretty inaccurate about
548 * the update-IRQ timing. The IRQ is issued before actually the
549 * data is processed. So, we need to process it afterwords in a
550 * workqueue.
551 */
552 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
553 {
554 struct snd_pcm_substream *substream = azx_dev->core.substream;
555 int stream = substream->stream;
556 u32 wallclk;
557 unsigned int pos;
558
559 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
560 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
561 return -1; /* bogus (too early) interrupt */
562
563 if (chip->get_position[stream])
564 pos = chip->get_position[stream](chip, azx_dev);
565 else { /* use the position buffer as default */
566 pos = azx_get_pos_posbuf(chip, azx_dev);
567 if (!pos || pos == (u32)-1) {
568 dev_info(chip->card->dev,
569 "Invalid position buffer, using LPIB read method instead.\n");
570 chip->get_position[stream] = azx_get_pos_lpib;
571 pos = azx_get_pos_lpib(chip, azx_dev);
572 chip->get_delay[stream] = NULL;
573 } else {
574 chip->get_position[stream] = azx_get_pos_posbuf;
575 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
576 chip->get_delay[stream] = azx_get_delay_from_lpib;
577 }
578 }
579
580 if (pos >= azx_dev->core.bufsize)
581 pos = 0;
582
583 if (WARN_ONCE(!azx_dev->core.period_bytes,
584 "hda-intel: zero azx_dev->period_bytes"))
585 return -1; /* this shouldn't happen! */
586 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
587 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
588 /* NG - it's below the first next period boundary */
589 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
590 azx_dev->core.start_wallclk += wallclk;
591 return 1; /* OK, it's fine */
592 }
593
594 /*
595 * The work for pending PCM period updates.
596 */
597 static void azx_irq_pending_work(struct work_struct *work)
598 {
599 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
600 struct azx *chip = &hda->chip;
601 struct hdac_bus *bus = azx_bus(chip);
602 struct hdac_stream *s;
603 int pending, ok;
604
605 if (!hda->irq_pending_warned) {
606 dev_info(chip->card->dev,
607 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
608 chip->card->number);
609 hda->irq_pending_warned = 1;
610 }
611
612 for (;;) {
613 pending = 0;
614 spin_lock_irq(&chip->reg_lock);
615 list_for_each_entry(s, &bus->stream_list, list) {
616 struct azx_dev *azx_dev = stream_to_azx_dev(s);
617 if (!azx_dev->irq_pending ||
618 !s->substream ||
619 !s->running)
620 continue;
621 ok = azx_position_ok(chip, azx_dev);
622 if (ok > 0) {
623 azx_dev->irq_pending = 0;
624 spin_unlock(&chip->reg_lock);
625 snd_pcm_period_elapsed(s->substream);
626 spin_lock(&chip->reg_lock);
627 } else if (ok < 0) {
628 pending = 0; /* too early */
629 } else
630 pending++;
631 }
632 spin_unlock_irq(&chip->reg_lock);
633 if (!pending)
634 return;
635 msleep(1);
636 }
637 }
638
639 /* clear irq_pending flags and assure no on-going workq */
640 static void azx_clear_irq_pending(struct azx *chip)
641 {
642 struct hdac_bus *bus = azx_bus(chip);
643 struct hdac_stream *s;
644
645 spin_lock_irq(&chip->reg_lock);
646 list_for_each_entry(s, &bus->stream_list, list) {
647 struct azx_dev *azx_dev = stream_to_azx_dev(s);
648 azx_dev->irq_pending = 0;
649 }
650 spin_unlock_irq(&chip->reg_lock);
651 }
652
653 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
654 {
655 if (request_irq(chip->pci->irq, azx_interrupt,
656 chip->msi ? 0 : IRQF_SHARED,
657 KBUILD_MODNAME, chip)) {
658 dev_err(chip->card->dev,
659 "unable to grab IRQ %d, disabling device\n",
660 chip->pci->irq);
661 if (do_disconnect)
662 snd_card_disconnect(chip->card);
663 return -1;
664 }
665 chip->irq = chip->pci->irq;
666 pci_intx(chip->pci, !chip->msi);
667 return 0;
668 }
669
670 /* get the current DMA position with correction on VIA chips */
671 static unsigned int azx_via_get_position(struct azx *chip,
672 struct azx_dev *azx_dev)
673 {
674 unsigned int link_pos, mini_pos, bound_pos;
675 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
676 unsigned int fifo_size;
677
678 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
679 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
680 /* Playback, no problem using link position */
681 return link_pos;
682 }
683
684 /* Capture */
685 /* For new chipset,
686 * use mod to get the DMA position just like old chipset
687 */
688 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
689 mod_dma_pos %= azx_dev->core.period_bytes;
690
691 /* azx_dev->fifo_size can't get FIFO size of in stream.
692 * Get from base address + offset.
693 */
694 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
695
696 if (azx_dev->insufficient) {
697 /* Link position never gather than FIFO size */
698 if (link_pos <= fifo_size)
699 return 0;
700
701 azx_dev->insufficient = 0;
702 }
703
704 if (link_pos <= fifo_size)
705 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
706 else
707 mini_pos = link_pos - fifo_size;
708
709 /* Find nearest previous boudary */
710 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
711 mod_link_pos = link_pos % azx_dev->core.period_bytes;
712 if (mod_link_pos >= fifo_size)
713 bound_pos = link_pos - mod_link_pos;
714 else if (mod_dma_pos >= mod_mini_pos)
715 bound_pos = mini_pos - mod_mini_pos;
716 else {
717 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
718 if (bound_pos >= azx_dev->core.bufsize)
719 bound_pos = 0;
720 }
721
722 /* Calculate real DMA position we want */
723 return bound_pos + mod_dma_pos;
724 }
725
726 #ifdef CONFIG_PM
727 static DEFINE_MUTEX(card_list_lock);
728 static LIST_HEAD(card_list);
729
730 static void azx_add_card_list(struct azx *chip)
731 {
732 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
733 mutex_lock(&card_list_lock);
734 list_add(&hda->list, &card_list);
735 mutex_unlock(&card_list_lock);
736 }
737
738 static void azx_del_card_list(struct azx *chip)
739 {
740 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
741 mutex_lock(&card_list_lock);
742 list_del_init(&hda->list);
743 mutex_unlock(&card_list_lock);
744 }
745
746 /* trigger power-save check at writing parameter */
747 static int param_set_xint(const char *val, const struct kernel_param *kp)
748 {
749 struct hda_intel *hda;
750 struct azx *chip;
751 int prev = power_save;
752 int ret = param_set_int(val, kp);
753
754 if (ret || prev == power_save)
755 return ret;
756
757 mutex_lock(&card_list_lock);
758 list_for_each_entry(hda, &card_list, list) {
759 chip = &hda->chip;
760 if (!chip->bus || chip->disabled)
761 continue;
762 snd_hda_set_power_save(chip->bus, power_save * 1000);
763 }
764 mutex_unlock(&card_list_lock);
765 return 0;
766 }
767 #else
768 #define azx_add_card_list(chip) /* NOP */
769 #define azx_del_card_list(chip) /* NOP */
770 #endif /* CONFIG_PM */
771
772 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
773 /*
774 * power management
775 */
776 static int azx_suspend(struct device *dev)
777 {
778 struct snd_card *card = dev_get_drvdata(dev);
779 struct azx *chip;
780 struct hda_intel *hda;
781
782 if (!card)
783 return 0;
784
785 chip = card->private_data;
786 hda = container_of(chip, struct hda_intel, chip);
787 if (chip->disabled || hda->init_failed)
788 return 0;
789
790 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
791 azx_clear_irq_pending(chip);
792 azx_stop_chip(chip);
793 azx_enter_link_reset(chip);
794 if (chip->irq >= 0) {
795 free_irq(chip->irq, chip);
796 chip->irq = -1;
797 }
798
799 if (chip->msi)
800 pci_disable_msi(chip->pci);
801 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
802 hda_display_power(hda, false);
803 return 0;
804 }
805
806 static int azx_resume(struct device *dev)
807 {
808 struct pci_dev *pci = to_pci_dev(dev);
809 struct snd_card *card = dev_get_drvdata(dev);
810 struct azx *chip;
811 struct hda_intel *hda;
812
813 if (!card)
814 return 0;
815
816 chip = card->private_data;
817 hda = container_of(chip, struct hda_intel, chip);
818 if (chip->disabled || hda->init_failed)
819 return 0;
820
821 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
822 hda_display_power(hda, true);
823 haswell_set_bclk(hda);
824 }
825 if (chip->msi)
826 if (pci_enable_msi(pci) < 0)
827 chip->msi = 0;
828 if (azx_acquire_irq(chip, 1) < 0)
829 return -EIO;
830 azx_init_pci(chip);
831
832 azx_init_chip(chip, true);
833
834 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
835 return 0;
836 }
837 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
838
839 #ifdef CONFIG_PM
840 static int azx_runtime_suspend(struct device *dev)
841 {
842 struct snd_card *card = dev_get_drvdata(dev);
843 struct azx *chip;
844 struct hda_intel *hda;
845
846 if (!card)
847 return 0;
848
849 chip = card->private_data;
850 hda = container_of(chip, struct hda_intel, chip);
851 if (chip->disabled || hda->init_failed)
852 return 0;
853
854 if (!azx_has_pm_runtime(chip))
855 return 0;
856
857 /* enable controller wake up event */
858 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
859 STATESTS_INT_MASK);
860
861 azx_stop_chip(chip);
862 azx_enter_link_reset(chip);
863 azx_clear_irq_pending(chip);
864 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
865 hda_display_power(hda, false);
866
867 return 0;
868 }
869
870 static int azx_runtime_resume(struct device *dev)
871 {
872 struct snd_card *card = dev_get_drvdata(dev);
873 struct azx *chip;
874 struct hda_intel *hda;
875 struct hda_bus *bus;
876 struct hda_codec *codec;
877 int status;
878
879 if (!card)
880 return 0;
881
882 chip = card->private_data;
883 hda = container_of(chip, struct hda_intel, chip);
884 if (chip->disabled || hda->init_failed)
885 return 0;
886
887 if (!azx_has_pm_runtime(chip))
888 return 0;
889
890 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
891 hda_display_power(hda, true);
892 haswell_set_bclk(hda);
893 }
894
895 /* Read STATESTS before controller reset */
896 status = azx_readw(chip, STATESTS);
897
898 azx_init_pci(chip);
899 azx_init_chip(chip, true);
900
901 bus = chip->bus;
902 if (status && bus) {
903 list_for_each_codec(codec, bus)
904 if (status & (1 << codec->addr))
905 schedule_delayed_work(&codec->jackpoll_work,
906 codec->jackpoll_interval);
907 }
908
909 /* disable controller Wake Up event*/
910 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
911 ~STATESTS_INT_MASK);
912
913 return 0;
914 }
915
916 static int azx_runtime_idle(struct device *dev)
917 {
918 struct snd_card *card = dev_get_drvdata(dev);
919 struct azx *chip;
920 struct hda_intel *hda;
921
922 if (!card)
923 return 0;
924
925 chip = card->private_data;
926 hda = container_of(chip, struct hda_intel, chip);
927 if (chip->disabled || hda->init_failed)
928 return 0;
929
930 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
931 chip->bus->core.codec_powered)
932 return -EBUSY;
933
934 return 0;
935 }
936
937 static const struct dev_pm_ops azx_pm = {
938 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
939 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
940 };
941
942 #define AZX_PM_OPS &azx_pm
943 #else
944 #define AZX_PM_OPS NULL
945 #endif /* CONFIG_PM */
946
947
948 static int azx_probe_continue(struct azx *chip);
949
950 #ifdef SUPPORT_VGA_SWITCHEROO
951 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
952
953 static void azx_vs_set_state(struct pci_dev *pci,
954 enum vga_switcheroo_state state)
955 {
956 struct snd_card *card = pci_get_drvdata(pci);
957 struct azx *chip = card->private_data;
958 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
959 bool disabled;
960
961 wait_for_completion(&hda->probe_wait);
962 if (hda->init_failed)
963 return;
964
965 disabled = (state == VGA_SWITCHEROO_OFF);
966 if (chip->disabled == disabled)
967 return;
968
969 if (!chip->bus) {
970 chip->disabled = disabled;
971 if (!disabled) {
972 dev_info(chip->card->dev,
973 "Start delayed initialization\n");
974 if (azx_probe_continue(chip) < 0) {
975 dev_err(chip->card->dev, "initialization error\n");
976 hda->init_failed = true;
977 }
978 }
979 } else {
980 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
981 disabled ? "Disabling" : "Enabling");
982 if (disabled) {
983 pm_runtime_put_sync_suspend(card->dev);
984 azx_suspend(card->dev);
985 /* when we get suspended by vga switcheroo we end up in D3cold,
986 * however we have no ACPI handle, so pci/acpi can't put us there,
987 * put ourselves there */
988 pci->current_state = PCI_D3cold;
989 chip->disabled = true;
990 if (snd_hda_lock_devices(chip->bus))
991 dev_warn(chip->card->dev,
992 "Cannot lock devices!\n");
993 } else {
994 snd_hda_unlock_devices(chip->bus);
995 pm_runtime_get_noresume(card->dev);
996 chip->disabled = false;
997 azx_resume(card->dev);
998 }
999 }
1000 }
1001
1002 static bool azx_vs_can_switch(struct pci_dev *pci)
1003 {
1004 struct snd_card *card = pci_get_drvdata(pci);
1005 struct azx *chip = card->private_data;
1006 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1007
1008 wait_for_completion(&hda->probe_wait);
1009 if (hda->init_failed)
1010 return false;
1011 if (chip->disabled || !chip->bus)
1012 return true;
1013 if (snd_hda_lock_devices(chip->bus))
1014 return false;
1015 snd_hda_unlock_devices(chip->bus);
1016 return true;
1017 }
1018
1019 static void init_vga_switcheroo(struct azx *chip)
1020 {
1021 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1022 struct pci_dev *p = get_bound_vga(chip->pci);
1023 if (p) {
1024 dev_info(chip->card->dev,
1025 "Handle VGA-switcheroo audio client\n");
1026 hda->use_vga_switcheroo = 1;
1027 pci_dev_put(p);
1028 }
1029 }
1030
1031 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1032 .set_gpu_state = azx_vs_set_state,
1033 .can_switch = azx_vs_can_switch,
1034 };
1035
1036 static int register_vga_switcheroo(struct azx *chip)
1037 {
1038 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1039 int err;
1040
1041 if (!hda->use_vga_switcheroo)
1042 return 0;
1043 /* FIXME: currently only handling DIS controller
1044 * is there any machine with two switchable HDMI audio controllers?
1045 */
1046 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1047 VGA_SWITCHEROO_DIS,
1048 chip->bus != NULL);
1049 if (err < 0)
1050 return err;
1051 hda->vga_switcheroo_registered = 1;
1052
1053 /* register as an optimus hdmi audio power domain */
1054 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1055 &hda->hdmi_pm_domain);
1056 return 0;
1057 }
1058 #else
1059 #define init_vga_switcheroo(chip) /* NOP */
1060 #define register_vga_switcheroo(chip) 0
1061 #define check_hdmi_disabled(pci) false
1062 #endif /* SUPPORT_VGA_SWITCHER */
1063
1064 /*
1065 * destructor
1066 */
1067 static int azx_free(struct azx *chip)
1068 {
1069 struct pci_dev *pci = chip->pci;
1070 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1071
1072 if (azx_has_pm_runtime(chip) && chip->running)
1073 pm_runtime_get_noresume(&pci->dev);
1074
1075 azx_del_card_list(chip);
1076
1077 hda->init_failed = 1; /* to be sure */
1078 complete_all(&hda->probe_wait);
1079
1080 if (use_vga_switcheroo(hda)) {
1081 if (chip->disabled && chip->bus)
1082 snd_hda_unlock_devices(chip->bus);
1083 if (hda->vga_switcheroo_registered)
1084 vga_switcheroo_unregister_client(chip->pci);
1085 }
1086
1087 if (chip->initialized) {
1088 azx_clear_irq_pending(chip);
1089 azx_stop_all_streams(chip);
1090 azx_stop_chip(chip);
1091 }
1092
1093 if (chip->irq >= 0)
1094 free_irq(chip->irq, (void*)chip);
1095 if (chip->msi)
1096 pci_disable_msi(chip->pci);
1097 iounmap(chip->remap_addr);
1098
1099 azx_free_stream_pages(chip);
1100 if (chip->region_requested)
1101 pci_release_regions(chip->pci);
1102 pci_disable_device(chip->pci);
1103 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1104 release_firmware(chip->fw);
1105 #endif
1106 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1107 hda_display_power(hda, false);
1108 hda_i915_exit(hda);
1109 }
1110 kfree(hda);
1111
1112 return 0;
1113 }
1114
1115 static int azx_dev_free(struct snd_device *device)
1116 {
1117 return azx_free(device->device_data);
1118 }
1119
1120 #ifdef SUPPORT_VGA_SWITCHEROO
1121 /*
1122 * Check of disabled HDMI controller by vga-switcheroo
1123 */
1124 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1125 {
1126 struct pci_dev *p;
1127
1128 /* check only discrete GPU */
1129 switch (pci->vendor) {
1130 case PCI_VENDOR_ID_ATI:
1131 case PCI_VENDOR_ID_AMD:
1132 case PCI_VENDOR_ID_NVIDIA:
1133 if (pci->devfn == 1) {
1134 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1135 pci->bus->number, 0);
1136 if (p) {
1137 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1138 return p;
1139 pci_dev_put(p);
1140 }
1141 }
1142 break;
1143 }
1144 return NULL;
1145 }
1146
1147 static bool check_hdmi_disabled(struct pci_dev *pci)
1148 {
1149 bool vga_inactive = false;
1150 struct pci_dev *p = get_bound_vga(pci);
1151
1152 if (p) {
1153 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1154 vga_inactive = true;
1155 pci_dev_put(p);
1156 }
1157 return vga_inactive;
1158 }
1159 #endif /* SUPPORT_VGA_SWITCHEROO */
1160
1161 /*
1162 * white/black-listing for position_fix
1163 */
1164 static struct snd_pci_quirk position_fix_list[] = {
1165 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1166 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1167 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1168 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1169 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1170 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1171 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1172 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1173 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1174 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1175 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1176 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1177 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1178 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1179 {}
1180 };
1181
1182 static int check_position_fix(struct azx *chip, int fix)
1183 {
1184 const struct snd_pci_quirk *q;
1185
1186 switch (fix) {
1187 case POS_FIX_AUTO:
1188 case POS_FIX_LPIB:
1189 case POS_FIX_POSBUF:
1190 case POS_FIX_VIACOMBO:
1191 case POS_FIX_COMBO:
1192 return fix;
1193 }
1194
1195 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1196 if (q) {
1197 dev_info(chip->card->dev,
1198 "position_fix set to %d for device %04x:%04x\n",
1199 q->value, q->subvendor, q->subdevice);
1200 return q->value;
1201 }
1202
1203 /* Check VIA/ATI HD Audio Controller exist */
1204 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1205 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1206 return POS_FIX_VIACOMBO;
1207 }
1208 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1209 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1210 return POS_FIX_LPIB;
1211 }
1212 return POS_FIX_AUTO;
1213 }
1214
1215 static void assign_position_fix(struct azx *chip, int fix)
1216 {
1217 static azx_get_pos_callback_t callbacks[] = {
1218 [POS_FIX_AUTO] = NULL,
1219 [POS_FIX_LPIB] = azx_get_pos_lpib,
1220 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1221 [POS_FIX_VIACOMBO] = azx_via_get_position,
1222 [POS_FIX_COMBO] = azx_get_pos_lpib,
1223 };
1224
1225 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1226
1227 /* combo mode uses LPIB only for playback */
1228 if (fix == POS_FIX_COMBO)
1229 chip->get_position[1] = NULL;
1230
1231 if (fix == POS_FIX_POSBUF &&
1232 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1233 chip->get_delay[0] = chip->get_delay[1] =
1234 azx_get_delay_from_lpib;
1235 }
1236
1237 }
1238
1239 /*
1240 * black-lists for probe_mask
1241 */
1242 static struct snd_pci_quirk probe_mask_list[] = {
1243 /* Thinkpad often breaks the controller communication when accessing
1244 * to the non-working (or non-existing) modem codec slot.
1245 */
1246 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1247 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1248 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1249 /* broken BIOS */
1250 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1251 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1252 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1253 /* forced codec slots */
1254 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1255 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1256 /* WinFast VP200 H (Teradici) user reported broken communication */
1257 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1258 {}
1259 };
1260
1261 #define AZX_FORCE_CODEC_MASK 0x100
1262
1263 static void check_probe_mask(struct azx *chip, int dev)
1264 {
1265 const struct snd_pci_quirk *q;
1266
1267 chip->codec_probe_mask = probe_mask[dev];
1268 if (chip->codec_probe_mask == -1) {
1269 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1270 if (q) {
1271 dev_info(chip->card->dev,
1272 "probe_mask set to 0x%x for device %04x:%04x\n",
1273 q->value, q->subvendor, q->subdevice);
1274 chip->codec_probe_mask = q->value;
1275 }
1276 }
1277
1278 /* check forced option */
1279 if (chip->codec_probe_mask != -1 &&
1280 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1281 chip->codec_mask = chip->codec_probe_mask & 0xff;
1282 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1283 chip->codec_mask);
1284 }
1285 }
1286
1287 /*
1288 * white/black-list for enable_msi
1289 */
1290 static struct snd_pci_quirk msi_black_list[] = {
1291 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1292 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1293 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1294 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1295 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1296 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1297 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1298 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1299 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1300 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1301 {}
1302 };
1303
1304 static void check_msi(struct azx *chip)
1305 {
1306 const struct snd_pci_quirk *q;
1307
1308 if (enable_msi >= 0) {
1309 chip->msi = !!enable_msi;
1310 return;
1311 }
1312 chip->msi = 1; /* enable MSI as default */
1313 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1314 if (q) {
1315 dev_info(chip->card->dev,
1316 "msi for device %04x:%04x set to %d\n",
1317 q->subvendor, q->subdevice, q->value);
1318 chip->msi = q->value;
1319 return;
1320 }
1321
1322 /* NVidia chipsets seem to cause troubles with MSI */
1323 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1324 dev_info(chip->card->dev, "Disabling MSI\n");
1325 chip->msi = 0;
1326 }
1327 }
1328
1329 /* check the snoop mode availability */
1330 static void azx_check_snoop_available(struct azx *chip)
1331 {
1332 int snoop = hda_snoop;
1333
1334 if (snoop >= 0) {
1335 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1336 snoop ? "snoop" : "non-snoop");
1337 chip->snoop = snoop;
1338 return;
1339 }
1340
1341 snoop = true;
1342 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1343 chip->driver_type == AZX_DRIVER_VIA) {
1344 /* force to non-snoop mode for a new VIA controller
1345 * when BIOS is set
1346 */
1347 u8 val;
1348 pci_read_config_byte(chip->pci, 0x42, &val);
1349 if (!(val & 0x80) && chip->pci->revision == 0x30)
1350 snoop = false;
1351 }
1352
1353 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1354 snoop = false;
1355
1356 chip->snoop = snoop;
1357 if (!snoop)
1358 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1359 }
1360
1361 static void azx_probe_work(struct work_struct *work)
1362 {
1363 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1364 azx_probe_continue(&hda->chip);
1365 }
1366
1367 /*
1368 * constructor
1369 */
1370 static const struct hdac_io_ops pci_hda_io_ops;
1371 static const struct hda_controller_ops pci_hda_ops;
1372
1373 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1374 int dev, unsigned int driver_caps,
1375 struct azx **rchip)
1376 {
1377 static struct snd_device_ops ops = {
1378 .dev_free = azx_dev_free,
1379 };
1380 struct hda_intel *hda;
1381 struct azx *chip;
1382 int err;
1383
1384 *rchip = NULL;
1385
1386 err = pci_enable_device(pci);
1387 if (err < 0)
1388 return err;
1389
1390 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1391 if (!hda) {
1392 pci_disable_device(pci);
1393 return -ENOMEM;
1394 }
1395
1396 chip = &hda->chip;
1397 spin_lock_init(&chip->reg_lock);
1398 mutex_init(&chip->open_mutex);
1399 chip->card = card;
1400 chip->pci = pci;
1401 chip->ops = &pci_hda_ops;
1402 chip->io_ops = &pci_hda_io_ops;
1403 chip->irq = -1;
1404 chip->driver_caps = driver_caps;
1405 chip->driver_type = driver_caps & 0xff;
1406 check_msi(chip);
1407 chip->dev_index = dev;
1408 chip->jackpoll_ms = jackpoll_ms;
1409 INIT_LIST_HEAD(&chip->pcm_list);
1410 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1411 INIT_LIST_HEAD(&hda->list);
1412 init_vga_switcheroo(chip);
1413 init_completion(&hda->probe_wait);
1414
1415 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1416
1417 check_probe_mask(chip, dev);
1418
1419 chip->single_cmd = single_cmd;
1420 azx_check_snoop_available(chip);
1421
1422 if (bdl_pos_adj[dev] < 0) {
1423 switch (chip->driver_type) {
1424 case AZX_DRIVER_ICH:
1425 case AZX_DRIVER_PCH:
1426 bdl_pos_adj[dev] = 1;
1427 break;
1428 default:
1429 bdl_pos_adj[dev] = 32;
1430 break;
1431 }
1432 }
1433 chip->bdl_pos_adj = bdl_pos_adj;
1434
1435 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1436 if (err < 0) {
1437 dev_err(card->dev, "Error creating device [card]!\n");
1438 azx_free(chip);
1439 return err;
1440 }
1441
1442 /* continue probing in work context as may trigger request module */
1443 INIT_WORK(&hda->probe_work, azx_probe_work);
1444
1445 *rchip = chip;
1446
1447 return 0;
1448 }
1449
1450 static int azx_first_init(struct azx *chip)
1451 {
1452 int dev = chip->dev_index;
1453 struct pci_dev *pci = chip->pci;
1454 struct snd_card *card = chip->card;
1455 int err;
1456 unsigned short gcap;
1457 unsigned int dma_bits = 64;
1458
1459 #if BITS_PER_LONG != 64
1460 /* Fix up base address on ULI M5461 */
1461 if (chip->driver_type == AZX_DRIVER_ULI) {
1462 u16 tmp3;
1463 pci_read_config_word(pci, 0x40, &tmp3);
1464 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1465 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1466 }
1467 #endif
1468
1469 err = pci_request_regions(pci, "ICH HD audio");
1470 if (err < 0)
1471 return err;
1472 chip->region_requested = 1;
1473
1474 chip->addr = pci_resource_start(pci, 0);
1475 chip->remap_addr = pci_ioremap_bar(pci, 0);
1476 if (chip->remap_addr == NULL) {
1477 dev_err(card->dev, "ioremap error\n");
1478 return -ENXIO;
1479 }
1480
1481 if (chip->msi) {
1482 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1483 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1484 pci->no_64bit_msi = true;
1485 }
1486 if (pci_enable_msi(pci) < 0)
1487 chip->msi = 0;
1488 }
1489
1490 if (azx_acquire_irq(chip, 0) < 0)
1491 return -EBUSY;
1492
1493 pci_set_master(pci);
1494 synchronize_irq(chip->irq);
1495
1496 gcap = azx_readw(chip, GCAP);
1497 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1498
1499 /* AMD devices support 40 or 48bit DMA, take the safe one */
1500 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1501 dma_bits = 40;
1502
1503 /* disable SB600 64bit support for safety */
1504 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1505 struct pci_dev *p_smbus;
1506 dma_bits = 40;
1507 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1508 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1509 NULL);
1510 if (p_smbus) {
1511 if (p_smbus->revision < 0x30)
1512 gcap &= ~AZX_GCAP_64OK;
1513 pci_dev_put(p_smbus);
1514 }
1515 }
1516
1517 /* disable 64bit DMA address on some devices */
1518 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1519 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1520 gcap &= ~AZX_GCAP_64OK;
1521 }
1522
1523 /* disable buffer size rounding to 128-byte multiples if supported */
1524 if (align_buffer_size >= 0)
1525 chip->align_buffer_size = !!align_buffer_size;
1526 else {
1527 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1528 chip->align_buffer_size = 0;
1529 else
1530 chip->align_buffer_size = 1;
1531 }
1532
1533 /* allow 64bit DMA address if supported by H/W */
1534 if (!(gcap & AZX_GCAP_64OK))
1535 dma_bits = 32;
1536 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1537 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1538 } else {
1539 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1540 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1541 }
1542
1543 /* read number of streams from GCAP register instead of using
1544 * hardcoded value
1545 */
1546 chip->capture_streams = (gcap >> 8) & 0x0f;
1547 chip->playback_streams = (gcap >> 12) & 0x0f;
1548 if (!chip->playback_streams && !chip->capture_streams) {
1549 /* gcap didn't give any info, switching to old method */
1550
1551 switch (chip->driver_type) {
1552 case AZX_DRIVER_ULI:
1553 chip->playback_streams = ULI_NUM_PLAYBACK;
1554 chip->capture_streams = ULI_NUM_CAPTURE;
1555 break;
1556 case AZX_DRIVER_ATIHDMI:
1557 case AZX_DRIVER_ATIHDMI_NS:
1558 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1559 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1560 break;
1561 case AZX_DRIVER_GENERIC:
1562 default:
1563 chip->playback_streams = ICH6_NUM_PLAYBACK;
1564 chip->capture_streams = ICH6_NUM_CAPTURE;
1565 break;
1566 }
1567 }
1568 chip->capture_index_offset = 0;
1569 chip->playback_index_offset = chip->capture_streams;
1570 chip->num_streams = chip->playback_streams + chip->capture_streams;
1571
1572 err = azx_alloc_stream_pages(chip);
1573 if (err < 0)
1574 return err;
1575
1576 /* initialize streams */
1577 azx_init_stream(chip);
1578
1579 /* initialize chip */
1580 azx_init_pci(chip);
1581
1582 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1583 struct hda_intel *hda;
1584
1585 hda = container_of(chip, struct hda_intel, chip);
1586 haswell_set_bclk(hda);
1587 }
1588
1589 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1590
1591 /* codec detection */
1592 if (!chip->codec_mask) {
1593 dev_err(card->dev, "no codecs found!\n");
1594 return -ENODEV;
1595 }
1596
1597 strcpy(card->driver, "HDA-Intel");
1598 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1599 sizeof(card->shortname));
1600 snprintf(card->longname, sizeof(card->longname),
1601 "%s at 0x%lx irq %i",
1602 card->shortname, chip->addr, chip->irq);
1603
1604 return 0;
1605 }
1606
1607 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1608 /* callback from request_firmware_nowait() */
1609 static void azx_firmware_cb(const struct firmware *fw, void *context)
1610 {
1611 struct snd_card *card = context;
1612 struct azx *chip = card->private_data;
1613 struct pci_dev *pci = chip->pci;
1614
1615 if (!fw) {
1616 dev_err(card->dev, "Cannot load firmware, aborting\n");
1617 goto error;
1618 }
1619
1620 chip->fw = fw;
1621 if (!chip->disabled) {
1622 /* continue probing */
1623 if (azx_probe_continue(chip))
1624 goto error;
1625 }
1626 return; /* OK */
1627
1628 error:
1629 snd_card_free(card);
1630 pci_set_drvdata(pci, NULL);
1631 }
1632 #endif
1633
1634 /*
1635 * HDA controller ops.
1636 */
1637
1638 /* PCI register access. */
1639 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1640 {
1641 writel(value, addr);
1642 }
1643
1644 static u32 pci_azx_readl(u32 __iomem *addr)
1645 {
1646 return readl(addr);
1647 }
1648
1649 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1650 {
1651 writew(value, addr);
1652 }
1653
1654 static u16 pci_azx_readw(u16 __iomem *addr)
1655 {
1656 return readw(addr);
1657 }
1658
1659 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1660 {
1661 writeb(value, addr);
1662 }
1663
1664 static u8 pci_azx_readb(u8 __iomem *addr)
1665 {
1666 return readb(addr);
1667 }
1668
1669 static int disable_msi_reset_irq(struct azx *chip)
1670 {
1671 int err;
1672
1673 free_irq(chip->irq, chip);
1674 chip->irq = -1;
1675 pci_disable_msi(chip->pci);
1676 chip->msi = 0;
1677 err = azx_acquire_irq(chip, 1);
1678 if (err < 0)
1679 return err;
1680
1681 return 0;
1682 }
1683
1684 /* DMA page allocation helpers. */
1685 static int dma_alloc_pages(struct hdac_bus *bus,
1686 int type,
1687 size_t size,
1688 struct snd_dma_buffer *buf)
1689 {
1690 struct azx *chip = to_hda_bus(bus)->private_data;
1691 int err;
1692
1693 err = snd_dma_alloc_pages(type,
1694 bus->dev,
1695 size, buf);
1696 if (err < 0)
1697 return err;
1698 mark_pages_wc(chip, buf, true);
1699 return 0;
1700 }
1701
1702 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1703 {
1704 struct azx *chip = to_hda_bus(bus)->private_data;
1705
1706 mark_pages_wc(chip, buf, false);
1707 snd_dma_free_pages(buf);
1708 }
1709
1710 static int substream_alloc_pages(struct azx *chip,
1711 struct snd_pcm_substream *substream,
1712 size_t size)
1713 {
1714 struct azx_dev *azx_dev = get_azx_dev(substream);
1715 int ret;
1716
1717 mark_runtime_wc(chip, azx_dev, substream, false);
1718 azx_dev->core.bufsize = 0;
1719 azx_dev->core.period_bytes = 0;
1720 azx_dev->core.format_val = 0;
1721 ret = snd_pcm_lib_malloc_pages(substream, size);
1722 if (ret < 0)
1723 return ret;
1724 mark_runtime_wc(chip, azx_dev, substream, true);
1725 return 0;
1726 }
1727
1728 static int substream_free_pages(struct azx *chip,
1729 struct snd_pcm_substream *substream)
1730 {
1731 struct azx_dev *azx_dev = get_azx_dev(substream);
1732 mark_runtime_wc(chip, azx_dev, substream, false);
1733 return snd_pcm_lib_free_pages(substream);
1734 }
1735
1736 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1737 struct vm_area_struct *area)
1738 {
1739 #ifdef CONFIG_X86
1740 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1741 struct azx *chip = apcm->chip;
1742 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1743 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1744 #endif
1745 }
1746
1747 static const struct hdac_io_ops pci_hda_io_ops = {
1748 .reg_writel = pci_azx_writel,
1749 .reg_readl = pci_azx_readl,
1750 .reg_writew = pci_azx_writew,
1751 .reg_readw = pci_azx_readw,
1752 .reg_writeb = pci_azx_writeb,
1753 .reg_readb = pci_azx_readb,
1754 .dma_alloc_pages = dma_alloc_pages,
1755 .dma_free_pages = dma_free_pages,
1756 };
1757
1758 static const struct hda_controller_ops pci_hda_ops = {
1759 .disable_msi_reset_irq = disable_msi_reset_irq,
1760 .substream_alloc_pages = substream_alloc_pages,
1761 .substream_free_pages = substream_free_pages,
1762 .pcm_mmap_prepare = pcm_mmap_prepare,
1763 .position_check = azx_position_check,
1764 };
1765
1766 static int azx_probe(struct pci_dev *pci,
1767 const struct pci_device_id *pci_id)
1768 {
1769 static int dev;
1770 struct snd_card *card;
1771 struct hda_intel *hda;
1772 struct azx *chip;
1773 bool schedule_probe;
1774 int err;
1775
1776 if (dev >= SNDRV_CARDS)
1777 return -ENODEV;
1778 if (!enable[dev]) {
1779 dev++;
1780 return -ENOENT;
1781 }
1782
1783 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1784 0, &card);
1785 if (err < 0) {
1786 dev_err(&pci->dev, "Error creating card!\n");
1787 return err;
1788 }
1789
1790 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1791 if (err < 0)
1792 goto out_free;
1793 card->private_data = chip;
1794 hda = container_of(chip, struct hda_intel, chip);
1795
1796 pci_set_drvdata(pci, card);
1797
1798 err = register_vga_switcheroo(chip);
1799 if (err < 0) {
1800 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1801 goto out_free;
1802 }
1803
1804 if (check_hdmi_disabled(pci)) {
1805 dev_info(card->dev, "VGA controller is disabled\n");
1806 dev_info(card->dev, "Delaying initialization\n");
1807 chip->disabled = true;
1808 }
1809
1810 schedule_probe = !chip->disabled;
1811
1812 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1813 if (patch[dev] && *patch[dev]) {
1814 dev_info(card->dev, "Applying patch firmware '%s'\n",
1815 patch[dev]);
1816 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1817 &pci->dev, GFP_KERNEL, card,
1818 azx_firmware_cb);
1819 if (err < 0)
1820 goto out_free;
1821 schedule_probe = false; /* continued in azx_firmware_cb() */
1822 }
1823 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1824
1825 #ifndef CONFIG_SND_HDA_I915
1826 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1827 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1828 #endif
1829
1830 if (schedule_probe)
1831 schedule_work(&hda->probe_work);
1832
1833 dev++;
1834 if (chip->disabled)
1835 complete_all(&hda->probe_wait);
1836 return 0;
1837
1838 out_free:
1839 snd_card_free(card);
1840 return err;
1841 }
1842
1843 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1844 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1845 [AZX_DRIVER_NVIDIA] = 8,
1846 [AZX_DRIVER_TERA] = 1,
1847 };
1848
1849 static int azx_probe_continue(struct azx *chip)
1850 {
1851 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1852 struct pci_dev *pci = chip->pci;
1853 int dev = chip->dev_index;
1854 int err;
1855
1856 /* Request power well for Haswell HDA controller and codec */
1857 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1858 #ifdef CONFIG_SND_HDA_I915
1859 err = hda_i915_init(hda);
1860 if (err < 0)
1861 goto out_free;
1862 err = hda_display_power(hda, true);
1863 if (err < 0) {
1864 dev_err(chip->card->dev,
1865 "Cannot turn on display power on i915\n");
1866 goto out_free;
1867 }
1868 #endif
1869 }
1870
1871 err = azx_bus_create(chip, model[dev]);
1872 if (err < 0)
1873 goto out_free;
1874
1875 err = azx_first_init(chip);
1876 if (err < 0)
1877 goto out_free;
1878
1879 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1880 chip->beep_mode = beep_mode[dev];
1881 #endif
1882
1883 /* create codec instances */
1884 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
1885 if (err < 0)
1886 goto out_free;
1887
1888 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1889 if (chip->fw) {
1890 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1891 chip->fw->data);
1892 if (err < 0)
1893 goto out_free;
1894 #ifndef CONFIG_PM
1895 release_firmware(chip->fw); /* no longer needed */
1896 chip->fw = NULL;
1897 #endif
1898 }
1899 #endif
1900 if ((probe_only[dev] & 1) == 0) {
1901 err = azx_codec_configure(chip);
1902 if (err < 0)
1903 goto out_free;
1904 }
1905
1906 err = snd_card_register(chip->card);
1907 if (err < 0)
1908 goto out_free;
1909
1910 chip->running = 1;
1911 azx_add_card_list(chip);
1912 snd_hda_set_power_save(chip->bus, power_save * 1000);
1913 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
1914 pm_runtime_put_noidle(&pci->dev);
1915
1916 out_free:
1917 if (err < 0)
1918 hda->init_failed = 1;
1919 complete_all(&hda->probe_wait);
1920 return err;
1921 }
1922
1923 static void azx_remove(struct pci_dev *pci)
1924 {
1925 struct snd_card *card = pci_get_drvdata(pci);
1926
1927 if (card)
1928 snd_card_free(card);
1929 }
1930
1931 static void azx_shutdown(struct pci_dev *pci)
1932 {
1933 struct snd_card *card = pci_get_drvdata(pci);
1934 struct azx *chip;
1935
1936 if (!card)
1937 return;
1938 chip = card->private_data;
1939 if (chip && chip->running)
1940 azx_stop_chip(chip);
1941 }
1942
1943 /* PCI IDs */
1944 static const struct pci_device_id azx_ids[] = {
1945 /* CPT */
1946 { PCI_DEVICE(0x8086, 0x1c20),
1947 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1948 /* PBG */
1949 { PCI_DEVICE(0x8086, 0x1d20),
1950 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1951 /* Panther Point */
1952 { PCI_DEVICE(0x8086, 0x1e20),
1953 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1954 /* Lynx Point */
1955 { PCI_DEVICE(0x8086, 0x8c20),
1956 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1957 /* 9 Series */
1958 { PCI_DEVICE(0x8086, 0x8ca0),
1959 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1960 /* Wellsburg */
1961 { PCI_DEVICE(0x8086, 0x8d20),
1962 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1963 { PCI_DEVICE(0x8086, 0x8d21),
1964 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1965 /* Lynx Point-LP */
1966 { PCI_DEVICE(0x8086, 0x9c20),
1967 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1968 /* Lynx Point-LP */
1969 { PCI_DEVICE(0x8086, 0x9c21),
1970 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1971 /* Wildcat Point-LP */
1972 { PCI_DEVICE(0x8086, 0x9ca0),
1973 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1974 /* Sunrise Point */
1975 { PCI_DEVICE(0x8086, 0xa170),
1976 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
1977 /* Sunrise Point-LP */
1978 { PCI_DEVICE(0x8086, 0x9d70),
1979 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
1980 /* Haswell */
1981 { PCI_DEVICE(0x8086, 0x0a0c),
1982 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1983 { PCI_DEVICE(0x8086, 0x0c0c),
1984 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1985 { PCI_DEVICE(0x8086, 0x0d0c),
1986 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
1987 /* Broadwell */
1988 { PCI_DEVICE(0x8086, 0x160c),
1989 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
1990 /* 5 Series/3400 */
1991 { PCI_DEVICE(0x8086, 0x3b56),
1992 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1993 /* Poulsbo */
1994 { PCI_DEVICE(0x8086, 0x811b),
1995 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1996 /* Oaktrail */
1997 { PCI_DEVICE(0x8086, 0x080a),
1998 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
1999 /* BayTrail */
2000 { PCI_DEVICE(0x8086, 0x0f04),
2001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2002 /* Braswell */
2003 { PCI_DEVICE(0x8086, 0x2284),
2004 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2005 /* ICH6 */
2006 { PCI_DEVICE(0x8086, 0x2668),
2007 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2008 /* ICH7 */
2009 { PCI_DEVICE(0x8086, 0x27d8),
2010 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2011 /* ESB2 */
2012 { PCI_DEVICE(0x8086, 0x269a),
2013 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2014 /* ICH8 */
2015 { PCI_DEVICE(0x8086, 0x284b),
2016 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2017 /* ICH9 */
2018 { PCI_DEVICE(0x8086, 0x293e),
2019 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2020 /* ICH9 */
2021 { PCI_DEVICE(0x8086, 0x293f),
2022 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2023 /* ICH10 */
2024 { PCI_DEVICE(0x8086, 0x3a3e),
2025 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2026 /* ICH10 */
2027 { PCI_DEVICE(0x8086, 0x3a6e),
2028 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2029 /* Generic Intel */
2030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2031 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2032 .class_mask = 0xffffff,
2033 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2034 /* ATI SB 450/600/700/800/900 */
2035 { PCI_DEVICE(0x1002, 0x437b),
2036 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2037 { PCI_DEVICE(0x1002, 0x4383),
2038 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2039 /* AMD Hudson */
2040 { PCI_DEVICE(0x1022, 0x780d),
2041 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2042 /* ATI HDMI */
2043 { PCI_DEVICE(0x1002, 0x793b),
2044 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2045 { PCI_DEVICE(0x1002, 0x7919),
2046 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2047 { PCI_DEVICE(0x1002, 0x960f),
2048 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2049 { PCI_DEVICE(0x1002, 0x970f),
2050 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2051 { PCI_DEVICE(0x1002, 0xaa00),
2052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2053 { PCI_DEVICE(0x1002, 0xaa08),
2054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2055 { PCI_DEVICE(0x1002, 0xaa10),
2056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2057 { PCI_DEVICE(0x1002, 0xaa18),
2058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2059 { PCI_DEVICE(0x1002, 0xaa20),
2060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2061 { PCI_DEVICE(0x1002, 0xaa28),
2062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2063 { PCI_DEVICE(0x1002, 0xaa30),
2064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2065 { PCI_DEVICE(0x1002, 0xaa38),
2066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2067 { PCI_DEVICE(0x1002, 0xaa40),
2068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2069 { PCI_DEVICE(0x1002, 0xaa48),
2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2071 { PCI_DEVICE(0x1002, 0xaa50),
2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2073 { PCI_DEVICE(0x1002, 0xaa58),
2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2075 { PCI_DEVICE(0x1002, 0xaa60),
2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2077 { PCI_DEVICE(0x1002, 0xaa68),
2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2079 { PCI_DEVICE(0x1002, 0xaa80),
2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2081 { PCI_DEVICE(0x1002, 0xaa88),
2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2083 { PCI_DEVICE(0x1002, 0xaa90),
2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2085 { PCI_DEVICE(0x1002, 0xaa98),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0x9902),
2088 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2089 { PCI_DEVICE(0x1002, 0xaaa0),
2090 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2091 { PCI_DEVICE(0x1002, 0xaaa8),
2092 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2093 { PCI_DEVICE(0x1002, 0xaab0),
2094 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2095 /* VIA VT8251/VT8237A */
2096 { PCI_DEVICE(0x1106, 0x3288),
2097 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2098 /* VIA GFX VT7122/VX900 */
2099 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2100 /* VIA GFX VT6122/VX11 */
2101 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2102 /* SIS966 */
2103 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2104 /* ULI M5461 */
2105 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2106 /* NVIDIA MCP */
2107 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2108 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2109 .class_mask = 0xffffff,
2110 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2111 /* Teradici */
2112 { PCI_DEVICE(0x6549, 0x1200),
2113 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2114 { PCI_DEVICE(0x6549, 0x2200),
2115 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2116 /* Creative X-Fi (CA0110-IBG) */
2117 /* CTHDA chips */
2118 { PCI_DEVICE(0x1102, 0x0010),
2119 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2120 { PCI_DEVICE(0x1102, 0x0012),
2121 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2122 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2123 /* the following entry conflicts with snd-ctxfi driver,
2124 * as ctxfi driver mutates from HD-audio to native mode with
2125 * a special command sequence.
2126 */
2127 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2128 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2129 .class_mask = 0xffffff,
2130 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2131 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2132 #else
2133 /* this entry seems still valid -- i.e. without emu20kx chip */
2134 { PCI_DEVICE(0x1102, 0x0009),
2135 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2136 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2137 #endif
2138 /* CM8888 */
2139 { PCI_DEVICE(0x13f6, 0x5011),
2140 .driver_data = AZX_DRIVER_CMEDIA |
2141 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2142 /* Vortex86MX */
2143 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2144 /* VMware HDAudio */
2145 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2146 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2147 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2148 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2149 .class_mask = 0xffffff,
2150 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2151 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2152 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2153 .class_mask = 0xffffff,
2154 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2155 { 0, }
2156 };
2157 MODULE_DEVICE_TABLE(pci, azx_ids);
2158
2159 /* pci_driver definition */
2160 static struct pci_driver azx_driver = {
2161 .name = KBUILD_MODNAME,
2162 .id_table = azx_ids,
2163 .probe = azx_probe,
2164 .remove = azx_remove,
2165 .shutdown = azx_shutdown,
2166 .driver = {
2167 .pm = AZX_PM_OPS,
2168 },
2169 };
2170
2171 module_pci_driver(azx_driver);
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