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ASoC: wm8994: mark expected switch fall-throughs
[mirror_ubuntu-bionic-kernel.git] / sound / soc / codecs / pcm512x.c
1 /*
2 * Driver for the PCM512x CODECs
3 *
4 * Author: Mark Brown <broonie@linaro.org>
5 * Copyright 2014 Linaro Ltd
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 */
16
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/clk.h>
21 #include <linux/kernel.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/gcd.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/tlv.h>
30
31 #include "pcm512x.h"
32
33 #define PCM512x_NUM_SUPPLIES 3
34 static const char * const pcm512x_supply_names[PCM512x_NUM_SUPPLIES] = {
35 "AVDD",
36 "DVDD",
37 "CPVDD",
38 };
39
40 struct pcm512x_priv {
41 struct regmap *regmap;
42 struct clk *sclk;
43 struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
44 struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
45 int fmt;
46 int pll_in;
47 int pll_out;
48 int pll_r;
49 int pll_j;
50 int pll_d;
51 int pll_p;
52 unsigned long real_pll;
53 unsigned long overclock_pll;
54 unsigned long overclock_dac;
55 unsigned long overclock_dsp;
56 };
57
58 /*
59 * We can't use the same notifier block for more than one supply and
60 * there's no way I can see to get from a callback to the caller
61 * except container_of().
62 */
63 #define PCM512x_REGULATOR_EVENT(n) \
64 static int pcm512x_regulator_event_##n(struct notifier_block *nb, \
65 unsigned long event, void *data) \
66 { \
67 struct pcm512x_priv *pcm512x = container_of(nb, struct pcm512x_priv, \
68 supply_nb[n]); \
69 if (event & REGULATOR_EVENT_DISABLE) { \
70 regcache_mark_dirty(pcm512x->regmap); \
71 regcache_cache_only(pcm512x->regmap, true); \
72 } \
73 return 0; \
74 }
75
76 PCM512x_REGULATOR_EVENT(0)
77 PCM512x_REGULATOR_EVENT(1)
78 PCM512x_REGULATOR_EVENT(2)
79
80 static const struct reg_default pcm512x_reg_defaults[] = {
81 { PCM512x_RESET, 0x00 },
82 { PCM512x_POWER, 0x00 },
83 { PCM512x_MUTE, 0x00 },
84 { PCM512x_DSP, 0x00 },
85 { PCM512x_PLL_REF, 0x00 },
86 { PCM512x_DAC_REF, 0x00 },
87 { PCM512x_DAC_ROUTING, 0x11 },
88 { PCM512x_DSP_PROGRAM, 0x01 },
89 { PCM512x_CLKDET, 0x00 },
90 { PCM512x_AUTO_MUTE, 0x00 },
91 { PCM512x_ERROR_DETECT, 0x00 },
92 { PCM512x_DIGITAL_VOLUME_1, 0x00 },
93 { PCM512x_DIGITAL_VOLUME_2, 0x30 },
94 { PCM512x_DIGITAL_VOLUME_3, 0x30 },
95 { PCM512x_DIGITAL_MUTE_1, 0x22 },
96 { PCM512x_DIGITAL_MUTE_2, 0x00 },
97 { PCM512x_DIGITAL_MUTE_3, 0x07 },
98 { PCM512x_OUTPUT_AMPLITUDE, 0x00 },
99 { PCM512x_ANALOG_GAIN_CTRL, 0x00 },
100 { PCM512x_UNDERVOLTAGE_PROT, 0x00 },
101 { PCM512x_ANALOG_MUTE_CTRL, 0x00 },
102 { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
103 { PCM512x_VCOM_CTRL_1, 0x00 },
104 { PCM512x_VCOM_CTRL_2, 0x01 },
105 { PCM512x_BCLK_LRCLK_CFG, 0x00 },
106 { PCM512x_MASTER_MODE, 0x7c },
107 { PCM512x_GPIO_DACIN, 0x00 },
108 { PCM512x_GPIO_PLLIN, 0x00 },
109 { PCM512x_SYNCHRONIZE, 0x10 },
110 { PCM512x_PLL_COEFF_0, 0x00 },
111 { PCM512x_PLL_COEFF_1, 0x00 },
112 { PCM512x_PLL_COEFF_2, 0x00 },
113 { PCM512x_PLL_COEFF_3, 0x00 },
114 { PCM512x_PLL_COEFF_4, 0x00 },
115 { PCM512x_DSP_CLKDIV, 0x00 },
116 { PCM512x_DAC_CLKDIV, 0x00 },
117 { PCM512x_NCP_CLKDIV, 0x00 },
118 { PCM512x_OSR_CLKDIV, 0x00 },
119 { PCM512x_MASTER_CLKDIV_1, 0x00 },
120 { PCM512x_MASTER_CLKDIV_2, 0x00 },
121 { PCM512x_FS_SPEED_MODE, 0x00 },
122 { PCM512x_IDAC_1, 0x01 },
123 { PCM512x_IDAC_2, 0x00 },
124 };
125
126 static bool pcm512x_readable(struct device *dev, unsigned int reg)
127 {
128 switch (reg) {
129 case PCM512x_RESET:
130 case PCM512x_POWER:
131 case PCM512x_MUTE:
132 case PCM512x_PLL_EN:
133 case PCM512x_SPI_MISO_FUNCTION:
134 case PCM512x_DSP:
135 case PCM512x_GPIO_EN:
136 case PCM512x_BCLK_LRCLK_CFG:
137 case PCM512x_DSP_GPIO_INPUT:
138 case PCM512x_MASTER_MODE:
139 case PCM512x_PLL_REF:
140 case PCM512x_DAC_REF:
141 case PCM512x_GPIO_DACIN:
142 case PCM512x_GPIO_PLLIN:
143 case PCM512x_SYNCHRONIZE:
144 case PCM512x_PLL_COEFF_0:
145 case PCM512x_PLL_COEFF_1:
146 case PCM512x_PLL_COEFF_2:
147 case PCM512x_PLL_COEFF_3:
148 case PCM512x_PLL_COEFF_4:
149 case PCM512x_DSP_CLKDIV:
150 case PCM512x_DAC_CLKDIV:
151 case PCM512x_NCP_CLKDIV:
152 case PCM512x_OSR_CLKDIV:
153 case PCM512x_MASTER_CLKDIV_1:
154 case PCM512x_MASTER_CLKDIV_2:
155 case PCM512x_FS_SPEED_MODE:
156 case PCM512x_IDAC_1:
157 case PCM512x_IDAC_2:
158 case PCM512x_ERROR_DETECT:
159 case PCM512x_I2S_1:
160 case PCM512x_I2S_2:
161 case PCM512x_DAC_ROUTING:
162 case PCM512x_DSP_PROGRAM:
163 case PCM512x_CLKDET:
164 case PCM512x_AUTO_MUTE:
165 case PCM512x_DIGITAL_VOLUME_1:
166 case PCM512x_DIGITAL_VOLUME_2:
167 case PCM512x_DIGITAL_VOLUME_3:
168 case PCM512x_DIGITAL_MUTE_1:
169 case PCM512x_DIGITAL_MUTE_2:
170 case PCM512x_DIGITAL_MUTE_3:
171 case PCM512x_GPIO_OUTPUT_1:
172 case PCM512x_GPIO_OUTPUT_2:
173 case PCM512x_GPIO_OUTPUT_3:
174 case PCM512x_GPIO_OUTPUT_4:
175 case PCM512x_GPIO_OUTPUT_5:
176 case PCM512x_GPIO_OUTPUT_6:
177 case PCM512x_GPIO_CONTROL_1:
178 case PCM512x_GPIO_CONTROL_2:
179 case PCM512x_OVERFLOW:
180 case PCM512x_RATE_DET_1:
181 case PCM512x_RATE_DET_2:
182 case PCM512x_RATE_DET_3:
183 case PCM512x_RATE_DET_4:
184 case PCM512x_CLOCK_STATUS:
185 case PCM512x_ANALOG_MUTE_DET:
186 case PCM512x_GPIN:
187 case PCM512x_DIGITAL_MUTE_DET:
188 case PCM512x_OUTPUT_AMPLITUDE:
189 case PCM512x_ANALOG_GAIN_CTRL:
190 case PCM512x_UNDERVOLTAGE_PROT:
191 case PCM512x_ANALOG_MUTE_CTRL:
192 case PCM512x_ANALOG_GAIN_BOOST:
193 case PCM512x_VCOM_CTRL_1:
194 case PCM512x_VCOM_CTRL_2:
195 case PCM512x_CRAM_CTRL:
196 case PCM512x_FLEX_A:
197 case PCM512x_FLEX_B:
198 return true;
199 default:
200 /* There are 256 raw register addresses */
201 return reg < 0xff;
202 }
203 }
204
205 static bool pcm512x_volatile(struct device *dev, unsigned int reg)
206 {
207 switch (reg) {
208 case PCM512x_PLL_EN:
209 case PCM512x_OVERFLOW:
210 case PCM512x_RATE_DET_1:
211 case PCM512x_RATE_DET_2:
212 case PCM512x_RATE_DET_3:
213 case PCM512x_RATE_DET_4:
214 case PCM512x_CLOCK_STATUS:
215 case PCM512x_ANALOG_MUTE_DET:
216 case PCM512x_GPIN:
217 case PCM512x_DIGITAL_MUTE_DET:
218 case PCM512x_CRAM_CTRL:
219 return true;
220 default:
221 /* There are 256 raw register addresses */
222 return reg < 0xff;
223 }
224 }
225
226 static int pcm512x_overclock_pll_get(struct snd_kcontrol *kcontrol,
227 struct snd_ctl_elem_value *ucontrol)
228 {
229 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
230 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
231
232 ucontrol->value.integer.value[0] = pcm512x->overclock_pll;
233 return 0;
234 }
235
236 static int pcm512x_overclock_pll_put(struct snd_kcontrol *kcontrol,
237 struct snd_ctl_elem_value *ucontrol)
238 {
239 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
240 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
241
242 switch (snd_soc_codec_get_bias_level(codec)) {
243 case SND_SOC_BIAS_OFF:
244 case SND_SOC_BIAS_STANDBY:
245 break;
246 default:
247 return -EBUSY;
248 }
249
250 pcm512x->overclock_pll = ucontrol->value.integer.value[0];
251 return 0;
252 }
253
254 static int pcm512x_overclock_dsp_get(struct snd_kcontrol *kcontrol,
255 struct snd_ctl_elem_value *ucontrol)
256 {
257 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
258 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
259
260 ucontrol->value.integer.value[0] = pcm512x->overclock_dsp;
261 return 0;
262 }
263
264 static int pcm512x_overclock_dsp_put(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266 {
267 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
268 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
269
270 switch (snd_soc_codec_get_bias_level(codec)) {
271 case SND_SOC_BIAS_OFF:
272 case SND_SOC_BIAS_STANDBY:
273 break;
274 default:
275 return -EBUSY;
276 }
277
278 pcm512x->overclock_dsp = ucontrol->value.integer.value[0];
279 return 0;
280 }
281
282 static int pcm512x_overclock_dac_get(struct snd_kcontrol *kcontrol,
283 struct snd_ctl_elem_value *ucontrol)
284 {
285 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
286 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
287
288 ucontrol->value.integer.value[0] = pcm512x->overclock_dac;
289 return 0;
290 }
291
292 static int pcm512x_overclock_dac_put(struct snd_kcontrol *kcontrol,
293 struct snd_ctl_elem_value *ucontrol)
294 {
295 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
296 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
297
298 switch (snd_soc_codec_get_bias_level(codec)) {
299 case SND_SOC_BIAS_OFF:
300 case SND_SOC_BIAS_STANDBY:
301 break;
302 default:
303 return -EBUSY;
304 }
305
306 pcm512x->overclock_dac = ucontrol->value.integer.value[0];
307 return 0;
308 }
309
310 static const DECLARE_TLV_DB_SCALE(digital_tlv, -10350, 50, 1);
311 static const DECLARE_TLV_DB_SCALE(analog_tlv, -600, 600, 0);
312 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 80, 0);
313
314 static const char * const pcm512x_dsp_program_texts[] = {
315 "FIR interpolation with de-emphasis",
316 "Low latency IIR with de-emphasis",
317 "High attenuation with de-emphasis",
318 "Fixed process flow",
319 "Ringing-less low latency FIR",
320 };
321
322 static const unsigned int pcm512x_dsp_program_values[] = {
323 1,
324 2,
325 3,
326 5,
327 7,
328 };
329
330 static SOC_VALUE_ENUM_SINGLE_DECL(pcm512x_dsp_program,
331 PCM512x_DSP_PROGRAM, 0, 0x1f,
332 pcm512x_dsp_program_texts,
333 pcm512x_dsp_program_values);
334
335 static const char * const pcm512x_clk_missing_text[] = {
336 "1s", "2s", "3s", "4s", "5s", "6s", "7s", "8s"
337 };
338
339 static const struct soc_enum pcm512x_clk_missing =
340 SOC_ENUM_SINGLE(PCM512x_CLKDET, 0, 8, pcm512x_clk_missing_text);
341
342 static const char * const pcm512x_autom_text[] = {
343 "21ms", "106ms", "213ms", "533ms", "1.07s", "2.13s", "5.33s", "10.66s"
344 };
345
346 static const struct soc_enum pcm512x_autom_l =
347 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATML_SHIFT, 8,
348 pcm512x_autom_text);
349
350 static const struct soc_enum pcm512x_autom_r =
351 SOC_ENUM_SINGLE(PCM512x_AUTO_MUTE, PCM512x_ATMR_SHIFT, 8,
352 pcm512x_autom_text);
353
354 static const char * const pcm512x_ramp_rate_text[] = {
355 "1 sample/update", "2 samples/update", "4 samples/update",
356 "Immediate"
357 };
358
359 static const struct soc_enum pcm512x_vndf =
360 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDF_SHIFT, 4,
361 pcm512x_ramp_rate_text);
362
363 static const struct soc_enum pcm512x_vnuf =
364 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUF_SHIFT, 4,
365 pcm512x_ramp_rate_text);
366
367 static const struct soc_enum pcm512x_vedf =
368 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDF_SHIFT, 4,
369 pcm512x_ramp_rate_text);
370
371 static const char * const pcm512x_ramp_step_text[] = {
372 "4dB/step", "2dB/step", "1dB/step", "0.5dB/step"
373 };
374
375 static const struct soc_enum pcm512x_vnds =
376 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNDS_SHIFT, 4,
377 pcm512x_ramp_step_text);
378
379 static const struct soc_enum pcm512x_vnus =
380 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_1, PCM512x_VNUS_SHIFT, 4,
381 pcm512x_ramp_step_text);
382
383 static const struct soc_enum pcm512x_veds =
384 SOC_ENUM_SINGLE(PCM512x_DIGITAL_MUTE_2, PCM512x_VEDS_SHIFT, 4,
385 pcm512x_ramp_step_text);
386
387 static const struct snd_kcontrol_new pcm512x_controls[] = {
388 SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2,
389 PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv),
390 SOC_DOUBLE_TLV("Analogue Playback Volume", PCM512x_ANALOG_GAIN_CTRL,
391 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv),
392 SOC_DOUBLE_TLV("Analogue Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST,
393 PCM512x_AGBL_SHIFT, PCM512x_AGBR_SHIFT, 1, 0, boost_tlv),
394 SOC_DOUBLE("Digital Playback Switch", PCM512x_MUTE, PCM512x_RQML_SHIFT,
395 PCM512x_RQMR_SHIFT, 1, 1),
396
397 SOC_SINGLE("Deemphasis Switch", PCM512x_DSP, PCM512x_DEMP_SHIFT, 1, 1),
398 SOC_ENUM("DSP Program", pcm512x_dsp_program),
399
400 SOC_ENUM("Clock Missing Period", pcm512x_clk_missing),
401 SOC_ENUM("Auto Mute Time Left", pcm512x_autom_l),
402 SOC_ENUM("Auto Mute Time Right", pcm512x_autom_r),
403 SOC_SINGLE("Auto Mute Mono Switch", PCM512x_DIGITAL_MUTE_3,
404 PCM512x_ACTL_SHIFT, 1, 0),
405 SOC_DOUBLE("Auto Mute Switch", PCM512x_DIGITAL_MUTE_3, PCM512x_AMLE_SHIFT,
406 PCM512x_AMRE_SHIFT, 1, 0),
407
408 SOC_ENUM("Volume Ramp Down Rate", pcm512x_vndf),
409 SOC_ENUM("Volume Ramp Down Step", pcm512x_vnds),
410 SOC_ENUM("Volume Ramp Up Rate", pcm512x_vnuf),
411 SOC_ENUM("Volume Ramp Up Step", pcm512x_vnus),
412 SOC_ENUM("Volume Ramp Down Emergency Rate", pcm512x_vedf),
413 SOC_ENUM("Volume Ramp Down Emergency Step", pcm512x_veds),
414
415 SOC_SINGLE_EXT("Max Overclock PLL", SND_SOC_NOPM, 0, 20, 0,
416 pcm512x_overclock_pll_get, pcm512x_overclock_pll_put),
417 SOC_SINGLE_EXT("Max Overclock DSP", SND_SOC_NOPM, 0, 40, 0,
418 pcm512x_overclock_dsp_get, pcm512x_overclock_dsp_put),
419 SOC_SINGLE_EXT("Max Overclock DAC", SND_SOC_NOPM, 0, 40, 0,
420 pcm512x_overclock_dac_get, pcm512x_overclock_dac_put),
421 };
422
423 static const struct snd_soc_dapm_widget pcm512x_dapm_widgets[] = {
424 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
425 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
426
427 SND_SOC_DAPM_OUTPUT("OUTL"),
428 SND_SOC_DAPM_OUTPUT("OUTR"),
429 };
430
431 static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
432 { "DACL", NULL, "Playback" },
433 { "DACR", NULL, "Playback" },
434
435 { "OUTL", NULL, "DACL" },
436 { "OUTR", NULL, "DACR" },
437 };
438
439 static unsigned long pcm512x_pll_max(struct pcm512x_priv *pcm512x)
440 {
441 return 25000000 + 25000000 * pcm512x->overclock_pll / 100;
442 }
443
444 static unsigned long pcm512x_dsp_max(struct pcm512x_priv *pcm512x)
445 {
446 return 50000000 + 50000000 * pcm512x->overclock_dsp / 100;
447 }
448
449 static unsigned long pcm512x_dac_max(struct pcm512x_priv *pcm512x,
450 unsigned long rate)
451 {
452 return rate + rate * pcm512x->overclock_dac / 100;
453 }
454
455 static unsigned long pcm512x_sck_max(struct pcm512x_priv *pcm512x)
456 {
457 if (!pcm512x->pll_out)
458 return 25000000;
459 return pcm512x_pll_max(pcm512x);
460 }
461
462 static unsigned long pcm512x_ncp_target(struct pcm512x_priv *pcm512x,
463 unsigned long dac_rate)
464 {
465 /*
466 * If the DAC is not actually overclocked, use the good old
467 * NCP target rate...
468 */
469 if (dac_rate <= 6144000)
470 return 1536000;
471 /*
472 * ...but if the DAC is in fact overclocked, bump the NCP target
473 * rate to get the recommended dividers even when overclocking.
474 */
475 return pcm512x_dac_max(pcm512x, 1536000);
476 }
477
478 static const u32 pcm512x_dai_rates[] = {
479 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
480 88200, 96000, 176400, 192000, 384000,
481 };
482
483 static const struct snd_pcm_hw_constraint_list constraints_slave = {
484 .count = ARRAY_SIZE(pcm512x_dai_rates),
485 .list = pcm512x_dai_rates,
486 };
487
488 static int pcm512x_hw_rule_rate(struct snd_pcm_hw_params *params,
489 struct snd_pcm_hw_rule *rule)
490 {
491 struct pcm512x_priv *pcm512x = rule->private;
492 struct snd_interval ranges[2];
493 int frame_size;
494
495 frame_size = snd_soc_params_to_frame_size(params);
496 if (frame_size < 0)
497 return frame_size;
498
499 switch (frame_size) {
500 case 32:
501 /* No hole when the frame size is 32. */
502 return 0;
503 case 48:
504 case 64:
505 /* There is only one hole in the range of supported
506 * rates, but it moves with the frame size.
507 */
508 memset(ranges, 0, sizeof(ranges));
509 ranges[0].min = 8000;
510 ranges[0].max = pcm512x_sck_max(pcm512x) / frame_size / 2;
511 ranges[1].min = DIV_ROUND_UP(16000000, frame_size);
512 ranges[1].max = 384000;
513 break;
514 default:
515 return -EINVAL;
516 }
517
518 return snd_interval_ranges(hw_param_interval(params, rule->var),
519 ARRAY_SIZE(ranges), ranges, 0);
520 }
521
522 static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
523 struct snd_soc_dai *dai)
524 {
525 struct snd_soc_codec *codec = dai->codec;
526 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
527 struct device *dev = dai->dev;
528 struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
529 struct snd_ratnum *rats_no_pll;
530
531 if (IS_ERR(pcm512x->sclk)) {
532 dev_err(dev, "Need SCLK for master mode: %ld\n",
533 PTR_ERR(pcm512x->sclk));
534 return PTR_ERR(pcm512x->sclk);
535 }
536
537 if (pcm512x->pll_out)
538 return snd_pcm_hw_rule_add(substream->runtime, 0,
539 SNDRV_PCM_HW_PARAM_RATE,
540 pcm512x_hw_rule_rate,
541 pcm512x,
542 SNDRV_PCM_HW_PARAM_FRAME_BITS,
543 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
544
545 constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
546 GFP_KERNEL);
547 if (!constraints_no_pll)
548 return -ENOMEM;
549 constraints_no_pll->nrats = 1;
550 rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
551 if (!rats_no_pll)
552 return -ENOMEM;
553 constraints_no_pll->rats = rats_no_pll;
554 rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
555 rats_no_pll->den_min = 1;
556 rats_no_pll->den_max = 128;
557 rats_no_pll->den_step = 1;
558
559 return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
560 SNDRV_PCM_HW_PARAM_RATE,
561 constraints_no_pll);
562 }
563
564 static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
565 struct snd_soc_dai *dai)
566 {
567 struct snd_soc_codec *codec = dai->codec;
568 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
569 struct device *dev = dai->dev;
570 struct regmap *regmap = pcm512x->regmap;
571
572 if (IS_ERR(pcm512x->sclk)) {
573 dev_info(dev, "No SCLK, using BCLK: %ld\n",
574 PTR_ERR(pcm512x->sclk));
575
576 /* Disable reporting of missing SCLK as an error */
577 regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
578 PCM512x_IDCH, PCM512x_IDCH);
579
580 /* Switch PLL input to BCLK */
581 regmap_update_bits(regmap, PCM512x_PLL_REF,
582 PCM512x_SREF, PCM512x_SREF_BCK);
583 }
584
585 return snd_pcm_hw_constraint_list(substream->runtime, 0,
586 SNDRV_PCM_HW_PARAM_RATE,
587 &constraints_slave);
588 }
589
590 static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
591 struct snd_soc_dai *dai)
592 {
593 struct snd_soc_codec *codec = dai->codec;
594 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
595
596 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
597 case SND_SOC_DAIFMT_CBM_CFM:
598 case SND_SOC_DAIFMT_CBM_CFS:
599 return pcm512x_dai_startup_master(substream, dai);
600
601 case SND_SOC_DAIFMT_CBS_CFS:
602 return pcm512x_dai_startup_slave(substream, dai);
603
604 default:
605 return -EINVAL;
606 }
607 }
608
609 static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
610 enum snd_soc_bias_level level)
611 {
612 struct pcm512x_priv *pcm512x = dev_get_drvdata(codec->dev);
613 int ret;
614
615 switch (level) {
616 case SND_SOC_BIAS_ON:
617 case SND_SOC_BIAS_PREPARE:
618 break;
619
620 case SND_SOC_BIAS_STANDBY:
621 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
622 PCM512x_RQST, 0);
623 if (ret != 0) {
624 dev_err(codec->dev, "Failed to remove standby: %d\n",
625 ret);
626 return ret;
627 }
628 break;
629
630 case SND_SOC_BIAS_OFF:
631 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
632 PCM512x_RQST, PCM512x_RQST);
633 if (ret != 0) {
634 dev_err(codec->dev, "Failed to request standby: %d\n",
635 ret);
636 return ret;
637 }
638 break;
639 }
640
641 return 0;
642 }
643
644 static unsigned long pcm512x_find_sck(struct snd_soc_dai *dai,
645 unsigned long bclk_rate)
646 {
647 struct device *dev = dai->dev;
648 struct snd_soc_codec *codec = dai->codec;
649 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
650 unsigned long sck_rate;
651 int pow2;
652
653 /* 64 MHz <= pll_rate <= 100 MHz, VREF mode */
654 /* 16 MHz <= sck_rate <= 25 MHz, VREF mode */
655
656 /* select sck_rate as a multiple of bclk_rate but still with
657 * as many factors of 2 as possible, as that makes it easier
658 * to find a fast DAC rate
659 */
660 pow2 = 1 << fls((pcm512x_pll_max(pcm512x) - 16000000) / bclk_rate);
661 for (; pow2; pow2 >>= 1) {
662 sck_rate = rounddown(pcm512x_pll_max(pcm512x),
663 bclk_rate * pow2);
664 if (sck_rate >= 16000000)
665 break;
666 }
667 if (!pow2) {
668 dev_err(dev, "Impossible to generate a suitable SCK\n");
669 return 0;
670 }
671
672 dev_dbg(dev, "sck_rate %lu\n", sck_rate);
673 return sck_rate;
674 }
675
676 /* pll_rate = pllin_rate * R * J.D / P
677 * 1 <= R <= 16
678 * 1 <= J <= 63
679 * 0 <= D <= 9999
680 * 1 <= P <= 15
681 * 64 MHz <= pll_rate <= 100 MHz
682 * if D == 0
683 * 1 MHz <= pllin_rate / P <= 20 MHz
684 * else if D > 0
685 * 6.667 MHz <= pllin_rate / P <= 20 MHz
686 * 4 <= J <= 11
687 * R = 1
688 */
689 static int pcm512x_find_pll_coeff(struct snd_soc_dai *dai,
690 unsigned long pllin_rate,
691 unsigned long pll_rate)
692 {
693 struct device *dev = dai->dev;
694 struct snd_soc_codec *codec = dai->codec;
695 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
696 unsigned long common;
697 int R, J, D, P;
698 unsigned long K; /* 10000 * J.D */
699 unsigned long num;
700 unsigned long den;
701
702 common = gcd(pll_rate, pllin_rate);
703 dev_dbg(dev, "pll %lu pllin %lu common %lu\n",
704 pll_rate, pllin_rate, common);
705 num = pll_rate / common;
706 den = pllin_rate / common;
707
708 /* pllin_rate / P (or here, den) cannot be greater than 20 MHz */
709 if (pllin_rate / den > 20000000 && num < 8) {
710 num *= DIV_ROUND_UP(pllin_rate / den, 20000000);
711 den *= DIV_ROUND_UP(pllin_rate / den, 20000000);
712 }
713 dev_dbg(dev, "num / den = %lu / %lu\n", num, den);
714
715 P = den;
716 if (den <= 15 && num <= 16 * 63
717 && 1000000 <= pllin_rate / P && pllin_rate / P <= 20000000) {
718 /* Try the case with D = 0 */
719 D = 0;
720 /* factor 'num' into J and R, such that R <= 16 and J <= 63 */
721 for (R = 16; R; R--) {
722 if (num % R)
723 continue;
724 J = num / R;
725 if (J == 0 || J > 63)
726 continue;
727
728 dev_dbg(dev, "R * J / P = %d * %d / %d\n", R, J, P);
729 pcm512x->real_pll = pll_rate;
730 goto done;
731 }
732 /* no luck */
733 }
734
735 R = 1;
736
737 if (num > 0xffffffffUL / 10000)
738 goto fallback;
739
740 /* Try to find an exact pll_rate using the D > 0 case */
741 common = gcd(10000 * num, den);
742 num = 10000 * num / common;
743 den /= common;
744 dev_dbg(dev, "num %lu den %lu common %lu\n", num, den, common);
745
746 for (P = den; P <= 15; P++) {
747 if (pllin_rate / P < 6667000 || 200000000 < pllin_rate / P)
748 continue;
749 if (num * P % den)
750 continue;
751 K = num * P / den;
752 /* J == 12 is ok if D == 0 */
753 if (K < 40000 || K > 120000)
754 continue;
755
756 J = K / 10000;
757 D = K % 10000;
758 dev_dbg(dev, "J.D / P = %d.%04d / %d\n", J, D, P);
759 pcm512x->real_pll = pll_rate;
760 goto done;
761 }
762
763 /* Fall back to an approximate pll_rate */
764
765 fallback:
766 /* find smallest possible P */
767 P = DIV_ROUND_UP(pllin_rate, 20000000);
768 if (!P)
769 P = 1;
770 else if (P > 15) {
771 dev_err(dev, "Need a slower clock as pll-input\n");
772 return -EINVAL;
773 }
774 if (pllin_rate / P < 6667000) {
775 dev_err(dev, "Need a faster clock as pll-input\n");
776 return -EINVAL;
777 }
778 K = DIV_ROUND_CLOSEST_ULL(10000ULL * pll_rate * P, pllin_rate);
779 if (K < 40000)
780 K = 40000;
781 /* J == 12 is ok if D == 0 */
782 if (K > 120000)
783 K = 120000;
784 J = K / 10000;
785 D = K % 10000;
786 dev_dbg(dev, "J.D / P ~ %d.%04d / %d\n", J, D, P);
787 pcm512x->real_pll = DIV_ROUND_DOWN_ULL((u64)K * pllin_rate, 10000 * P);
788
789 done:
790 pcm512x->pll_r = R;
791 pcm512x->pll_j = J;
792 pcm512x->pll_d = D;
793 pcm512x->pll_p = P;
794 return 0;
795 }
796
797 static unsigned long pcm512x_pllin_dac_rate(struct snd_soc_dai *dai,
798 unsigned long osr_rate,
799 unsigned long pllin_rate)
800 {
801 struct snd_soc_codec *codec = dai->codec;
802 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
803 unsigned long dac_rate;
804
805 if (!pcm512x->pll_out)
806 return 0; /* no PLL to bypass, force SCK as DAC input */
807
808 if (pllin_rate % osr_rate)
809 return 0; /* futile, quit early */
810
811 /* run DAC no faster than 6144000 Hz */
812 for (dac_rate = rounddown(pcm512x_dac_max(pcm512x, 6144000), osr_rate);
813 dac_rate;
814 dac_rate -= osr_rate) {
815
816 if (pllin_rate / dac_rate > 128)
817 return 0; /* DAC divider would be too big */
818
819 if (!(pllin_rate % dac_rate))
820 return dac_rate;
821
822 dac_rate -= osr_rate;
823 }
824
825 return 0;
826 }
827
828 static int pcm512x_set_dividers(struct snd_soc_dai *dai,
829 struct snd_pcm_hw_params *params)
830 {
831 struct device *dev = dai->dev;
832 struct snd_soc_codec *codec = dai->codec;
833 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
834 unsigned long pllin_rate = 0;
835 unsigned long pll_rate;
836 unsigned long sck_rate;
837 unsigned long mck_rate;
838 unsigned long bclk_rate;
839 unsigned long sample_rate;
840 unsigned long osr_rate;
841 unsigned long dacsrc_rate;
842 int bclk_div;
843 int lrclk_div;
844 int dsp_div;
845 int dac_div;
846 unsigned long dac_rate;
847 int ncp_div;
848 int osr_div;
849 int ret;
850 int idac;
851 int fssp;
852 int gpio;
853
854 lrclk_div = snd_soc_params_to_frame_size(params);
855 if (lrclk_div == 0) {
856 dev_err(dev, "No LRCLK?\n");
857 return -EINVAL;
858 }
859
860 if (!pcm512x->pll_out) {
861 sck_rate = clk_get_rate(pcm512x->sclk);
862 bclk_div = params->rate_den * 64 / lrclk_div;
863 bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
864
865 mck_rate = sck_rate;
866 } else {
867 ret = snd_soc_params_to_bclk(params);
868 if (ret < 0) {
869 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret);
870 return ret;
871 }
872 if (ret == 0) {
873 dev_err(dev, "No BCLK?\n");
874 return -EINVAL;
875 }
876 bclk_rate = ret;
877
878 pllin_rate = clk_get_rate(pcm512x->sclk);
879
880 sck_rate = pcm512x_find_sck(dai, bclk_rate);
881 if (!sck_rate)
882 return -EINVAL;
883 pll_rate = 4 * sck_rate;
884
885 ret = pcm512x_find_pll_coeff(dai, pllin_rate, pll_rate);
886 if (ret != 0)
887 return ret;
888
889 ret = regmap_write(pcm512x->regmap,
890 PCM512x_PLL_COEFF_0, pcm512x->pll_p - 1);
891 if (ret != 0) {
892 dev_err(dev, "Failed to write PLL P: %d\n", ret);
893 return ret;
894 }
895
896 ret = regmap_write(pcm512x->regmap,
897 PCM512x_PLL_COEFF_1, pcm512x->pll_j);
898 if (ret != 0) {
899 dev_err(dev, "Failed to write PLL J: %d\n", ret);
900 return ret;
901 }
902
903 ret = regmap_write(pcm512x->regmap,
904 PCM512x_PLL_COEFF_2, pcm512x->pll_d >> 8);
905 if (ret != 0) {
906 dev_err(dev, "Failed to write PLL D msb: %d\n", ret);
907 return ret;
908 }
909
910 ret = regmap_write(pcm512x->regmap,
911 PCM512x_PLL_COEFF_3, pcm512x->pll_d & 0xff);
912 if (ret != 0) {
913 dev_err(dev, "Failed to write PLL D lsb: %d\n", ret);
914 return ret;
915 }
916
917 ret = regmap_write(pcm512x->regmap,
918 PCM512x_PLL_COEFF_4, pcm512x->pll_r - 1);
919 if (ret != 0) {
920 dev_err(dev, "Failed to write PLL R: %d\n", ret);
921 return ret;
922 }
923
924 mck_rate = pcm512x->real_pll;
925
926 bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
927 }
928
929 if (bclk_div > 128) {
930 dev_err(dev, "Failed to find BCLK divider\n");
931 return -EINVAL;
932 }
933
934 /* the actual rate */
935 sample_rate = sck_rate / bclk_div / lrclk_div;
936 osr_rate = 16 * sample_rate;
937
938 /* run DSP no faster than 50 MHz */
939 dsp_div = mck_rate > pcm512x_dsp_max(pcm512x) ? 2 : 1;
940
941 dac_rate = pcm512x_pllin_dac_rate(dai, osr_rate, pllin_rate);
942 if (dac_rate) {
943 /* the desired clock rate is "compatible" with the pll input
944 * clock, so use that clock as dac input instead of the pll
945 * output clock since the pll will introduce jitter and thus
946 * noise.
947 */
948 dev_dbg(dev, "using pll input as dac input\n");
949 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
950 PCM512x_SDAC, PCM512x_SDAC_GPIO);
951 if (ret != 0) {
952 dev_err(codec->dev,
953 "Failed to set gpio as dacref: %d\n", ret);
954 return ret;
955 }
956
957 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
958 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_DACIN,
959 PCM512x_GREF, gpio);
960 if (ret != 0) {
961 dev_err(codec->dev,
962 "Failed to set gpio %d as dacin: %d\n",
963 pcm512x->pll_in, ret);
964 return ret;
965 }
966
967 dacsrc_rate = pllin_rate;
968 } else {
969 /* run DAC no faster than 6144000 Hz */
970 unsigned long dac_mul = pcm512x_dac_max(pcm512x, 6144000)
971 / osr_rate;
972 unsigned long sck_mul = sck_rate / osr_rate;
973
974 for (; dac_mul; dac_mul--) {
975 if (!(sck_mul % dac_mul))
976 break;
977 }
978 if (!dac_mul) {
979 dev_err(dev, "Failed to find DAC rate\n");
980 return -EINVAL;
981 }
982
983 dac_rate = dac_mul * osr_rate;
984 dev_dbg(dev, "dac_rate %lu sample_rate %lu\n",
985 dac_rate, sample_rate);
986
987 ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
988 PCM512x_SDAC, PCM512x_SDAC_SCK);
989 if (ret != 0) {
990 dev_err(codec->dev,
991 "Failed to set sck as dacref: %d\n", ret);
992 return ret;
993 }
994
995 dacsrc_rate = sck_rate;
996 }
997
998 osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
999 if (osr_div > 128) {
1000 dev_err(dev, "Failed to find OSR divider\n");
1001 return -EINVAL;
1002 }
1003
1004 dac_div = DIV_ROUND_CLOSEST(dacsrc_rate, dac_rate);
1005 if (dac_div > 128) {
1006 dev_err(dev, "Failed to find DAC divider\n");
1007 return -EINVAL;
1008 }
1009 dac_rate = dacsrc_rate / dac_div;
1010
1011 ncp_div = DIV_ROUND_CLOSEST(dac_rate,
1012 pcm512x_ncp_target(pcm512x, dac_rate));
1013 if (ncp_div > 128 || dac_rate / ncp_div > 2048000) {
1014 /* run NCP no faster than 2048000 Hz, but why? */
1015 ncp_div = DIV_ROUND_UP(dac_rate, 2048000);
1016 if (ncp_div > 128) {
1017 dev_err(dev, "Failed to find NCP divider\n");
1018 return -EINVAL;
1019 }
1020 }
1021
1022 idac = mck_rate / (dsp_div * sample_rate);
1023
1024 ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
1025 if (ret != 0) {
1026 dev_err(dev, "Failed to write DSP divider: %d\n", ret);
1027 return ret;
1028 }
1029
1030 ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
1031 if (ret != 0) {
1032 dev_err(dev, "Failed to write DAC divider: %d\n", ret);
1033 return ret;
1034 }
1035
1036 ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
1037 if (ret != 0) {
1038 dev_err(dev, "Failed to write NCP divider: %d\n", ret);
1039 return ret;
1040 }
1041
1042 ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
1043 if (ret != 0) {
1044 dev_err(dev, "Failed to write OSR divider: %d\n", ret);
1045 return ret;
1046 }
1047
1048 ret = regmap_write(pcm512x->regmap,
1049 PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
1050 if (ret != 0) {
1051 dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
1052 return ret;
1053 }
1054
1055 ret = regmap_write(pcm512x->regmap,
1056 PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
1057 if (ret != 0) {
1058 dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
1059 return ret;
1060 }
1061
1062 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
1063 if (ret != 0) {
1064 dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
1065 return ret;
1066 }
1067
1068 ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
1069 if (ret != 0) {
1070 dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
1071 return ret;
1072 }
1073
1074 if (sample_rate <= pcm512x_dac_max(pcm512x, 48000))
1075 fssp = PCM512x_FSSP_48KHZ;
1076 else if (sample_rate <= pcm512x_dac_max(pcm512x, 96000))
1077 fssp = PCM512x_FSSP_96KHZ;
1078 else if (sample_rate <= pcm512x_dac_max(pcm512x, 192000))
1079 fssp = PCM512x_FSSP_192KHZ;
1080 else
1081 fssp = PCM512x_FSSP_384KHZ;
1082 ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
1083 PCM512x_FSSP, fssp);
1084 if (ret != 0) {
1085 dev_err(codec->dev, "Failed to set fs speed: %d\n", ret);
1086 return ret;
1087 }
1088
1089 dev_dbg(codec->dev, "DSP divider %d\n", dsp_div);
1090 dev_dbg(codec->dev, "DAC divider %d\n", dac_div);
1091 dev_dbg(codec->dev, "NCP divider %d\n", ncp_div);
1092 dev_dbg(codec->dev, "OSR divider %d\n", osr_div);
1093 dev_dbg(codec->dev, "BCK divider %d\n", bclk_div);
1094 dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div);
1095 dev_dbg(codec->dev, "IDAC %d\n", idac);
1096 dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp);
1097
1098 return 0;
1099 }
1100
1101 static int pcm512x_hw_params(struct snd_pcm_substream *substream,
1102 struct snd_pcm_hw_params *params,
1103 struct snd_soc_dai *dai)
1104 {
1105 struct snd_soc_codec *codec = dai->codec;
1106 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
1107 int alen;
1108 int gpio;
1109 int clock_output;
1110 int master_mode;
1111 int ret;
1112
1113 dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
1114 params_rate(params),
1115 params_channels(params));
1116
1117 switch (params_width(params)) {
1118 case 16:
1119 alen = PCM512x_ALEN_16;
1120 break;
1121 case 20:
1122 alen = PCM512x_ALEN_20;
1123 break;
1124 case 24:
1125 alen = PCM512x_ALEN_24;
1126 break;
1127 case 32:
1128 alen = PCM512x_ALEN_32;
1129 break;
1130 default:
1131 dev_err(codec->dev, "Bad frame size: %d\n",
1132 params_width(params));
1133 return -EINVAL;
1134 }
1135
1136 switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1137 case SND_SOC_DAIFMT_CBS_CFS:
1138 ret = regmap_update_bits(pcm512x->regmap,
1139 PCM512x_BCLK_LRCLK_CFG,
1140 PCM512x_BCKP
1141 | PCM512x_BCKO | PCM512x_LRKO,
1142 0);
1143 if (ret != 0) {
1144 dev_err(codec->dev,
1145 "Failed to enable slave mode: %d\n", ret);
1146 return ret;
1147 }
1148
1149 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1150 PCM512x_DCAS, 0);
1151 if (ret != 0) {
1152 dev_err(codec->dev,
1153 "Failed to enable clock divider autoset: %d\n",
1154 ret);
1155 return ret;
1156 }
1157 return 0;
1158 case SND_SOC_DAIFMT_CBM_CFM:
1159 clock_output = PCM512x_BCKO | PCM512x_LRKO;
1160 master_mode = PCM512x_RLRK | PCM512x_RBCK;
1161 break;
1162 case SND_SOC_DAIFMT_CBM_CFS:
1163 clock_output = PCM512x_BCKO;
1164 master_mode = PCM512x_RBCK;
1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170 ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
1171 PCM512x_ALEN, alen);
1172 if (ret != 0) {
1173 dev_err(codec->dev, "Failed to set frame size: %d\n", ret);
1174 return ret;
1175 }
1176
1177 if (pcm512x->pll_out) {
1178 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_A, 0x11);
1179 if (ret != 0) {
1180 dev_err(codec->dev, "Failed to set FLEX_A: %d\n", ret);
1181 return ret;
1182 }
1183
1184 ret = regmap_write(pcm512x->regmap, PCM512x_FLEX_B, 0xff);
1185 if (ret != 0) {
1186 dev_err(codec->dev, "Failed to set FLEX_B: %d\n", ret);
1187 return ret;
1188 }
1189
1190 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1191 PCM512x_IDFS | PCM512x_IDBK
1192 | PCM512x_IDSK | PCM512x_IDCH
1193 | PCM512x_IDCM | PCM512x_DCAS
1194 | PCM512x_IPLK,
1195 PCM512x_IDFS | PCM512x_IDBK
1196 | PCM512x_IDSK | PCM512x_IDCH
1197 | PCM512x_DCAS);
1198 if (ret != 0) {
1199 dev_err(codec->dev,
1200 "Failed to ignore auto-clock failures: %d\n",
1201 ret);
1202 return ret;
1203 }
1204 } else {
1205 ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
1206 PCM512x_IDFS | PCM512x_IDBK
1207 | PCM512x_IDSK | PCM512x_IDCH
1208 | PCM512x_IDCM | PCM512x_DCAS
1209 | PCM512x_IPLK,
1210 PCM512x_IDFS | PCM512x_IDBK
1211 | PCM512x_IDSK | PCM512x_IDCH
1212 | PCM512x_DCAS | PCM512x_IPLK);
1213 if (ret != 0) {
1214 dev_err(codec->dev,
1215 "Failed to ignore auto-clock failures: %d\n",
1216 ret);
1217 return ret;
1218 }
1219
1220 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1221 PCM512x_PLLE, 0);
1222 if (ret != 0) {
1223 dev_err(codec->dev, "Failed to disable pll: %d\n", ret);
1224 return ret;
1225 }
1226 }
1227
1228 ret = pcm512x_set_dividers(dai, params);
1229 if (ret != 0)
1230 return ret;
1231
1232 if (pcm512x->pll_out) {
1233 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_REF,
1234 PCM512x_SREF, PCM512x_SREF_GPIO);
1235 if (ret != 0) {
1236 dev_err(codec->dev,
1237 "Failed to set gpio as pllref: %d\n", ret);
1238 return ret;
1239 }
1240
1241 gpio = PCM512x_GREF_GPIO1 + pcm512x->pll_in - 1;
1242 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_PLLIN,
1243 PCM512x_GREF, gpio);
1244 if (ret != 0) {
1245 dev_err(codec->dev,
1246 "Failed to set gpio %d as pllin: %d\n",
1247 pcm512x->pll_in, ret);
1248 return ret;
1249 }
1250
1251 ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
1252 PCM512x_PLLE, PCM512x_PLLE);
1253 if (ret != 0) {
1254 dev_err(codec->dev, "Failed to enable pll: %d\n", ret);
1255 return ret;
1256 }
1257 }
1258
1259 ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
1260 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
1261 clock_output);
1262 if (ret != 0) {
1263 dev_err(codec->dev, "Failed to enable clock output: %d\n", ret);
1264 return ret;
1265 }
1266
1267 ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
1268 PCM512x_RLRK | PCM512x_RBCK,
1269 master_mode);
1270 if (ret != 0) {
1271 dev_err(codec->dev, "Failed to enable master mode: %d\n", ret);
1272 return ret;
1273 }
1274
1275 if (pcm512x->pll_out) {
1276 gpio = PCM512x_G1OE << (pcm512x->pll_out - 1);
1277 ret = regmap_update_bits(pcm512x->regmap, PCM512x_GPIO_EN,
1278 gpio, gpio);
1279 if (ret != 0) {
1280 dev_err(codec->dev, "Failed to enable gpio %d: %d\n",
1281 pcm512x->pll_out, ret);
1282 return ret;
1283 }
1284
1285 gpio = PCM512x_GPIO_OUTPUT_1 + pcm512x->pll_out - 1;
1286 ret = regmap_update_bits(pcm512x->regmap, gpio,
1287 PCM512x_GxSL, PCM512x_GxSL_PLLCK);
1288 if (ret != 0) {
1289 dev_err(codec->dev, "Failed to output pll on %d: %d\n",
1290 ret, pcm512x->pll_out);
1291 return ret;
1292 }
1293 }
1294
1295 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1296 PCM512x_RQSY, PCM512x_RQSY_HALT);
1297 if (ret != 0) {
1298 dev_err(codec->dev, "Failed to halt clocks: %d\n", ret);
1299 return ret;
1300 }
1301
1302 ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
1303 PCM512x_RQSY, PCM512x_RQSY_RESUME);
1304 if (ret != 0) {
1305 dev_err(codec->dev, "Failed to resume clocks: %d\n", ret);
1306 return ret;
1307 }
1308
1309 return 0;
1310 }
1311
1312 static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1313 {
1314 struct snd_soc_codec *codec = dai->codec;
1315 struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
1316
1317 pcm512x->fmt = fmt;
1318
1319 return 0;
1320 }
1321
1322 static const struct snd_soc_dai_ops pcm512x_dai_ops = {
1323 .startup = pcm512x_dai_startup,
1324 .hw_params = pcm512x_hw_params,
1325 .set_fmt = pcm512x_set_fmt,
1326 };
1327
1328 static struct snd_soc_dai_driver pcm512x_dai = {
1329 .name = "pcm512x-hifi",
1330 .playback = {
1331 .stream_name = "Playback",
1332 .channels_min = 2,
1333 .channels_max = 2,
1334 .rates = SNDRV_PCM_RATE_CONTINUOUS,
1335 .rate_min = 8000,
1336 .rate_max = 384000,
1337 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1338 SNDRV_PCM_FMTBIT_S24_LE |
1339 SNDRV_PCM_FMTBIT_S32_LE
1340 },
1341 .ops = &pcm512x_dai_ops,
1342 };
1343
1344 static const struct snd_soc_codec_driver pcm512x_codec_driver = {
1345 .set_bias_level = pcm512x_set_bias_level,
1346 .idle_bias_off = true,
1347
1348 .component_driver = {
1349 .controls = pcm512x_controls,
1350 .num_controls = ARRAY_SIZE(pcm512x_controls),
1351 .dapm_widgets = pcm512x_dapm_widgets,
1352 .num_dapm_widgets = ARRAY_SIZE(pcm512x_dapm_widgets),
1353 .dapm_routes = pcm512x_dapm_routes,
1354 .num_dapm_routes = ARRAY_SIZE(pcm512x_dapm_routes),
1355 },
1356 };
1357
1358 static const struct regmap_range_cfg pcm512x_range = {
1359 .name = "Pages", .range_min = PCM512x_VIRT_BASE,
1360 .range_max = PCM512x_MAX_REGISTER,
1361 .selector_reg = PCM512x_PAGE,
1362 .selector_mask = 0xff,
1363 .window_start = 0, .window_len = 0x100,
1364 };
1365
1366 const struct regmap_config pcm512x_regmap = {
1367 .reg_bits = 8,
1368 .val_bits = 8,
1369
1370 .readable_reg = pcm512x_readable,
1371 .volatile_reg = pcm512x_volatile,
1372
1373 .ranges = &pcm512x_range,
1374 .num_ranges = 1,
1375
1376 .max_register = PCM512x_MAX_REGISTER,
1377 .reg_defaults = pcm512x_reg_defaults,
1378 .num_reg_defaults = ARRAY_SIZE(pcm512x_reg_defaults),
1379 .cache_type = REGCACHE_RBTREE,
1380 };
1381 EXPORT_SYMBOL_GPL(pcm512x_regmap);
1382
1383 int pcm512x_probe(struct device *dev, struct regmap *regmap)
1384 {
1385 struct pcm512x_priv *pcm512x;
1386 int i, ret;
1387
1388 pcm512x = devm_kzalloc(dev, sizeof(struct pcm512x_priv), GFP_KERNEL);
1389 if (!pcm512x)
1390 return -ENOMEM;
1391
1392 dev_set_drvdata(dev, pcm512x);
1393 pcm512x->regmap = regmap;
1394
1395 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++)
1396 pcm512x->supplies[i].supply = pcm512x_supply_names[i];
1397
1398 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pcm512x->supplies),
1399 pcm512x->supplies);
1400 if (ret != 0) {
1401 dev_err(dev, "Failed to get supplies: %d\n", ret);
1402 return ret;
1403 }
1404
1405 pcm512x->supply_nb[0].notifier_call = pcm512x_regulator_event_0;
1406 pcm512x->supply_nb[1].notifier_call = pcm512x_regulator_event_1;
1407 pcm512x->supply_nb[2].notifier_call = pcm512x_regulator_event_2;
1408
1409 for (i = 0; i < ARRAY_SIZE(pcm512x->supplies); i++) {
1410 ret = regulator_register_notifier(pcm512x->supplies[i].consumer,
1411 &pcm512x->supply_nb[i]);
1412 if (ret != 0) {
1413 dev_err(dev,
1414 "Failed to register regulator notifier: %d\n",
1415 ret);
1416 }
1417 }
1418
1419 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1420 pcm512x->supplies);
1421 if (ret != 0) {
1422 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1423 return ret;
1424 }
1425
1426 /* Reset the device, verifying I/O in the process for I2C */
1427 ret = regmap_write(regmap, PCM512x_RESET,
1428 PCM512x_RSTM | PCM512x_RSTR);
1429 if (ret != 0) {
1430 dev_err(dev, "Failed to reset device: %d\n", ret);
1431 goto err;
1432 }
1433
1434 ret = regmap_write(regmap, PCM512x_RESET, 0);
1435 if (ret != 0) {
1436 dev_err(dev, "Failed to reset device: %d\n", ret);
1437 goto err;
1438 }
1439
1440 pcm512x->sclk = devm_clk_get(dev, NULL);
1441 if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
1442 return -EPROBE_DEFER;
1443 if (!IS_ERR(pcm512x->sclk)) {
1444 ret = clk_prepare_enable(pcm512x->sclk);
1445 if (ret != 0) {
1446 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1447 return ret;
1448 }
1449 }
1450
1451 /* Default to standby mode */
1452 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1453 PCM512x_RQST, PCM512x_RQST);
1454 if (ret != 0) {
1455 dev_err(dev, "Failed to request standby: %d\n",
1456 ret);
1457 goto err_clk;
1458 }
1459
1460 pm_runtime_set_active(dev);
1461 pm_runtime_enable(dev);
1462 pm_runtime_idle(dev);
1463
1464 #ifdef CONFIG_OF
1465 if (dev->of_node) {
1466 const struct device_node *np = dev->of_node;
1467 u32 val;
1468
1469 if (of_property_read_u32(np, "pll-in", &val) >= 0) {
1470 if (val > 6) {
1471 dev_err(dev, "Invalid pll-in\n");
1472 ret = -EINVAL;
1473 goto err_clk;
1474 }
1475 pcm512x->pll_in = val;
1476 }
1477
1478 if (of_property_read_u32(np, "pll-out", &val) >= 0) {
1479 if (val > 6) {
1480 dev_err(dev, "Invalid pll-out\n");
1481 ret = -EINVAL;
1482 goto err_clk;
1483 }
1484 pcm512x->pll_out = val;
1485 }
1486
1487 if (!pcm512x->pll_in != !pcm512x->pll_out) {
1488 dev_err(dev,
1489 "Error: both pll-in and pll-out, or none\n");
1490 ret = -EINVAL;
1491 goto err_clk;
1492 }
1493 if (pcm512x->pll_in && pcm512x->pll_in == pcm512x->pll_out) {
1494 dev_err(dev, "Error: pll-in == pll-out\n");
1495 ret = -EINVAL;
1496 goto err_clk;
1497 }
1498 }
1499 #endif
1500
1501 ret = snd_soc_register_codec(dev, &pcm512x_codec_driver,
1502 &pcm512x_dai, 1);
1503 if (ret != 0) {
1504 dev_err(dev, "Failed to register CODEC: %d\n", ret);
1505 goto err_pm;
1506 }
1507
1508 return 0;
1509
1510 err_pm:
1511 pm_runtime_disable(dev);
1512 err_clk:
1513 if (!IS_ERR(pcm512x->sclk))
1514 clk_disable_unprepare(pcm512x->sclk);
1515 err:
1516 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1517 pcm512x->supplies);
1518 return ret;
1519 }
1520 EXPORT_SYMBOL_GPL(pcm512x_probe);
1521
1522 void pcm512x_remove(struct device *dev)
1523 {
1524 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1525
1526 snd_soc_unregister_codec(dev);
1527 pm_runtime_disable(dev);
1528 if (!IS_ERR(pcm512x->sclk))
1529 clk_disable_unprepare(pcm512x->sclk);
1530 regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1531 pcm512x->supplies);
1532 }
1533 EXPORT_SYMBOL_GPL(pcm512x_remove);
1534
1535 #ifdef CONFIG_PM
1536 static int pcm512x_suspend(struct device *dev)
1537 {
1538 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1539 int ret;
1540
1541 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1542 PCM512x_RQPD, PCM512x_RQPD);
1543 if (ret != 0) {
1544 dev_err(dev, "Failed to request power down: %d\n", ret);
1545 return ret;
1546 }
1547
1548 ret = regulator_bulk_disable(ARRAY_SIZE(pcm512x->supplies),
1549 pcm512x->supplies);
1550 if (ret != 0) {
1551 dev_err(dev, "Failed to disable supplies: %d\n", ret);
1552 return ret;
1553 }
1554
1555 if (!IS_ERR(pcm512x->sclk))
1556 clk_disable_unprepare(pcm512x->sclk);
1557
1558 return 0;
1559 }
1560
1561 static int pcm512x_resume(struct device *dev)
1562 {
1563 struct pcm512x_priv *pcm512x = dev_get_drvdata(dev);
1564 int ret;
1565
1566 if (!IS_ERR(pcm512x->sclk)) {
1567 ret = clk_prepare_enable(pcm512x->sclk);
1568 if (ret != 0) {
1569 dev_err(dev, "Failed to enable SCLK: %d\n", ret);
1570 return ret;
1571 }
1572 }
1573
1574 ret = regulator_bulk_enable(ARRAY_SIZE(pcm512x->supplies),
1575 pcm512x->supplies);
1576 if (ret != 0) {
1577 dev_err(dev, "Failed to enable supplies: %d\n", ret);
1578 return ret;
1579 }
1580
1581 regcache_cache_only(pcm512x->regmap, false);
1582 ret = regcache_sync(pcm512x->regmap);
1583 if (ret != 0) {
1584 dev_err(dev, "Failed to sync cache: %d\n", ret);
1585 return ret;
1586 }
1587
1588 ret = regmap_update_bits(pcm512x->regmap, PCM512x_POWER,
1589 PCM512x_RQPD, 0);
1590 if (ret != 0) {
1591 dev_err(dev, "Failed to remove power down: %d\n", ret);
1592 return ret;
1593 }
1594
1595 return 0;
1596 }
1597 #endif
1598
1599 const struct dev_pm_ops pcm512x_pm_ops = {
1600 SET_RUNTIME_PM_OPS(pcm512x_suspend, pcm512x_resume, NULL)
1601 };
1602 EXPORT_SYMBOL_GPL(pcm512x_pm_ops);
1603
1604 MODULE_DESCRIPTION("ASoC PCM512x codec driver");
1605 MODULE_AUTHOR("Mark Brown <broonie@linaro.org>");
1606 MODULE_LICENSE("GPL v2");
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