2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
34 #include <plat/control.h>
36 #include <plat/mcbsp.h>
37 #include "omap-mcbsp.h"
40 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
42 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
43 xhandler_get, xhandler_put) \
44 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
45 .info = omap_mcbsp_st_info_volsw, \
46 .get = xhandler_get, .put = xhandler_put, \
47 .private_value = (unsigned long) &(struct soc_mixer_control) \
48 {.min = xmin, .max = xmax} }
50 struct omap_mcbsp_data
{
52 struct omap_mcbsp_reg_cfg regs
;
55 * Flags indicating is the bus already activated and configured by
65 static struct omap_mcbsp_data mcbsp_data
[NUM_LINKS
];
68 * Stream DMA parameters. DMA request line and port address are set runtime
69 * since they are different between OMAP1 and later OMAPs
71 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params
[NUM_LINKS
][2];
73 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
74 static const int omap1_dma_reqs
[][2] = {
75 { OMAP_DMA_MCBSP1_TX
, OMAP_DMA_MCBSP1_RX
},
76 { OMAP_DMA_MCBSP2_TX
, OMAP_DMA_MCBSP2_RX
},
77 { OMAP_DMA_MCBSP3_TX
, OMAP_DMA_MCBSP3_RX
},
79 static const unsigned long omap1_mcbsp_port
[][2] = {
80 { OMAP1510_MCBSP1_BASE
+ OMAP_MCBSP_REG_DXR1
,
81 OMAP1510_MCBSP1_BASE
+ OMAP_MCBSP_REG_DRR1
},
82 { OMAP1510_MCBSP2_BASE
+ OMAP_MCBSP_REG_DXR1
,
83 OMAP1510_MCBSP2_BASE
+ OMAP_MCBSP_REG_DRR1
},
84 { OMAP1510_MCBSP3_BASE
+ OMAP_MCBSP_REG_DXR1
,
85 OMAP1510_MCBSP3_BASE
+ OMAP_MCBSP_REG_DRR1
},
88 static const int omap1_dma_reqs
[][2] = {};
89 static const unsigned long omap1_mcbsp_port
[][2] = {};
92 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
93 static const int omap24xx_dma_reqs
[][2] = {
94 { OMAP24XX_DMA_MCBSP1_TX
, OMAP24XX_DMA_MCBSP1_RX
},
95 { OMAP24XX_DMA_MCBSP2_TX
, OMAP24XX_DMA_MCBSP2_RX
},
96 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
97 { OMAP24XX_DMA_MCBSP3_TX
, OMAP24XX_DMA_MCBSP3_RX
},
98 { OMAP24XX_DMA_MCBSP4_TX
, OMAP24XX_DMA_MCBSP4_RX
},
99 { OMAP24XX_DMA_MCBSP5_TX
, OMAP24XX_DMA_MCBSP5_RX
},
103 static const int omap24xx_dma_reqs
[][2] = {};
106 #if defined(CONFIG_ARCH_OMAP2420)
107 static const unsigned long omap2420_mcbsp_port
[][2] = {
108 { OMAP24XX_MCBSP1_BASE
+ OMAP_MCBSP_REG_DXR1
,
109 OMAP24XX_MCBSP1_BASE
+ OMAP_MCBSP_REG_DRR1
},
110 { OMAP24XX_MCBSP2_BASE
+ OMAP_MCBSP_REG_DXR1
,
111 OMAP24XX_MCBSP2_BASE
+ OMAP_MCBSP_REG_DRR1
},
114 static const unsigned long omap2420_mcbsp_port
[][2] = {};
117 #if defined(CONFIG_ARCH_OMAP2430)
118 static const unsigned long omap2430_mcbsp_port
[][2] = {
119 { OMAP24XX_MCBSP1_BASE
+ OMAP_MCBSP_REG_DXR
,
120 OMAP24XX_MCBSP1_BASE
+ OMAP_MCBSP_REG_DRR
},
121 { OMAP24XX_MCBSP2_BASE
+ OMAP_MCBSP_REG_DXR
,
122 OMAP24XX_MCBSP2_BASE
+ OMAP_MCBSP_REG_DRR
},
123 { OMAP2430_MCBSP3_BASE
+ OMAP_MCBSP_REG_DXR
,
124 OMAP2430_MCBSP3_BASE
+ OMAP_MCBSP_REG_DRR
},
125 { OMAP2430_MCBSP4_BASE
+ OMAP_MCBSP_REG_DXR
,
126 OMAP2430_MCBSP4_BASE
+ OMAP_MCBSP_REG_DRR
},
127 { OMAP2430_MCBSP5_BASE
+ OMAP_MCBSP_REG_DXR
,
128 OMAP2430_MCBSP5_BASE
+ OMAP_MCBSP_REG_DRR
},
131 static const unsigned long omap2430_mcbsp_port
[][2] = {};
134 #if defined(CONFIG_ARCH_OMAP3)
135 static const unsigned long omap34xx_mcbsp_port
[][2] = {
136 { OMAP34XX_MCBSP1_BASE
+ OMAP_MCBSP_REG_DXR
,
137 OMAP34XX_MCBSP1_BASE
+ OMAP_MCBSP_REG_DRR
},
138 { OMAP34XX_MCBSP2_BASE
+ OMAP_MCBSP_REG_DXR
,
139 OMAP34XX_MCBSP2_BASE
+ OMAP_MCBSP_REG_DRR
},
140 { OMAP34XX_MCBSP3_BASE
+ OMAP_MCBSP_REG_DXR
,
141 OMAP34XX_MCBSP3_BASE
+ OMAP_MCBSP_REG_DRR
},
142 { OMAP34XX_MCBSP4_BASE
+ OMAP_MCBSP_REG_DXR
,
143 OMAP34XX_MCBSP4_BASE
+ OMAP_MCBSP_REG_DRR
},
144 { OMAP34XX_MCBSP5_BASE
+ OMAP_MCBSP_REG_DXR
,
145 OMAP34XX_MCBSP5_BASE
+ OMAP_MCBSP_REG_DRR
},
148 static const unsigned long omap34xx_mcbsp_port
[][2] = {};
151 static void omap_mcbsp_set_threshold(struct snd_pcm_substream
*substream
)
153 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
154 struct snd_soc_dai
*cpu_dai
= rtd
->cpu_dai
;
155 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
156 struct omap_pcm_dma_data
*dma_data
;
157 int dma_op_mode
= omap_mcbsp_get_dma_op_mode(mcbsp_data
->bus_id
);
160 dma_data
= snd_soc_dai_get_dma_data(rtd
->cpu_dai
, substream
);
162 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
163 if (dma_op_mode
== MCBSP_DMA_MODE_THRESHOLD
)
165 * Configure McBSP threshold based on either:
166 * packet_size, when the sDMA is in packet mode, or
167 * based on the period size.
169 if (dma_data
->packet_size
)
170 words
= dma_data
->packet_size
;
172 words
= snd_pcm_lib_period_bytes(substream
) /
173 (mcbsp_data
->wlen
/ 8);
177 /* Configure McBSP internal buffer usage */
178 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
179 omap_mcbsp_set_tx_threshold(mcbsp_data
->bus_id
, words
);
181 omap_mcbsp_set_rx_threshold(mcbsp_data
->bus_id
, words
);
184 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params
*params
,
185 struct snd_pcm_hw_rule
*rule
)
187 struct snd_interval
*buffer_size
= hw_param_interval(params
,
188 SNDRV_PCM_HW_PARAM_BUFFER_SIZE
);
189 struct snd_interval
*channels
= hw_param_interval(params
,
190 SNDRV_PCM_HW_PARAM_CHANNELS
);
191 struct omap_mcbsp_data
*mcbsp_data
= rule
->private;
192 struct snd_interval frames
;
195 snd_interval_any(&frames
);
196 size
= omap_mcbsp_get_fifo_size(mcbsp_data
->bus_id
);
198 frames
.min
= size
/ channels
->min
;
200 return snd_interval_refine(buffer_size
, &frames
);
203 static int omap_mcbsp_dai_startup(struct snd_pcm_substream
*substream
,
204 struct snd_soc_dai
*cpu_dai
)
206 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
207 int bus_id
= mcbsp_data
->bus_id
;
210 if (!cpu_dai
->active
)
211 err
= omap_mcbsp_request(bus_id
);
214 * OMAP3 McBSP FIFO is word structured.
215 * McBSP2 has 1024 + 256 = 1280 word long buffer,
216 * McBSP1,3,4,5 has 128 word long buffer
217 * This means that the size of the FIFO depends on the sample format.
218 * For example on McBSP3:
219 * 16bit samples: size is 128 * 2 = 256 bytes
220 * 32bit samples: size is 128 * 4 = 512 bytes
221 * It is simpler to place constraint for buffer and period based on
223 * McBSP3 as example again (16 or 32 bit samples):
224 * 1 channel (mono): size is 128 frames (128 words)
225 * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
226 * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
228 if (cpu_is_omap343x()) {
230 * Rule for the buffer size. We should not allow
231 * smaller buffer than the FIFO size to avoid underruns
233 snd_pcm_hw_rule_add(substream
->runtime
, 0,
234 SNDRV_PCM_HW_PARAM_CHANNELS
,
235 omap_mcbsp_hwrule_min_buffersize
,
237 SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, -1);
239 /* Make sure, that the period size is always even */
240 snd_pcm_hw_constraint_step(substream
->runtime
, 0,
241 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
, 2);
247 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream
*substream
,
248 struct snd_soc_dai
*cpu_dai
)
250 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
252 if (!cpu_dai
->active
) {
253 omap_mcbsp_free(mcbsp_data
->bus_id
);
254 mcbsp_data
->configured
= 0;
258 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream
*substream
, int cmd
,
259 struct snd_soc_dai
*cpu_dai
)
261 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
262 int err
= 0, play
= (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
);
265 case SNDRV_PCM_TRIGGER_START
:
266 case SNDRV_PCM_TRIGGER_RESUME
:
267 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
268 mcbsp_data
->active
++;
269 omap_mcbsp_start(mcbsp_data
->bus_id
, play
, !play
);
272 case SNDRV_PCM_TRIGGER_STOP
:
273 case SNDRV_PCM_TRIGGER_SUSPEND
:
274 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
275 omap_mcbsp_stop(mcbsp_data
->bus_id
, play
, !play
);
276 mcbsp_data
->active
--;
285 static snd_pcm_sframes_t
omap_mcbsp_dai_delay(
286 struct snd_pcm_substream
*substream
,
287 struct snd_soc_dai
*dai
)
289 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
290 struct snd_soc_dai
*cpu_dai
= rtd
->cpu_dai
;
291 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
293 snd_pcm_sframes_t delay
;
295 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
296 fifo_use
= omap_mcbsp_get_tx_delay(mcbsp_data
->bus_id
);
298 fifo_use
= omap_mcbsp_get_rx_delay(mcbsp_data
->bus_id
);
301 * Divide the used locations with the channel count to get the
302 * FIFO usage in samples (don't care about partial samples in the
305 delay
= fifo_use
/ substream
->runtime
->channels
;
310 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream
*substream
,
311 struct snd_pcm_hw_params
*params
,
312 struct snd_soc_dai
*cpu_dai
)
314 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
315 struct omap_mcbsp_reg_cfg
*regs
= &mcbsp_data
->regs
;
316 struct omap_pcm_dma_data
*dma_data
;
317 int dma
, bus_id
= mcbsp_data
->bus_id
;
318 int wlen
, channels
, wpf
, sync_mode
= OMAP_DMA_SYNC_ELEMENT
;
321 unsigned int format
, div
, framesize
, master
;
323 dma_data
= &omap_mcbsp_dai_dma_params
[cpu_dai
->id
][substream
->stream
];
324 if (cpu_class_is_omap1()) {
325 dma
= omap1_dma_reqs
[bus_id
][substream
->stream
];
326 port
= omap1_mcbsp_port
[bus_id
][substream
->stream
];
327 } else if (cpu_is_omap2420()) {
328 dma
= omap24xx_dma_reqs
[bus_id
][substream
->stream
];
329 port
= omap2420_mcbsp_port
[bus_id
][substream
->stream
];
330 } else if (cpu_is_omap2430()) {
331 dma
= omap24xx_dma_reqs
[bus_id
][substream
->stream
];
332 port
= omap2430_mcbsp_port
[bus_id
][substream
->stream
];
333 } else if (cpu_is_omap343x()) {
334 dma
= omap24xx_dma_reqs
[bus_id
][substream
->stream
];
335 port
= omap34xx_mcbsp_port
[bus_id
][substream
->stream
];
339 switch (params_format(params
)) {
340 case SNDRV_PCM_FORMAT_S16_LE
:
341 dma_data
->data_type
= OMAP_DMA_DATA_TYPE_S16
;
344 case SNDRV_PCM_FORMAT_S32_LE
:
345 dma_data
->data_type
= OMAP_DMA_DATA_TYPE_S32
;
351 if (cpu_is_omap343x()) {
352 dma_data
->set_threshold
= omap_mcbsp_set_threshold
;
353 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
354 if (omap_mcbsp_get_dma_op_mode(bus_id
) ==
355 MCBSP_DMA_MODE_THRESHOLD
) {
356 int period_words
, max_thrsh
;
358 period_words
= params_period_bytes(params
) / (wlen
/ 8);
359 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
360 max_thrsh
= omap_mcbsp_get_max_tx_threshold(
363 max_thrsh
= omap_mcbsp_get_max_rx_threshold(
366 * If the period contains less or equal number of words,
367 * we are using the original threshold mode setup:
368 * McBSP threshold = sDMA frame size = period_size
369 * Otherwise we switch to sDMA packet mode:
370 * McBSP threshold = sDMA packet size
371 * sDMA frame size = period size
373 if (period_words
> max_thrsh
) {
377 * Look for the biggest threshold value, which
378 * divides the period size evenly.
380 divider
= period_words
/ max_thrsh
;
381 if (period_words
% max_thrsh
)
383 while (period_words
% divider
&&
384 divider
< period_words
)
386 if (divider
== period_words
)
389 pkt_size
= period_words
/ divider
;
390 sync_mode
= OMAP_DMA_SYNC_PACKET
;
392 sync_mode
= OMAP_DMA_SYNC_FRAME
;
397 dma_data
->name
= substream
->stream
? "Audio Capture" : "Audio Playback";
398 dma_data
->dma_req
= dma
;
399 dma_data
->port_addr
= port
;
400 dma_data
->sync_mode
= sync_mode
;
401 dma_data
->packet_size
= pkt_size
;
403 snd_soc_dai_set_dma_data(cpu_dai
, substream
, dma_data
);
405 if (mcbsp_data
->configured
) {
406 /* McBSP already configured by another stream */
410 format
= mcbsp_data
->fmt
& SND_SOC_DAIFMT_FORMAT_MASK
;
411 wpf
= channels
= params_channels(params
);
412 if (channels
== 2 && (format
== SND_SOC_DAIFMT_I2S
||
413 format
== SND_SOC_DAIFMT_LEFT_J
)) {
414 /* Use dual-phase frames */
415 regs
->rcr2
|= RPHASE
;
416 regs
->xcr2
|= XPHASE
;
417 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
419 regs
->rcr2
|= RFRLEN2(wpf
- 1);
420 regs
->xcr2
|= XFRLEN2(wpf
- 1);
423 regs
->rcr1
|= RFRLEN1(wpf
- 1);
424 regs
->xcr1
|= XFRLEN1(wpf
- 1);
426 switch (params_format(params
)) {
427 case SNDRV_PCM_FORMAT_S16_LE
:
428 /* Set word lengths */
429 regs
->rcr2
|= RWDLEN2(OMAP_MCBSP_WORD_16
);
430 regs
->rcr1
|= RWDLEN1(OMAP_MCBSP_WORD_16
);
431 regs
->xcr2
|= XWDLEN2(OMAP_MCBSP_WORD_16
);
432 regs
->xcr1
|= XWDLEN1(OMAP_MCBSP_WORD_16
);
434 case SNDRV_PCM_FORMAT_S32_LE
:
435 /* Set word lengths */
436 regs
->rcr2
|= RWDLEN2(OMAP_MCBSP_WORD_32
);
437 regs
->rcr1
|= RWDLEN1(OMAP_MCBSP_WORD_32
);
438 regs
->xcr2
|= XWDLEN2(OMAP_MCBSP_WORD_32
);
439 regs
->xcr1
|= XWDLEN1(OMAP_MCBSP_WORD_32
);
442 /* Unsupported PCM format */
446 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
447 * by _counting_ BCLKs. Calculate frame size in BCLKs */
448 master
= mcbsp_data
->fmt
& SND_SOC_DAIFMT_MASTER_MASK
;
449 if (master
== SND_SOC_DAIFMT_CBS_CFS
) {
450 div
= mcbsp_data
->clk_div
? mcbsp_data
->clk_div
: 1;
451 framesize
= (mcbsp_data
->in_freq
/ div
) / params_rate(params
);
453 if (framesize
< wlen
* channels
) {
454 printk(KERN_ERR
"%s: not enough bandwidth for desired rate and "
455 "channels\n", __func__
);
459 framesize
= wlen
* channels
;
461 /* Set FS period and length in terms of bit clock periods */
463 case SND_SOC_DAIFMT_I2S
:
464 case SND_SOC_DAIFMT_LEFT_J
:
465 regs
->srgr2
|= FPER(framesize
- 1);
466 regs
->srgr1
|= FWID((framesize
>> 1) - 1);
468 case SND_SOC_DAIFMT_DSP_A
:
469 case SND_SOC_DAIFMT_DSP_B
:
470 regs
->srgr2
|= FPER(framesize
- 1);
471 regs
->srgr1
|= FWID(0);
475 omap_mcbsp_config(bus_id
, &mcbsp_data
->regs
);
476 mcbsp_data
->wlen
= wlen
;
477 mcbsp_data
->configured
= 1;
483 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
484 * cache is initialized here
486 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai
*cpu_dai
,
489 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
490 struct omap_mcbsp_reg_cfg
*regs
= &mcbsp_data
->regs
;
491 unsigned int temp_fmt
= fmt
;
493 if (mcbsp_data
->configured
)
496 mcbsp_data
->fmt
= fmt
;
497 memset(regs
, 0, sizeof(*regs
));
498 /* Generic McBSP register settings */
499 regs
->spcr2
|= XINTM(3) | FREE
;
500 regs
->spcr1
|= RINTM(3);
501 /* RFIG and XFIG are not defined in 34xx */
502 if (!cpu_is_omap34xx()) {
506 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
507 regs
->xccr
= DXENDLY(1) | XDMAEN
| XDISABLE
;
508 regs
->rccr
= RFULL_CYCLE
| RDMAEN
| RDISABLE
;
511 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
512 case SND_SOC_DAIFMT_I2S
:
513 /* 1-bit data delay */
514 regs
->rcr2
|= RDATDLY(1);
515 regs
->xcr2
|= XDATDLY(1);
517 case SND_SOC_DAIFMT_LEFT_J
:
518 /* 0-bit data delay */
519 regs
->rcr2
|= RDATDLY(0);
520 regs
->xcr2
|= XDATDLY(0);
521 regs
->spcr1
|= RJUST(2);
522 /* Invert FS polarity configuration */
523 temp_fmt
^= SND_SOC_DAIFMT_NB_IF
;
525 case SND_SOC_DAIFMT_DSP_A
:
526 /* 1-bit data delay */
527 regs
->rcr2
|= RDATDLY(1);
528 regs
->xcr2
|= XDATDLY(1);
529 /* Invert FS polarity configuration */
530 temp_fmt
^= SND_SOC_DAIFMT_NB_IF
;
532 case SND_SOC_DAIFMT_DSP_B
:
533 /* 0-bit data delay */
534 regs
->rcr2
|= RDATDLY(0);
535 regs
->xcr2
|= XDATDLY(0);
536 /* Invert FS polarity configuration */
537 temp_fmt
^= SND_SOC_DAIFMT_NB_IF
;
540 /* Unsupported data format */
544 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
545 case SND_SOC_DAIFMT_CBS_CFS
:
546 /* McBSP master. Set FS and bit clocks as outputs */
547 regs
->pcr0
|= FSXM
| FSRM
|
549 /* Sample rate generator drives the FS */
552 case SND_SOC_DAIFMT_CBM_CFM
:
556 /* Unsupported master/slave configuration */
560 /* Set bit clock (CLKX/CLKR) and FS polarities */
561 switch (temp_fmt
& SND_SOC_DAIFMT_INV_MASK
) {
562 case SND_SOC_DAIFMT_NB_NF
:
565 * FS active low. TX data driven on falling edge of bit clock
566 * and RX data sampled on rising edge of bit clock.
568 regs
->pcr0
|= FSXP
| FSRP
|
571 case SND_SOC_DAIFMT_NB_IF
:
572 regs
->pcr0
|= CLKXP
| CLKRP
;
574 case SND_SOC_DAIFMT_IB_NF
:
575 regs
->pcr0
|= FSXP
| FSRP
;
577 case SND_SOC_DAIFMT_IB_IF
:
586 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai
*cpu_dai
,
589 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
590 struct omap_mcbsp_reg_cfg
*regs
= &mcbsp_data
->regs
;
592 if (div_id
!= OMAP_MCBSP_CLKGDV
)
595 mcbsp_data
->clk_div
= div
;
596 regs
->srgr1
|= CLKGDV(div
- 1);
601 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data
*mcbsp_data
,
605 u16 reg
, reg_devconf1
= OMAP243X_CONTROL_DEVCONF1
;
607 if (cpu_class_is_omap1()) {
608 /* OMAP1's can use only external source clock */
609 if (unlikely(clk_id
== OMAP_MCBSP_SYSCLK_CLKS_FCLK
))
615 if (cpu_is_omap2420() && mcbsp_data
->bus_id
> 1)
618 if (cpu_is_omap343x())
619 reg_devconf1
= OMAP343X_CONTROL_DEVCONF1
;
621 switch (mcbsp_data
->bus_id
) {
623 reg
= OMAP2_CONTROL_DEVCONF0
;
627 reg
= OMAP2_CONTROL_DEVCONF0
;
646 if (clk_id
== OMAP_MCBSP_SYSCLK_CLKS_FCLK
)
647 omap_ctrl_writel(omap_ctrl_readl(reg
) & ~(1 << sel_bit
), reg
);
649 omap_ctrl_writel(omap_ctrl_readl(reg
) | (1 << sel_bit
), reg
);
654 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data
*mcbsp_data
,
657 int sel_bit
, set
= 0;
658 u16 reg
= OMAP2_CONTROL_DEVCONF0
;
660 if (cpu_class_is_omap1())
661 return -EINVAL
; /* TODO: Can this be implemented for OMAP1? */
662 if (mcbsp_data
->bus_id
!= 0)
666 case OMAP_MCBSP_CLKR_SRC_CLKX
:
668 case OMAP_MCBSP_CLKR_SRC_CLKR
:
671 case OMAP_MCBSP_FSR_SRC_FSX
:
673 case OMAP_MCBSP_FSR_SRC_FSR
:
681 omap_ctrl_writel(omap_ctrl_readl(reg
) | (1 << sel_bit
), reg
);
683 omap_ctrl_writel(omap_ctrl_readl(reg
) & ~(1 << sel_bit
), reg
);
688 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai
*cpu_dai
,
689 int clk_id
, unsigned int freq
,
692 struct omap_mcbsp_data
*mcbsp_data
= snd_soc_dai_get_drvdata(cpu_dai
);
693 struct omap_mcbsp_reg_cfg
*regs
= &mcbsp_data
->regs
;
696 mcbsp_data
->in_freq
= freq
;
699 case OMAP_MCBSP_SYSCLK_CLK
:
700 regs
->srgr2
|= CLKSM
;
702 case OMAP_MCBSP_SYSCLK_CLKS_FCLK
:
703 case OMAP_MCBSP_SYSCLK_CLKS_EXT
:
704 err
= omap_mcbsp_dai_set_clks_src(mcbsp_data
, clk_id
);
707 case OMAP_MCBSP_SYSCLK_CLKX_EXT
:
708 regs
->srgr2
|= CLKSM
;
709 case OMAP_MCBSP_SYSCLK_CLKR_EXT
:
710 regs
->pcr0
|= SCLKME
;
713 case OMAP_MCBSP_CLKR_SRC_CLKR
:
714 case OMAP_MCBSP_CLKR_SRC_CLKX
:
715 case OMAP_MCBSP_FSR_SRC_FSR
:
716 case OMAP_MCBSP_FSR_SRC_FSX
:
717 err
= omap_mcbsp_dai_set_rcvr_src(mcbsp_data
, clk_id
);
726 static struct snd_soc_dai_ops mcbsp_dai_ops
= {
727 .startup
= omap_mcbsp_dai_startup
,
728 .shutdown
= omap_mcbsp_dai_shutdown
,
729 .trigger
= omap_mcbsp_dai_trigger
,
730 .delay
= omap_mcbsp_dai_delay
,
731 .hw_params
= omap_mcbsp_dai_hw_params
,
732 .set_fmt
= omap_mcbsp_dai_set_dai_fmt
,
733 .set_clkdiv
= omap_mcbsp_dai_set_clkdiv
,
734 .set_sysclk
= omap_mcbsp_dai_set_dai_sysclk
,
737 static int mcbsp_dai_probe(struct snd_soc_dai
*dai
)
739 mcbsp_data
[dai
->id
].bus_id
= dai
->id
;
740 snd_soc_dai_set_drvdata(dai
, &mcbsp_data
[dai
->id
].bus_id
);
744 static struct snd_soc_dai_driver omap_mcbsp_dai
=
746 .probe
= mcbsp_dai_probe
,
750 .rates
= OMAP_MCBSP_RATES
,
751 .formats
= SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S32_LE
,
756 .rates
= OMAP_MCBSP_RATES
,
757 .formats
= SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S32_LE
,
759 .ops
= &mcbsp_dai_ops
,
762 int omap_mcbsp_st_info_volsw(struct snd_kcontrol
*kcontrol
,
763 struct snd_ctl_elem_info
*uinfo
)
765 struct soc_mixer_control
*mc
=
766 (struct soc_mixer_control
*)kcontrol
->private_value
;
770 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
772 uinfo
->value
.integer
.min
= min
;
773 uinfo
->value
.integer
.max
= max
;
777 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
779 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
780 struct snd_ctl_elem_value *uc) \
782 struct soc_mixer_control *mc = \
783 (struct soc_mixer_control *)kc->private_value; \
786 int val = uc->value.integer.value[0]; \
788 if (val < min || val > max) \
791 /* OMAP McBSP implementation uses index values 0..4 */ \
792 return omap_st_set_chgain((id)-1, channel, val); \
795 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
797 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
798 struct snd_ctl_elem_value *uc) \
802 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
805 uc->value.integer.value[0] = chgain; \
809 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
810 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
811 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
812 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
813 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
814 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
815 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
816 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
818 static int omap_mcbsp_st_put_mode(struct snd_kcontrol
*kcontrol
,
819 struct snd_ctl_elem_value
*ucontrol
)
821 struct soc_mixer_control
*mc
=
822 (struct soc_mixer_control
*)kcontrol
->private_value
;
823 u8 value
= ucontrol
->value
.integer
.value
[0];
825 if (value
== omap_st_is_enabled(mc
->reg
))
829 omap_st_enable(mc
->reg
);
831 omap_st_disable(mc
->reg
);
836 static int omap_mcbsp_st_get_mode(struct snd_kcontrol
*kcontrol
,
837 struct snd_ctl_elem_value
*ucontrol
)
839 struct soc_mixer_control
*mc
=
840 (struct soc_mixer_control
*)kcontrol
->private_value
;
842 ucontrol
->value
.integer
.value
[0] = omap_st_is_enabled(mc
->reg
);
846 static const struct snd_kcontrol_new omap_mcbsp2_st_controls
[] = {
847 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
848 omap_mcbsp_st_get_mode
, omap_mcbsp_st_put_mode
),
849 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
851 omap_mcbsp2_get_st_ch0_volume
,
852 omap_mcbsp2_set_st_ch0_volume
),
853 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
855 omap_mcbsp2_get_st_ch1_volume
,
856 omap_mcbsp2_set_st_ch1_volume
),
859 static const struct snd_kcontrol_new omap_mcbsp3_st_controls
[] = {
860 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
861 omap_mcbsp_st_get_mode
, omap_mcbsp_st_put_mode
),
862 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
864 omap_mcbsp3_get_st_ch0_volume
,
865 omap_mcbsp3_set_st_ch0_volume
),
866 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
868 omap_mcbsp3_get_st_ch1_volume
,
869 omap_mcbsp3_set_st_ch1_volume
),
872 int omap_mcbsp_st_add_controls(struct snd_soc_codec
*codec
, int mcbsp_id
)
874 if (!cpu_is_omap34xx())
878 case 1: /* McBSP 2 */
879 return snd_soc_add_controls(codec
, omap_mcbsp2_st_controls
,
880 ARRAY_SIZE(omap_mcbsp2_st_controls
));
881 case 2: /* McBSP 3 */
882 return snd_soc_add_controls(codec
, omap_mcbsp3_st_controls
,
883 ARRAY_SIZE(omap_mcbsp3_st_controls
));
890 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls
);
892 static __devinit
int asoc_mcbsp_probe(struct platform_device
*pdev
)
894 return snd_soc_register_dai(&pdev
->dev
, &omap_mcbsp_dai
);
897 static int __devexit
asoc_mcbsp_remove(struct platform_device
*pdev
)
899 snd_soc_unregister_dai(&pdev
->dev
);
903 static struct platform_driver asoc_mcbsp_driver
= {
905 .name
= "omap-mcbsp-dai",
906 .owner
= THIS_MODULE
,
909 .probe
= asoc_mcbsp_probe
,
910 .remove
= __devexit_p(asoc_mcbsp_remove
),
913 static int __init
snd_omap_mcbsp_init(void)
915 return platform_driver_register(&asoc_mcbsp_driver
);
917 module_init(snd_omap_mcbsp_init
);
919 static void __exit
snd_omap_mcbsp_exit(void)
921 platform_driver_unregister(&asoc_mcbsp_driver
);
923 module_exit(snd_omap_mcbsp_exit
);
925 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
926 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
927 MODULE_LICENSE("GPL");