src/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp

   1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This class prints an Hexagon MCInst to a .s file.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "HexagonAsmPrinter.h"
  15 #include "Hexagon.h"
  16 #include "HexagonInstPrinter.h"
  17 #include "MCTargetDesc/HexagonMCInst.h"
  18 #include "llvm/ADT/StringExtras.h"
  19 #include "llvm/MC/MCAsmInfo.h"
  20 #include "llvm/MC/MCExpr.h"
  21 #include "llvm/MC/MCInst.h"
  22 #include "llvm/Support/raw_ostream.h"
  23
  24 using namespace llvm;
  25
  26 #define DEBUG_TYPE "asm-printer"
  27
  28 #define GET_INSTRUCTION_NAME
  29 #include "HexagonGenAsmWriter.inc"
  30
  31 const char HexagonInstPrinter::PacketPadding = '\t';
  32 // Return the minimum value that a constant extendable operand can have
  33 // without being extended.
  34 static int getMinValue(uint64_t TSFlags) {
  35   unsigned isSigned =
  36       (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
  37   unsigned bits =
  38       (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
  39
  40   if (isSigned)
  41     return -1U << (bits - 1);
  42
  43   return 0;
  44 }
  45
  46 // Return the maximum value that a constant extendable operand can have
  47 // without being extended.
  48 static int getMaxValue(uint64_t TSFlags) {
  49   unsigned isSigned =
  50       (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
  51   unsigned bits =
  52       (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
  53
  54   if (isSigned)
  55     return ~(-1U << (bits - 1));
  56
  57   return ~(-1U << bits);
  58 }
  59
  60 // Return true if the instruction must be extended.
  61 static bool isExtended(uint64_t TSFlags) {
  62   return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
  63 }
  64
  65 // Currently just used in an assert statement
  66 static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;
  67 // Return true if the instruction may be extended based on the operand value.
  68 static bool isExtendable(uint64_t TSFlags) {
  69   return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
  70 }
  71
  72 StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
  73   return MII.getName(Opcode);
  74 }
  75
  76 StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {
  77   return getRegisterName(RegNo);
  78 }
  79
  80 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
  81                                    StringRef Annot) {
  82   printInst((const HexagonMCInst*)(MI), O, Annot);
  83 }
  84
  85 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,
  86                                    StringRef Annot) {
  87   const char startPacket = '{',
  88              endPacket = '}';
  89   // TODO: add outer HW loop when it's supported too.
  90   if (MI->getOpcode() == Hexagon::ENDLOOP0) {
  91     // Ending a harware loop is different from ending an regular packet.
  92     assert(MI->isPacketEnd() && "Loop-end must also end the packet");
  93
  94     if (MI->isPacketBegin()) {
  95       // There must be a packet to end a loop.
  96       // FIXME: when shuffling is always run, this shouldn't be needed.
  97       HexagonMCInst Nop;
  98       StringRef NoAnnot;
  99
 100       Nop.setOpcode (Hexagon::A2_nop);
 101       Nop.setPacketBegin (MI->isPacketBegin());
 102       printInst (&Nop, O, NoAnnot);
 103     }
 104
 105     // Close the packet.
 106     if (MI->isPacketEnd())
 107       O << PacketPadding << endPacket;
 108
 109     printInstruction(MI, O);
 110   }
 111   else {
 112     // Prefix the insn opening the packet.
 113     if (MI->isPacketBegin())
 114       O << PacketPadding << startPacket << '\n';
 115
 116     printInstruction(MI, O);
 117
 118     // Suffix the insn closing the packet.
 119     if (MI->isPacketEnd())
 120       // Suffix the packet in a new line always, since the GNU assembler has
 121       // issues with a closing brace on the same line as CONST{32,64}.
 122       O << '\n' << PacketPadding << endPacket;
 123   }
 124
 125   printAnnotation(O, Annot);
 126 }
 127
 128 void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
 129                                       raw_ostream &O) const {
 130   const MCOperand& MO = MI->getOperand(OpNo);
 131
 132   if (MO.isReg()) {
 133     O << getRegisterName(MO.getReg());
 134   } else if(MO.isExpr()) {
 135     O << *MO.getExpr();
 136   } else if(MO.isImm()) {
 137     printImmOperand(MI, OpNo, O);
 138   } else {
 139     llvm_unreachable("Unknown operand");
 140   }
 141 }
 142
 143 void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
 144                                          raw_ostream &O) const {
 145   const MCOperand& MO = MI->getOperand(OpNo);
 146
 147   if(MO.isExpr()) {
 148     O << *MO.getExpr();
 149   } else if(MO.isImm()) {
 150     O << MI->getOperand(OpNo).getImm();
 151   } else {
 152     llvm_unreachable("Unknown operand");
 153   }
 154 }
 155
 156 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
 157                                          raw_ostream &O) const {
 158   const MCOperand &MO = MI->getOperand(OpNo);
 159   const MCInstrDesc &MII = getMII().get(MI->getOpcode());
 160
 161   assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
 162          "Expecting an extendable operand");
 163
 164   if (MO.isExpr() || isExtended(MII.TSFlags)) {
 165     O << "#";
 166   } else if (MO.isImm()) {
 167     int ImmValue = MO.getImm();
 168     if (ImmValue < getMinValue(MII.TSFlags) ||
 169         ImmValue > getMaxValue(MII.TSFlags))
 170       O << "#";
 171   }
 172   printOperand(MI, OpNo, O);
 173 }
 174
 175 void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
 176                                     unsigned OpNo, raw_ostream &O) const {
 177   O << MI->getOperand(OpNo).getImm();
 178 }
 179
 180 void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
 181                                             raw_ostream &O) const {
 182   O << -MI->getOperand(OpNo).getImm();
 183 }
 184
 185 void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
 186                                              raw_ostream &O) const {
 187   O << -1;
 188 }
 189
 190 void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
 191                                            raw_ostream &O) const {
 192   const MCOperand& MO0 = MI->getOperand(OpNo);
 193   const MCOperand& MO1 = MI->getOperand(OpNo + 1);
 194
 195   O << getRegisterName(MO0.getReg());
 196   O << " + #" << MO1.getImm();
 197 }
 198
 199 void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
 200                                                 raw_ostream &O) const {
 201   const MCOperand& MO0 = MI->getOperand(OpNo);
 202   const MCOperand& MO1 = MI->getOperand(OpNo + 1);
 203
 204   O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();
 205 }
 206
 207 void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
 208                                             raw_ostream &O) const {
 209   assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
 210
 211   printOperand(MI, OpNo, O);
 212 }
 213
 214 void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
 215                                         raw_ostream &O) const {
 216   assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
 217
 218   printOperand(MI, OpNo, O);
 219 }
 220
 221 void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
 222                                            raw_ostream &O) const {
 223   assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
 224
 225   printOperand(MI, OpNo, O);
 226 }
 227
 228 void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
 229                                             raw_ostream &O) const {
 230   // Branches can take an immediate operand.  This is used by the branch
 231   // selection pass to print $+8, an eight byte displacement from the PC.
 232   llvm_unreachable("Unknown branch operand.");
 233 }
 234
 235 void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,
 236                                           raw_ostream &O) const {
 237 }
 238
 239 void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
 240                                              raw_ostream &O) const {
 241 }
 242
 243 void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
 244                                                raw_ostream &O) const {
 245 }
 246
 247 void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
 248                                      raw_ostream &O, bool hi) const {
 249   assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");
 250
 251   O << '#' << (hi ? "HI" : "LO") << "(#";
 252   printOperand(MI, OpNo, O);
 253   O << ')';
 254 }