src/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  61       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  62     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  63   }
  64
  65   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  66   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  67   bool hasMips32r6() const {
  68     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  69   }
  70
  71   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  72
  73   bool hasCOP3() const {
  74     // Only present in MIPS-I and MIPS-II
  75     return !hasMips32() && !hasMips3();
  76   }
  77
  78   /// getInstruction - See MCDisassembler.
  79   DecodeStatus getInstruction(MCInst &instr,
  80                               uint64_t &size,
  81                               const MemoryObject &region,
  82                               uint64_t address,
  83                               raw_ostream &vStream,
  84                               raw_ostream &cStream) const override;
  85 };
  86
  87
  88 /// Mips64Disassembler - a disasembler class for Mips64.
  89 class Mips64Disassembler : public MipsDisassemblerBase {
  90 public:
  91   /// Constructor     - Initializes the disassembler.
  92   ///
  93   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  94                      bool bigEndian) :
  95     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  96
  97   /// getInstruction - See MCDisassembler.
  98   DecodeStatus getInstruction(MCInst &instr,
  99                               uint64_t &size,
 100                               const MemoryObject &region,
 101                               uint64_t address,
 102                               raw_ostream &vStream,
 103                               raw_ostream &cStream) const override;
 104 };
 105
 106 } // end anonymous namespace
 107
 108 // Forward declare these because the autogenerated code will reference them.
 109 // Definitions are further down.
 110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 111                                              unsigned RegNo,
 112                                              uint64_t Address,
 113                                              const void *Decoder);
 114
 115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 116                                                  unsigned RegNo,
 117                                                  uint64_t Address,
 118                                                  const void *Decoder);
 119
 120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 121                                              unsigned RegNo,
 122                                              uint64_t Address,
 123                                              const void *Decoder);
 124
 125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 126                                            unsigned Insn,
 127                                            uint64_t Address,
 128                                            const void *Decoder);
 129
 130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 131                                             unsigned RegNo,
 132                                             uint64_t Address,
 133                                             const void *Decoder);
 134
 135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 136                                              unsigned RegNo,
 137                                              uint64_t Address,
 138                                              const void *Decoder);
 139
 140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 141                                              unsigned RegNo,
 142                                              uint64_t Address,
 143                                              const void *Decoder);
 144
 145 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 146                                            unsigned RegNo,
 147                                            uint64_t Address,
 148                                            const void *Decoder);
 149
 150 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 151                                            unsigned RegNo,
 152                                            uint64_t Address,
 153                                            const void *Decoder);
 154
 155 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 156                                              uint64_t Address,
 157                                              const void *Decoder);
 158
 159 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 160                                               unsigned Insn,
 161                                               uint64_t Address,
 162                                               const void *Decoder);
 163
 164 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 165                                               unsigned RegNo,
 166                                               uint64_t Address,
 167                                               const void *Decoder);
 168
 169 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 170                                                 unsigned RegNo,
 171                                                 uint64_t Address,
 172                                                 const void *Decoder);
 173
 174 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 175                                                unsigned RegNo,
 176                                                uint64_t Address,
 177                                                const void *Decoder);
 178
 179 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 180                                                unsigned RegNo,
 181                                                uint64_t Address,
 182                                                const void *Decoder);
 183
 184 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 185                                                unsigned RegNo,
 186                                                uint64_t Address,
 187                                                const void *Decoder);
 188
 189 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 190                                                unsigned RegNo,
 191                                                uint64_t Address,
 192                                                const void *Decoder);
 193
 194 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 195                                                unsigned RegNo,
 196                                                uint64_t Address,
 197                                                const void *Decoder);
 198
 199 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 200                                                unsigned RegNo,
 201                                                uint64_t Address,
 202                                                const void *Decoder);
 203
 204 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 205                                                unsigned RegNo,
 206                                                uint64_t Address,
 207                                                const void *Decoder);
 208
 209 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 210                                             unsigned RegNo,
 211                                             uint64_t Address,
 212                                             const void *Decoder);
 213
 214 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 215                                        unsigned Offset,
 216                                        uint64_t Address,
 217                                        const void *Decoder);
 218
 219 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 220                                      unsigned Insn,
 221                                      uint64_t Address,
 222                                      const void *Decoder);
 223
 224 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 225                                          unsigned Offset,
 226                                          uint64_t Address,
 227                                          const void *Decoder);
 228
 229 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 230                                          unsigned Offset,
 231                                          uint64_t Address,
 232                                          const void *Decoder);
 233
 234 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 235 // shifted left by 1 bit.
 236 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 237                                          unsigned Offset,
 238                                          uint64_t Address,
 239                                          const void *Decoder);
 240
 241 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 242 // shifted left by 1 bit.
 243 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 244                                        unsigned Insn,
 245                                        uint64_t Address,
 246                                        const void *Decoder);
 247
 248 static DecodeStatus DecodeMem(MCInst &Inst,
 249                               unsigned Insn,
 250                               uint64_t Address,
 251                               const void *Decoder);
 252
 253 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 254                               unsigned Insn,
 255                               uint64_t Address,
 256                               const void *Decoder);
 257
 258 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 259                                     uint64_t Address, const void *Decoder);
 260
 261 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 262                                      unsigned Insn,
 263                                      uint64_t Address,
 264                                      const void *Decoder);
 265
 266 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 267                                      unsigned Insn,
 268                                      uint64_t Address,
 269                                      const void *Decoder);
 270
 271 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 272                                uint64_t Address,
 273                                const void *Decoder);
 274
 275 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 276                                uint64_t Address,
 277                                const void *Decoder);
 278
 279 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 280                                uint64_t Address,
 281                                const void *Decoder);
 282
 283 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 284                                        unsigned Insn,
 285                                        uint64_t Address,
 286                                        const void *Decoder);
 287
 288 static DecodeStatus DecodeSimm16(MCInst &Inst,
 289                                  unsigned Insn,
 290                                  uint64_t Address,
 291                                  const void *Decoder);
 292
 293 // Decode the immediate field of an LSA instruction which
 294 // is off by one.
 295 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 296                                  unsigned Insn,
 297                                  uint64_t Address,
 298                                  const void *Decoder);
 299
 300 static DecodeStatus DecodeInsSize(MCInst &Inst,
 301                                   unsigned Insn,
 302                                   uint64_t Address,
 303                                   const void *Decoder);
 304
 305 static DecodeStatus DecodeExtSize(MCInst &Inst,
 306                                   unsigned Insn,
 307                                   uint64_t Address,
 308                                   const void *Decoder);
 309
 310 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 311                                      uint64_t Address, const void *Decoder);
 312
 313 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 314                                      uint64_t Address, const void *Decoder);
 315
 316 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 317 /// handle.
 318 template <typename InsnType>
 319 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 320                                    const void *Decoder);
 321
 322 template <typename InsnType>
 323 static DecodeStatus
 324 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 325                       const void *Decoder);
 326
 327 template <typename InsnType>
 328 static DecodeStatus
 329 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 330                        const void *Decoder);
 331
 332 template <typename InsnType>
 333 static DecodeStatus
 334 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 335                        const void *Decoder);
 336
 337 template <typename InsnType>
 338 static DecodeStatus
 339 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 340                        const void *Decoder);
 341
 342 template <typename InsnType>
 343 static DecodeStatus
 344 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 345                       const void *Decoder);
 346
 347 template <typename InsnType>
 348 static DecodeStatus
 349 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 350                        const void *Decoder);
 351
 352 namespace llvm {
 353 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 354               TheMips64elTarget;
 355 }
 356
 357 static MCDisassembler *createMipsDisassembler(
 358                        const Target &T,
 359                        const MCSubtargetInfo &STI,
 360                        MCContext &Ctx) {
 361   return new MipsDisassembler(STI, Ctx, true);
 362 }
 363
 364 static MCDisassembler *createMipselDisassembler(
 365                        const Target &T,
 366                        const MCSubtargetInfo &STI,
 367                        MCContext &Ctx) {
 368   return new MipsDisassembler(STI, Ctx, false);
 369 }
 370
 371 static MCDisassembler *createMips64Disassembler(
 372                        const Target &T,
 373                        const MCSubtargetInfo &STI,
 374                        MCContext &Ctx) {
 375   return new Mips64Disassembler(STI, Ctx, true);
 376 }
 377
 378 static MCDisassembler *createMips64elDisassembler(
 379                        const Target &T,
 380                        const MCSubtargetInfo &STI,
 381                        MCContext &Ctx) {
 382   return new Mips64Disassembler(STI, Ctx, false);
 383 }
 384
 385 extern "C" void LLVMInitializeMipsDisassembler() {
 386   // Register the disassembler.
 387   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 388                                          createMipsDisassembler);
 389   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 390                                          createMipselDisassembler);
 391   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 392                                          createMips64Disassembler);
 393   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 394                                          createMips64elDisassembler);
 395 }
 396
 397 #include "MipsGenDisassemblerTables.inc"
 398
 399 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 400   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 401   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 402   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 403 }
 404
 405 template <typename InsnType>
 406 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 407                                    const void *Decoder) {
 408   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 409   // The size of the n field depends on the element size
 410   // The register class also depends on this.
 411   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 412   unsigned NSize = 0;
 413   DecodeFN RegDecoder = nullptr;
 414   if ((tmp & 0x18) == 0x00) { // INSVE_B
 415     NSize = 4;
 416     RegDecoder = DecodeMSA128BRegisterClass;
 417   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 418     NSize = 3;
 419     RegDecoder = DecodeMSA128HRegisterClass;
 420   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 421     NSize = 2;
 422     RegDecoder = DecodeMSA128WRegisterClass;
 423   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 424     NSize = 1;
 425     RegDecoder = DecodeMSA128DRegisterClass;
 426   } else
 427     llvm_unreachable("Invalid encoding");
 428
 429   assert(NSize != 0 && RegDecoder != nullptr);
 430
 431   // $wd
 432   tmp = fieldFromInstruction(insn, 6, 5);
 433   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 434     return MCDisassembler::Fail;
 435   // $wd_in
 436   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 437     return MCDisassembler::Fail;
 438   // $n
 439   tmp = fieldFromInstruction(insn, 16, NSize);
 440   MI.addOperand(MCOperand::CreateImm(tmp));
 441   // $ws
 442   tmp = fieldFromInstruction(insn, 11, 5);
 443   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 444     return MCDisassembler::Fail;
 445   // $n2
 446   MI.addOperand(MCOperand::CreateImm(0));
 447
 448   return MCDisassembler::Success;
 449 }
 450
 451 template <typename InsnType>
 452 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 453                                           uint64_t Address,
 454                                           const void *Decoder) {
 455   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 456   // (otherwise we would have matched the ADDI instruction from the earlier
 457   // ISA's instead).
 458   //
 459   // We have:
 460   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 461   //      BOVC if rs >= rt
 462   //      BEQZALC if rs == 0 && rt != 0
 463   //      BEQC if rs < rt && rs != 0
 464
 465   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 466   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 467   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 468   bool HasRs = false;
 469
 470   if (Rs >= Rt) {
 471     MI.setOpcode(Mips::BOVC);
 472     HasRs = true;
 473   } else if (Rs != 0 && Rs < Rt) {
 474     MI.setOpcode(Mips::BEQC);
 475     HasRs = true;
 476   } else
 477     MI.setOpcode(Mips::BEQZALC);
 478
 479   if (HasRs)
 480     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 481                                        Rs)));
 482
 483   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 484                                      Rt)));
 485   MI.addOperand(MCOperand::CreateImm(Imm));
 486
 487   return MCDisassembler::Success;
 488 }
 489
 490 template <typename InsnType>
 491 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 492                                            uint64_t Address,
 493                                            const void *Decoder) {
 494   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 495   // (otherwise we would have matched the ADDI instruction from the earlier
 496   // ISA's instead).
 497   //
 498   // We have:
 499   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 500   //      BNVC if rs >= rt
 501   //      BNEZALC if rs == 0 && rt != 0
 502   //      BNEC if rs < rt && rs != 0
 503
 504   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 505   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 506   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 507   bool HasRs = false;
 508
 509   if (Rs >= Rt) {
 510     MI.setOpcode(Mips::BNVC);
 511     HasRs = true;
 512   } else if (Rs != 0 && Rs < Rt) {
 513     MI.setOpcode(Mips::BNEC);
 514     HasRs = true;
 515   } else
 516     MI.setOpcode(Mips::BNEZALC);
 517
 518   if (HasRs)
 519     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 520                                        Rs)));
 521
 522   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 523                                      Rt)));
 524   MI.addOperand(MCOperand::CreateImm(Imm));
 525
 526   return MCDisassembler::Success;
 527 }
 528
 529 template <typename InsnType>
 530 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 531                                            uint64_t Address,
 532                                            const void *Decoder) {
 533   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 534   // (otherwise we would have matched the BLEZL instruction from the earlier
 535   // ISA's instead).
 536   //
 537   // We have:
 538   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 539   //      Invalid if rs == 0
 540   //      BLEZC   if rs == 0  && rt != 0
 541   //      BGEZC   if rs == rt && rt != 0
 542   //      BGEC    if rs != rt && rs != 0  && rt != 0
 543
 544   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 545   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 546   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 547   bool HasRs = false;
 548
 549   if (Rt == 0)
 550     return MCDisassembler::Fail;
 551   else if (Rs == 0)
 552     MI.setOpcode(Mips::BLEZC);
 553   else if (Rs == Rt)
 554     MI.setOpcode(Mips::BGEZC);
 555   else {
 556     HasRs = true;
 557     MI.setOpcode(Mips::BGEC);
 558   }
 559
 560   if (HasRs)
 561     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 562                                        Rs)));
 563
 564   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 565                                      Rt)));
 566
 567   MI.addOperand(MCOperand::CreateImm(Imm));
 568
 569   return MCDisassembler::Success;
 570 }
 571
 572 template <typename InsnType>
 573 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 574                                            uint64_t Address,
 575                                            const void *Decoder) {
 576   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 577   // (otherwise we would have matched the BGTZL instruction from the earlier
 578   // ISA's instead).
 579   //
 580   // We have:
 581   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 582   //      Invalid if rs == 0
 583   //      BGTZC   if rs == 0  && rt != 0
 584   //      BLTZC   if rs == rt && rt != 0
 585   //      BLTC    if rs != rt && rs != 0  && rt != 0
 586
 587   bool HasRs = false;
 588
 589   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 590   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 591   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 592
 593   if (Rt == 0)
 594     return MCDisassembler::Fail;
 595   else if (Rs == 0)
 596     MI.setOpcode(Mips::BGTZC);
 597   else if (Rs == Rt)
 598     MI.setOpcode(Mips::BLTZC);
 599   else {
 600     MI.setOpcode(Mips::BLTC);
 601     HasRs = true;
 602   }
 603
 604   if (HasRs)
 605     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 606                                               Rs)));
 607
 608   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 609                                      Rt)));
 610
 611   MI.addOperand(MCOperand::CreateImm(Imm));
 612
 613   return MCDisassembler::Success;
 614 }
 615
 616 template <typename InsnType>
 617 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 618                                           uint64_t Address,
 619                                           const void *Decoder) {
 620   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 621   // (otherwise we would have matched the BGTZ instruction from the earlier
 622   // ISA's instead).
 623   //
 624   // We have:
 625   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 626   //      BGTZ    if rt == 0
 627   //      BGTZALC if rs == 0 && rt != 0
 628   //      BLTZALC if rs != 0 && rs == rt
 629   //      BLTUC   if rs != 0 && rs != rt
 630
 631   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 632   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 633   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 634   bool HasRs = false;
 635   bool HasRt = false;
 636
 637   if (Rt == 0) {
 638     MI.setOpcode(Mips::BGTZ);
 639     HasRs = true;
 640   } else if (Rs == 0) {
 641     MI.setOpcode(Mips::BGTZALC);
 642     HasRt = true;
 643   } else if (Rs == Rt) {
 644     MI.setOpcode(Mips::BLTZALC);
 645     HasRs = true;
 646   } else {
 647     MI.setOpcode(Mips::BLTUC);
 648     HasRs = true;
 649     HasRt = true;
 650   }
 651
 652   if (HasRs)
 653     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 654                                        Rs)));
 655
 656   if (HasRt)
 657     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 658                                        Rt)));
 659
 660   MI.addOperand(MCOperand::CreateImm(Imm));
 661
 662   return MCDisassembler::Success;
 663 }
 664
 665 template <typename InsnType>
 666 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 667                                            uint64_t Address,
 668                                            const void *Decoder) {
 669   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 670   // (otherwise we would have matched the BLEZL instruction from the earlier
 671   // ISA's instead).
 672   //
 673   // We have:
 674   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 675   //      Invalid   if rs == 0
 676   //      BLEZALC   if rs == 0  && rt != 0
 677   //      BGEZALC   if rs == rt && rt != 0
 678   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 679
 680   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 681   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 682   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 683   bool HasRs = false;
 684
 685   if (Rt == 0)
 686     return MCDisassembler::Fail;
 687   else if (Rs == 0)
 688     MI.setOpcode(Mips::BLEZALC);
 689   else if (Rs == Rt)
 690     MI.setOpcode(Mips::BGEZALC);
 691   else {
 692     HasRs = true;
 693     MI.setOpcode(Mips::BGEUC);
 694   }
 695
 696   if (HasRs)
 697     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 698                                        Rs)));
 699   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 700                                      Rt)));
 701
 702   MI.addOperand(MCOperand::CreateImm(Imm));
 703
 704   return MCDisassembler::Success;
 705 }
 706
 707   /// readInstruction - read four bytes from the MemoryObject
 708   /// and return 32 bit word sorted according to the given endianess
 709 static DecodeStatus readInstruction32(const MemoryObject &region,
 710                                       uint64_t address,
 711                                       uint64_t &size,
 712                                       uint32_t &insn,
 713                                       bool isBigEndian,
 714                                       bool IsMicroMips) {
 715   uint8_t Bytes[4];
 716
 717   // We want to read exactly 4 Bytes of data.
 718   if (region.readBytes(address, 4, Bytes) == -1) {
 719     size = 0;
 720     return MCDisassembler::Fail;
 721   }
 722
 723   if (isBigEndian) {
 724     // Encoded as a big-endian 32-bit word in the stream.
 725     insn = (Bytes[3] <<  0) |
 726            (Bytes[2] <<  8) |
 727            (Bytes[1] << 16) |
 728            (Bytes[0] << 24);
 729   }
 730   else {
 731     // Encoded as a small-endian 32-bit word in the stream.
 732     // Little-endian byte ordering:
 733     //   mips32r2:   4 | 3 | 2 | 1
 734     //   microMIPS:  2 | 1 | 4 | 3
 735     if (IsMicroMips) {
 736       insn = (Bytes[2] <<  0) |
 737              (Bytes[3] <<  8) |
 738              (Bytes[0] << 16) |
 739              (Bytes[1] << 24);
 740     } else {
 741       insn = (Bytes[0] <<  0) |
 742              (Bytes[1] <<  8) |
 743              (Bytes[2] << 16) |
 744              (Bytes[3] << 24);
 745     }
 746   }
 747
 748   return MCDisassembler::Success;
 749 }
 750
 751 DecodeStatus
 752 MipsDisassembler::getInstruction(MCInst &instr,
 753                                  uint64_t &Size,
 754                                  const MemoryObject &Region,
 755                                  uint64_t Address,
 756                                  raw_ostream &vStream,
 757                                  raw_ostream &cStream) const {
 758   uint32_t Insn;
 759
 760   DecodeStatus Result = readInstruction32(Region, Address, Size,
 761                                           Insn, isBigEndian, IsMicroMips);
 762   if (Result == MCDisassembler::Fail)
 763     return MCDisassembler::Fail;
 764
 765   if (IsMicroMips) {
 766     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
 767     // Calling the auto-generated decoder function.
 768     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 769                                this, STI);
 770     if (Result != MCDisassembler::Fail) {
 771       Size = 4;
 772       return Result;
 773     }
 774     return MCDisassembler::Fail;
 775   }
 776
 777   if (hasCOP3()) {
 778     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 779     Result =
 780         decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
 781     if (Result != MCDisassembler::Fail) {
 782       Size = 4;
 783       return Result;
 784     }
 785   }
 786
 787   if (hasMips32r6() && isGP64()) {
 788     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 789     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
 790                                Address, this, STI);
 791     if (Result != MCDisassembler::Fail) {
 792       Size = 4;
 793       return Result;
 794     }
 795   }
 796
 797   if (hasMips32r6()) {
 798     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 799     Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
 800                                Address, this, STI);
 801     if (Result != MCDisassembler::Fail) {
 802       Size = 4;
 803       return Result;
 804     }
 805   }
 806
 807   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 808   // Calling the auto-generated decoder function.
 809   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 810                              this, STI);
 811   if (Result != MCDisassembler::Fail) {
 812     Size = 4;
 813     return Result;
 814   }
 815
 816   return MCDisassembler::Fail;
 817 }
 818
 819 DecodeStatus
 820 Mips64Disassembler::getInstruction(MCInst &instr,
 821                                    uint64_t &Size,
 822                                    const MemoryObject &Region,
 823                                    uint64_t Address,
 824                                    raw_ostream &vStream,
 825                                    raw_ostream &cStream) const {
 826   uint32_t Insn;
 827
 828   DecodeStatus Result = readInstruction32(Region, Address, Size,
 829                                           Insn, isBigEndian, false);
 830   if (Result == MCDisassembler::Fail)
 831     return MCDisassembler::Fail;
 832
 833   // Calling the auto-generated decoder function.
 834   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 835                              this, STI);
 836   if (Result != MCDisassembler::Fail) {
 837     Size = 4;
 838     return Result;
 839   }
 840   // If we fail to decode in Mips64 decoder space we can try in Mips32
 841   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 842                              this, STI);
 843   if (Result != MCDisassembler::Fail) {
 844     Size = 4;
 845     return Result;
 846   }
 847
 848   return MCDisassembler::Fail;
 849 }
 850
 851 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 852                                                  unsigned RegNo,
 853                                                  uint64_t Address,
 854                                                  const void *Decoder) {
 855
 856   return MCDisassembler::Fail;
 857
 858 }
 859
 860 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 861                                              unsigned RegNo,
 862                                              uint64_t Address,
 863                                              const void *Decoder) {
 864
 865   if (RegNo > 31)
 866     return MCDisassembler::Fail;
 867
 868   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 869   Inst.addOperand(MCOperand::CreateReg(Reg));
 870   return MCDisassembler::Success;
 871 }
 872
 873 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 874                                              unsigned RegNo,
 875                                              uint64_t Address,
 876                                              const void *Decoder) {
 877   if (RegNo > 31)
 878     return MCDisassembler::Fail;
 879   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 880   Inst.addOperand(MCOperand::CreateReg(Reg));
 881   return MCDisassembler::Success;
 882 }
 883
 884 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 885                                            unsigned RegNo,
 886                                            uint64_t Address,
 887                                            const void *Decoder) {
 888   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 889     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 890
 891   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 892 }
 893
 894 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 895                                             unsigned RegNo,
 896                                             uint64_t Address,
 897                                             const void *Decoder) {
 898   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 899 }
 900
 901 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 902                                              unsigned RegNo,
 903                                              uint64_t Address,
 904                                              const void *Decoder) {
 905   if (RegNo > 31)
 906     return MCDisassembler::Fail;
 907
 908   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 909   Inst.addOperand(MCOperand::CreateReg(Reg));
 910   return MCDisassembler::Success;
 911 }
 912
 913 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 914                                              unsigned RegNo,
 915                                              uint64_t Address,
 916                                              const void *Decoder) {
 917   if (RegNo > 31)
 918     return MCDisassembler::Fail;
 919
 920   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 921   Inst.addOperand(MCOperand::CreateReg(Reg));
 922   return MCDisassembler::Success;
 923 }
 924
 925 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 926                                            unsigned RegNo,
 927                                            uint64_t Address,
 928                                            const void *Decoder) {
 929   if (RegNo > 31)
 930     return MCDisassembler::Fail;
 931   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 932   Inst.addOperand(MCOperand::CreateReg(Reg));
 933   return MCDisassembler::Success;
 934 }
 935
 936 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 937                                            unsigned RegNo,
 938                                            uint64_t Address,
 939                                            const void *Decoder) {
 940   if (RegNo > 7)
 941     return MCDisassembler::Fail;
 942   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 943   Inst.addOperand(MCOperand::CreateReg(Reg));
 944   return MCDisassembler::Success;
 945 }
 946
 947 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 948                                              uint64_t Address,
 949                                              const void *Decoder) {
 950   if (RegNo > 31)
 951     return MCDisassembler::Fail;
 952
 953   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 954   Inst.addOperand(MCOperand::CreateReg(Reg));
 955   return MCDisassembler::Success;
 956 }
 957
 958 static DecodeStatus DecodeMem(MCInst &Inst,
 959                               unsigned Insn,
 960                               uint64_t Address,
 961                               const void *Decoder) {
 962   int Offset = SignExtend32<16>(Insn & 0xffff);
 963   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 964   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 965
 966   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 967   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 968
 969   if(Inst.getOpcode() == Mips::SC){
 970     Inst.addOperand(MCOperand::CreateReg(Reg));
 971   }
 972
 973   Inst.addOperand(MCOperand::CreateReg(Reg));
 974   Inst.addOperand(MCOperand::CreateReg(Base));
 975   Inst.addOperand(MCOperand::CreateImm(Offset));
 976
 977   return MCDisassembler::Success;
 978 }
 979
 980 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 981                               unsigned Insn,
 982                               uint64_t Address,
 983                               const void *Decoder) {
 984   int Offset = SignExtend32<16>(Insn & 0xffff);
 985   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
 986   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 987
 988   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 989
 990   Inst.addOperand(MCOperand::CreateReg(Base));
 991   Inst.addOperand(MCOperand::CreateImm(Offset));
 992   Inst.addOperand(MCOperand::CreateImm(Hint));
 993
 994   return MCDisassembler::Success;
 995 }
 996
 997 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 998                                     uint64_t Address, const void *Decoder) {
 999   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1000   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1001   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1002
1003   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1004   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1005
1006   Inst.addOperand(MCOperand::CreateReg(Reg));
1007   Inst.addOperand(MCOperand::CreateReg(Base));
1008
1009   // The immediate field of an LD/ST instruction is scaled which means it must
1010   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1011   // data format.
1012   // .b - 1 byte
1013   // .h - 2 bytes
1014   // .w - 4 bytes
1015   // .d - 8 bytes
1016   switch(Inst.getOpcode())
1017   {
1018   default:
1019     assert (0 && "Unexpected instruction");
1020     return MCDisassembler::Fail;
1021     break;
1022   case Mips::LD_B:
1023   case Mips::ST_B:
1024     Inst.addOperand(MCOperand::CreateImm(Offset));
1025     break;
1026   case Mips::LD_H:
1027   case Mips::ST_H:
1028     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1029     break;
1030   case Mips::LD_W:
1031   case Mips::ST_W:
1032     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1033     break;
1034   case Mips::LD_D:
1035   case Mips::ST_D:
1036     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1037     break;
1038   }
1039
1040   return MCDisassembler::Success;
1041 }
1042
1043 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1044                                      unsigned Insn,
1045                                      uint64_t Address,
1046                                      const void *Decoder) {
1047   int Offset = SignExtend32<12>(Insn & 0x0fff);
1048   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1049   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1050
1051   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1052   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1053
1054   if (Inst.getOpcode() == Mips::SC_MM)
1055     Inst.addOperand(MCOperand::CreateReg(Reg));
1056
1057   Inst.addOperand(MCOperand::CreateReg(Reg));
1058   Inst.addOperand(MCOperand::CreateReg(Base));
1059   Inst.addOperand(MCOperand::CreateImm(Offset));
1060
1061   return MCDisassembler::Success;
1062 }
1063
1064 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1065                                      unsigned Insn,
1066                                      uint64_t Address,
1067                                      const void *Decoder) {
1068   int Offset = SignExtend32<16>(Insn & 0xffff);
1069   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1070   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1071
1072   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1073   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1074
1075   Inst.addOperand(MCOperand::CreateReg(Reg));
1076   Inst.addOperand(MCOperand::CreateReg(Base));
1077   Inst.addOperand(MCOperand::CreateImm(Offset));
1078
1079   return MCDisassembler::Success;
1080 }
1081
1082 static DecodeStatus DecodeFMem(MCInst &Inst,
1083                                unsigned Insn,
1084                                uint64_t Address,
1085                                const void *Decoder) {
1086   int Offset = SignExtend32<16>(Insn & 0xffff);
1087   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1088   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1089
1090   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1091   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1092
1093   Inst.addOperand(MCOperand::CreateReg(Reg));
1094   Inst.addOperand(MCOperand::CreateReg(Base));
1095   Inst.addOperand(MCOperand::CreateImm(Offset));
1096
1097   return MCDisassembler::Success;
1098 }
1099
1100 static DecodeStatus DecodeFMem2(MCInst &Inst,
1101                                unsigned Insn,
1102                                uint64_t Address,
1103                                const void *Decoder) {
1104   int Offset = SignExtend32<16>(Insn & 0xffff);
1105   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1106   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1107
1108   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1109   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1110
1111   Inst.addOperand(MCOperand::CreateReg(Reg));
1112   Inst.addOperand(MCOperand::CreateReg(Base));
1113   Inst.addOperand(MCOperand::CreateImm(Offset));
1114
1115   return MCDisassembler::Success;
1116 }
1117
1118 static DecodeStatus DecodeFMem3(MCInst &Inst,
1119                                unsigned Insn,
1120                                uint64_t Address,
1121                                const void *Decoder) {
1122   int Offset = SignExtend32<16>(Insn & 0xffff);
1123   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1124   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1125
1126   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1127   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1128
1129   Inst.addOperand(MCOperand::CreateReg(Reg));
1130   Inst.addOperand(MCOperand::CreateReg(Base));
1131   Inst.addOperand(MCOperand::CreateImm(Offset));
1132
1133   return MCDisassembler::Success;
1134 }
1135
1136 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1137                                        unsigned Insn,
1138                                        uint64_t Address,
1139                                        const void *Decoder) {
1140   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1141   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1142   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1143
1144   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1145   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1146
1147   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1148     Inst.addOperand(MCOperand::CreateReg(Rt));
1149   }
1150
1151   Inst.addOperand(MCOperand::CreateReg(Rt));
1152   Inst.addOperand(MCOperand::CreateReg(Base));
1153   Inst.addOperand(MCOperand::CreateImm(Offset));
1154
1155   return MCDisassembler::Success;
1156 }
1157
1158 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1159                                               unsigned RegNo,
1160                                               uint64_t Address,
1161                                               const void *Decoder) {
1162   // Currently only hardware register 29 is supported.
1163   if (RegNo != 29)
1164     return  MCDisassembler::Fail;
1165   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1166   return MCDisassembler::Success;
1167 }
1168
1169 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1170                                               unsigned RegNo,
1171                                               uint64_t Address,
1172                                               const void *Decoder) {
1173   if (RegNo > 30 || RegNo %2)
1174     return MCDisassembler::Fail;
1175
1176   ;
1177   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1178   Inst.addOperand(MCOperand::CreateReg(Reg));
1179   return MCDisassembler::Success;
1180 }
1181
1182 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1183                                                 unsigned RegNo,
1184                                                 uint64_t Address,
1185                                                 const void *Decoder) {
1186   if (RegNo >= 4)
1187     return MCDisassembler::Fail;
1188
1189   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1190   Inst.addOperand(MCOperand::CreateReg(Reg));
1191   return MCDisassembler::Success;
1192 }
1193
1194 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1195                                                unsigned RegNo,
1196                                                uint64_t Address,
1197                                                const void *Decoder) {
1198   if (RegNo >= 4)
1199     return MCDisassembler::Fail;
1200
1201   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1202   Inst.addOperand(MCOperand::CreateReg(Reg));
1203   return MCDisassembler::Success;
1204 }
1205
1206 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1207                                                unsigned RegNo,
1208                                                uint64_t Address,
1209                                                const void *Decoder) {
1210   if (RegNo >= 4)
1211     return MCDisassembler::Fail;
1212
1213   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1214   Inst.addOperand(MCOperand::CreateReg(Reg));
1215   return MCDisassembler::Success;
1216 }
1217
1218 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1219                                                unsigned RegNo,
1220                                                uint64_t Address,
1221                                                const void *Decoder) {
1222   if (RegNo > 31)
1223     return MCDisassembler::Fail;
1224
1225   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1226   Inst.addOperand(MCOperand::CreateReg(Reg));
1227   return MCDisassembler::Success;
1228 }
1229
1230 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1231                                                unsigned RegNo,
1232                                                uint64_t Address,
1233                                                const void *Decoder) {
1234   if (RegNo > 31)
1235     return MCDisassembler::Fail;
1236
1237   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1238   Inst.addOperand(MCOperand::CreateReg(Reg));
1239   return MCDisassembler::Success;
1240 }
1241
1242 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1243                                                unsigned RegNo,
1244                                                uint64_t Address,
1245                                                const void *Decoder) {
1246   if (RegNo > 31)
1247     return MCDisassembler::Fail;
1248
1249   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1250   Inst.addOperand(MCOperand::CreateReg(Reg));
1251   return MCDisassembler::Success;
1252 }
1253
1254 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1255                                                unsigned RegNo,
1256                                                uint64_t Address,
1257                                                const void *Decoder) {
1258   if (RegNo > 31)
1259     return MCDisassembler::Fail;
1260
1261   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1262   Inst.addOperand(MCOperand::CreateReg(Reg));
1263   return MCDisassembler::Success;
1264 }
1265
1266 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1267                                                unsigned RegNo,
1268                                                uint64_t Address,
1269                                                const void *Decoder) {
1270   if (RegNo > 7)
1271     return MCDisassembler::Fail;
1272
1273   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1274   Inst.addOperand(MCOperand::CreateReg(Reg));
1275   return MCDisassembler::Success;
1276 }
1277
1278 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1279                                             unsigned RegNo,
1280                                             uint64_t Address,
1281                                             const void *Decoder) {
1282   if (RegNo > 31)
1283     return MCDisassembler::Fail;
1284
1285   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1286   Inst.addOperand(MCOperand::CreateReg(Reg));
1287   return MCDisassembler::Success;
1288 }
1289
1290 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1291                                        unsigned Offset,
1292                                        uint64_t Address,
1293                                        const void *Decoder) {
1294   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1295   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1296   return MCDisassembler::Success;
1297 }
1298
1299 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1300                                      unsigned Insn,
1301                                      uint64_t Address,
1302                                      const void *Decoder) {
1303
1304   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1305   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1306   return MCDisassembler::Success;
1307 }
1308
1309 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1310                                          unsigned Offset,
1311                                          uint64_t Address,
1312                                          const void *Decoder) {
1313   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1314
1315   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1316   return MCDisassembler::Success;
1317 }
1318
1319 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1320                                          unsigned Offset,
1321                                          uint64_t Address,
1322                                          const void *Decoder) {
1323   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1324
1325   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1326   return MCDisassembler::Success;
1327 }
1328
1329 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1330                                          unsigned Offset,
1331                                          uint64_t Address,
1332                                          const void *Decoder) {
1333   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1334   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1335   return MCDisassembler::Success;
1336 }
1337
1338 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1339                                        unsigned Insn,
1340                                        uint64_t Address,
1341                                        const void *Decoder) {
1342   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1343   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1344   return MCDisassembler::Success;
1345 }
1346
1347 static DecodeStatus DecodeSimm16(MCInst &Inst,
1348                                  unsigned Insn,
1349                                  uint64_t Address,
1350                                  const void *Decoder) {
1351   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1352   return MCDisassembler::Success;
1353 }
1354
1355 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1356                                  unsigned Insn,
1357                                  uint64_t Address,
1358                                  const void *Decoder) {
1359   // We add one to the immediate field as it was encoded as 'imm - 1'.
1360   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1361   return MCDisassembler::Success;
1362 }
1363
1364 static DecodeStatus DecodeInsSize(MCInst &Inst,
1365                                   unsigned Insn,
1366                                   uint64_t Address,
1367                                   const void *Decoder) {
1368   // First we need to grab the pos(lsb) from MCInst.
1369   int Pos = Inst.getOperand(2).getImm();
1370   int Size = (int) Insn - Pos + 1;
1371   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1372   return MCDisassembler::Success;
1373 }
1374
1375 static DecodeStatus DecodeExtSize(MCInst &Inst,
1376                                   unsigned Insn,
1377                                   uint64_t Address,
1378                                   const void *Decoder) {
1379   int Size = (int) Insn  + 1;
1380   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1381   return MCDisassembler::Success;
1382 }
1383
1384 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1385                                      uint64_t Address, const void *Decoder) {
1386   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1387   return MCDisassembler::Success;
1388 }
1389
1390 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1391                                      uint64_t Address, const void *Decoder) {
1392   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1393   return MCDisassembler::Success;
1394 }