src/llvm/lib/Target/Mips/MipsDSPInstrFormats.td

   1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 def HasDSP : Predicate<"Subtarget.hasDSP()">,
  11              AssemblerPredicate<"FeatureDSP">;
  12 def HasDSPR2 : Predicate<"Subtarget.hasDSPR2()">,
  13                AssemblerPredicate<"FeatureDSPR2">;
  14
  15 // Fields.
  16 class Field6<bits<6> val> {
  17   bits<6> V = val;
  18 }
  19
  20 def SPECIAL3_OPCODE : Field6<0b011111>;
  21 def REGIMM_OPCODE : Field6<0b000001>;
  22
  23 class DSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
  24   let Predicates = [HasDSP];
  25 }
  26
  27 class PseudoDSP<dag outs, dag ins, list<dag> pattern,
  28                 InstrItinClass itin = IIPseudo>:
  29   MipsPseudo<outs, ins, pattern, itin> {
  30   let Predicates = [HasDSP];
  31 }
  32
  33 // ADDU.QB sub-class format.
  34 class ADDU_QB_FMT<bits<5> op> : DSPInst {
  35   bits<5> rd;
  36   bits<5> rs;
  37   bits<5> rt;
  38
  39   let Opcode = SPECIAL3_OPCODE.V;
  40
  41   let Inst{25-21} = rs;
  42   let Inst{20-16} = rt;
  43   let Inst{15-11} = rd;
  44   let Inst{10-6}  = op;
  45   let Inst{5-0}   = 0b010000;
  46 }
  47
  48 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
  49   bits<5> rd;
  50   bits<5> rs;
  51
  52   let Opcode = SPECIAL3_OPCODE.V;
  53
  54   let Inst{25-21} = rs;
  55   let Inst{20-16} = 0;
  56   let Inst{15-11} = rd;
  57   let Inst{10-6}  = op;
  58   let Inst{5-0}   = 0b010000;
  59 }
  60
  61 // CMPU.EQ.QB sub-class format.
  62 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
  63   bits<5> rs;
  64   bits<5> rt;
  65
  66   let Opcode = SPECIAL3_OPCODE.V;
  67
  68   let Inst{25-21} = rs;
  69   let Inst{20-16} = rt;
  70   let Inst{15-11} = 0;
  71   let Inst{10-6}  = op;
  72   let Inst{5-0}   = 0b010001;
  73 }
  74
  75 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
  76   bits<5> rs;
  77   bits<5> rt;
  78   bits<5> rd;
  79
  80   let Opcode = SPECIAL3_OPCODE.V;
  81
  82   let Inst{25-21} = rs;
  83   let Inst{20-16} = rt;
  84   let Inst{15-11} = rd;
  85   let Inst{10-6}  = op;
  86   let Inst{5-0}   = 0b010001;
  87 }
  88
  89 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
  90   bits<5> rs;
  91   bits<5> rt;
  92   bits<5> sa;
  93
  94   let Opcode = SPECIAL3_OPCODE.V;
  95
  96   let Inst{25-21} = rs;
  97   let Inst{20-16} = rt;
  98   let Inst{15-11} = sa;
  99   let Inst{10-6}  = op;
 100   let Inst{5-0}   = 0b010001;
 101 }
 102
 103 // ABSQ_S.PH sub-class format.
 104 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
 105   bits<5> rd;
 106   bits<5> rt;
 107
 108   let Opcode = SPECIAL3_OPCODE.V;
 109
 110   let Inst{25-21} = 0;
 111   let Inst{20-16} = rt;
 112   let Inst{15-11} = rd;
 113   let Inst{10-6}  = op;
 114   let Inst{5-0}   = 0b010010;
 115 }
 116
 117
 118 class REPL_FMT<bits<5> op> : DSPInst {
 119   bits<5> rd;
 120   bits<10> imm;
 121
 122   let Opcode = SPECIAL3_OPCODE.V;
 123
 124   let Inst{25-16} = imm;
 125   let Inst{15-11} = rd;
 126   let Inst{10-6}  = op;
 127   let Inst{5-0}   = 0b010010;
 128 }
 129
 130 // SHLL.QB sub-class format.
 131 class SHLL_QB_FMT<bits<5> op> : DSPInst {
 132   bits<5> rd;
 133   bits<5> rt;
 134   bits<5> rs_sa;
 135
 136   let Opcode = SPECIAL3_OPCODE.V;
 137
 138   let Inst{25-21} = rs_sa;
 139   let Inst{20-16} = rt;
 140   let Inst{15-11} = rd;
 141   let Inst{10-6}  = op;
 142   let Inst{5-0}   = 0b010011;
 143 }
 144
 145 // LX sub-class format.
 146 class LX_FMT<bits<5> op> : DSPInst {
 147   bits<5> rd;
 148   bits<5> base;
 149   bits<5> index;
 150
 151   let Opcode = SPECIAL3_OPCODE.V;
 152
 153   let Inst{25-21} = base;
 154   let Inst{20-16} = index;
 155   let Inst{15-11} = rd;
 156   let Inst{10-6}  = op;
 157   let Inst{5-0} = 0b001010;
 158 }
 159
 160 // ADDUH.QB sub-class format.
 161 class ADDUH_QB_FMT<bits<5> op> : DSPInst {
 162   bits<5> rd;
 163   bits<5> rs;
 164   bits<5> rt;
 165
 166   let Opcode = SPECIAL3_OPCODE.V;
 167
 168   let Inst{25-21} = rs;
 169   let Inst{20-16} = rt;
 170   let Inst{15-11} = rd;
 171   let Inst{10-6} = op;
 172   let Inst{5-0} = 0b011000;
 173 }
 174
 175 // APPEND sub-class format.
 176 class APPEND_FMT<bits<5> op> : DSPInst {
 177   bits<5> rt;
 178   bits<5> rs;
 179   bits<5> sa;
 180
 181   let Opcode = SPECIAL3_OPCODE.V;
 182
 183   let Inst{25-21} = rs;
 184   let Inst{20-16} = rt;
 185   let Inst{15-11} = sa;
 186   let Inst{10-6} = op;
 187   let Inst{5-0} = 0b110001;
 188 }
 189
 190 // DPA.W.PH sub-class format.
 191 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
 192   bits<2> ac;
 193   bits<5> rs;
 194   bits<5> rt;
 195
 196   let Opcode = SPECIAL3_OPCODE.V;
 197
 198   let Inst{25-21} = rs;
 199   let Inst{20-16} = rt;
 200   let Inst{15-13} = 0;
 201   let Inst{12-11} = ac;
 202   let Inst{10-6}  = op;
 203   let Inst{5-0} = 0b110000;
 204 }
 205
 206 // MULT sub-class format.
 207 class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
 208   bits<2> ac;
 209   bits<5> rs;
 210   bits<5> rt;
 211
 212   let Opcode = opcode;
 213
 214   let Inst{25-21} = rs;
 215   let Inst{20-16} = rt;
 216   let Inst{15-13} = 0;
 217   let Inst{12-11} = ac;
 218   let Inst{10-6}  = 0;
 219   let Inst{5-0} = funct;
 220 }
 221
 222 // EXTR.W sub-class format (type 1).
 223 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
 224   bits<5> rt;
 225   bits<2> ac;
 226   bits<5> shift_rs;
 227
 228   let Opcode = SPECIAL3_OPCODE.V;
 229
 230   let Inst{25-21} = shift_rs;
 231   let Inst{20-16} = rt;
 232   let Inst{15-13} = 0;
 233   let Inst{12-11} = ac;
 234   let Inst{10-6} = op;
 235   let Inst{5-0} = 0b111000;
 236 }
 237
 238 // SHILO sub-class format.
 239 class SHILO_R1_FMT<bits<5> op> : DSPInst {
 240   bits<2> ac;
 241   bits<6> shift;
 242
 243   let Opcode = SPECIAL3_OPCODE.V;
 244
 245   let Inst{25-20} = shift;
 246   let Inst{19-13} = 0;
 247   let Inst{12-11} = ac;
 248   let Inst{10-6} = op;
 249   let Inst{5-0} = 0b111000;
 250 }
 251
 252 class SHILO_R2_FMT<bits<5> op> : DSPInst {
 253   bits<2> ac;
 254   bits<5> rs;
 255
 256   let Opcode = SPECIAL3_OPCODE.V;
 257
 258   let Inst{25-21} = rs;
 259   let Inst{20-13} = 0;
 260   let Inst{12-11} = ac;
 261   let Inst{10-6} = op;
 262   let Inst{5-0} = 0b111000;
 263 }
 264
 265 class RDDSP_FMT<bits<5> op> : DSPInst {
 266   bits<5> rd;
 267   bits<10> mask;
 268
 269   let Opcode = SPECIAL3_OPCODE.V;
 270
 271   let Inst{25-16} = mask;
 272   let Inst{15-11} = rd;
 273   let Inst{10-6} = op;
 274   let Inst{5-0} = 0b111000;
 275 }
 276
 277 class WRDSP_FMT<bits<5> op> : DSPInst {
 278   bits<5> rs;
 279   bits<10> mask;
 280
 281   let Opcode = SPECIAL3_OPCODE.V;
 282
 283   let Inst{25-21} = rs;
 284   let Inst{20-11} = mask;
 285   let Inst{10-6} = op;
 286   let Inst{5-0} = 0b111000;
 287 }
 288
 289 class BPOSGE32_FMT<bits<5> op> : DSPInst {
 290   bits<16> offset;
 291
 292   let Opcode = REGIMM_OPCODE.V;
 293
 294   let Inst{25-21} = 0;
 295   let Inst{20-16} = op;
 296   let Inst{15-0} = offset;
 297 }
 298
 299 // INSV sub-class format.
 300 class INSV_FMT<bits<6> op> : DSPInst {
 301   bits<5> rt;
 302   bits<5> rs;
 303
 304   let Opcode = SPECIAL3_OPCODE.V;
 305
 306   let Inst{25-21} = rs;
 307   let Inst{20-16} = rt;
 308   let Inst{15-6} = 0;
 309   let Inst{5-0} = op;
 310 }