src/llvm/lib/Target/X86/X86InstrCompiler.td

   1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the various pseudo instructions used by the compiler,
  11 // as well as Pat patterns used during instruction selection.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 //===----------------------------------------------------------------------===//
  16 // Pattern Matching Support
  17
  18 def GetLo32XForm : SDNodeXForm<imm, [{
  19   // Transformation function: get the low 32 bits.
  20   return getI32Imm((unsigned)N->getZExtValue());
  21 }]>;
  22
  23 def GetLo8XForm : SDNodeXForm<imm, [{
  24   // Transformation function: get the low 8 bits.
  25   return getI8Imm((uint8_t)N->getZExtValue());
  26 }]>;
  27
  28
  29 //===----------------------------------------------------------------------===//
  30 // Random Pseudo Instructions.
  31
  32 // PIC base construction.  This expands to code that looks like this:
  33 //     call  $next_inst
  34 //     popl %destreg"
  35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
  36   def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
  37                       "", []>;
  38
  39
  40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
  41 // a stack adjustment and the codegen must know that they may modify the stack
  42 // pointer before prolog-epilog rewriting occurs.
  43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
  44 // sub / add which can clobber EFLAGS.
  45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
  46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
  47                            "#ADJCALLSTACKDOWN",
  48                            [(X86callseq_start timm:$amt)]>,
  49                           Requires<[In32BitMode]>;
  50 def ADJCALLSTACKUP32   : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
  51                            "#ADJCALLSTACKUP",
  52                            [(X86callseq_end timm:$amt1, timm:$amt2)]>,
  53                           Requires<[In32BitMode]>;
  54 }
  55
  56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
  57 // a stack adjustment and the codegen must know that they may modify the stack
  58 // pointer before prolog-epilog rewriting occurs.
  59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
  60 // sub / add which can clobber EFLAGS.
  61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
  62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
  63                            "#ADJCALLSTACKDOWN",
  64                            [(X86callseq_start timm:$amt)]>,
  65                           Requires<[In64BitMode]>;
  66 def ADJCALLSTACKUP64   : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
  67                            "#ADJCALLSTACKUP",
  68                            [(X86callseq_end timm:$amt1, timm:$amt2)]>,
  69                           Requires<[In64BitMode]>;
  70 }
  71
  72
  73
  74 // x86-64 va_start lowering magic.
  75 let usesCustomInserter = 1 in {
  76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
  77                               (outs),
  78                               (ins GR8:$al,
  79                                    i64imm:$regsavefi, i64imm:$offset,
  80                                    variable_ops),
  81                               "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
  82                               [(X86vastart_save_xmm_regs GR8:$al,
  83                                                          imm:$regsavefi,
  84                                                          imm:$offset)]>;
  85
  86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
  87 // and places the address of the next argument into a register.
  88 let Defs = [EFLAGS] in
  89 def VAARG_64 : I<0, Pseudo,
  90                  (outs GR64:$dst),
  91                  (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
  92                  "#VAARG_64 $dst, $ap, $size, $mode, $align",
  93                  [(set GR64:$dst,
  94                     (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
  95                   (implicit EFLAGS)]>;
  96
  97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
  98 // targets.  These calls are needed to probe the stack when allocating more than
  99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
 100 // ensure that the guard pages used by the OS virtual memory manager are
 101 // allocated in correct sequence.
 102 // The main point of having separate instruction are extra unmodelled effects
 103 // (compared to ordinary calls) like stack pointer change.
 104
 105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
 106   def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
 107                      "# dynamic stack allocation",
 108                      [(X86WinAlloca)]>;
 109
 110 // When using segmented stacks these are lowered into instructions which first
 111 // check if the current stacklet has enough free memory. If it does, memory is
 112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
 113 // the heap.
 114
 115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
 116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
 117                       "# variable sized alloca for segmented stacks",
 118                       [(set GR32:$dst,
 119                          (X86SegAlloca GR32:$size))]>,
 120                     Requires<[In32BitMode]>;
 121
 122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
 123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
 124                       "# variable sized alloca for segmented stacks",
 125                       [(set GR64:$dst,
 126                          (X86SegAlloca GR64:$size))]>,
 127                     Requires<[In64BitMode]>;
 128 }
 129
 130 // The MSVC runtime contains an _ftol2 routine for converting floating-point
 131 // to integer values. It has a strange calling convention: the input is
 132 // popped from the x87 stack, and the return value is given in EDX:EAX. No
 133 // other registers (aside from flags) are touched.
 134 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
 135 // variant is unnecessary.
 136
 137 let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in {
 138   def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
 139                       "# win32 fptoui",
 140                       [(X86WinFTOL RFP32:$src)]>,
 141                     Requires<[In32BitMode]>;
 142
 143   def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
 144                       "# win32 fptoui",
 145                       [(X86WinFTOL RFP64:$src)]>,
 146                     Requires<[In32BitMode]>;
 147 }
 148
 149 //===----------------------------------------------------------------------===//
 150 // EH Pseudo Instructions
 151 //
 152 let isTerminator = 1, isReturn = 1, isBarrier = 1,
 153     hasCtrlDep = 1, isCodeGenOnly = 1 in {
 154 def EH_RETURN   : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
 155                     "ret\t#eh_return, addr: $addr",
 156                     [(X86ehret GR32:$addr)], IIC_RET>;
 157
 158 }
 159
 160 let isTerminator = 1, isReturn = 1, isBarrier = 1,
 161     hasCtrlDep = 1, isCodeGenOnly = 1 in {
 162 def EH_RETURN64   : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
 163                      "ret\t#eh_return, addr: $addr",
 164                      [(X86ehret GR64:$addr)], IIC_RET>;
 165
 166 }
 167
 168 //===----------------------------------------------------------------------===//
 169 // Pseudo instructions used by segmented stacks.
 170 //
 171
 172 // This is lowered into a RET instruction by MCInstLower.  We need
 173 // this so that we don't have to have a MachineBasicBlock which ends
 174 // with a RET and also has successors.
 175 let isPseudo = 1 in {
 176 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
 177                           "", []>;
 178
 179 // This instruction is lowered to a RET followed by a MOV.  The two
 180 // instructions are not generated on a higher level since then the
 181 // verifier sees a MachineBasicBlock ending with a non-terminator.
 182 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
 183                                   "", []>;
 184 }
 185
 186 //===----------------------------------------------------------------------===//
 187 // Alias Instructions
 188 //===----------------------------------------------------------------------===//
 189
 190 // Alias instructions that map movr0 to xor.
 191 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
 192 // FIXME: Set encoding to pseudo.
 193 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
 194     isCodeGenOnly = 1 in {
 195 def MOV8r0   : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
 196                  [(set GR8:$dst, 0)], IIC_ALU_NONMEM>;
 197
 198 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
 199 // encoding and avoids a partial-register update sometimes, but doing so
 200 // at isel time interferes with rematerialization in the current register
 201 // allocator. For now, this is rewritten when the instruction is lowered
 202 // to an MCInst.
 203 def MOV16r0   : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
 204                  "",
 205                  [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize;
 206
 207 // FIXME: Set encoding to pseudo.
 208 def MOV32r0  : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
 209                  [(set GR32:$dst, 0)], IIC_ALU_NONMEM>;
 210 }
 211
 212 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
 213 // smaller encoding, but doing so at isel time interferes with rematerialization
 214 // in the current register allocator. For now, this is rewritten when the
 215 // instruction is lowered to an MCInst.
 216 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
 217 // when we have a better way to specify isel priority.
 218 let Defs = [EFLAGS], isCodeGenOnly=1,
 219     AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
 220 def MOV64r0   : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
 221                  [(set GR64:$dst, 0)], IIC_ALU_NONMEM>;
 222
 223 // Materialize i64 constant where top 32-bits are zero. This could theoretically
 224 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
 225 // that would make it more difficult to rematerialize.
 226 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
 227     isCodeGenOnly = 1 in
 228 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
 229                         "", [(set GR64:$dst, i64immZExt32:$src)],
 230                         IIC_ALU_NONMEM>;
 231
 232 // Use sbb to materialize carry bit.
 233 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
 234 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
 235 // However, Pat<> can't replicate the destination reg into the inputs of the
 236 // result.
 237 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
 238 // X86CodeEmitter.
 239 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
 240                  [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
 241                  IIC_ALU_NONMEM>;
 242 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
 243                  [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
 244                  IIC_ALU_NONMEM>,
 245                 OpSize;
 246 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
 247                  [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
 248                  IIC_ALU_NONMEM>;
 249 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
 250                  [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
 251                  IIC_ALU_NONMEM>;
 252 } // isCodeGenOnly
 253
 254
 255 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
 256           (SETB_C16r)>;
 257 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
 258           (SETB_C32r)>;
 259 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
 260           (SETB_C64r)>;
 261
 262 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
 263           (SETB_C16r)>;
 264 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
 265           (SETB_C32r)>;
 266 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
 267           (SETB_C64r)>;
 268
 269 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
 270 // will be eliminated and that the sbb can be extended up to a wider type.  When
 271 // this happens, it is great.  However, if we are left with an 8-bit sbb and an
 272 // and, we might as well just match it as a setb.
 273 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
 274           (SETBr)>;
 275
 276 // (add OP, SETB) -> (adc OP, 0)
 277 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
 278           (ADC8ri GR8:$op, 0)>;
 279 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
 280           (ADC32ri8 GR32:$op, 0)>;
 281 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
 282           (ADC64ri8 GR64:$op, 0)>;
 283
 284 // (sub OP, SETB) -> (sbb OP, 0)
 285 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
 286           (SBB8ri GR8:$op, 0)>;
 287 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
 288           (SBB32ri8 GR32:$op, 0)>;
 289 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
 290           (SBB64ri8 GR64:$op, 0)>;
 291
 292 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
 293 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
 294           (ADC8ri GR8:$op, 0)>;
 295 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
 296           (ADC32ri8 GR32:$op, 0)>;
 297 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
 298           (ADC64ri8 GR64:$op, 0)>;
 299
 300 //===----------------------------------------------------------------------===//
 301 // String Pseudo Instructions
 302 //
 303 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
 304 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
 305                     [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
 306                    Requires<[In32BitMode]>;
 307 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
 308                     [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
 309                    Requires<[In32BitMode]>;
 310 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
 311                     [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
 312                    Requires<[In32BitMode]>;
 313 }
 314
 315 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
 316 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
 317                     [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
 318                    Requires<[In64BitMode]>;
 319 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
 320                     [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
 321                    Requires<[In64BitMode]>;
 322 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
 323                     [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
 324                    Requires<[In64BitMode]>;
 325 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
 326                     [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
 327                    Requires<[In64BitMode]>;
 328 }
 329
 330 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
 331 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
 332   let Uses = [AL,ECX,EDI] in
 333   def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
 334                       [(X86rep_stos i8)], IIC_REP_STOS>, REP,
 335                      Requires<[In32BitMode]>;
 336   let Uses = [AX,ECX,EDI] in
 337   def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
 338                       [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
 339                      Requires<[In32BitMode]>;
 340   let Uses = [EAX,ECX,EDI] in
 341   def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
 342                       [(X86rep_stos i32)], IIC_REP_STOS>, REP,
 343                      Requires<[In32BitMode]>;
 344 }
 345
 346 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
 347   let Uses = [AL,RCX,RDI] in
 348   def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
 349                       [(X86rep_stos i8)], IIC_REP_STOS>, REP,
 350                      Requires<[In64BitMode]>;
 351   let Uses = [AX,RCX,RDI] in
 352   def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
 353                       [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
 354                      Requires<[In64BitMode]>;
 355   let Uses = [RAX,RCX,RDI] in
 356   def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
 357                       [(X86rep_stos i32)], IIC_REP_STOS>, REP,
 358                      Requires<[In64BitMode]>;
 359
 360   let Uses = [RAX,RCX,RDI] in
 361   def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
 362                       [(X86rep_stos i64)], IIC_REP_STOS>, REP,
 363                      Requires<[In64BitMode]>;
 364 }
 365
 366 //===----------------------------------------------------------------------===//
 367 // Thread Local Storage Instructions
 368 //
 369
 370 // ELF TLS Support
 371 // All calls clobber the non-callee saved registers. ESP is marked as
 372 // a use to prevent stack-pointer assignments that appear immediately
 373 // before calls from potentially appearing dead.
 374 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
 375             MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
 376             XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
 377             XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
 378     Uses = [ESP] in {
 379 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
 380                   "# TLS_addr32",
 381                   [(X86tlsaddr tls32addr:$sym)]>,
 382                   Requires<[In32BitMode]>;
 383 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
 384                   "# TLS_base_addr32",
 385                   [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
 386                   Requires<[In32BitMode]>;
 387 }
 388
 389 // All calls clobber the non-callee saved registers. RSP is marked as
 390 // a use to prevent stack-pointer assignments that appear immediately
 391 // before calls from potentially appearing dead.
 392 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
 393             FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
 394             MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
 395             XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
 396             XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
 397     Uses = [RSP] in {
 398 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
 399                    "# TLS_addr64",
 400                   [(X86tlsaddr tls64addr:$sym)]>,
 401                   Requires<[In64BitMode]>;
 402 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
 403                    "# TLS_base_addr64",
 404                   [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
 405                   Requires<[In64BitMode]>;
 406 }
 407
 408 // Darwin TLS Support
 409 // For i386, the address of the thunk is passed on the stack, on return the
 410 // address of the variable is in %eax.  %ecx is trashed during the function
 411 // call.  All other registers are preserved.
 412 let Defs = [EAX, ECX, EFLAGS],
 413     Uses = [ESP],
 414     usesCustomInserter = 1 in
 415 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
 416                 "# TLSCall_32",
 417                 [(X86TLSCall addr:$sym)]>,
 418                 Requires<[In32BitMode]>;
 419
 420 // For x86_64, the address of the thunk is passed in %rdi, on return
 421 // the address of the variable is in %rax.  All other registers are preserved.
 422 let Defs = [RAX, EFLAGS],
 423     Uses = [RSP, RDI],
 424     usesCustomInserter = 1 in
 425 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
 426                   "# TLSCall_64",
 427                   [(X86TLSCall addr:$sym)]>,
 428                   Requires<[In64BitMode]>;
 429
 430
 431 //===----------------------------------------------------------------------===//
 432 // Conditional Move Pseudo Instructions
 433
 434 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
 435 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
 436 // however that requires promoting the operands, and can induce additional
 437 // i8 register pressure.
 438 let usesCustomInserter = 1, Uses = [EFLAGS] in {
 439 def CMOV_GR8 : I<0, Pseudo,
 440                  (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
 441                  "#CMOV_GR8 PSEUDO!",
 442                  [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
 443                                           imm:$cond, EFLAGS))]>;
 444
 445 let Predicates = [NoCMov] in {
 446 def CMOV_GR32 : I<0, Pseudo,
 447                     (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
 448                     "#CMOV_GR32* PSEUDO!",
 449                     [(set GR32:$dst,
 450                       (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
 451 def CMOV_GR16 : I<0, Pseudo,
 452                     (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
 453                     "#CMOV_GR16* PSEUDO!",
 454                     [(set GR16:$dst,
 455                       (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
 456 def CMOV_RFP32 : I<0, Pseudo,
 457                     (outs RFP32:$dst),
 458                     (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
 459                     "#CMOV_RFP32 PSEUDO!",
 460                     [(set RFP32:$dst,
 461                       (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
 462                                                   EFLAGS))]>;
 463 def CMOV_RFP64 : I<0, Pseudo,
 464                     (outs RFP64:$dst),
 465                     (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
 466                     "#CMOV_RFP64 PSEUDO!",
 467                     [(set RFP64:$dst,
 468                       (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
 469                                                   EFLAGS))]>;
 470 def CMOV_RFP80 : I<0, Pseudo,
 471                     (outs RFP80:$dst),
 472                     (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
 473                     "#CMOV_RFP80 PSEUDO!",
 474                     [(set RFP80:$dst,
 475                       (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
 476                                                   EFLAGS))]>;
 477 } // Predicates = [NoCMov]
 478 } // UsesCustomInserter = 1, Uses = [EFLAGS]
 479
 480
 481 //===----------------------------------------------------------------------===//
 482 // Atomic Instruction Pseudo Instructions
 483 //===----------------------------------------------------------------------===//
 484
 485 // Pseudo atomic instructions
 486
 487 multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
 488   let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
 489     def #NAME#8  : I<0, Pseudo, (outs GR8:$dst),
 490                      (ins i8mem:$ptr, GR8:$val),
 491                      !strconcat(mnemonic, "8 PSEUDO!"), []>;
 492     def #NAME#16 : I<0, Pseudo,(outs GR16:$dst),
 493                      (ins i16mem:$ptr, GR16:$val),
 494                      !strconcat(mnemonic, "16 PSEUDO!"), []>;
 495     def #NAME#32 : I<0, Pseudo, (outs GR32:$dst),
 496                      (ins i32mem:$ptr, GR32:$val),
 497                      !strconcat(mnemonic, "32 PSEUDO!"), []>;
 498     def #NAME#64 : I<0, Pseudo, (outs GR64:$dst),
 499                      (ins i64mem:$ptr, GR64:$val),
 500                      !strconcat(mnemonic, "64 PSEUDO!"), []>;
 501   }
 502 }
 503
 504 multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
 505   def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
 506             (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
 507   def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
 508             (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
 509   def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
 510             (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
 511   def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
 512             (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
 513 }
 514
 515 // Atomic exchange, and, or, xor
 516 defm ATOMAND  : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
 517 defm ATOMOR   : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
 518 defm ATOMXOR  : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
 519 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
 520 defm ATOMMAX  : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
 521 defm ATOMMIN  : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
 522 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
 523 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
 524
 525 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND",  "atomic_load_and">;
 526 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR",   "atomic_load_or">;
 527 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR",  "atomic_load_xor">;
 528 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
 529 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX",  "atomic_load_max">;
 530 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN",  "atomic_load_min">;
 531 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
 532 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
 533
 534 multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
 535   let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in
 536     def #NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
 537                        (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
 538                        !strconcat(mnemonic, "6432 PSEUDO!"), []>;
 539 }
 540
 541 defm ATOMAND  : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">;
 542 defm ATOMOR   : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">;
 543 defm ATOMXOR  : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">;
 544 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">;
 545 defm ATOMADD  : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">;
 546 defm ATOMSUB  : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">;
 547 defm ATOMMAX  : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">;
 548 defm ATOMMIN  : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">;
 549 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">;
 550 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">;
 551 defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">;
 552
 553 //===----------------------------------------------------------------------===//
 554 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
 555 //===----------------------------------------------------------------------===//
 556
 557 // FIXME: Use normal instructions and add lock prefix dynamically.
 558
 559 // Memory barriers
 560
 561 // TODO: Get this to fold the constant into the instruction.
 562 let isCodeGenOnly = 1, Defs = [EFLAGS] in
 563 def OR32mrLocked  : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
 564                       "or{l}\t{$zero, $dst|$dst, $zero}",
 565                       [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK;
 566
 567 let hasSideEffects = 1 in
 568 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
 569                      "#MEMBARRIER",
 570                      [(X86MemBarrier)]>;
 571
 572 // RegOpc corresponds to the mr version of the instruction
 573 // ImmOpc corresponds to the mi version of the instruction
 574 // ImmOpc8 corresponds to the mi8 version of the instruction
 575 // ImmMod corresponds to the instruction format of the mi and mi8 versions
 576 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
 577                            Format ImmMod, string mnemonic> {
 578 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
 579
 580 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
 581                    RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
 582                    MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
 583                    !strconcat(mnemonic, "{b}\t",
 584                               "{$src2, $dst|$dst, $src2}"),
 585                    [], IIC_ALU_NONMEM>, LOCK;
 586 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
 587                     RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
 588                     MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
 589                     !strconcat(mnemonic, "{w}\t",
 590                                "{$src2, $dst|$dst, $src2}"),
 591                     [], IIC_ALU_NONMEM>, OpSize, LOCK;
 592 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
 593                     RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
 594                     MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
 595                     !strconcat(mnemonic, "{l}\t",
 596                                "{$src2, $dst|$dst, $src2}"),
 597                     [], IIC_ALU_NONMEM>, LOCK;
 598 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
 599                      RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
 600                      MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
 601                      !strconcat(mnemonic, "{q}\t",
 602                                 "{$src2, $dst|$dst, $src2}"),
 603                      [], IIC_ALU_NONMEM>, LOCK;
 604
 605 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
 606                      ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
 607                      ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
 608                      !strconcat(mnemonic, "{b}\t",
 609                                 "{$src2, $dst|$dst, $src2}"),
 610                      [], IIC_ALU_MEM>, LOCK;
 611
 612 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
 613                        ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
 614                        ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
 615                        !strconcat(mnemonic, "{w}\t",
 616                                   "{$src2, $dst|$dst, $src2}"),
 617                        [], IIC_ALU_MEM>, OpSize, LOCK;
 618
 619 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
 620                        ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
 621                        ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
 622                        !strconcat(mnemonic, "{l}\t",
 623                                   "{$src2, $dst|$dst, $src2}"),
 624                        [], IIC_ALU_MEM>, LOCK;
 625
 626 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
 627                           ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
 628                           ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
 629                           !strconcat(mnemonic, "{q}\t",
 630                                      "{$src2, $dst|$dst, $src2}"),
 631                           [], IIC_ALU_MEM>, LOCK;
 632
 633 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
 634                        ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
 635                        ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
 636                        !strconcat(mnemonic, "{w}\t",
 637                                   "{$src2, $dst|$dst, $src2}"),
 638                        [], IIC_ALU_MEM>, OpSize, LOCK;
 639 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
 640                        ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
 641                        ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
 642                        !strconcat(mnemonic, "{l}\t",
 643                                   "{$src2, $dst|$dst, $src2}"),
 644                        [], IIC_ALU_MEM>, LOCK;
 645 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
 646                         ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
 647                         ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
 648                         !strconcat(mnemonic, "{q}\t",
 649                                    "{$src2, $dst|$dst, $src2}"),
 650                         [], IIC_ALU_MEM>, LOCK;
 651
 652 }
 653
 654 }
 655
 656 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
 657 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
 658 defm LOCK_OR  : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
 659 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
 660 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
 661
 662 // Optimized codegen when the non-memory output is not used.
 663 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
 664                           string mnemonic> {
 665 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
 666
 667 def #NAME#8m  : I<Opc8, Form, (outs), (ins i8mem :$dst),
 668                   !strconcat(mnemonic, "{b}\t$dst"),
 669                   [], IIC_UNARY_MEM>, LOCK;
 670 def #NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
 671                   !strconcat(mnemonic, "{w}\t$dst"),
 672                   [], IIC_UNARY_MEM>, OpSize, LOCK;
 673 def #NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
 674                   !strconcat(mnemonic, "{l}\t$dst"),
 675                   [], IIC_UNARY_MEM>, LOCK;
 676 def #NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
 677                    !strconcat(mnemonic, "{q}\t$dst"),
 678                    [], IIC_UNARY_MEM>, LOCK;
 679 }
 680 }
 681
 682 defm LOCK_INC    : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
 683 defm LOCK_DEC    : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
 684
 685 // Atomic compare and swap.
 686 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
 687                          SDPatternOperator frag, X86MemOperand x86memop,
 688                          InstrItinClass itin> {
 689 let isCodeGenOnly = 1 in {
 690   def #NAME# : I<Opc, Form, (outs), (ins x86memop:$ptr),
 691                  !strconcat(mnemonic, "\t$ptr"),
 692                  [(frag addr:$ptr)], itin>, TB, LOCK;
 693 }
 694 }
 695
 696 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
 697                           string mnemonic, SDPatternOperator frag,
 698                           InstrItinClass itin8, InstrItinClass itin> {
 699 let isCodeGenOnly = 1 in {
 700   let Defs = [AL, EFLAGS], Uses = [AL] in
 701   def #NAME#8  : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
 702                    !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
 703                    [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
 704   let Defs = [AX, EFLAGS], Uses = [AX] in
 705   def #NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
 706                    !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
 707                    [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
 708   let Defs = [EAX, EFLAGS], Uses = [EAX] in
 709   def #NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
 710                    !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
 711                    [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
 712   let Defs = [RAX, EFLAGS], Uses = [RAX] in
 713   def #NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
 714                     !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
 715                     [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
 716 }
 717 }
 718
 719 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
 720 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
 721                                 X86cas8, i64mem,
 722                                 IIC_CMPX_LOCK_8B>;
 723 }
 724
 725 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
 726     Predicates = [HasCmpxchg16b] in {
 727 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
 728                                  X86cas16, i128mem,
 729                                  IIC_CMPX_LOCK_16B>, REX_W;
 730 }
 731
 732 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
 733                                X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
 734
 735 // Atomic exchange and add
 736 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
 737                              string frag,
 738                              InstrItinClass itin8, InstrItinClass itin> {
 739   let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
 740     def #NAME#8  : I<opc8, MRMSrcMem, (outs GR8:$dst),
 741                      (ins GR8:$val, i8mem:$ptr),
 742                      !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
 743                      [(set GR8:$dst,
 744                            (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
 745                      itin8>;
 746     def #NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
 747                      (ins GR16:$val, i16mem:$ptr),
 748                      !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
 749                      [(set
 750                         GR16:$dst,
 751                         (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
 752                      itin>, OpSize;
 753     def #NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
 754                      (ins GR32:$val, i32mem:$ptr),
 755                      !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
 756                      [(set
 757                         GR32:$dst,
 758                         (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
 759                      itin>;
 760     def #NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
 761                       (ins GR64:$val, i64mem:$ptr),
 762                       !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
 763                       [(set
 764                          GR64:$dst,
 765                          (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
 766                       itin>;
 767   }
 768 }
 769
 770 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
 771                                IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
 772              TB, LOCK;
 773
 774 def ACQUIRE_MOV8rm  : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
 775                       "#ACQUIRE_MOV PSEUDO!",
 776                       [(set GR8:$dst,  (atomic_load_8  addr:$src))]>;
 777 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
 778                       "#ACQUIRE_MOV PSEUDO!",
 779                       [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
 780 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
 781                       "#ACQUIRE_MOV PSEUDO!",
 782                       [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
 783 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
 784                       "#ACQUIRE_MOV PSEUDO!",
 785                       [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
 786
 787 def RELEASE_MOV8mr  : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
 788                         "#RELEASE_MOV PSEUDO!",
 789                         [(atomic_store_8  addr:$dst, GR8 :$src)]>;
 790 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
 791                         "#RELEASE_MOV PSEUDO!",
 792                         [(atomic_store_16 addr:$dst, GR16:$src)]>;
 793 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
 794                         "#RELEASE_MOV PSEUDO!",
 795                         [(atomic_store_32 addr:$dst, GR32:$src)]>;
 796 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
 797                         "#RELEASE_MOV PSEUDO!",
 798                         [(atomic_store_64 addr:$dst, GR64:$src)]>;
 799
 800 //===----------------------------------------------------------------------===//
 801 // Conditional Move Pseudo Instructions.
 802 //===----------------------------------------------------------------------===//
 803
 804
 805 // CMOV* - Used to implement the SSE SELECT DAG operation.  Expanded after
 806 // instruction selection into a branch sequence.
 807 let Uses = [EFLAGS], usesCustomInserter = 1 in {
 808   def CMOV_FR32 : I<0, Pseudo,
 809                     (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
 810                     "#CMOV_FR32 PSEUDO!",
 811                     [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
 812                                                   EFLAGS))]>;
 813   def CMOV_FR64 : I<0, Pseudo,
 814                     (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
 815                     "#CMOV_FR64 PSEUDO!",
 816                     [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
 817                                                   EFLAGS))]>;
 818   def CMOV_V4F32 : I<0, Pseudo,
 819                     (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
 820                     "#CMOV_V4F32 PSEUDO!",
 821                     [(set VR128:$dst,
 822                       (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
 823                                           EFLAGS)))]>;
 824   def CMOV_V2F64 : I<0, Pseudo,
 825                     (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
 826                     "#CMOV_V2F64 PSEUDO!",
 827                     [(set VR128:$dst,
 828                       (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
 829                                           EFLAGS)))]>;
 830   def CMOV_V2I64 : I<0, Pseudo,
 831                     (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
 832                     "#CMOV_V2I64 PSEUDO!",
 833                     [(set VR128:$dst,
 834                       (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
 835                                           EFLAGS)))]>;
 836   def CMOV_V8F32 : I<0, Pseudo,
 837                     (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
 838                     "#CMOV_V8F32 PSEUDO!",
 839                     [(set VR256:$dst,
 840                       (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
 841                                           EFLAGS)))]>;
 842   def CMOV_V4F64 : I<0, Pseudo,
 843                     (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
 844                     "#CMOV_V4F64 PSEUDO!",
 845                     [(set VR256:$dst,
 846                       (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
 847                                           EFLAGS)))]>;
 848   def CMOV_V4I64 : I<0, Pseudo,
 849                     (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
 850                     "#CMOV_V4I64 PSEUDO!",
 851                     [(set VR256:$dst,
 852                       (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
 853                                           EFLAGS)))]>;
 854 }
 855
 856
 857 //===----------------------------------------------------------------------===//
 858 // DAG Pattern Matching Rules
 859 //===----------------------------------------------------------------------===//
 860
 861 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
 862 def : Pat<(i32 (X86Wrapper tconstpool  :$dst)), (MOV32ri tconstpool  :$dst)>;
 863 def : Pat<(i32 (X86Wrapper tjumptable  :$dst)), (MOV32ri tjumptable  :$dst)>;
 864 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
 865 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
 866 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
 867 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
 868
 869 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
 870           (ADD32ri GR32:$src1, tconstpool:$src2)>;
 871 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
 872           (ADD32ri GR32:$src1, tjumptable:$src2)>;
 873 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
 874           (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
 875 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
 876           (ADD32ri GR32:$src1, texternalsym:$src2)>;
 877 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
 878           (ADD32ri GR32:$src1, tblockaddress:$src2)>;
 879
 880 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
 881           (MOV32mi addr:$dst, tglobaladdr:$src)>;
 882 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
 883           (MOV32mi addr:$dst, texternalsym:$src)>;
 884 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
 885           (MOV32mi addr:$dst, tblockaddress:$src)>;
 886
 887
 888
 889 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
 890 // code model mode, should use 'movabs'.  FIXME: This is really a hack, the
 891 //  'movabs' predicate should handle this sort of thing.
 892 def : Pat<(i64 (X86Wrapper tconstpool  :$dst)),
 893           (MOV64ri tconstpool  :$dst)>, Requires<[FarData]>;
 894 def : Pat<(i64 (X86Wrapper tjumptable  :$dst)),
 895           (MOV64ri tjumptable  :$dst)>, Requires<[FarData]>;
 896 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
 897           (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
 898 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
 899           (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
 900 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
 901           (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
 902
 903 // In static codegen with small code model, we can get the address of a label
 904 // into a register with 'movl'.  FIXME: This is a hack, the 'imm' predicate of
 905 // the MOV64ri64i32 should accept these.
 906 def : Pat<(i64 (X86Wrapper tconstpool  :$dst)),
 907           (MOV64ri64i32 tconstpool  :$dst)>, Requires<[SmallCode]>;
 908 def : Pat<(i64 (X86Wrapper tjumptable  :$dst)),
 909           (MOV64ri64i32 tjumptable  :$dst)>, Requires<[SmallCode]>;
 910 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
 911           (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
 912 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
 913           (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
 914 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
 915           (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
 916
 917 // In kernel code model, we can get the address of a label
 918 // into a register with 'movq'.  FIXME: This is a hack, the 'imm' predicate of
 919 // the MOV64ri32 should accept these.
 920 def : Pat<(i64 (X86Wrapper tconstpool  :$dst)),
 921           (MOV64ri32 tconstpool  :$dst)>, Requires<[KernelCode]>;
 922 def : Pat<(i64 (X86Wrapper tjumptable  :$dst)),
 923           (MOV64ri32 tjumptable  :$dst)>, Requires<[KernelCode]>;
 924 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
 925           (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
 926 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
 927           (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
 928 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
 929           (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
 930
 931 // If we have small model and -static mode, it is safe to store global addresses
 932 // directly as immediates.  FIXME: This is really a hack, the 'imm' predicate
 933 // for MOV64mi32 should handle this sort of thing.
 934 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
 935           (MOV64mi32 addr:$dst, tconstpool:$src)>,
 936           Requires<[NearData, IsStatic]>;
 937 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
 938           (MOV64mi32 addr:$dst, tjumptable:$src)>,
 939           Requires<[NearData, IsStatic]>;
 940 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
 941           (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
 942           Requires<[NearData, IsStatic]>;
 943 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
 944           (MOV64mi32 addr:$dst, texternalsym:$src)>,
 945           Requires<[NearData, IsStatic]>;
 946 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
 947           (MOV64mi32 addr:$dst, tblockaddress:$src)>,
 948           Requires<[NearData, IsStatic]>;
 949
 950
 951
 952 // Calls
 953
 954 // tls has some funny stuff here...
 955 // This corresponds to movabs $foo@tpoff, %rax
 956 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
 957           (MOV64ri tglobaltlsaddr :$dst)>;
 958 // This corresponds to add $foo@tpoff, %rax
 959 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
 960           (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
 961 // This corresponds to mov foo@tpoff(%rbx), %eax
 962 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
 963           (MOV64rm tglobaltlsaddr :$dst)>;
 964
 965
 966 // Direct PC relative function call for small code model. 32-bit displacement
 967 // sign extended to 64-bit.
 968 def : Pat<(X86call (i64 tglobaladdr:$dst)),
 969           (CALL64pcrel32 tglobaladdr:$dst)>;
 970 def : Pat<(X86call (i64 texternalsym:$dst)),
 971           (CALL64pcrel32 texternalsym:$dst)>;
 972
 973 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
 974 // can never use callee-saved registers. That is the purpose of the GR64_TC
 975 // register classes.
 976 //
 977 // The only volatile register that is never used by the calling convention is
 978 // %r11. This happens when calling a vararg function with 6 arguments.
 979 //
 980 // Match an X86tcret that uses less than 7 volatile registers.
 981 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
 982                              (X86tcret node:$ptr, node:$off), [{
 983   // X86tcret args: (*chain, ptr, imm, regs..., glue)
 984   unsigned NumRegs = 0;
 985   for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
 986     if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
 987       return false;
 988   return true;
 989 }]>;
 990
 991 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
 992           (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
 993           Requires<[In32BitMode]>;
 994
 995 // FIXME: This is disabled for 32-bit PIC mode because the global base
 996 // register which is part of the address mode may be assigned a
 997 // callee-saved register.
 998 def : Pat<(X86tcret (load addr:$dst), imm:$off),
 999           (TCRETURNmi addr:$dst, imm:$off)>,
1000           Requires<[In32BitMode, IsNotPIC]>;
1001
1002 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1003           (TCRETURNdi texternalsym:$dst, imm:$off)>,
1004           Requires<[In32BitMode]>;
1005
1006 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1007           (TCRETURNdi texternalsym:$dst, imm:$off)>,
1008           Requires<[In32BitMode]>;
1009
1010 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1011           (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1012           Requires<[In64BitMode]>;
1013
1014 // Don't fold loads into X86tcret requiring more than 6 regs.
1015 // There wouldn't be enough scratch registers for base+index.
1016 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1017           (TCRETURNmi64 addr:$dst, imm:$off)>,
1018           Requires<[In64BitMode]>;
1019
1020 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1021           (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1022           Requires<[In64BitMode]>;
1023
1024 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1025           (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1026           Requires<[In64BitMode]>;
1027
1028 // Normal calls, with various flavors of addresses.
1029 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1030           (CALLpcrel32 tglobaladdr:$dst)>;
1031 def : Pat<(X86call (i32 texternalsym:$dst)),
1032           (CALLpcrel32 texternalsym:$dst)>;
1033 def : Pat<(X86call (i32 imm:$dst)),
1034           (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1035
1036 // Comparisons.
1037
1038 // TEST R,R is smaller than CMP R,0
1039 def : Pat<(X86cmp GR8:$src1, 0),
1040           (TEST8rr GR8:$src1, GR8:$src1)>;
1041 def : Pat<(X86cmp GR16:$src1, 0),
1042           (TEST16rr GR16:$src1, GR16:$src1)>;
1043 def : Pat<(X86cmp GR32:$src1, 0),
1044           (TEST32rr GR32:$src1, GR32:$src1)>;
1045 def : Pat<(X86cmp GR64:$src1, 0),
1046           (TEST64rr GR64:$src1, GR64:$src1)>;
1047
1048 // Conditional moves with folded loads with operands swapped and conditions
1049 // inverted.
1050 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1051                   Instruction Inst64> {
1052   def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1053             (Inst16 GR16:$src2, addr:$src1)>;
1054   def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1055             (Inst32 GR32:$src2, addr:$src1)>;
1056   def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1057             (Inst64 GR64:$src2, addr:$src1)>;
1058 }
1059
1060 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1061 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1062 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1063 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1064 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1065 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1066 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1067 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1068 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1069 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1070 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1071 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1072 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1073 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1074 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1075 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1076
1077 // zextload bool -> zextload byte
1078 def : Pat<(zextloadi8i1  addr:$src), (MOV8rm     addr:$src)>;
1079 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1080 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1081 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1082
1083 // extload bool -> extload byte
1084 // When extloading from 16-bit and smaller memory locations into 64-bit
1085 // registers, use zero-extending loads so that the entire 64-bit register is
1086 // defined, avoiding partial-register updates.
1087
1088 def : Pat<(extloadi8i1 addr:$src),   (MOV8rm      addr:$src)>;
1089 def : Pat<(extloadi16i1 addr:$src),  (MOVZX16rm8  addr:$src)>;
1090 def : Pat<(extloadi32i1 addr:$src),  (MOVZX32rm8  addr:$src)>;
1091 def : Pat<(extloadi16i8 addr:$src),  (MOVZX16rm8  addr:$src)>;
1092 def : Pat<(extloadi32i8 addr:$src),  (MOVZX32rm8  addr:$src)>;
1093 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1094
1095 def : Pat<(extloadi64i1 addr:$src),  (MOVZX64rm8  addr:$src)>;
1096 def : Pat<(extloadi64i8 addr:$src),  (MOVZX64rm8  addr:$src)>;
1097 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1098 // For other extloads, use subregs, since the high contents of the register are
1099 // defined after an extload.
1100 def : Pat<(extloadi64i32 addr:$src),
1101           (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1102                          sub_32bit)>;
1103
1104 // anyext. Define these to do an explicit zero-extend to
1105 // avoid partial-register updates.
1106 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1107                                      (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1108 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8  GR8 :$src)>;
1109
1110 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1111 def : Pat<(i32 (anyext GR16:$src)),
1112           (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1113
1114 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8  GR8  :$src)>;
1115 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1116 def : Pat<(i64 (anyext GR32:$src)),
1117           (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1118
1119
1120 // Any instruction that defines a 32-bit result leaves the high half of the
1121 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1122 // be copying from a truncate. And x86's cmov doesn't do anything if the
1123 // condition is false. But any other 32-bit operation will zero-extend
1124 // up to 64 bits.
1125 def def32 : PatLeaf<(i32 GR32:$src), [{
1126   return N->getOpcode() != ISD::TRUNCATE &&
1127          N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1128          N->getOpcode() != ISD::CopyFromReg &&
1129          N->getOpcode() != X86ISD::CMOV;
1130 }]>;
1131
1132 // In the case of a 32-bit def that is known to implicitly zero-extend,
1133 // we can use a SUBREG_TO_REG.
1134 def : Pat<(i64 (zext def32:$src)),
1135           (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1136
1137 //===----------------------------------------------------------------------===//
1138 // Pattern match OR as ADD
1139 //===----------------------------------------------------------------------===//
1140
1141 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1142 // 3-addressified into an LEA instruction to avoid copies.  However, we also
1143 // want to finally emit these instructions as an or at the end of the code
1144 // generator to make the generated code easier to read.  To do this, we select
1145 // into "disjoint bits" pseudo ops.
1146
1147 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1148 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1149   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1150     return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1151
1152   APInt KnownZero0, KnownOne0;
1153   CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1154   APInt KnownZero1, KnownOne1;
1155   CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1156   return (~KnownZero0 & ~KnownZero1) == 0;
1157 }]>;
1158
1159
1160 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1161 let AddedComplexity = 5 in { // Try this before the selecting to OR
1162
1163 let isConvertibleToThreeAddress = 1,
1164     Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1165 let isCommutable = 1 in {
1166 def ADD16rr_DB  : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1167                     "", // orw/addw REG, REG
1168                     [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1169 def ADD32rr_DB  : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1170                     "", // orl/addl REG, REG
1171                     [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1172 def ADD64rr_DB  : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1173                     "", // orq/addq REG, REG
1174                     [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1175 } // isCommutable
1176
1177 // NOTE: These are order specific, we want the ri8 forms to be listed
1178 // first so that they are slightly preferred to the ri forms.
1179
1180 def ADD16ri8_DB : I<0, Pseudo,
1181                     (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1182                     "", // orw/addw REG, imm8
1183                     [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1184 def ADD16ri_DB  : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1185                     "", // orw/addw REG, imm
1186                     [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1187
1188 def ADD32ri8_DB : I<0, Pseudo,
1189                     (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1190                     "", // orl/addl REG, imm8
1191                     [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1192 def ADD32ri_DB  : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1193                     "", // orl/addl REG, imm
1194                     [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1195
1196
1197 def ADD64ri8_DB : I<0, Pseudo,
1198                     (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1199                     "", // orq/addq REG, imm8
1200                     [(set GR64:$dst, (or_is_add GR64:$src1,
1201                                                 i64immSExt8:$src2))]>;
1202 def ADD64ri32_DB : I<0, Pseudo,
1203                      (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1204                       "", // orq/addq REG, imm
1205                       [(set GR64:$dst, (or_is_add GR64:$src1,
1206                                                   i64immSExt32:$src2))]>;
1207 }
1208 } // AddedComplexity
1209
1210
1211 //===----------------------------------------------------------------------===//
1212 // Some peepholes
1213 //===----------------------------------------------------------------------===//
1214
1215 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1216 // +128 doesn't, so in this special case use a sub instead of an add.
1217 def : Pat<(add GR16:$src1, 128),
1218           (SUB16ri8 GR16:$src1, -128)>;
1219 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1220           (SUB16mi8 addr:$dst, -128)>;
1221
1222 def : Pat<(add GR32:$src1, 128),
1223           (SUB32ri8 GR32:$src1, -128)>;
1224 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1225           (SUB32mi8 addr:$dst, -128)>;
1226
1227 def : Pat<(add GR64:$src1, 128),
1228           (SUB64ri8 GR64:$src1, -128)>;
1229 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1230           (SUB64mi8 addr:$dst, -128)>;
1231
1232 // The same trick applies for 32-bit immediate fields in 64-bit
1233 // instructions.
1234 def : Pat<(add GR64:$src1, 0x0000000080000000),
1235           (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1236 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1237           (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1238
1239 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1240 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1241 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1242 // represented with a sign extension of a 8 bit constant, use that.
1243
1244 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1245           (SUBREG_TO_REG
1246             (i64 0),
1247             (AND32ri8
1248               (EXTRACT_SUBREG GR64:$src, sub_32bit),
1249               (i32 (GetLo8XForm imm:$imm))),
1250             sub_32bit)>;
1251
1252 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1253           (SUBREG_TO_REG
1254             (i64 0),
1255             (AND32ri
1256               (EXTRACT_SUBREG GR64:$src, sub_32bit),
1257               (i32 (GetLo32XForm imm:$imm))),
1258             sub_32bit)>;
1259
1260
1261 // r & (2^16-1) ==> movz
1262 def : Pat<(and GR32:$src1, 0xffff),
1263           (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1264 // r & (2^8-1) ==> movz
1265 def : Pat<(and GR32:$src1, 0xff),
1266           (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1267                                                              GR32_ABCD)),
1268                                       sub_8bit))>,
1269       Requires<[In32BitMode]>;
1270 // r & (2^8-1) ==> movz
1271 def : Pat<(and GR16:$src1, 0xff),
1272            (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1273             (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1274              sub_16bit)>,
1275       Requires<[In32BitMode]>;
1276
1277 // r & (2^32-1) ==> movz
1278 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1279           (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1280 // r & (2^16-1) ==> movz
1281 def : Pat<(and GR64:$src, 0xffff),
1282           (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1283 // r & (2^8-1) ==> movz
1284 def : Pat<(and GR64:$src, 0xff),
1285           (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1286 // r & (2^8-1) ==> movz
1287 def : Pat<(and GR32:$src1, 0xff),
1288            (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1289       Requires<[In64BitMode]>;
1290 // r & (2^8-1) ==> movz
1291 def : Pat<(and GR16:$src1, 0xff),
1292            (EXTRACT_SUBREG (MOVZX32rr8 (i8
1293             (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1294       Requires<[In64BitMode]>;
1295
1296
1297 // sext_inreg patterns
1298 def : Pat<(sext_inreg GR32:$src, i16),
1299           (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1300 def : Pat<(sext_inreg GR32:$src, i8),
1301           (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1302                                                              GR32_ABCD)),
1303                                       sub_8bit))>,
1304       Requires<[In32BitMode]>;
1305
1306 def : Pat<(sext_inreg GR16:$src, i8),
1307            (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1308             (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1309              sub_16bit)>,
1310       Requires<[In32BitMode]>;
1311
1312 def : Pat<(sext_inreg GR64:$src, i32),
1313           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1314 def : Pat<(sext_inreg GR64:$src, i16),
1315           (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1316 def : Pat<(sext_inreg GR64:$src, i8),
1317           (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1318 def : Pat<(sext_inreg GR32:$src, i8),
1319           (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1320       Requires<[In64BitMode]>;
1321 def : Pat<(sext_inreg GR16:$src, i8),
1322            (EXTRACT_SUBREG (MOVSX32rr8
1323             (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1324       Requires<[In64BitMode]>;
1325
1326 // sext, sext_load, zext, zext_load
1327 def: Pat<(i16 (sext GR8:$src)),
1328           (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1329 def: Pat<(sextloadi16i8 addr:$src),
1330           (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1331 def: Pat<(i16 (zext GR8:$src)),
1332           (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1333 def: Pat<(zextloadi16i8 addr:$src),
1334           (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1335
1336 // trunc patterns
1337 def : Pat<(i16 (trunc GR32:$src)),
1338           (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1339 def : Pat<(i8 (trunc GR32:$src)),
1340           (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1341                           sub_8bit)>,
1342       Requires<[In32BitMode]>;
1343 def : Pat<(i8 (trunc GR16:$src)),
1344           (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1345                           sub_8bit)>,
1346       Requires<[In32BitMode]>;
1347 def : Pat<(i32 (trunc GR64:$src)),
1348           (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1349 def : Pat<(i16 (trunc GR64:$src)),
1350           (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1351 def : Pat<(i8 (trunc GR64:$src)),
1352           (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1353 def : Pat<(i8 (trunc GR32:$src)),
1354           (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1355       Requires<[In64BitMode]>;
1356 def : Pat<(i8 (trunc GR16:$src)),
1357           (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1358       Requires<[In64BitMode]>;
1359
1360 // h-register tricks
1361 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1362           (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1363                           sub_8bit_hi)>,
1364       Requires<[In32BitMode]>;
1365 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1366           (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1367                           sub_8bit_hi)>,
1368       Requires<[In32BitMode]>;
1369 def : Pat<(srl GR16:$src, (i8 8)),
1370           (EXTRACT_SUBREG
1371             (MOVZX32rr8
1372               (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1373                               sub_8bit_hi)),
1374             sub_16bit)>,
1375       Requires<[In32BitMode]>;
1376 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1377           (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1378                                                              GR16_ABCD)),
1379                                       sub_8bit_hi))>,
1380       Requires<[In32BitMode]>;
1381 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1382           (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1383                                                              GR16_ABCD)),
1384                                       sub_8bit_hi))>,
1385       Requires<[In32BitMode]>;
1386 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1387           (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1388                                                              GR32_ABCD)),
1389                                       sub_8bit_hi))>,
1390       Requires<[In32BitMode]>;
1391 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1392           (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1393                                                              GR32_ABCD)),
1394                                       sub_8bit_hi))>,
1395       Requires<[In32BitMode]>;
1396
1397 // h-register tricks.
1398 // For now, be conservative on x86-64 and use an h-register extract only if the
1399 // value is immediately zero-extended or stored, which are somewhat common
1400 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1401 // from being allocated in the same instruction as the h register, as there's
1402 // currently no way to describe this requirement to the register allocator.
1403
1404 // h-register extract and zero-extend.
1405 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1406           (SUBREG_TO_REG
1407             (i64 0),
1408             (MOVZX32_NOREXrr8
1409               (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1410                               sub_8bit_hi)),
1411             sub_32bit)>;
1412 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1413           (MOVZX32_NOREXrr8
1414             (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1415                             sub_8bit_hi))>,
1416       Requires<[In64BitMode]>;
1417 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1418           (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1419                                                                    GR32_ABCD)),
1420                                              sub_8bit_hi))>,
1421       Requires<[In64BitMode]>;
1422 def : Pat<(srl GR16:$src, (i8 8)),
1423           (EXTRACT_SUBREG
1424             (MOVZX32_NOREXrr8
1425               (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1426                               sub_8bit_hi)),
1427             sub_16bit)>,
1428       Requires<[In64BitMode]>;
1429 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1430           (MOVZX32_NOREXrr8
1431             (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1432                             sub_8bit_hi))>,
1433       Requires<[In64BitMode]>;
1434 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1435           (MOVZX32_NOREXrr8
1436             (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1437                             sub_8bit_hi))>,
1438       Requires<[In64BitMode]>;
1439 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1440           (SUBREG_TO_REG
1441             (i64 0),
1442             (MOVZX32_NOREXrr8
1443               (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1444                               sub_8bit_hi)),
1445             sub_32bit)>;
1446 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1447           (SUBREG_TO_REG
1448             (i64 0),
1449             (MOVZX32_NOREXrr8
1450               (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1451                               sub_8bit_hi)),
1452             sub_32bit)>;
1453
1454 // h-register extract and store.
1455 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1456           (MOV8mr_NOREX
1457             addr:$dst,
1458             (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1459                             sub_8bit_hi))>;
1460 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1461           (MOV8mr_NOREX
1462             addr:$dst,
1463             (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1464                             sub_8bit_hi))>,
1465       Requires<[In64BitMode]>;
1466 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1467           (MOV8mr_NOREX
1468             addr:$dst,
1469             (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1470                             sub_8bit_hi))>,
1471       Requires<[In64BitMode]>;
1472
1473
1474 // (shl x, 1) ==> (add x, x)
1475 // Note that if x is undef (immediate or otherwise), we could theoretically
1476 // end up with the two uses of x getting different values, producing a result
1477 // where the least significant bit is not 0. However, the probability of this
1478 // happening is considered low enough that this is officially not a
1479 // "real problem".
1480 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr  GR8 :$src1, GR8 :$src1)>;
1481 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1482 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1483 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1484
1485 // Helper imms that check if a mask doesn't change significant shift bits.
1486 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1487 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1488
1489 // (shl x (and y, 31)) ==> (shl x, y)
1490 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1491           (SHL8rCL GR8:$src1)>;
1492 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1493           (SHL16rCL GR16:$src1)>;
1494 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1495           (SHL32rCL GR32:$src1)>;
1496 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1497           (SHL8mCL addr:$dst)>;
1498 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1499           (SHL16mCL addr:$dst)>;
1500 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1501           (SHL32mCL addr:$dst)>;
1502
1503 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1504           (SHR8rCL GR8:$src1)>;
1505 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1506           (SHR16rCL GR16:$src1)>;
1507 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1508           (SHR32rCL GR32:$src1)>;
1509 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1510           (SHR8mCL addr:$dst)>;
1511 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1512           (SHR16mCL addr:$dst)>;
1513 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1514           (SHR32mCL addr:$dst)>;
1515
1516 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1517           (SAR8rCL GR8:$src1)>;
1518 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1519           (SAR16rCL GR16:$src1)>;
1520 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1521           (SAR32rCL GR32:$src1)>;
1522 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1523           (SAR8mCL addr:$dst)>;
1524 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1525           (SAR16mCL addr:$dst)>;
1526 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1527           (SAR32mCL addr:$dst)>;
1528
1529 // (shl x (and y, 63)) ==> (shl x, y)
1530 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1531           (SHL64rCL GR64:$src1)>;
1532 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1533           (SHL64mCL addr:$dst)>;
1534
1535 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1536           (SHR64rCL GR64:$src1)>;
1537 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1538           (SHR64mCL addr:$dst)>;
1539
1540 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1541           (SAR64rCL GR64:$src1)>;
1542 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1543           (SAR64mCL addr:$dst)>;
1544
1545
1546 // (anyext (setcc_carry)) -> (setcc_carry)
1547 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1548           (SETB_C16r)>;
1549 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1550           (SETB_C32r)>;
1551 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1552           (SETB_C32r)>;
1553
1554
1555
1556
1557 //===----------------------------------------------------------------------===//
1558 // EFLAGS-defining Patterns
1559 //===----------------------------------------------------------------------===//
1560
1561 // add reg, reg
1562 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr  GR8 :$src1, GR8 :$src2)>;
1563 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1564 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1565
1566 // add reg, mem
1567 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1568           (ADD8rm GR8:$src1, addr:$src2)>;
1569 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1570           (ADD16rm GR16:$src1, addr:$src2)>;
1571 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1572           (ADD32rm GR32:$src1, addr:$src2)>;
1573
1574 // add reg, imm
1575 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri  GR8:$src1 , imm:$src2)>;
1576 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1577 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1578 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1579           (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1580 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1581           (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1582
1583 // sub reg, reg
1584 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr  GR8 :$src1, GR8 :$src2)>;
1585 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1586 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1587
1588 // sub reg, mem
1589 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1590           (SUB8rm GR8:$src1, addr:$src2)>;
1591 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1592           (SUB16rm GR16:$src1, addr:$src2)>;
1593 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1594           (SUB32rm GR32:$src1, addr:$src2)>;
1595
1596 // sub reg, imm
1597 def : Pat<(sub GR8:$src1, imm:$src2),
1598           (SUB8ri GR8:$src1, imm:$src2)>;
1599 def : Pat<(sub GR16:$src1, imm:$src2),
1600           (SUB16ri GR16:$src1, imm:$src2)>;
1601 def : Pat<(sub GR32:$src1, imm:$src2),
1602           (SUB32ri GR32:$src1, imm:$src2)>;
1603 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1604           (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1605 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1606           (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1607
1608 // sub 0, reg
1609 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r  GR8 :$src)>;
1610 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1611 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1612 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1613
1614 // mul reg, reg
1615 def : Pat<(mul GR16:$src1, GR16:$src2),
1616           (IMUL16rr GR16:$src1, GR16:$src2)>;
1617 def : Pat<(mul GR32:$src1, GR32:$src2),
1618           (IMUL32rr GR32:$src1, GR32:$src2)>;
1619
1620 // mul reg, mem
1621 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1622           (IMUL16rm GR16:$src1, addr:$src2)>;
1623 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1624           (IMUL32rm GR32:$src1, addr:$src2)>;
1625
1626 // mul reg, imm
1627 def : Pat<(mul GR16:$src1, imm:$src2),
1628           (IMUL16rri GR16:$src1, imm:$src2)>;
1629 def : Pat<(mul GR32:$src1, imm:$src2),
1630           (IMUL32rri GR32:$src1, imm:$src2)>;
1631 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1632           (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1633 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1634           (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1635
1636 // reg = mul mem, imm
1637 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1638           (IMUL16rmi addr:$src1, imm:$src2)>;
1639 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1640           (IMUL32rmi addr:$src1, imm:$src2)>;
1641 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1642           (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1643 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1644           (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1645
1646 // Patterns for nodes that do not produce flags, for instructions that do.
1647
1648 // addition
1649 def : Pat<(add GR64:$src1, GR64:$src2),
1650           (ADD64rr GR64:$src1, GR64:$src2)>;
1651 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1652           (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1653 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1654           (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1655 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1656           (ADD64rm GR64:$src1, addr:$src2)>;
1657
1658 // subtraction
1659 def : Pat<(sub GR64:$src1, GR64:$src2),
1660           (SUB64rr GR64:$src1, GR64:$src2)>;
1661 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1662           (SUB64rm GR64:$src1, addr:$src2)>;
1663 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1664           (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1665 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1666           (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1667
1668 // Multiply
1669 def : Pat<(mul GR64:$src1, GR64:$src2),
1670           (IMUL64rr GR64:$src1, GR64:$src2)>;
1671 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1672           (IMUL64rm GR64:$src1, addr:$src2)>;
1673 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1674           (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1675 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1676           (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1677 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1678           (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1679 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1680           (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1681
1682 // Increment reg.
1683 def : Pat<(add GR8 :$src, 1), (INC8r     GR8 :$src)>;
1684 def : Pat<(add GR16:$src, 1), (INC16r    GR16:$src)>, Requires<[In32BitMode]>;
1685 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1686 def : Pat<(add GR32:$src, 1), (INC32r    GR32:$src)>, Requires<[In32BitMode]>;
1687 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1688 def : Pat<(add GR64:$src, 1), (INC64r    GR64:$src)>;
1689
1690 // Decrement reg.
1691 def : Pat<(add GR8 :$src, -1), (DEC8r     GR8 :$src)>;
1692 def : Pat<(add GR16:$src, -1), (DEC16r    GR16:$src)>, Requires<[In32BitMode]>;
1693 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1694 def : Pat<(add GR32:$src, -1), (DEC32r    GR32:$src)>, Requires<[In32BitMode]>;
1695 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1696 def : Pat<(add GR64:$src, -1), (DEC64r    GR64:$src)>;
1697
1698 // or reg/reg.
1699 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr  GR8 :$src1, GR8 :$src2)>;
1700 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1701 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1702 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1703
1704 // or reg/mem
1705 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1706           (OR8rm GR8:$src1, addr:$src2)>;
1707 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1708           (OR16rm GR16:$src1, addr:$src2)>;
1709 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1710           (OR32rm GR32:$src1, addr:$src2)>;
1711 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1712           (OR64rm GR64:$src1, addr:$src2)>;
1713
1714 // or reg/imm
1715 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri  GR8 :$src1, imm:$src2)>;
1716 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1717 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1718 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1719           (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1720 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1721           (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1722 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1723           (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1724 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1725           (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1726
1727 // xor reg/reg
1728 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr  GR8 :$src1, GR8 :$src2)>;
1729 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1730 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1731 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1732
1733 // xor reg/mem
1734 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1735           (XOR8rm GR8:$src1, addr:$src2)>;
1736 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1737           (XOR16rm GR16:$src1, addr:$src2)>;
1738 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1739           (XOR32rm GR32:$src1, addr:$src2)>;
1740 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1741           (XOR64rm GR64:$src1, addr:$src2)>;
1742
1743 // xor reg/imm
1744 def : Pat<(xor GR8:$src1, imm:$src2),
1745           (XOR8ri GR8:$src1, imm:$src2)>;
1746 def : Pat<(xor GR16:$src1, imm:$src2),
1747           (XOR16ri GR16:$src1, imm:$src2)>;
1748 def : Pat<(xor GR32:$src1, imm:$src2),
1749           (XOR32ri GR32:$src1, imm:$src2)>;
1750 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1751           (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1752 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1753           (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1754 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1755           (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1756 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1757           (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1758
1759 // and reg/reg
1760 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr  GR8 :$src1, GR8 :$src2)>;
1761 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1762 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1763 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1764
1765 // and reg/mem
1766 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1767           (AND8rm GR8:$src1, addr:$src2)>;
1768 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1769           (AND16rm GR16:$src1, addr:$src2)>;
1770 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1771           (AND32rm GR32:$src1, addr:$src2)>;
1772 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1773           (AND64rm GR64:$src1, addr:$src2)>;
1774
1775 // and reg/imm
1776 def : Pat<(and GR8:$src1, imm:$src2),
1777           (AND8ri GR8:$src1, imm:$src2)>;
1778 def : Pat<(and GR16:$src1, imm:$src2),
1779           (AND16ri GR16:$src1, imm:$src2)>;
1780 def : Pat<(and GR32:$src1, imm:$src2),
1781           (AND32ri GR32:$src1, imm:$src2)>;
1782 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1783           (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1784 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1785           (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1786 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1787           (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1788 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1789           (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1790
1791 // Bit scan instruction patterns to match explicit zero-undef behavior.
1792 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1793 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1794 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1795 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1796 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1797 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;