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Imported Upstream version 0.6
[rustc.git] / src / llvm / lib / Target / X86 / X86InstrSSE.td
1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
13 //
14 //===----------------------------------------------------------------------===//
15
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 }
20
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
22 OpndItins s = arg_s;
23 OpndItins d = arg_d;
24 }
25
26
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
32 }
33
34
35 // scalar
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
38 >;
39
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
42 >;
43
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
46 >;
47
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
50 >;
51
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
54 >;
55
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
58 >;
59
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
62 >;
63
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
66 >;
67
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
70 >;
71
72 // parallel
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
75 >;
76
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
79 >;
80
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
83 >;
84
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
87 >;
88
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
91 >;
92
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
95 >;
96
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
99 >;
100
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
103 >;
104
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
107 >;
108
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
111 >;
112
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
115 >;
116
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
119 >;
120
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
123 >;
124
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
127 >;
128
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
131 >;
132
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
135 >;
136
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
140
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
144 OpndItins itins,
145 bit Is2Addr = 1> {
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
148 !if(Is2Addr,
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
152 }
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
154 !if(Is2Addr,
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
158 }
159
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
164 OpndItins itins,
165 bit Is2Addr = 1> {
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
167 !if(Is2Addr,
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
174 !if(Is2Addr,
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
180 }
181
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
189 !if(Is2Addr,
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
193 let mayLoad = 1 in
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
195 !if(Is2Addr,
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
199 itins.rm, d>;
200 }
201
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
206 bit Is2Addr = 1,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
210 !if(Is2Addr,
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
215 !if(Is2Addr,
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
219 }
220
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
227 !if(Is2Addr,
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
234 !if(Is2Addr,
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
240 }
241
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
245
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
251
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
258
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
263
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
268
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
272 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
273 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
274 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
275 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
276 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
277 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
278 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
279 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
280 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
281 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
282 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
283 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 }
285
286 // Implicitly promote a 32-bit scalar to a vector.
287 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
288 (COPY_TO_REGCLASS FR32:$src, VR128)>;
289 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
290 (COPY_TO_REGCLASS FR32:$src, VR128)>;
291 // Implicitly promote a 64-bit scalar to a vector.
292 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
293 (COPY_TO_REGCLASS FR64:$src, VR128)>;
294 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
295 (COPY_TO_REGCLASS FR64:$src, VR128)>;
296
297 // Bitcasts between 128-bit vector types. Return the original type since
298 // no instruction is needed for the conversion
299 let Predicates = [HasSSE2] in {
300 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
329 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 }
331
332 // Bitcasts between 256-bit vector types. Return the original type since
333 // no instruction is needed for the conversion
334 let Predicates = [HasAVX] in {
335 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
364 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 }
366
367 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
368 // This is expanded by ExpandPostRAPseudos.
369 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
370 isPseudo = 1 in {
371 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
372 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
373 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
374 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 }
376
377 //===----------------------------------------------------------------------===//
378 // AVX & SSE - Zero/One Vectors
379 //===----------------------------------------------------------------------===//
380
381 // Alias instruction that maps zero vector to pxor / xorp* for sse.
382 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
383 // swizzled by ExecutionDepsFix to pxor.
384 // We set canFoldAsLoad because this can be converted to a constant-pool
385 // load of an all-zeros value if folding it would be beneficial.
386 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
387 isPseudo = 1 in {
388 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
389 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
390 }
391
392 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
394 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
395 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
396 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397
398
399 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
400 // and doesn't need it because on sandy bridge the register is set to zero
401 // at the rename stage without using any execution unit, so SET0PSY
402 // and SET0PDY can be used for vector int instructions without penalty
403 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
404 isPseudo = 1, Predicates = [HasAVX] in {
405 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
406 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
407 }
408
409 let Predicates = [HasAVX] in
410 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
411
412 let Predicates = [HasAVX2] in {
413 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
414 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
415 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
416 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
417 }
418
419 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
420 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
421 let Predicates = [HasAVX1Only] in {
422 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
423 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
424 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
425
426 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
429
430 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
433
434 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
437 }
438
439 // We set canFoldAsLoad because this can be converted to a constant-pool
440 // load of an all-ones value if folding it would be beneficial.
441 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
442 isPseudo = 1 in {
443 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
444 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
445 let Predicates = [HasAVX2] in
446 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
447 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
448 }
449
450
451 //===----------------------------------------------------------------------===//
452 // SSE 1 & 2 - Move FP Scalar Instructions
453 //
454 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
455 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
456 // is used instead. Register-to-register movss/movsd is not modeled as an
457 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
458 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
459 //===----------------------------------------------------------------------===//
460
461 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
462 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
463 [(set VR128:$dst, (vt (OpNode VR128:$src1,
464 (scalar_to_vector RC:$src2))))],
465 IIC_SSE_MOV_S_RR>;
466
467 // Loading from memory automatically zeroing upper bits.
468 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
469 PatFrag mem_pat, string OpcodeStr> :
470 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
472 [(set RC:$dst, (mem_pat addr:$src))],
473 IIC_SSE_MOV_S_RM>;
474
475 // AVX
476 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
477 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
478 VEX_LIG;
479 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
480 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
481 VEX_LIG;
482
483 // For the disassembler
484 let isCodeGenOnly = 1 in {
485 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
486 (ins VR128:$src1, FR32:$src2),
487 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
488 IIC_SSE_MOV_S_RR>,
489 XS, VEX_4V, VEX_LIG;
490 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
491 (ins VR128:$src1, FR64:$src2),
492 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
493 IIC_SSE_MOV_S_RR>,
494 XD, VEX_4V, VEX_LIG;
495 }
496
497 let canFoldAsLoad = 1, isReMaterializable = 1 in {
498 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
499 VEX_LIG;
500 let AddedComplexity = 20 in
501 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
502 VEX_LIG;
503 }
504
505 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
506 "movss\t{$src, $dst|$dst, $src}",
507 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
508 XS, VEX, VEX_LIG;
509 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
510 "movsd\t{$src, $dst|$dst, $src}",
511 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
512 XD, VEX, VEX_LIG;
513
514 // SSE1 & 2
515 let Constraints = "$src1 = $dst" in {
516 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
517 "movss\t{$src2, $dst|$dst, $src2}">, XS;
518 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
519 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
520
521 // For the disassembler
522 let isCodeGenOnly = 1 in {
523 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
524 (ins VR128:$src1, FR32:$src2),
525 "movss\t{$src2, $dst|$dst, $src2}", [],
526 IIC_SSE_MOV_S_RR>, XS;
527 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
528 (ins VR128:$src1, FR64:$src2),
529 "movsd\t{$src2, $dst|$dst, $src2}", [],
530 IIC_SSE_MOV_S_RR>, XD;
531 }
532 }
533
534 let canFoldAsLoad = 1, isReMaterializable = 1 in {
535 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
536
537 let AddedComplexity = 20 in
538 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
539 }
540
541 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
542 "movss\t{$src, $dst|$dst, $src}",
543 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
544 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
545 "movsd\t{$src, $dst|$dst, $src}",
546 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
547
548 // Patterns
549 let Predicates = [HasAVX] in {
550 let AddedComplexity = 15 in {
551 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
552 // MOVS{S,D} to the lower bits.
553 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
554 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
555 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
556 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
557 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
558 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
559 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
560 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
561
562 // Move low f32 and clear high bits.
563 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
564 (SUBREG_TO_REG (i32 0),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
567 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
568 (SUBREG_TO_REG (i32 0),
569 (VMOVSSrr (v4i32 (V_SET0)),
570 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
571 }
572
573 let AddedComplexity = 20 in {
574 // MOVSSrm zeros the high parts of the register; represent this
575 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
576 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
577 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
578 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
579 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
580 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
581 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
582
583 // MOVSDrm zeros the high parts of the register; represent this
584 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
585 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
586 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
587 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
588 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
589 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
590 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
591 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
592 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
593 def : Pat<(v2f64 (X86vzload addr:$src)),
594 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
595
596 // Represent the same patterns above but in the form they appear for
597 // 256-bit types
598 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
599 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
600 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
601 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
602 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
603 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
604 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
605 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
606 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
607 }
608 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
609 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
610 (SUBREG_TO_REG (i32 0),
611 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
612 sub_xmm)>;
613 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
614 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
615 (SUBREG_TO_REG (i64 0),
616 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
617 sub_xmm)>;
618 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
619 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
620 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
621
622 // Move low f64 and clear high bits.
623 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
624 (SUBREG_TO_REG (i32 0),
625 (VMOVSDrr (v2f64 (V_SET0)),
626 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
627
628 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSDrr (v2i64 (V_SET0)),
631 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
632
633 // Extract and store.
634 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
635 addr:$dst),
636 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
637 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
638 addr:$dst),
639 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
640
641 // Shuffle with VMOVSS
642 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
643 (VMOVSSrr (v4i32 VR128:$src1),
644 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
645 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
646 (VMOVSSrr (v4f32 VR128:$src1),
647 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
648
649 // 256-bit variants
650 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
651 (SUBREG_TO_REG (i32 0),
652 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
653 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
654 sub_xmm)>;
655 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
656 (SUBREG_TO_REG (i32 0),
657 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
658 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
659 sub_xmm)>;
660
661 // Shuffle with VMOVSD
662 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
663 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
664 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
665 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
666 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
667 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
668 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
670
671 // 256-bit variants
672 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
673 (SUBREG_TO_REG (i32 0),
674 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
675 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
676 sub_xmm)>;
677 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
678 (SUBREG_TO_REG (i32 0),
679 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
680 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
681 sub_xmm)>;
682
683
684 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
685 // is during lowering, where it's not possible to recognize the fold cause
686 // it has two uses through a bitcast. One use disappears at isel time and the
687 // fold opportunity reappears.
688 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
689 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
690 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
691 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
692 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
693 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
694 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
695 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
696 }
697
698 let Predicates = [UseSSE1] in {
699 let AddedComplexity = 15 in {
700 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
701 // MOVSS to the lower bits.
702 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
703 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
704 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
705 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
706 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
707 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
708 }
709
710 let AddedComplexity = 20 in {
711 // MOVSSrm already zeros the high parts of the register.
712 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
713 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
714 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
715 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
716 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
717 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
718 }
719
720 // Extract and store.
721 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
722 addr:$dst),
723 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
724
725 // Shuffle with MOVSS
726 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
727 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
728 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
729 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
730 }
731
732 let Predicates = [UseSSE2] in {
733 let AddedComplexity = 15 in {
734 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
735 // MOVSD to the lower bits.
736 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
737 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
738 }
739
740 let AddedComplexity = 20 in {
741 // MOVSDrm already zeros the high parts of the register.
742 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
743 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
744 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
745 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
746 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
747 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
748 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
749 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
750 def : Pat<(v2f64 (X86vzload addr:$src)),
751 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
752 }
753
754 // Extract and store.
755 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
756 addr:$dst),
757 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
758
759 // Shuffle with MOVSD
760 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
761 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
762 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
763 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
764 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
765 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
766 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
767 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
768
769 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
770 // is during lowering, where it's not possible to recognize the fold cause
771 // it has two uses through a bitcast. One use disappears at isel time and the
772 // fold opportunity reappears.
773 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
774 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
775 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
776 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
777 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
778 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
779 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
780 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
781 }
782
783 //===----------------------------------------------------------------------===//
784 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
785 //===----------------------------------------------------------------------===//
786
787 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
788 X86MemOperand x86memop, PatFrag ld_frag,
789 string asm, Domain d,
790 OpndItins itins,
791 bit IsReMaterializable = 1> {
792 let neverHasSideEffects = 1 in
793 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
794 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
795 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
796 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
797 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
798 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
799 }
800
801 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
802 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
803 TB, VEX;
804 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
805 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
806 TB, OpSize, VEX;
807 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
808 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
809 TB, VEX;
810 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
811 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
812 TB, OpSize, VEX;
813
814 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
815 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
816 TB, VEX, VEX_L;
817 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
818 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
819 TB, OpSize, VEX, VEX_L;
820 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
821 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
822 TB, VEX, VEX_L;
823 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
824 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
825 TB, OpSize, VEX, VEX_L;
826 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
827 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
828 TB;
829 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
830 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
831 TB, OpSize;
832 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
833 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
834 TB;
835 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
836 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 TB, OpSize;
838
839 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
840 "movaps\t{$src, $dst|$dst, $src}",
841 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
842 IIC_SSE_MOVA_P_MR>, VEX;
843 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
844 "movapd\t{$src, $dst|$dst, $src}",
845 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
846 IIC_SSE_MOVA_P_MR>, VEX;
847 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
848 "movups\t{$src, $dst|$dst, $src}",
849 [(store (v4f32 VR128:$src), addr:$dst)],
850 IIC_SSE_MOVU_P_MR>, VEX;
851 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
852 "movupd\t{$src, $dst|$dst, $src}",
853 [(store (v2f64 VR128:$src), addr:$dst)],
854 IIC_SSE_MOVU_P_MR>, VEX;
855 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
856 "movaps\t{$src, $dst|$dst, $src}",
857 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
858 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
859 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
860 "movapd\t{$src, $dst|$dst, $src}",
861 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
862 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
863 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
864 "movups\t{$src, $dst|$dst, $src}",
865 [(store (v8f32 VR256:$src), addr:$dst)],
866 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
867 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
868 "movupd\t{$src, $dst|$dst, $src}",
869 [(store (v4f64 VR256:$src), addr:$dst)],
870 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
871
872 // For disassembler
873 let isCodeGenOnly = 1 in {
874 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
875 (ins VR128:$src),
876 "movaps\t{$src, $dst|$dst, $src}", [],
877 IIC_SSE_MOVA_P_RR>, VEX;
878 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
879 (ins VR128:$src),
880 "movapd\t{$src, $dst|$dst, $src}", [],
881 IIC_SSE_MOVA_P_RR>, VEX;
882 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
883 (ins VR128:$src),
884 "movups\t{$src, $dst|$dst, $src}", [],
885 IIC_SSE_MOVU_P_RR>, VEX;
886 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
887 (ins VR128:$src),
888 "movupd\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVU_P_RR>, VEX;
890 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
891 (ins VR256:$src),
892 "movaps\t{$src, $dst|$dst, $src}", [],
893 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
894 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
895 (ins VR256:$src),
896 "movapd\t{$src, $dst|$dst, $src}", [],
897 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
898 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
899 (ins VR256:$src),
900 "movups\t{$src, $dst|$dst, $src}", [],
901 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
902 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
903 (ins VR256:$src),
904 "movupd\t{$src, $dst|$dst, $src}", [],
905 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
906 }
907
908 let Predicates = [HasAVX] in {
909 def : Pat<(v8i32 (X86vzmovl
910 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
911 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
912 def : Pat<(v4i64 (X86vzmovl
913 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
914 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
915 def : Pat<(v8f32 (X86vzmovl
916 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
917 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
918 def : Pat<(v4f64 (X86vzmovl
919 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
920 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
921 }
922
923
924 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
925 (VMOVUPSYmr addr:$dst, VR256:$src)>;
926 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
927 (VMOVUPDYmr addr:$dst, VR256:$src)>;
928
929 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
930 "movaps\t{$src, $dst|$dst, $src}",
931 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
932 IIC_SSE_MOVA_P_MR>;
933 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
934 "movapd\t{$src, $dst|$dst, $src}",
935 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
936 IIC_SSE_MOVA_P_MR>;
937 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
938 "movups\t{$src, $dst|$dst, $src}",
939 [(store (v4f32 VR128:$src), addr:$dst)],
940 IIC_SSE_MOVU_P_MR>;
941 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
942 "movupd\t{$src, $dst|$dst, $src}",
943 [(store (v2f64 VR128:$src), addr:$dst)],
944 IIC_SSE_MOVU_P_MR>;
945
946 // For disassembler
947 let isCodeGenOnly = 1 in {
948 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
949 "movaps\t{$src, $dst|$dst, $src}", [],
950 IIC_SSE_MOVA_P_RR>;
951 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
952 "movapd\t{$src, $dst|$dst, $src}", [],
953 IIC_SSE_MOVA_P_RR>;
954 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
955 "movups\t{$src, $dst|$dst, $src}", [],
956 IIC_SSE_MOVU_P_RR>;
957 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
958 "movupd\t{$src, $dst|$dst, $src}", [],
959 IIC_SSE_MOVU_P_RR>;
960 }
961
962 let Predicates = [HasAVX] in {
963 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
964 (VMOVUPSmr addr:$dst, VR128:$src)>;
965 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
966 (VMOVUPDmr addr:$dst, VR128:$src)>;
967 }
968
969 let Predicates = [UseSSE1] in
970 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
971 (MOVUPSmr addr:$dst, VR128:$src)>;
972 let Predicates = [UseSSE2] in
973 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
974 (MOVUPDmr addr:$dst, VR128:$src)>;
975
976 // Use vmovaps/vmovups for AVX integer load/store.
977 let Predicates = [HasAVX] in {
978 // 128-bit load/store
979 def : Pat<(alignedloadv2i64 addr:$src),
980 (VMOVAPSrm addr:$src)>;
981 def : Pat<(loadv2i64 addr:$src),
982 (VMOVUPSrm addr:$src)>;
983
984 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
985 (VMOVAPSmr addr:$dst, VR128:$src)>;
986 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
987 (VMOVAPSmr addr:$dst, VR128:$src)>;
988 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
989 (VMOVAPSmr addr:$dst, VR128:$src)>;
990 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
991 (VMOVAPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
993 (VMOVUPSmr addr:$dst, VR128:$src)>;
994 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
995 (VMOVUPSmr addr:$dst, VR128:$src)>;
996 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
999 (VMOVUPSmr addr:$dst, VR128:$src)>;
1000
1001 // 256-bit load/store
1002 def : Pat<(alignedloadv4i64 addr:$src),
1003 (VMOVAPSYrm addr:$src)>;
1004 def : Pat<(loadv4i64 addr:$src),
1005 (VMOVUPSYrm addr:$src)>;
1006 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1007 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1008 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1009 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1010 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1011 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1012 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1013 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1014 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1015 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1016 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1017 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1018 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1019 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1020 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1021 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1022
1023 // Special patterns for storing subvector extracts of lower 128-bits
1024 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1025 def : Pat<(alignedstore (v2f64 (extract_subvector
1026 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1027 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1028 def : Pat<(alignedstore (v4f32 (extract_subvector
1029 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1030 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1031 def : Pat<(alignedstore (v2i64 (extract_subvector
1032 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1033 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1034 def : Pat<(alignedstore (v4i32 (extract_subvector
1035 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1036 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1037 def : Pat<(alignedstore (v8i16 (extract_subvector
1038 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1039 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1040 def : Pat<(alignedstore (v16i8 (extract_subvector
1041 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1042 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1043
1044 def : Pat<(store (v2f64 (extract_subvector
1045 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1046 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1047 def : Pat<(store (v4f32 (extract_subvector
1048 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1049 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 def : Pat<(store (v2i64 (extract_subvector
1051 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1052 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1053 def : Pat<(store (v4i32 (extract_subvector
1054 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1055 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1056 def : Pat<(store (v8i16 (extract_subvector
1057 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1058 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1059 def : Pat<(store (v16i8 (extract_subvector
1060 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1061 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1062 }
1063
1064 // Use movaps / movups for SSE integer load / store (one byte shorter).
1065 // The instructions selected below are then converted to MOVDQA/MOVDQU
1066 // during the SSE domain pass.
1067 let Predicates = [UseSSE1] in {
1068 def : Pat<(alignedloadv2i64 addr:$src),
1069 (MOVAPSrm addr:$src)>;
1070 def : Pat<(loadv2i64 addr:$src),
1071 (MOVUPSrm addr:$src)>;
1072
1073 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1074 (MOVAPSmr addr:$dst, VR128:$src)>;
1075 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1076 (MOVAPSmr addr:$dst, VR128:$src)>;
1077 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1078 (MOVAPSmr addr:$dst, VR128:$src)>;
1079 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1080 (MOVAPSmr addr:$dst, VR128:$src)>;
1081 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1082 (MOVUPSmr addr:$dst, VR128:$src)>;
1083 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1084 (MOVUPSmr addr:$dst, VR128:$src)>;
1085 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1086 (MOVUPSmr addr:$dst, VR128:$src)>;
1087 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1088 (MOVUPSmr addr:$dst, VR128:$src)>;
1089 }
1090
1091 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1092 // bits are disregarded. FIXME: Set encoding to pseudo!
1093 let neverHasSideEffects = 1 in {
1094 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1095 "movaps\t{$src, $dst|$dst, $src}", [],
1096 IIC_SSE_MOVA_P_RR>, VEX;
1097 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1098 "movapd\t{$src, $dst|$dst, $src}", [],
1099 IIC_SSE_MOVA_P_RR>, VEX;
1100 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1101 "movaps\t{$src, $dst|$dst, $src}", [],
1102 IIC_SSE_MOVA_P_RR>;
1103 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1104 "movapd\t{$src, $dst|$dst, $src}", [],
1105 IIC_SSE_MOVA_P_RR>;
1106 }
1107
1108 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1109 // bits are disregarded. FIXME: Set encoding to pseudo!
1110 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1111 let isCodeGenOnly = 1 in {
1112 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1113 "movaps\t{$src, $dst|$dst, $src}",
1114 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1115 IIC_SSE_MOVA_P_RM>, VEX;
1116 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1117 "movapd\t{$src, $dst|$dst, $src}",
1118 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1119 IIC_SSE_MOVA_P_RM>, VEX;
1120 }
1121 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1122 "movaps\t{$src, $dst|$dst, $src}",
1123 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1124 IIC_SSE_MOVA_P_RM>;
1125 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1126 "movapd\t{$src, $dst|$dst, $src}",
1127 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1128 IIC_SSE_MOVA_P_RM>;
1129 }
1130
1131 //===----------------------------------------------------------------------===//
1132 // SSE 1 & 2 - Move Low packed FP Instructions
1133 //===----------------------------------------------------------------------===//
1134
1135 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1136 SDNode psnode, SDNode pdnode, string base_opc,
1137 string asm_opr, InstrItinClass itin> {
1138 def PSrm : PI<opc, MRMSrcMem,
1139 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1140 !strconcat(base_opc, "s", asm_opr),
1141 [(set RC:$dst,
1142 (psnode RC:$src1,
1143 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1144 itin, SSEPackedSingle>, TB;
1145
1146 def PDrm : PI<opc, MRMSrcMem,
1147 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1148 !strconcat(base_opc, "d", asm_opr),
1149 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1150 (scalar_to_vector (loadf64 addr:$src2)))))],
1151 itin, SSEPackedDouble>, TB, OpSize;
1152 }
1153
1154 let AddedComplexity = 20 in {
1155 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1156 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1157 IIC_SSE_MOV_LH>, VEX_4V;
1158 }
1159 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1160 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1161 "\t{$src2, $dst|$dst, $src2}",
1162 IIC_SSE_MOV_LH>;
1163 }
1164
1165 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1166 "movlps\t{$src, $dst|$dst, $src}",
1167 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1168 (iPTR 0))), addr:$dst)],
1169 IIC_SSE_MOV_LH>, VEX;
1170 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1171 "movlpd\t{$src, $dst|$dst, $src}",
1172 [(store (f64 (vector_extract (v2f64 VR128:$src),
1173 (iPTR 0))), addr:$dst)],
1174 IIC_SSE_MOV_LH>, VEX;
1175 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1176 "movlps\t{$src, $dst|$dst, $src}",
1177 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1178 (iPTR 0))), addr:$dst)],
1179 IIC_SSE_MOV_LH>;
1180 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1181 "movlpd\t{$src, $dst|$dst, $src}",
1182 [(store (f64 (vector_extract (v2f64 VR128:$src),
1183 (iPTR 0))), addr:$dst)],
1184 IIC_SSE_MOV_LH>;
1185
1186 let Predicates = [HasAVX] in {
1187 // Shuffle with VMOVLPS
1188 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1189 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1190 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1191 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1192
1193 // Shuffle with VMOVLPD
1194 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1195 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1196 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1197 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1198
1199 // Store patterns
1200 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1201 addr:$src1),
1202 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1203 def : Pat<(store (v4i32 (X86Movlps
1204 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1205 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1206 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1207 addr:$src1),
1208 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1209 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1210 addr:$src1),
1211 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1212 }
1213
1214 let Predicates = [UseSSE1] in {
1215 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1216 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1217 (iPTR 0))), addr:$src1),
1218 (MOVLPSmr addr:$src1, VR128:$src2)>;
1219
1220 // Shuffle with MOVLPS
1221 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1222 (MOVLPSrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1224 (MOVLPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(X86Movlps VR128:$src1,
1226 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1227 (MOVLPSrm VR128:$src1, addr:$src2)>;
1228
1229 // Store patterns
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1231 addr:$src1),
1232 (MOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1235 addr:$src1),
1236 (MOVLPSmr addr:$src1, VR128:$src2)>;
1237 }
1238
1239 let Predicates = [UseSSE2] in {
1240 // Shuffle with MOVLPD
1241 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1242 (MOVLPDrm VR128:$src1, addr:$src2)>;
1243 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1244 (MOVLPDrm VR128:$src1, addr:$src2)>;
1245
1246 // Store patterns
1247 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1248 addr:$src1),
1249 (MOVLPDmr addr:$src1, VR128:$src2)>;
1250 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1251 addr:$src1),
1252 (MOVLPDmr addr:$src1, VR128:$src2)>;
1253 }
1254
1255 //===----------------------------------------------------------------------===//
1256 // SSE 1 & 2 - Move Hi packed FP Instructions
1257 //===----------------------------------------------------------------------===//
1258
1259 let AddedComplexity = 20 in {
1260 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1261 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1262 IIC_SSE_MOV_LH>, VEX_4V;
1263 }
1264 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1265 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1266 "\t{$src2, $dst|$dst, $src2}",
1267 IIC_SSE_MOV_LH>;
1268 }
1269
1270 // v2f64 extract element 1 is always custom lowered to unpack high to low
1271 // and extract element 0 so the non-store version isn't too horrible.
1272 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1273 "movhps\t{$src, $dst|$dst, $src}",
1274 [(store (f64 (vector_extract
1275 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1276 (bc_v2f64 (v4f32 VR128:$src))),
1277 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1278 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1279 "movhpd\t{$src, $dst|$dst, $src}",
1280 [(store (f64 (vector_extract
1281 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1282 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1283 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1284 "movhps\t{$src, $dst|$dst, $src}",
1285 [(store (f64 (vector_extract
1286 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1287 (bc_v2f64 (v4f32 VR128:$src))),
1288 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1289 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1290 "movhpd\t{$src, $dst|$dst, $src}",
1291 [(store (f64 (vector_extract
1292 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1293 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1294
1295 let Predicates = [HasAVX] in {
1296 // VMOVHPS patterns
1297 def : Pat<(X86Movlhps VR128:$src1,
1298 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1299 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1300 def : Pat<(X86Movlhps VR128:$src1,
1301 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1302 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1303
1304 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1305 // is during lowering, where it's not possible to recognize the load fold
1306 // cause it has two uses through a bitcast. One use disappears at isel time
1307 // and the fold opportunity reappears.
1308 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1309 (scalar_to_vector (loadf64 addr:$src2)))),
1310 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1311 }
1312
1313 let Predicates = [UseSSE1] in {
1314 // MOVHPS patterns
1315 def : Pat<(X86Movlhps VR128:$src1,
1316 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1317 (MOVHPSrm VR128:$src1, addr:$src2)>;
1318 def : Pat<(X86Movlhps VR128:$src1,
1319 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1320 (MOVHPSrm VR128:$src1, addr:$src2)>;
1321 }
1322
1323 let Predicates = [UseSSE2] in {
1324 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1325 // is during lowering, where it's not possible to recognize the load fold
1326 // cause it has two uses through a bitcast. One use disappears at isel time
1327 // and the fold opportunity reappears.
1328 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1329 (scalar_to_vector (loadf64 addr:$src2)))),
1330 (MOVHPDrm VR128:$src1, addr:$src2)>;
1331 }
1332
1333 //===----------------------------------------------------------------------===//
1334 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1335 //===----------------------------------------------------------------------===//
1336
1337 let AddedComplexity = 20 in {
1338 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1341 [(set VR128:$dst,
1342 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1343 IIC_SSE_MOV_LH>,
1344 VEX_4V;
1345 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1346 (ins VR128:$src1, VR128:$src2),
1347 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1348 [(set VR128:$dst,
1349 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1350 IIC_SSE_MOV_LH>,
1351 VEX_4V;
1352 }
1353 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1354 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1355 (ins VR128:$src1, VR128:$src2),
1356 "movlhps\t{$src2, $dst|$dst, $src2}",
1357 [(set VR128:$dst,
1358 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1359 IIC_SSE_MOV_LH>;
1360 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1361 (ins VR128:$src1, VR128:$src2),
1362 "movhlps\t{$src2, $dst|$dst, $src2}",
1363 [(set VR128:$dst,
1364 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1365 IIC_SSE_MOV_LH>;
1366 }
1367
1368 let Predicates = [HasAVX] in {
1369 // MOVLHPS patterns
1370 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1371 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1372 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1373 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1374
1375 // MOVHLPS patterns
1376 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1377 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1378 }
1379
1380 let Predicates = [UseSSE1] in {
1381 // MOVLHPS patterns
1382 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1383 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1384 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1385 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1386
1387 // MOVHLPS patterns
1388 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1389 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1390 }
1391
1392 //===----------------------------------------------------------------------===//
1393 // SSE 1 & 2 - Conversion Instructions
1394 //===----------------------------------------------------------------------===//
1395
1396 def SSE_CVT_PD : OpndItins<
1397 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1398 >;
1399
1400 def SSE_CVT_PS : OpndItins<
1401 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1402 >;
1403
1404 def SSE_CVT_Scalar : OpndItins<
1405 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1406 >;
1407
1408 def SSE_CVT_SS2SI_32 : OpndItins<
1409 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1410 >;
1411
1412 def SSE_CVT_SS2SI_64 : OpndItins<
1413 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1414 >;
1415
1416 def SSE_CVT_SD2SI : OpndItins<
1417 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1418 >;
1419
1420 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1421 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1422 string asm, OpndItins itins> {
1423 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1424 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1425 itins.rr>;
1426 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1427 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1428 itins.rm>;
1429 }
1430
1431 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1432 X86MemOperand x86memop, string asm, Domain d,
1433 OpndItins itins> {
1434 let neverHasSideEffects = 1 in {
1435 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1436 [], itins.rr, d>;
1437 let mayLoad = 1 in
1438 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1439 [], itins.rm, d>;
1440 }
1441 }
1442
1443 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1444 X86MemOperand x86memop, string asm> {
1445 let neverHasSideEffects = 1 in {
1446 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1447 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1448 let mayLoad = 1 in
1449 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1450 (ins DstRC:$src1, x86memop:$src),
1451 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1452 } // neverHasSideEffects = 1
1453 }
1454
1455 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1456 "cvttss2si\t{$src, $dst|$dst, $src}",
1457 SSE_CVT_SS2SI_32>,
1458 XS, VEX, VEX_LIG;
1459 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1460 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1461 SSE_CVT_SS2SI_64>,
1462 XS, VEX, VEX_W, VEX_LIG;
1463 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1464 "cvttsd2si\t{$src, $dst|$dst, $src}",
1465 SSE_CVT_SD2SI>,
1466 XD, VEX, VEX_LIG;
1467 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1468 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1469 SSE_CVT_SD2SI>,
1470 XD, VEX, VEX_W, VEX_LIG;
1471
1472 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1473 // register, but the same isn't true when only using memory operands,
1474 // provide other assembly "l" and "q" forms to address this explicitly
1475 // where appropriate to do so.
1476 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1477 XS, VEX_4V, VEX_LIG;
1478 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1479 XS, VEX_4V, VEX_W, VEX_LIG;
1480 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1481 XD, VEX_4V, VEX_LIG;
1482 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1483 XD, VEX_4V, VEX_W, VEX_LIG;
1484
1485 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1486 (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
1487 def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
1488 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1489
1490 let Predicates = [HasAVX] in {
1491 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1492 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1493 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1494 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1495 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1496 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1497 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1498 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1499
1500 def : Pat<(f32 (sint_to_fp GR32:$src)),
1501 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1502 def : Pat<(f32 (sint_to_fp GR64:$src)),
1503 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1504 def : Pat<(f64 (sint_to_fp GR32:$src)),
1505 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1506 def : Pat<(f64 (sint_to_fp GR64:$src)),
1507 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1508 }
1509
1510 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1511 "cvttss2si\t{$src, $dst|$dst, $src}",
1512 SSE_CVT_SS2SI_32>, XS;
1513 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1514 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1515 SSE_CVT_SS2SI_64>, XS, REX_W;
1516 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1517 "cvttsd2si\t{$src, $dst|$dst, $src}",
1518 SSE_CVT_SD2SI>, XD;
1519 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1520 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1521 SSE_CVT_SD2SI>, XD, REX_W;
1522 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1523 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1524 SSE_CVT_Scalar>, XS;
1525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1527 SSE_CVT_Scalar>, XS, REX_W;
1528 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1529 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1530 SSE_CVT_Scalar>, XD;
1531 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1532 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1533 SSE_CVT_Scalar>, XD, REX_W;
1534
1535 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1536 // and/or XMM operand(s).
1537
1538 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1539 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1540 string asm, OpndItins itins> {
1541 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1543 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1544 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1545 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1546 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>;
1547 }
1548
1549 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1550 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1551 PatFrag ld_frag, string asm, OpndItins itins,
1552 bit Is2Addr = 1> {
1553 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1554 !if(Is2Addr,
1555 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1556 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1557 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1558 itins.rr>;
1559 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1560 (ins DstRC:$src1, x86memop:$src2),
1561 !if(Is2Addr,
1562 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1563 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1564 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1565 itins.rm>;
1566 }
1567
1568 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1569 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
1570 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1571 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1572 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
1573 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1574
1575 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1576 sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1577 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1578 sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1579
1580
1581 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1582 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1583 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1584 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1585 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1586 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1587 VEX_W;
1588 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1589 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1590 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1591 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1592 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1593 SSE_CVT_Scalar, 0>, XD,
1594 VEX_4V, VEX_W;
1595
1596 let Constraints = "$src1 = $dst" in {
1597 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1598 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1599 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1600 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1601 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1602 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1603 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1604 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1605 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1606 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1607 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1608 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1609 }
1610
1611 /// SSE 1 Only
1612
1613 // Aliases for intrinsics
1614 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1615 ssmem, sse_load_f32, "cvttss2si",
1616 SSE_CVT_SS2SI_32>, XS, VEX;
1617 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1618 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1619 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1620 XS, VEX, VEX_W;
1621 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1622 sdmem, sse_load_f64, "cvttsd2si",
1623 SSE_CVT_SD2SI>, XD, VEX;
1624 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1625 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1626 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1627 XD, VEX, VEX_W;
1628 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1629 ssmem, sse_load_f32, "cvttss2si",
1630 SSE_CVT_SS2SI_32>, XS;
1631 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1632 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1633 "cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
1634 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1635 sdmem, sse_load_f64, "cvttsd2si",
1636 SSE_CVT_SD2SI>, XD;
1637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1638 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1639 "cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1640
1641 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1642 ssmem, sse_load_f32, "cvtss2si{l}",
1643 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1644 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1645 ssmem, sse_load_f32, "cvtss2si{q}",
1646 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1647
1648 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1649 ssmem, sse_load_f32, "cvtss2si{l}",
1650 SSE_CVT_SS2SI_32>, XS;
1651 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1652 ssmem, sse_load_f32, "cvtss2si{q}",
1653 SSE_CVT_SS2SI_64>, XS, REX_W;
1654
1655 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1656 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1657 SSEPackedSingle, SSE_CVT_PS>,
1658 TB, VEX, Requires<[HasAVX]>;
1659 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1660 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1661 SSEPackedSingle, SSE_CVT_PS>,
1662 TB, VEX, VEX_L, Requires<[HasAVX]>;
1663
1664 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1665 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1666 SSEPackedSingle, SSE_CVT_PS>,
1667 TB, Requires<[UseSSE2]>;
1668
1669 /// SSE 2 Only
1670
1671 // Convert scalar double to scalar single
1672 let neverHasSideEffects = 1 in {
1673 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1674 (ins FR64:$src1, FR64:$src2),
1675 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1676 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1677 let mayLoad = 1 in
1678 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1679 (ins FR64:$src1, f64mem:$src2),
1680 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1681 [], IIC_SSE_CVT_Scalar_RM>,
1682 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1683 }
1684
1685 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1686 Requires<[HasAVX]>;
1687
1688 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1689 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1690 [(set FR32:$dst, (fround FR64:$src))],
1691 IIC_SSE_CVT_Scalar_RR>;
1692 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1695 IIC_SSE_CVT_Scalar_RM>,
1696 XD,
1697 Requires<[UseSSE2, OptForSize]>;
1698
1699 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1700 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1701 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1702 [(set VR128:$dst,
1703 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1704 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>;
1705 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1706 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1707 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1708 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1709 VR128:$src1, sse_load_f64:$src2))],
1710 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>;
1711
1712 let Constraints = "$src1 = $dst" in {
1713 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1714 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1715 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1716 [(set VR128:$dst,
1717 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1718 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>;
1719 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1720 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1721 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1722 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1723 VR128:$src1, sse_load_f64:$src2))],
1724 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>;
1725 }
1726
1727 // Convert scalar single to scalar double
1728 // SSE2 instructions with XS prefix
1729 let neverHasSideEffects = 1 in {
1730 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1731 (ins FR32:$src1, FR32:$src2),
1732 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1733 [], IIC_SSE_CVT_Scalar_RR>,
1734 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1735 let mayLoad = 1 in
1736 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1737 (ins FR32:$src1, f32mem:$src2),
1738 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1739 [], IIC_SSE_CVT_Scalar_RM>,
1740 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1741 }
1742
1743 def : Pat<(f64 (fextend FR32:$src)),
1744 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1745 def : Pat<(fextend (loadf32 addr:$src)),
1746 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1747
1748 def : Pat<(extloadf32 addr:$src),
1749 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1750 Requires<[HasAVX, OptForSize]>;
1751 def : Pat<(extloadf32 addr:$src),
1752 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1753 Requires<[HasAVX, OptForSpeed]>;
1754
1755 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1756 "cvtss2sd\t{$src, $dst|$dst, $src}",
1757 [(set FR64:$dst, (fextend FR32:$src))],
1758 IIC_SSE_CVT_Scalar_RR>, XS,
1759 Requires<[UseSSE2]>;
1760 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1761 "cvtss2sd\t{$src, $dst|$dst, $src}",
1762 [(set FR64:$dst, (extloadf32 addr:$src))],
1763 IIC_SSE_CVT_Scalar_RM>, XS,
1764 Requires<[UseSSE2, OptForSize]>;
1765
1766 // extload f32 -> f64. This matches load+fextend because we have a hack in
1767 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1768 // combine.
1769 // Since these loads aren't folded into the fextend, we have to match it
1770 // explicitly here.
1771 def : Pat<(fextend (loadf32 addr:$src)),
1772 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1773 def : Pat<(extloadf32 addr:$src),
1774 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1775
1776 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1779 [(set VR128:$dst,
1780 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1781 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>;
1782 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1784 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1785 [(set VR128:$dst,
1786 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1787 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>;
1788 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1789 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1790 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1791 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1792 [(set VR128:$dst,
1793 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1794 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>;
1795 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1796 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1797 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1798 [(set VR128:$dst,
1799 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1800 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>;
1801 }
1802
1803 // Convert packed single/double fp to doubleword
1804 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtps2dq\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1807 IIC_SSE_CVT_PS_RR>, VEX;
1808 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvtps2dq\t{$src, $dst|$dst, $src}",
1810 [(set VR128:$dst,
1811 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1812 IIC_SSE_CVT_PS_RM>, VEX;
1813 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1814 "cvtps2dq\t{$src, $dst|$dst, $src}",
1815 [(set VR256:$dst,
1816 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1817 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1818 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1819 "cvtps2dq\t{$src, $dst|$dst, $src}",
1820 [(set VR256:$dst,
1821 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1822 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1823 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1824 "cvtps2dq\t{$src, $dst|$dst, $src}",
1825 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1826 IIC_SSE_CVT_PS_RR>;
1827 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1828 "cvtps2dq\t{$src, $dst|$dst, $src}",
1829 [(set VR128:$dst,
1830 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1831 IIC_SSE_CVT_PS_RM>;
1832
1833
1834 // Convert Packed Double FP to Packed DW Integers
1835 let Predicates = [HasAVX] in {
1836 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1837 // register, but the same isn't true when using memory operands instead.
1838 // Provide other assembly rr and rm forms to address this explicitly.
1839 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1840 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1841 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1842 VEX;
1843
1844 // XMM only
1845 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1846 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1847 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1848 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1849 [(set VR128:$dst,
1850 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX;
1851
1852 // YMM only
1853 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1854 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1855 [(set VR128:$dst,
1856 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L;
1857 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1858 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1859 [(set VR128:$dst,
1860 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1861 VEX, VEX_L;
1862 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1863 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1864 }
1865
1866 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1867 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1868 [(set VR128:$dst,
1869 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1870 IIC_SSE_CVT_PD_RM>;
1871 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1872 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1873 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1874 IIC_SSE_CVT_PD_RR>;
1875
1876 // Convert with truncation packed single/double fp to doubleword
1877 // SSE2 packed instructions with XS prefix
1878 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1879 "cvttps2dq\t{$src, $dst|$dst, $src}",
1880 [(set VR128:$dst,
1881 (int_x86_sse2_cvttps2dq VR128:$src))],
1882 IIC_SSE_CVT_PS_RR>, VEX;
1883 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1884 "cvttps2dq\t{$src, $dst|$dst, $src}",
1885 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1886 (memopv4f32 addr:$src)))],
1887 IIC_SSE_CVT_PS_RM>, VEX;
1888 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1889 "cvttps2dq\t{$src, $dst|$dst, $src}",
1890 [(set VR256:$dst,
1891 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1892 IIC_SSE_CVT_PS_RR>, VEX, VEX_L;
1893 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1894 "cvttps2dq\t{$src, $dst|$dst, $src}",
1895 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1896 (memopv8f32 addr:$src)))],
1897 IIC_SSE_CVT_PS_RM>, VEX, VEX_L;
1898
1899 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "cvttps2dq\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1902 IIC_SSE_CVT_PS_RR>;
1903 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1904 "cvttps2dq\t{$src, $dst|$dst, $src}",
1905 [(set VR128:$dst,
1906 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1907 IIC_SSE_CVT_PS_RM>;
1908
1909 let Predicates = [HasAVX] in {
1910 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1911 (VCVTDQ2PSrr VR128:$src)>;
1912 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1913 (VCVTDQ2PSrm addr:$src)>;
1914
1915 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1916 (VCVTDQ2PSrr VR128:$src)>;
1917 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1918 (VCVTDQ2PSrm addr:$src)>;
1919
1920 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1921 (VCVTTPS2DQrr VR128:$src)>;
1922 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1923 (VCVTTPS2DQrm addr:$src)>;
1924
1925 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1926 (VCVTDQ2PSYrr VR256:$src)>;
1927 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1928 (VCVTDQ2PSYrm addr:$src)>;
1929
1930 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1931 (VCVTTPS2DQYrr VR256:$src)>;
1932 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1933 (VCVTTPS2DQYrm addr:$src)>;
1934 }
1935
1936 let Predicates = [UseSSE2] in {
1937 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1938 (CVTDQ2PSrr VR128:$src)>;
1939 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1940 (CVTDQ2PSrm addr:$src)>;
1941
1942 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1943 (CVTDQ2PSrr VR128:$src)>;
1944 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
1945 (CVTDQ2PSrm addr:$src)>;
1946
1947 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1948 (CVTTPS2DQrr VR128:$src)>;
1949 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1950 (CVTTPS2DQrm addr:$src)>;
1951 }
1952
1953 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1954 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1955 [(set VR128:$dst,
1956 (int_x86_sse2_cvttpd2dq VR128:$src))],
1957 IIC_SSE_CVT_PD_RR>, VEX;
1958
1959 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1960 // register, but the same isn't true when using memory operands instead.
1961 // Provide other assembly rr and rm forms to address this explicitly.
1962
1963 // XMM only
1964 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
1965 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
1966 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1967 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1969 (memopv2f64 addr:$src)))],
1970 IIC_SSE_CVT_PD_RM>, VEX;
1971
1972 // YMM only
1973 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1974 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1975 [(set VR128:$dst,
1976 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
1977 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
1978 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1979 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
1980 [(set VR128:$dst,
1981 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
1982 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1983 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
1984 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
1985
1986 let Predicates = [HasAVX] in {
1987 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
1988 (VCVTTPD2DQYrr VR256:$src)>;
1989 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
1990 (VCVTTPD2DQYrm addr:$src)>;
1991 } // Predicates = [HasAVX]
1992
1993 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1994 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1995 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1996 IIC_SSE_CVT_PD_RR>;
1997 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1998 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1999 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2000 (memopv2f64 addr:$src)))],
2001 IIC_SSE_CVT_PD_RM>;
2002
2003 // Convert packed single to packed double
2004 let Predicates = [HasAVX] in {
2005 // SSE2 instructions without OpSize prefix
2006 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2007 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2008 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2009 IIC_SSE_CVT_PD_RR>, TB, VEX;
2010 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2011 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2012 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2013 IIC_SSE_CVT_PD_RM>, TB, VEX;
2014 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2015 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2016 [(set VR256:$dst,
2017 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2018 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L;
2019 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2020 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2021 [(set VR256:$dst,
2022 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2023 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L;
2024 }
2025
2026 let Predicates = [UseSSE2] in {
2027 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2028 "cvtps2pd\t{$src, $dst|$dst, $src}",
2029 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2030 IIC_SSE_CVT_PD_RR>, TB;
2031 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2032 "cvtps2pd\t{$src, $dst|$dst, $src}",
2033 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2034 IIC_SSE_CVT_PD_RM>, TB;
2035 }
2036
2037 // Convert Packed DW Integers to Packed Double FP
2038 let Predicates = [HasAVX] in {
2039 let neverHasSideEffects = 1, mayLoad = 1 in
2040 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2041 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2042 []>, VEX;
2043 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2045 [(set VR128:$dst,
2046 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX;
2047 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2048 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2049 [(set VR256:$dst,
2050 (int_x86_avx_cvtdq2_pd_256
2051 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L;
2052 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2053 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2054 [(set VR256:$dst,
2055 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L;
2056 }
2057
2058 let neverHasSideEffects = 1, mayLoad = 1 in
2059 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2060 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2061 IIC_SSE_CVT_PD_RR>;
2062 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2063 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2064 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2065 IIC_SSE_CVT_PD_RM>;
2066
2067 // AVX 256-bit register conversion intrinsics
2068 let Predicates = [HasAVX] in {
2069 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2070 (VCVTDQ2PDYrr VR128:$src)>;
2071 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2072 (VCVTDQ2PDYrm addr:$src)>;
2073 } // Predicates = [HasAVX]
2074
2075 // Convert packed double to packed single
2076 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2077 // register, but the same isn't true when using memory operands instead.
2078 // Provide other assembly rr and rm forms to address this explicitly.
2079 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2080 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2081 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2082 IIC_SSE_CVT_PD_RR>, VEX;
2083
2084 // XMM only
2085 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2086 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2087 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2088 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2089 [(set VR128:$dst,
2090 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX;
2092
2093 // YMM only
2094 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2095 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2096 [(set VR128:$dst,
2097 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2098 IIC_SSE_CVT_PD_RR>, VEX, VEX_L;
2099 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2100 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2101 [(set VR128:$dst,
2102 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2103 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2104 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2105 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2106
2107 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2108 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2109 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2110 IIC_SSE_CVT_PD_RR>;
2111 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2112 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2113 [(set VR128:$dst,
2114 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2115 IIC_SSE_CVT_PD_RM>;
2116
2117
2118 // AVX 256-bit register conversion intrinsics
2119 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2120 // whenever possible to avoid declaring two versions of each one.
2121 let Predicates = [HasAVX] in {
2122 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2123 (VCVTDQ2PSYrr VR256:$src)>;
2124 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2125 (VCVTDQ2PSYrm addr:$src)>;
2126
2127 // Match fround and fextend for 128/256-bit conversions
2128 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2129 (VCVTPD2PSYrr VR256:$src)>;
2130 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2131 (VCVTPD2PSYrm addr:$src)>;
2132
2133 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2134 (VCVTPS2PDrr VR128:$src)>;
2135 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2136 (VCVTPS2PDYrr VR128:$src)>;
2137 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2138 (VCVTPS2PDYrm addr:$src)>;
2139 }
2140
2141 let Predicates = [UseSSE2] in {
2142 // Match fextend for 128 conversions
2143 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2144 (CVTPS2PDrr VR128:$src)>;
2145 }
2146
2147 //===----------------------------------------------------------------------===//
2148 // SSE 1 & 2 - Compare Instructions
2149 //===----------------------------------------------------------------------===//
2150
2151 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2152 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2153 Operand CC, SDNode OpNode, ValueType VT,
2154 PatFrag ld_frag, string asm, string asm_alt,
2155 OpndItins itins> {
2156 def rr : SIi8<0xC2, MRMSrcReg,
2157 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2158 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2159 itins.rr>;
2160 def rm : SIi8<0xC2, MRMSrcMem,
2161 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2162 [(set RC:$dst, (OpNode (VT RC:$src1),
2163 (ld_frag addr:$src2), imm:$cc))],
2164 itins.rm>;
2165
2166 // Accept explicit immediate argument form instead of comparison code.
2167 let neverHasSideEffects = 1 in {
2168 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2169 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2170 IIC_SSE_ALU_F32S_RR>;
2171 let mayLoad = 1 in
2172 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2173 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2174 IIC_SSE_ALU_F32S_RM>;
2175 }
2176 }
2177
2178 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2179 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2180 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2181 SSE_ALU_F32S>,
2182 XS, VEX_4V, VEX_LIG;
2183 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2184 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2185 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2186 SSE_ALU_F32S>, // same latency as 32 bit compare
2187 XD, VEX_4V, VEX_LIG;
2188
2189 let Constraints = "$src1 = $dst" in {
2190 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2191 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2192 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2193 XS;
2194 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2195 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2196 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2197 SSE_ALU_F32S>, // same latency as 32 bit compare
2198 XD;
2199 }
2200
2201 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2202 Intrinsic Int, string asm, OpndItins itins> {
2203 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2204 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2205 [(set VR128:$dst, (Int VR128:$src1,
2206 VR128:$src, imm:$cc))],
2207 itins.rr>;
2208 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2209 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2210 [(set VR128:$dst, (Int VR128:$src1,
2211 (load addr:$src), imm:$cc))],
2212 itins.rm>;
2213 }
2214
2215 // Aliases to match intrinsics which expect XMM operand(s).
2216 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2217 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2218 SSE_ALU_F32S>,
2219 XS, VEX_4V;
2220 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2221 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2222 SSE_ALU_F32S>, // same latency as f32
2223 XD, VEX_4V;
2224 let Constraints = "$src1 = $dst" in {
2225 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2226 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2227 SSE_ALU_F32S>, XS;
2228 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2229 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2230 SSE_ALU_F32S>, // same latency as f32
2231 XD;
2232 }
2233
2234
2235 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2236 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2237 ValueType vt, X86MemOperand x86memop,
2238 PatFrag ld_frag, string OpcodeStr, Domain d> {
2239 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2240 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2241 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2242 IIC_SSE_COMIS_RR, d>;
2243 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2244 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2245 [(set EFLAGS, (OpNode (vt RC:$src1),
2246 (ld_frag addr:$src2)))],
2247 IIC_SSE_COMIS_RM, d>;
2248 }
2249
2250 let Defs = [EFLAGS] in {
2251 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2252 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2253 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2254 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2255 VEX_LIG;
2256 let Pattern = []<dag> in {
2257 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2258 "comiss", SSEPackedSingle>, TB, VEX,
2259 VEX_LIG;
2260 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2261 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2262 VEX_LIG;
2263 }
2264
2265 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2266 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2267 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2268 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2269
2270 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2271 load, "comiss", SSEPackedSingle>, TB, VEX;
2272 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2273 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2274 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2275 "ucomiss", SSEPackedSingle>, TB;
2276 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2277 "ucomisd", SSEPackedDouble>, TB, OpSize;
2278
2279 let Pattern = []<dag> in {
2280 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2281 "comiss", SSEPackedSingle>, TB;
2282 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2283 "comisd", SSEPackedDouble>, TB, OpSize;
2284 }
2285
2286 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2287 load, "ucomiss", SSEPackedSingle>, TB;
2288 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2289 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2290
2291 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2292 "comiss", SSEPackedSingle>, TB;
2293 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2294 "comisd", SSEPackedDouble>, TB, OpSize;
2295 } // Defs = [EFLAGS]
2296
2297 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2298 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2299 Operand CC, Intrinsic Int, string asm,
2300 string asm_alt, Domain d> {
2301 def rri : PIi8<0xC2, MRMSrcReg,
2302 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2303 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2304 IIC_SSE_CMPP_RR, d>;
2305 def rmi : PIi8<0xC2, MRMSrcMem,
2306 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2307 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2308 IIC_SSE_CMPP_RM, d>;
2309
2310 // Accept explicit immediate argument form instead of comparison code.
2311 let neverHasSideEffects = 1 in {
2312 def rri_alt : PIi8<0xC2, MRMSrcReg,
2313 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2314 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2315 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2316 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2317 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2318 }
2319 }
2320
2321 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2322 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2323 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2324 SSEPackedSingle>, TB, VEX_4V;
2325 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2326 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2327 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2328 SSEPackedDouble>, TB, OpSize, VEX_4V;
2329 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2330 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2331 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2332 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2333 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2334 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2335 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2336 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2337 let Constraints = "$src1 = $dst" in {
2338 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2339 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2340 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2341 SSEPackedSingle>, TB;
2342 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2343 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2344 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2345 SSEPackedDouble>, TB, OpSize;
2346 }
2347
2348 let Predicates = [HasAVX] in {
2349 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2350 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2351 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2352 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2353 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2354 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2355 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2356 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2357
2358 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2359 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2360 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2361 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2362 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2363 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2364 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2365 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2366 }
2367
2368 let Predicates = [UseSSE1] in {
2369 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2370 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2371 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2372 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2373 }
2374
2375 let Predicates = [UseSSE2] in {
2376 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2377 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2378 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2379 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2380 }
2381
2382 //===----------------------------------------------------------------------===//
2383 // SSE 1 & 2 - Shuffle Instructions
2384 //===----------------------------------------------------------------------===//
2385
2386 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2387 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2388 ValueType vt, string asm, PatFrag mem_frag,
2389 Domain d, bit IsConvertibleToThreeAddress = 0> {
2390 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2391 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2392 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2393 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2394 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2395 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2396 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2397 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2398 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2399 }
2400
2401 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2402 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2403 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2404 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2405 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2406 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2407 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2408 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2409 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2410 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2411 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2412 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2413
2414 let Constraints = "$src1 = $dst" in {
2415 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2416 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2417 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2418 TB;
2419 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2420 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2421 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2422 TB, OpSize;
2423 }
2424
2425 let Predicates = [HasAVX] in {
2426 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2427 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2428 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2429 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2430 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2431
2432 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2433 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2434 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2435 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2436 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2437
2438 // 256-bit patterns
2439 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2440 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2441 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2442 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2443 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2444
2445 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2446 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2447 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2448 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2449 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2450 }
2451
2452 let Predicates = [UseSSE1] in {
2453 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2454 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2455 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2456 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2457 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2458 }
2459
2460 let Predicates = [UseSSE2] in {
2461 // Generic SHUFPD patterns
2462 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2463 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2464 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2465 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2466 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2467 }
2468
2469 //===----------------------------------------------------------------------===//
2470 // SSE 1 & 2 - Unpack Instructions
2471 //===----------------------------------------------------------------------===//
2472
2473 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2474 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2475 PatFrag mem_frag, RegisterClass RC,
2476 X86MemOperand x86memop, string asm,
2477 Domain d> {
2478 def rr : PI<opc, MRMSrcReg,
2479 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2480 asm, [(set RC:$dst,
2481 (vt (OpNode RC:$src1, RC:$src2)))],
2482 IIC_SSE_UNPCK, d>;
2483 def rm : PI<opc, MRMSrcMem,
2484 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2485 asm, [(set RC:$dst,
2486 (vt (OpNode RC:$src1,
2487 (mem_frag addr:$src2))))],
2488 IIC_SSE_UNPCK, d>;
2489 }
2490
2491 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2492 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2493 SSEPackedSingle>, TB, VEX_4V;
2494 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2495 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2496 SSEPackedDouble>, TB, OpSize, VEX_4V;
2497 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2498 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2499 SSEPackedSingle>, TB, VEX_4V;
2500 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2501 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2502 SSEPackedDouble>, TB, OpSize, VEX_4V;
2503
2504 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2505 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2506 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2507 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2508 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2509 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2510 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2511 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2512 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2513 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2514 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2515 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2516
2517 let Constraints = "$src1 = $dst" in {
2518 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2519 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2520 SSEPackedSingle>, TB;
2521 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2522 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2523 SSEPackedDouble>, TB, OpSize;
2524 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2525 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2526 SSEPackedSingle>, TB;
2527 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2528 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2529 SSEPackedDouble>, TB, OpSize;
2530 } // Constraints = "$src1 = $dst"
2531
2532 let Predicates = [HasAVX1Only] in {
2533 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2534 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2535 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2536 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2537 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2538 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2539 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2540 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2541
2542 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2543 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2544 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2545 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2546 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2547 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2548 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2549 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2550 }
2551
2552 let Predicates = [HasAVX] in {
2553 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2554 // problem is during lowering, where it's not possible to recognize the load
2555 // fold cause it has two uses through a bitcast. One use disappears at isel
2556 // time and the fold opportunity reappears.
2557 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2558 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2559 }
2560
2561 let Predicates = [UseSSE2] in {
2562 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2563 // problem is during lowering, where it's not possible to recognize the load
2564 // fold cause it has two uses through a bitcast. One use disappears at isel
2565 // time and the fold opportunity reappears.
2566 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2567 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2568 }
2569
2570 //===----------------------------------------------------------------------===//
2571 // SSE 1 & 2 - Extract Floating-Point Sign mask
2572 //===----------------------------------------------------------------------===//
2573
2574 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2575 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2576 Domain d> {
2577 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2578 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2579 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2580 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2581 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2582 IIC_SSE_MOVMSK, d>, REX_W;
2583 }
2584
2585 let Predicates = [HasAVX] in {
2586 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2587 "movmskps", SSEPackedSingle>, TB, VEX;
2588 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2589 "movmskpd", SSEPackedDouble>, TB,
2590 OpSize, VEX;
2591 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2592 "movmskps", SSEPackedSingle>, TB,
2593 VEX, VEX_L;
2594 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2595 "movmskpd", SSEPackedDouble>, TB,
2596 OpSize, VEX, VEX_L;
2597
2598 def : Pat<(i32 (X86fgetsign FR32:$src)),
2599 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2600 def : Pat<(i64 (X86fgetsign FR32:$src)),
2601 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2602 def : Pat<(i32 (X86fgetsign FR64:$src)),
2603 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2604 def : Pat<(i64 (X86fgetsign FR64:$src)),
2605 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2606
2607 // Assembler Only
2608 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2609 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2610 SSEPackedSingle>, TB, VEX;
2611 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2612 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2613 SSEPackedDouble>, TB,
2614 OpSize, VEX;
2615 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2616 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2617 SSEPackedSingle>, TB, VEX, VEX_L;
2618 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2619 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2620 SSEPackedDouble>, TB,
2621 OpSize, VEX, VEX_L;
2622 }
2623
2624 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2625 SSEPackedSingle>, TB;
2626 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2627 SSEPackedDouble>, TB, OpSize;
2628
2629 def : Pat<(i32 (X86fgetsign FR32:$src)),
2630 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2631 Requires<[UseSSE1]>;
2632 def : Pat<(i64 (X86fgetsign FR32:$src)),
2633 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2634 Requires<[UseSSE1]>;
2635 def : Pat<(i32 (X86fgetsign FR64:$src)),
2636 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2637 Requires<[UseSSE2]>;
2638 def : Pat<(i64 (X86fgetsign FR64:$src)),
2639 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2640 Requires<[UseSSE2]>;
2641
2642 //===---------------------------------------------------------------------===//
2643 // SSE2 - Packed Integer Logical Instructions
2644 //===---------------------------------------------------------------------===//
2645
2646 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2647
2648 /// PDI_binop_rm - Simple SSE2 binary operator.
2649 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2650 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2651 X86MemOperand x86memop,
2652 OpndItins itins,
2653 bit IsCommutable = 0,
2654 bit Is2Addr = 1> {
2655 let isCommutable = IsCommutable in
2656 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2657 (ins RC:$src1, RC:$src2),
2658 !if(Is2Addr,
2659 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2661 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2662 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2663 (ins RC:$src1, x86memop:$src2),
2664 !if(Is2Addr,
2665 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2666 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2667 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2668 (bitconvert (memop_frag addr:$src2)))))],
2669 itins.rm>;
2670 }
2671 } // ExeDomain = SSEPackedInt
2672
2673 // These are ordered here for pattern ordering requirements with the fp versions
2674
2675 let Predicates = [HasAVX] in {
2676 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2677 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2678 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2679 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2680 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2681 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2682 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2683 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2684 }
2685
2686 let Constraints = "$src1 = $dst" in {
2687 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2688 i128mem, SSE_BIT_ITINS_P, 1>;
2689 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2690 i128mem, SSE_BIT_ITINS_P, 1>;
2691 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2692 i128mem, SSE_BIT_ITINS_P, 1>;
2693 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2694 i128mem, SSE_BIT_ITINS_P, 0>;
2695 } // Constraints = "$src1 = $dst"
2696
2697 let Predicates = [HasAVX2] in {
2698 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2699 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2700 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2701 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2702 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2703 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V, VEX_L;
2704 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2705 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V, VEX_L;
2706 }
2707
2708 //===----------------------------------------------------------------------===//
2709 // SSE 1 & 2 - Logical Instructions
2710 //===----------------------------------------------------------------------===//
2711
2712 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2713 ///
2714 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2715 SDNode OpNode, OpndItins itins> {
2716 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2717 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2718 TB, VEX_4V;
2719
2720 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2721 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2722 TB, OpSize, VEX_4V;
2723
2724 let Constraints = "$src1 = $dst" in {
2725 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2726 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2727 TB;
2728
2729 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2730 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2731 TB, OpSize;
2732 }
2733 }
2734
2735 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2736 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2737 SSE_BIT_ITINS_P>;
2738 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2739 SSE_BIT_ITINS_P>;
2740 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2741 SSE_BIT_ITINS_P>;
2742
2743 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2744 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2745 SSE_BIT_ITINS_P>;
2746
2747 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2748 ///
2749 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2750 SDNode OpNode> {
2751 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2752 // are all promoted to v2i64, and the patterns are covered by the int
2753 // version. This is needed in SSE only, because v2i64 isn't supported on
2754 // SSE1, but only on SSE2.
2755 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2756 !strconcat(OpcodeStr, "ps"), f128mem, [],
2757 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2758 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2759
2760 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2761 !strconcat(OpcodeStr, "pd"), f128mem,
2762 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2763 (bc_v2i64 (v2f64 VR128:$src2))))],
2764 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2765 (memopv2i64 addr:$src2)))], 0>,
2766 TB, OpSize, VEX_4V;
2767 let Constraints = "$src1 = $dst" in {
2768 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2769 !strconcat(OpcodeStr, "ps"), f128mem,
2770 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2771 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2772 (memopv2i64 addr:$src2)))]>, TB;
2773
2774 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2775 !strconcat(OpcodeStr, "pd"), f128mem,
2776 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2777 (bc_v2i64 (v2f64 VR128:$src2))))],
2778 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2779 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2780 }
2781 }
2782
2783 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2784 ///
2785 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2786 SDNode OpNode> {
2787 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2788 !strconcat(OpcodeStr, "ps"), f256mem,
2789 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2790 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2791 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2792
2793 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2794 !strconcat(OpcodeStr, "pd"), f256mem,
2795 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2796 (bc_v4i64 (v4f64 VR256:$src2))))],
2797 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2798 (memopv4i64 addr:$src2)))], 0>,
2799 TB, OpSize, VEX_4V, VEX_L;
2800 }
2801
2802 // AVX 256-bit packed logical ops forms
2803 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2804 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2805 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2806 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2807
2808 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2809 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2810 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2811 let isCommutable = 0 in
2812 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2813
2814 //===----------------------------------------------------------------------===//
2815 // SSE 1 & 2 - Arithmetic Instructions
2816 //===----------------------------------------------------------------------===//
2817
2818 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2819 /// vector forms.
2820 ///
2821 /// In addition, we also have a special variant of the scalar form here to
2822 /// represent the associated intrinsic operation. This form is unlike the
2823 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2824 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2825 ///
2826 /// These three forms can each be reg+reg or reg+mem.
2827 ///
2828
2829 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2830 /// classes below
2831 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2832 SizeItins itins,
2833 bit Is2Addr = 1> {
2834 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2835 OpNode, FR32, f32mem,
2836 itins.s, Is2Addr>, XS;
2837 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2838 OpNode, FR64, f64mem,
2839 itins.d, Is2Addr>, XD;
2840 }
2841
2842 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2843 SizeItins itins,
2844 bit Is2Addr = 1> {
2845 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2846 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2847 TB;
2848 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2849 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2850 TB, OpSize;
2851 }
2852
2853 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2854 SDNode OpNode,
2855 SizeItins itins> {
2856 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2857 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2858 TB, VEX_L;
2859 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2860 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2861 TB, OpSize, VEX_L;
2862 }
2863
2864 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2865 SizeItins itins,
2866 bit Is2Addr = 1> {
2867 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2868 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2869 itins.s, Is2Addr>, XS;
2870 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2871 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2872 itins.d, Is2Addr>, XD;
2873 }
2874
2875 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2876 SizeItins itins,
2877 bit Is2Addr = 1> {
2878 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2879 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2880 SSEPackedSingle, itins.s, Is2Addr>,
2881 TB;
2882
2883 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2884 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2885 SSEPackedDouble, itins.d, Is2Addr>,
2886 TB, OpSize;
2887 }
2888
2889 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2890 SizeItins itins> {
2891 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2892 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2893 SSEPackedSingle, itins.s, 0>, TB, VEX_L;
2894
2895 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2896 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2897 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_L;
2898 }
2899
2900 // Binary Arithmetic instructions
2901 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2902 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2903 VEX_4V, VEX_LIG;
2904 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2905 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2906 VEX_4V;
2907 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2908 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2909 VEX_4V, VEX_LIG;
2910 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2911 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2912 VEX_4V;
2913
2914 let isCommutable = 0 in {
2915 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2916 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2917 VEX_4V, VEX_LIG;
2918 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2919 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2920 VEX_4V;
2921 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2922 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2923 VEX_4V, VEX_LIG;
2924 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2925 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2926 VEX_4V;
2927 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2928 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2929 VEX_4V, VEX_LIG;
2930 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2931 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2932 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2933 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2934 VEX_4V;
2935 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2936 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2937 VEX_4V, VEX_LIG;
2938 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2939 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2940 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2941 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2942 VEX_4V;
2943 }
2944
2945 let Constraints = "$src1 = $dst" in {
2946 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2947 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2948 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2949 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2950 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2951 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2952
2953 let isCommutable = 0 in {
2954 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2955 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2956 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2957 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2958 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2959 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2960 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2961 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2962 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2963 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2964 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2965 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2966 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2967 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2968 }
2969 }
2970
2971 let isCodeGenOnly = 1 in {
2972 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
2973 VEX_4V, VEX_LIG;
2974 defm VMAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P, 0>,
2975 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>, VEX_4V;
2976 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
2977 VEX_4V, VEX_LIG;
2978 defm VMINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P, 0>,
2979 basic_sse12_fp_binop_p_y<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>, VEX_4V;
2980 let Constraints = "$src1 = $dst" in {
2981 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>,
2982 basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2983 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>,
2984 basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2985 }
2986 }
2987
2988 /// Unop Arithmetic
2989 /// In addition, we also have a special variant of the scalar form here to
2990 /// represent the associated intrinsic operation. This form is unlike the
2991 /// plain scalar form, in that it takes an entire vector (instead of a
2992 /// scalar) and leaves the top elements undefined.
2993 ///
2994 /// And, we have a special variant form for a full-vector intrinsic form.
2995
2996 def SSE_SQRTP : OpndItins<
2997 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2998 >;
2999
3000 def SSE_SQRTS : OpndItins<
3001 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
3002 >;
3003
3004 def SSE_RCPP : OpndItins<
3005 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3006 >;
3007
3008 def SSE_RCPS : OpndItins<
3009 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3010 >;
3011
3012 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3013 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3014 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3015 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3016 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3017 [(set FR32:$dst, (OpNode FR32:$src))]>;
3018 // For scalar unary operations, fold a load into the operation
3019 // only in OptForSize mode. It eliminates an instruction, but it also
3020 // eliminates a whole-register clobber (the load), so it introduces a
3021 // partial register update condition.
3022 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3023 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3024 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3025 Requires<[UseSSE1, OptForSize]>;
3026 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3027 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3028 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3029 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3030 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3031 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3032 }
3033
3034 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3035 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3036 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3037 !strconcat(OpcodeStr,
3038 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3039 let mayLoad = 1 in {
3040 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3041 !strconcat(OpcodeStr,
3042 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3043 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3044 (ins VR128:$src1, ssmem:$src2),
3045 !strconcat(OpcodeStr,
3046 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3047 }
3048 }
3049
3050 /// sse1_fp_unop_p - SSE1 unops in packed form.
3051 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3052 OpndItins itins> {
3053 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3054 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3055 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3056 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3057 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3058 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3059 }
3060
3061 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3062 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3063 OpndItins itins> {
3064 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3065 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3066 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3067 itins.rr>, VEX_L;
3068 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3069 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3070 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3071 itins.rm>, VEX_L;
3072 }
3073
3074 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3075 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3076 Intrinsic V4F32Int, OpndItins itins> {
3077 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3078 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3079 [(set VR128:$dst, (V4F32Int VR128:$src))],
3080 itins.rr>;
3081 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3082 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3083 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3084 itins.rm>;
3085 }
3086
3087 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3088 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3089 Intrinsic V4F32Int, OpndItins itins> {
3090 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3091 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3092 [(set VR256:$dst, (V4F32Int VR256:$src))],
3093 itins.rr>, VEX_L;
3094 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3095 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3096 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3097 itins.rm>, VEX_L;
3098 }
3099
3100 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3101 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3102 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3103 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3104 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3105 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3106 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3107 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3108 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3109 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3110 Requires<[UseSSE2, OptForSize]>;
3111 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3112 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3113 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3114 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3115 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3116 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3117 }
3118
3119 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3120 let hasSideEffects = 0 in
3121 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3122 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3123 !strconcat(OpcodeStr,
3124 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3125 let mayLoad = 1 in {
3126 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3127 !strconcat(OpcodeStr,
3128 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3129 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3130 (ins VR128:$src1, sdmem:$src2),
3131 !strconcat(OpcodeStr,
3132 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3133 }
3134 }
3135
3136 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3137 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3138 SDNode OpNode, OpndItins itins> {
3139 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3140 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3141 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3142 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3143 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3144 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3145 }
3146
3147 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3148 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3149 OpndItins itins> {
3150 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3151 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3152 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3153 itins.rr>, VEX_L;
3154 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3155 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3156 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3157 itins.rm>, VEX_L;
3158 }
3159
3160 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3161 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3162 Intrinsic V2F64Int, OpndItins itins> {
3163 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3164 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3165 [(set VR128:$dst, (V2F64Int VR128:$src))],
3166 itins.rr>;
3167 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3168 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3169 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3170 itins.rm>;
3171 }
3172
3173 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3174 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3175 Intrinsic V2F64Int, OpndItins itins> {
3176 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3177 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3178 [(set VR256:$dst, (V2F64Int VR256:$src))],
3179 itins.rr>, VEX_L;
3180 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3181 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3182 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3183 itins.rm>, VEX_L;
3184 }
3185
3186 let Predicates = [HasAVX] in {
3187 // Square root.
3188 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3189 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3190
3191 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3192 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3193 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3194 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3195 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3196 SSE_SQRTP>,
3197 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3198 SSE_SQRTP>,
3199 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3200 SSE_SQRTP>,
3201 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3202 SSE_SQRTP>,
3203 VEX;
3204
3205 // Reciprocal approximations. Note that these typically require refinement
3206 // in order to obtain suitable precision.
3207 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3208 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3209 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3210 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3211 SSE_SQRTP>,
3212 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3213 SSE_SQRTP>, VEX;
3214
3215 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3216 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3217 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3218 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3219 SSE_RCPP>,
3220 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3221 SSE_RCPP>, VEX;
3222 }
3223
3224 def : Pat<(f32 (fsqrt FR32:$src)),
3225 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3226 def : Pat<(f32 (fsqrt (load addr:$src))),
3227 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3228 Requires<[HasAVX, OptForSize]>;
3229 def : Pat<(f64 (fsqrt FR64:$src)),
3230 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3231 def : Pat<(f64 (fsqrt (load addr:$src))),
3232 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3233 Requires<[HasAVX, OptForSize]>;
3234
3235 def : Pat<(f32 (X86frsqrt FR32:$src)),
3236 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3237 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3238 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3239 Requires<[HasAVX, OptForSize]>;
3240
3241 def : Pat<(f32 (X86frcp FR32:$src)),
3242 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3243 def : Pat<(f32 (X86frcp (load addr:$src))),
3244 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3245 Requires<[HasAVX, OptForSize]>;
3246
3247 let Predicates = [HasAVX] in {
3248 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3249 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3250 (COPY_TO_REGCLASS VR128:$src, FR32)),
3251 VR128)>;
3252 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3253 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3254
3255 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3256 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3257 (COPY_TO_REGCLASS VR128:$src, FR64)),
3258 VR128)>;
3259 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3260 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3261
3262 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3263 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3264 (COPY_TO_REGCLASS VR128:$src, FR32)),
3265 VR128)>;
3266 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3267 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3268
3269 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3270 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3271 (COPY_TO_REGCLASS VR128:$src, FR32)),
3272 VR128)>;
3273 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3274 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3275 }
3276
3277 // Square root.
3278 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3279 SSE_SQRTS>,
3280 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3281 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3282 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3283 SSE_SQRTS>,
3284 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3285 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3286
3287 // Reciprocal approximations. Note that these typically require refinement
3288 // in order to obtain suitable precision.
3289 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3290 SSE_SQRTS>,
3291 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3292 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3293 SSE_SQRTS>;
3294 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3295 SSE_RCPS>,
3296 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3297 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3298
3299 // There is no f64 version of the reciprocal approximation instructions.
3300
3301 //===----------------------------------------------------------------------===//
3302 // SSE 1 & 2 - Non-temporal stores
3303 //===----------------------------------------------------------------------===//
3304
3305 let AddedComplexity = 400 in { // Prefer non-temporal versions
3306 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3307 (ins f128mem:$dst, VR128:$src),
3308 "movntps\t{$src, $dst|$dst, $src}",
3309 [(alignednontemporalstore (v4f32 VR128:$src),
3310 addr:$dst)],
3311 IIC_SSE_MOVNT>, VEX;
3312 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3313 (ins f128mem:$dst, VR128:$src),
3314 "movntpd\t{$src, $dst|$dst, $src}",
3315 [(alignednontemporalstore (v2f64 VR128:$src),
3316 addr:$dst)],
3317 IIC_SSE_MOVNT>, VEX;
3318
3319 let ExeDomain = SSEPackedInt in
3320 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3321 (ins f128mem:$dst, VR128:$src),
3322 "movntdq\t{$src, $dst|$dst, $src}",
3323 [(alignednontemporalstore (v2i64 VR128:$src),
3324 addr:$dst)],
3325 IIC_SSE_MOVNT>, VEX;
3326
3327 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3328 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3329
3330 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3331 (ins f256mem:$dst, VR256:$src),
3332 "movntps\t{$src, $dst|$dst, $src}",
3333 [(alignednontemporalstore (v8f32 VR256:$src),
3334 addr:$dst)],
3335 IIC_SSE_MOVNT>, VEX, VEX_L;
3336 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3337 (ins f256mem:$dst, VR256:$src),
3338 "movntpd\t{$src, $dst|$dst, $src}",
3339 [(alignednontemporalstore (v4f64 VR256:$src),
3340 addr:$dst)],
3341 IIC_SSE_MOVNT>, VEX, VEX_L;
3342 let ExeDomain = SSEPackedInt in
3343 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3344 (ins f256mem:$dst, VR256:$src),
3345 "movntdq\t{$src, $dst|$dst, $src}",
3346 [(alignednontemporalstore (v4i64 VR256:$src),
3347 addr:$dst)],
3348 IIC_SSE_MOVNT>, VEX, VEX_L;
3349 }
3350
3351 let AddedComplexity = 400 in { // Prefer non-temporal versions
3352 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3353 "movntps\t{$src, $dst|$dst, $src}",
3354 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3355 IIC_SSE_MOVNT>;
3356 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3357 "movntpd\t{$src, $dst|$dst, $src}",
3358 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3359 IIC_SSE_MOVNT>;
3360
3361 let ExeDomain = SSEPackedInt in
3362 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3363 "movntdq\t{$src, $dst|$dst, $src}",
3364 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3365 IIC_SSE_MOVNT>;
3366
3367 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3368 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3369
3370 // There is no AVX form for instructions below this point
3371 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3372 "movnti{l}\t{$src, $dst|$dst, $src}",
3373 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3374 IIC_SSE_MOVNT>,
3375 TB, Requires<[HasSSE2]>;
3376 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3377 "movnti{q}\t{$src, $dst|$dst, $src}",
3378 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3379 IIC_SSE_MOVNT>,
3380 TB, Requires<[HasSSE2]>;
3381 }
3382
3383 //===----------------------------------------------------------------------===//
3384 // SSE 1 & 2 - Prefetch and memory fence
3385 //===----------------------------------------------------------------------===//
3386
3387 // Prefetch intrinsic.
3388 let Predicates = [HasSSE1] in {
3389 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3390 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3391 IIC_SSE_PREFETCH>, TB;
3392 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3393 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3394 IIC_SSE_PREFETCH>, TB;
3395 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3396 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3397 IIC_SSE_PREFETCH>, TB;
3398 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3399 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3400 IIC_SSE_PREFETCH>, TB;
3401 }
3402
3403 // Flush cache
3404 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3405 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3406 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3407
3408 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3409 // was introduced with SSE2, it's backward compatible.
3410 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3411
3412 // Load, store, and memory fence
3413 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3414 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3415 TB, Requires<[HasSSE1]>;
3416 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3417 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3418 TB, Requires<[HasSSE2]>;
3419 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3420 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3421 TB, Requires<[HasSSE2]>;
3422
3423 def : Pat<(X86SFence), (SFENCE)>;
3424 def : Pat<(X86LFence), (LFENCE)>;
3425 def : Pat<(X86MFence), (MFENCE)>;
3426
3427 //===----------------------------------------------------------------------===//
3428 // SSE 1 & 2 - Load/Store XCSR register
3429 //===----------------------------------------------------------------------===//
3430
3431 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3432 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3433 IIC_SSE_LDMXCSR>, VEX;
3434 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3435 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3436 IIC_SSE_STMXCSR>, VEX;
3437
3438 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3439 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3440 IIC_SSE_LDMXCSR>;
3441 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3442 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3443 IIC_SSE_STMXCSR>;
3444
3445 //===---------------------------------------------------------------------===//
3446 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3447 //===---------------------------------------------------------------------===//
3448
3449 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3450
3451 let neverHasSideEffects = 1 in {
3452 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3453 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3454 VEX;
3455 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3456 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3457 VEX, VEX_L;
3458 }
3459 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3460 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3461 VEX;
3462 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3463 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3464 VEX, VEX_L;
3465
3466 // For Disassembler
3467 let isCodeGenOnly = 1 in {
3468 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3469 "movdqa\t{$src, $dst|$dst, $src}", [],
3470 IIC_SSE_MOVA_P_RR>,
3471 VEX;
3472 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3473 "movdqa\t{$src, $dst|$dst, $src}", [],
3474 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3475 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3476 "movdqu\t{$src, $dst|$dst, $src}", [],
3477 IIC_SSE_MOVU_P_RR>,
3478 VEX;
3479 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3480 "movdqu\t{$src, $dst|$dst, $src}", [],
3481 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3482 }
3483
3484 let canFoldAsLoad = 1, mayLoad = 1 in {
3485 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3486 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3487 VEX;
3488 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3489 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3490 VEX, VEX_L;
3491 let Predicates = [HasAVX] in {
3492 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3493 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3494 XS, VEX;
3495 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3496 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3497 XS, VEX, VEX_L;
3498 }
3499 }
3500
3501 let mayStore = 1 in {
3502 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3503 (ins i128mem:$dst, VR128:$src),
3504 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3505 VEX;
3506 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3507 (ins i256mem:$dst, VR256:$src),
3508 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3509 VEX, VEX_L;
3510 let Predicates = [HasAVX] in {
3511 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3512 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3513 XS, VEX;
3514 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3515 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3516 XS, VEX, VEX_L;
3517 }
3518 }
3519
3520 let neverHasSideEffects = 1 in
3521 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3522 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3523
3524 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3525 "movdqu\t{$src, $dst|$dst, $src}",
3526 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3527
3528 // For Disassembler
3529 let isCodeGenOnly = 1 in {
3530 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3531 "movdqa\t{$src, $dst|$dst, $src}", [],
3532 IIC_SSE_MOVA_P_RR>;
3533
3534 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3535 "movdqu\t{$src, $dst|$dst, $src}",
3536 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3537 }
3538
3539 let canFoldAsLoad = 1, mayLoad = 1 in {
3540 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3541 "movdqa\t{$src, $dst|$dst, $src}",
3542 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3543 IIC_SSE_MOVA_P_RM>;
3544 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3545 "movdqu\t{$src, $dst|$dst, $src}",
3546 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3547 IIC_SSE_MOVU_P_RM>,
3548 XS, Requires<[UseSSE2]>;
3549 }
3550
3551 let mayStore = 1 in {
3552 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3553 "movdqa\t{$src, $dst|$dst, $src}",
3554 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3555 IIC_SSE_MOVA_P_MR>;
3556 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3557 "movdqu\t{$src, $dst|$dst, $src}",
3558 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3559 IIC_SSE_MOVU_P_MR>,
3560 XS, Requires<[UseSSE2]>;
3561 }
3562
3563 // Intrinsic forms of MOVDQU load and store
3564 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3565 "vmovdqu\t{$src, $dst|$dst, $src}",
3566 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3567 IIC_SSE_MOVU_P_MR>,
3568 XS, VEX, Requires<[HasAVX]>;
3569
3570 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3571 "movdqu\t{$src, $dst|$dst, $src}",
3572 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3573 IIC_SSE_MOVU_P_MR>,
3574 XS, Requires<[UseSSE2]>;
3575
3576 } // ExeDomain = SSEPackedInt
3577
3578 let Predicates = [HasAVX] in {
3579 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3580 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3581 }
3582
3583 //===---------------------------------------------------------------------===//
3584 // SSE2 - Packed Integer Arithmetic Instructions
3585 //===---------------------------------------------------------------------===//
3586
3587 def SSE_PMADD : OpndItins<
3588 IIC_SSE_PMADD, IIC_SSE_PMADD
3589 >;
3590
3591 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3592
3593 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3594 RegisterClass RC, PatFrag memop_frag,
3595 X86MemOperand x86memop,
3596 OpndItins itins,
3597 bit IsCommutable = 0,
3598 bit Is2Addr = 1> {
3599 let isCommutable = IsCommutable in
3600 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3601 (ins RC:$src1, RC:$src2),
3602 !if(Is2Addr,
3603 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3604 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3605 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3606 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3607 (ins RC:$src1, x86memop:$src2),
3608 !if(Is2Addr,
3609 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3611 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3612 itins.rm>;
3613 }
3614
3615 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3616 string OpcodeStr, SDNode OpNode,
3617 SDNode OpNode2, RegisterClass RC,
3618 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3619 ShiftOpndItins itins,
3620 bit Is2Addr = 1> {
3621 // src2 is always 128-bit
3622 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3623 (ins RC:$src1, VR128:$src2),
3624 !if(Is2Addr,
3625 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3626 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3627 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3628 itins.rr>;
3629 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3630 (ins RC:$src1, i128mem:$src2),
3631 !if(Is2Addr,
3632 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3633 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3634 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3635 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3636 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3637 (ins RC:$src1, i32i8imm:$src2),
3638 !if(Is2Addr,
3639 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3640 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3641 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3642 }
3643
3644 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3645 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3646 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3647 PatFrag memop_frag, X86MemOperand x86memop,
3648 OpndItins itins,
3649 bit IsCommutable = 0, bit Is2Addr = 1> {
3650 let isCommutable = IsCommutable in
3651 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3652 (ins RC:$src1, RC:$src2),
3653 !if(Is2Addr,
3654 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3655 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3656 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3657 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3658 (ins RC:$src1, x86memop:$src2),
3659 !if(Is2Addr,
3660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3662 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3663 (bitconvert (memop_frag addr:$src2)))))]>;
3664 }
3665 } // ExeDomain = SSEPackedInt
3666
3667 // 128-bit Integer Arithmetic
3668
3669 let Predicates = [HasAVX] in {
3670 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3671 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3672 VEX_4V;
3673 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3674 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3675 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3676 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3677 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3678 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3679 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3680 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3681 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3682 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3683 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3684 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3685 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3686 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3687 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3688 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3689 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3690 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3691 VEX_4V;
3692
3693 // Intrinsic forms
3694 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3695 VR128, memopv2i64, i128mem,
3696 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3697 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3698 VR128, memopv2i64, i128mem,
3699 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3700 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3701 VR128, memopv2i64, i128mem,
3702 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3703 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3704 VR128, memopv2i64, i128mem,
3705 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3706 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3707 VR128, memopv2i64, i128mem,
3708 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3709 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3710 VR128, memopv2i64, i128mem,
3711 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3712 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3713 VR128, memopv2i64, i128mem,
3714 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3715 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3716 VR128, memopv2i64, i128mem,
3717 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3718 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3719 VR128, memopv2i64, i128mem,
3720 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3721 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3722 VR128, memopv2i64, i128mem,
3723 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3724 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3725 VR128, memopv2i64, i128mem,
3726 SSE_PMADD, 1, 0>, VEX_4V;
3727 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3728 VR128, memopv2i64, i128mem,
3729 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3730 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3731 VR128, memopv2i64, i128mem,
3732 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3733 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3734 VR128, memopv2i64, i128mem,
3735 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3736 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3737 VR128, memopv2i64, i128mem,
3738 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3739 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3740 VR128, memopv2i64, i128mem,
3741 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3742 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3743 VR128, memopv2i64, i128mem,
3744 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3745 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3746 VR128, memopv2i64, i128mem,
3747 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3748 }
3749
3750 let Predicates = [HasAVX2] in {
3751 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3752 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3753 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3754 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3755 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3756 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3757 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3758 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3759 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3760 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3761 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3762 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3763 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3764 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3765 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3766 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3767 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3768 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3769 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3770 VR256, memopv4i64, i256mem,
3771 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3772
3773 // Intrinsic forms
3774 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3775 VR256, memopv4i64, i256mem,
3776 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3777 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3778 VR256, memopv4i64, i256mem,
3779 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3780 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3781 VR256, memopv4i64, i256mem,
3782 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3783 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3784 VR256, memopv4i64, i256mem,
3785 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
3786 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3787 VR256, memopv4i64, i256mem,
3788 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3789 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3790 VR256, memopv4i64, i256mem,
3791 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3792 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3793 VR256, memopv4i64, i256mem,
3794 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3795 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3796 VR256, memopv4i64, i256mem,
3797 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3798 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3799 VR256, memopv4i64, i256mem,
3800 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3801 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3802 VR256, memopv4i64, i256mem,
3803 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3804 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3805 VR256, memopv4i64, i256mem,
3806 SSE_PMADD, 1, 0>, VEX_4V, VEX_L;
3807 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3808 VR256, memopv4i64, i256mem,
3809 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3810 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3811 VR256, memopv4i64, i256mem,
3812 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3813 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3814 VR256, memopv4i64, i256mem,
3815 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3816 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3817 VR256, memopv4i64, i256mem,
3818 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3819 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3820 VR256, memopv4i64, i256mem,
3821 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3822 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3823 VR256, memopv4i64, i256mem,
3824 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3825 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3826 VR256, memopv4i64, i256mem,
3827 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3828 }
3829
3830 let Constraints = "$src1 = $dst" in {
3831 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3832 i128mem, SSE_INTALU_ITINS_P, 1>;
3833 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3834 i128mem, SSE_INTALU_ITINS_P, 1>;
3835 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3836 i128mem, SSE_INTALU_ITINS_P, 1>;
3837 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3838 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3839 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3840 i128mem, SSE_INTMUL_ITINS_P, 1>;
3841 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3842 i128mem, SSE_INTALU_ITINS_P>;
3843 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3844 i128mem, SSE_INTALU_ITINS_P>;
3845 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3846 i128mem, SSE_INTALU_ITINS_P>;
3847 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3848 i128mem, SSE_INTALUQ_ITINS_P>;
3849 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3850 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3851
3852 // Intrinsic forms
3853 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3854 VR128, memopv2i64, i128mem,
3855 SSE_INTALU_ITINS_P>;
3856 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3857 VR128, memopv2i64, i128mem,
3858 SSE_INTALU_ITINS_P>;
3859 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3860 VR128, memopv2i64, i128mem,
3861 SSE_INTALU_ITINS_P>;
3862 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3863 VR128, memopv2i64, i128mem,
3864 SSE_INTALU_ITINS_P>;
3865 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3866 VR128, memopv2i64, i128mem,
3867 SSE_INTALU_ITINS_P, 1>;
3868 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3869 VR128, memopv2i64, i128mem,
3870 SSE_INTALU_ITINS_P, 1>;
3871 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3872 VR128, memopv2i64, i128mem,
3873 SSE_INTALU_ITINS_P, 1>;
3874 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3875 VR128, memopv2i64, i128mem,
3876 SSE_INTALU_ITINS_P, 1>;
3877 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3878 VR128, memopv2i64, i128mem,
3879 SSE_INTMUL_ITINS_P, 1>;
3880 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3881 VR128, memopv2i64, i128mem,
3882 SSE_INTMUL_ITINS_P, 1>;
3883 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3884 VR128, memopv2i64, i128mem,
3885 SSE_PMADD, 1>;
3886 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3887 VR128, memopv2i64, i128mem,
3888 SSE_INTALU_ITINS_P, 1>;
3889 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3890 VR128, memopv2i64, i128mem,
3891 SSE_INTALU_ITINS_P, 1>;
3892 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3893 VR128, memopv2i64, i128mem,
3894 SSE_INTALU_ITINS_P, 1>;
3895 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3896 VR128, memopv2i64, i128mem,
3897 SSE_INTALU_ITINS_P, 1>;
3898 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3899 VR128, memopv2i64, i128mem,
3900 SSE_INTALU_ITINS_P, 1>;
3901 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3902 VR128, memopv2i64, i128mem,
3903 SSE_INTALU_ITINS_P, 1>;
3904 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3905 VR128, memopv2i64, i128mem,
3906 SSE_INTALU_ITINS_P, 1>;
3907
3908 } // Constraints = "$src1 = $dst"
3909
3910 //===---------------------------------------------------------------------===//
3911 // SSE2 - Packed Integer Logical Instructions
3912 //===---------------------------------------------------------------------===//
3913
3914 let Predicates = [HasAVX] in {
3915 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3916 VR128, v8i16, v8i16, bc_v8i16,
3917 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3918 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3919 VR128, v4i32, v4i32, bc_v4i32,
3920 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3921 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3922 VR128, v2i64, v2i64, bc_v2i64,
3923 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3924
3925 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3926 VR128, v8i16, v8i16, bc_v8i16,
3927 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3928 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3929 VR128, v4i32, v4i32, bc_v4i32,
3930 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3931 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3932 VR128, v2i64, v2i64, bc_v2i64,
3933 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3934
3935 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3936 VR128, v8i16, v8i16, bc_v8i16,
3937 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3938 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3939 VR128, v4i32, v4i32, bc_v4i32,
3940 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3941
3942 let ExeDomain = SSEPackedInt in {
3943 // 128-bit logical shifts.
3944 def VPSLLDQri : PDIi8<0x73, MRM7r,
3945 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3946 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3947 [(set VR128:$dst,
3948 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3949 VEX_4V;
3950 def VPSRLDQri : PDIi8<0x73, MRM3r,
3951 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3952 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3953 [(set VR128:$dst,
3954 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3955 VEX_4V;
3956 // PSRADQri doesn't exist in SSE[1-3].
3957 }
3958 } // Predicates = [HasAVX]
3959
3960 let Predicates = [HasAVX2] in {
3961 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3962 VR256, v16i16, v8i16, bc_v8i16,
3963 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3964 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3965 VR256, v8i32, v4i32, bc_v4i32,
3966 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3967 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3968 VR256, v4i64, v2i64, bc_v2i64,
3969 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3970
3971 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3972 VR256, v16i16, v8i16, bc_v8i16,
3973 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3974 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3975 VR256, v8i32, v4i32, bc_v4i32,
3976 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3977 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3978 VR256, v4i64, v2i64, bc_v2i64,
3979 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3980
3981 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3982 VR256, v16i16, v8i16, bc_v8i16,
3983 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3984 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3985 VR256, v8i32, v4i32, bc_v4i32,
3986 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3987
3988 let ExeDomain = SSEPackedInt in {
3989 // 256-bit logical shifts.
3990 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3991 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3992 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3993 [(set VR256:$dst,
3994 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3995 VEX_4V, VEX_L;
3996 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3997 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3998 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3999 [(set VR256:$dst,
4000 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4001 VEX_4V, VEX_L;
4002 // PSRADQYri doesn't exist in SSE[1-3].
4003 }
4004 } // Predicates = [HasAVX2]
4005
4006 let Constraints = "$src1 = $dst" in {
4007 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4008 VR128, v8i16, v8i16, bc_v8i16,
4009 SSE_INTSHIFT_ITINS_P>;
4010 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4011 VR128, v4i32, v4i32, bc_v4i32,
4012 SSE_INTSHIFT_ITINS_P>;
4013 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4014 VR128, v2i64, v2i64, bc_v2i64,
4015 SSE_INTSHIFT_ITINS_P>;
4016
4017 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4018 VR128, v8i16, v8i16, bc_v8i16,
4019 SSE_INTSHIFT_ITINS_P>;
4020 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4021 VR128, v4i32, v4i32, bc_v4i32,
4022 SSE_INTSHIFT_ITINS_P>;
4023 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4024 VR128, v2i64, v2i64, bc_v2i64,
4025 SSE_INTSHIFT_ITINS_P>;
4026
4027 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4028 VR128, v8i16, v8i16, bc_v8i16,
4029 SSE_INTSHIFT_ITINS_P>;
4030 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4031 VR128, v4i32, v4i32, bc_v4i32,
4032 SSE_INTSHIFT_ITINS_P>;
4033
4034 let ExeDomain = SSEPackedInt in {
4035 // 128-bit logical shifts.
4036 def PSLLDQri : PDIi8<0x73, MRM7r,
4037 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4038 "pslldq\t{$src2, $dst|$dst, $src2}",
4039 [(set VR128:$dst,
4040 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4041 def PSRLDQri : PDIi8<0x73, MRM3r,
4042 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4043 "psrldq\t{$src2, $dst|$dst, $src2}",
4044 [(set VR128:$dst,
4045 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4046 // PSRADQri doesn't exist in SSE[1-3].
4047 }
4048 } // Constraints = "$src1 = $dst"
4049
4050 let Predicates = [HasAVX] in {
4051 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4052 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4053 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4054 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4055 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4056 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4057
4058 // Shift up / down and insert zero's.
4059 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4060 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4061 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4062 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4063 }
4064
4065 let Predicates = [HasAVX2] in {
4066 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4067 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4068 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4069 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4070 }
4071
4072 let Predicates = [UseSSE2] in {
4073 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4074 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4075 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4076 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4077 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4078 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4079
4080 // Shift up / down and insert zero's.
4081 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4082 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4083 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4084 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4085 }
4086
4087 //===---------------------------------------------------------------------===//
4088 // SSE2 - Packed Integer Comparison Instructions
4089 //===---------------------------------------------------------------------===//
4090
4091 let Predicates = [HasAVX] in {
4092 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4093 VR128, memopv2i64, i128mem,
4094 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4095 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4096 VR128, memopv2i64, i128mem,
4097 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4098 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4099 VR128, memopv2i64, i128mem,
4100 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4101 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4102 VR128, memopv2i64, i128mem,
4103 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4104 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4105 VR128, memopv2i64, i128mem,
4106 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4107 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4108 VR128, memopv2i64, i128mem,
4109 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4110 }
4111
4112 let Predicates = [HasAVX2] in {
4113 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4114 VR256, memopv4i64, i256mem,
4115 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4116 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4117 VR256, memopv4i64, i256mem,
4118 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4119 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4120 VR256, memopv4i64, i256mem,
4121 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4122 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4123 VR256, memopv4i64, i256mem,
4124 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4125 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4126 VR256, memopv4i64, i256mem,
4127 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4128 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4129 VR256, memopv4i64, i256mem,
4130 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4131 }
4132
4133 let Constraints = "$src1 = $dst" in {
4134 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4135 VR128, memopv2i64, i128mem,
4136 SSE_INTALU_ITINS_P, 1>;
4137 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4138 VR128, memopv2i64, i128mem,
4139 SSE_INTALU_ITINS_P, 1>;
4140 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4141 VR128, memopv2i64, i128mem,
4142 SSE_INTALU_ITINS_P, 1>;
4143 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4144 VR128, memopv2i64, i128mem,
4145 SSE_INTALU_ITINS_P>;
4146 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4147 VR128, memopv2i64, i128mem,
4148 SSE_INTALU_ITINS_P>;
4149 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4150 VR128, memopv2i64, i128mem,
4151 SSE_INTALU_ITINS_P>;
4152 } // Constraints = "$src1 = $dst"
4153
4154 //===---------------------------------------------------------------------===//
4155 // SSE2 - Packed Integer Pack Instructions
4156 //===---------------------------------------------------------------------===//
4157
4158 let Predicates = [HasAVX] in {
4159 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4160 VR128, memopv2i64, i128mem,
4161 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4162 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4163 VR128, memopv2i64, i128mem,
4164 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4165 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4166 VR128, memopv2i64, i128mem,
4167 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4168 }
4169
4170 let Predicates = [HasAVX2] in {
4171 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4172 VR256, memopv4i64, i256mem,
4173 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4174 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4175 VR256, memopv4i64, i256mem,
4176 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4177 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4178 VR256, memopv4i64, i256mem,
4179 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
4180 }
4181
4182 let Constraints = "$src1 = $dst" in {
4183 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4184 VR128, memopv2i64, i128mem,
4185 SSE_INTALU_ITINS_P>;
4186 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4187 VR128, memopv2i64, i128mem,
4188 SSE_INTALU_ITINS_P>;
4189 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4190 VR128, memopv2i64, i128mem,
4191 SSE_INTALU_ITINS_P>;
4192 } // Constraints = "$src1 = $dst"
4193
4194 //===---------------------------------------------------------------------===//
4195 // SSE2 - Packed Integer Shuffle Instructions
4196 //===---------------------------------------------------------------------===//
4197
4198 let ExeDomain = SSEPackedInt in {
4199 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4200 def ri : Ii8<0x70, MRMSrcReg,
4201 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4202 !strconcat(OpcodeStr,
4203 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4204 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4205 IIC_SSE_PSHUF>;
4206 def mi : Ii8<0x70, MRMSrcMem,
4207 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4208 !strconcat(OpcodeStr,
4209 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4210 [(set VR128:$dst,
4211 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4212 (i8 imm:$src2))))],
4213 IIC_SSE_PSHUF>;
4214 }
4215
4216 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4217 def Yri : Ii8<0x70, MRMSrcReg,
4218 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4219 !strconcat(OpcodeStr,
4220 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4221 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4222 def Ymi : Ii8<0x70, MRMSrcMem,
4223 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4224 !strconcat(OpcodeStr,
4225 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4226 [(set VR256:$dst,
4227 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4228 (i8 imm:$src2))))]>;
4229 }
4230 } // ExeDomain = SSEPackedInt
4231
4232 let Predicates = [HasAVX] in {
4233 let AddedComplexity = 5 in
4234 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4235
4236 // SSE2 with ImmT == Imm8 and XS prefix.
4237 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4238
4239 // SSE2 with ImmT == Imm8 and XD prefix.
4240 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4241
4242 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4243 (VPSHUFDmi addr:$src1, imm:$imm)>;
4244 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4245 (VPSHUFDri VR128:$src1, imm:$imm)>;
4246 }
4247
4248 let Predicates = [HasAVX2] in {
4249 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>,
4250 TB, OpSize, VEX,VEX_L;
4251 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>,
4252 XS, VEX, VEX_L;
4253 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>,
4254 XD, VEX, VEX_L;
4255 }
4256
4257 let Predicates = [UseSSE2] in {
4258 let AddedComplexity = 5 in
4259 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4260
4261 // SSE2 with ImmT == Imm8 and XS prefix.
4262 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4263
4264 // SSE2 with ImmT == Imm8 and XD prefix.
4265 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4266
4267 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4268 (PSHUFDmi addr:$src1, imm:$imm)>;
4269 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4270 (PSHUFDri VR128:$src1, imm:$imm)>;
4271 }
4272
4273 //===---------------------------------------------------------------------===//
4274 // SSE2 - Packed Integer Unpack Instructions
4275 //===---------------------------------------------------------------------===//
4276
4277 let ExeDomain = SSEPackedInt in {
4278 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4279 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4280 def rr : PDI<opc, MRMSrcReg,
4281 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4282 !if(Is2Addr,
4283 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4284 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4285 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4286 IIC_SSE_UNPCK>;
4287 def rm : PDI<opc, MRMSrcMem,
4288 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4289 !if(Is2Addr,
4290 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4291 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4292 [(set VR128:$dst, (OpNode VR128:$src1,
4293 (bc_frag (memopv2i64
4294 addr:$src2))))],
4295 IIC_SSE_UNPCK>;
4296 }
4297
4298 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4299 SDNode OpNode, PatFrag bc_frag> {
4300 def Yrr : PDI<opc, MRMSrcReg,
4301 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4302 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4303 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4304 def Yrm : PDI<opc, MRMSrcMem,
4305 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4306 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4307 [(set VR256:$dst, (OpNode VR256:$src1,
4308 (bc_frag (memopv4i64 addr:$src2))))]>;
4309 }
4310
4311 let Predicates = [HasAVX] in {
4312 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4313 bc_v16i8, 0>, VEX_4V;
4314 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4315 bc_v8i16, 0>, VEX_4V;
4316 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4317 bc_v4i32, 0>, VEX_4V;
4318 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4319 bc_v2i64, 0>, VEX_4V;
4320
4321 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4322 bc_v16i8, 0>, VEX_4V;
4323 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4324 bc_v8i16, 0>, VEX_4V;
4325 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4326 bc_v4i32, 0>, VEX_4V;
4327 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4328 bc_v2i64, 0>, VEX_4V;
4329 }
4330
4331 let Predicates = [HasAVX2] in {
4332 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4333 bc_v32i8>, VEX_4V, VEX_L;
4334 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4335 bc_v16i16>, VEX_4V, VEX_L;
4336 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4337 bc_v8i32>, VEX_4V, VEX_L;
4338 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4339 bc_v4i64>, VEX_4V, VEX_L;
4340
4341 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4342 bc_v32i8>, VEX_4V, VEX_L;
4343 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4344 bc_v16i16>, VEX_4V, VEX_L;
4345 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4346 bc_v8i32>, VEX_4V, VEX_L;
4347 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4348 bc_v4i64>, VEX_4V, VEX_L;
4349 }
4350
4351 let Constraints = "$src1 = $dst" in {
4352 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4353 bc_v16i8>;
4354 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4355 bc_v8i16>;
4356 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4357 bc_v4i32>;
4358 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4359 bc_v2i64>;
4360
4361 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4362 bc_v16i8>;
4363 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4364 bc_v8i16>;
4365 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4366 bc_v4i32>;
4367 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4368 bc_v2i64>;
4369 }
4370 } // ExeDomain = SSEPackedInt
4371
4372 //===---------------------------------------------------------------------===//
4373 // SSE2 - Packed Integer Extract and Insert
4374 //===---------------------------------------------------------------------===//
4375
4376 let ExeDomain = SSEPackedInt in {
4377 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4378 def rri : Ii8<0xC4, MRMSrcReg,
4379 (outs VR128:$dst), (ins VR128:$src1,
4380 GR32:$src2, i32i8imm:$src3),
4381 !if(Is2Addr,
4382 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4383 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4384 [(set VR128:$dst,
4385 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4386 def rmi : Ii8<0xC4, MRMSrcMem,
4387 (outs VR128:$dst), (ins VR128:$src1,
4388 i16mem:$src2, i32i8imm:$src3),
4389 !if(Is2Addr,
4390 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4391 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4392 [(set VR128:$dst,
4393 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4394 imm:$src3))], IIC_SSE_PINSRW>;
4395 }
4396
4397 // Extract
4398 let Predicates = [HasAVX] in
4399 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4400 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4401 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4402 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4403 imm:$src2))]>, TB, OpSize, VEX;
4404 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4405 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4406 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4407 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4408 imm:$src2))], IIC_SSE_PEXTRW>;
4409
4410 // Insert
4411 let Predicates = [HasAVX] in {
4412 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4413 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4414 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4415 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4416 []>, TB, OpSize, VEX_4V;
4417 }
4418
4419 let Constraints = "$src1 = $dst" in
4420 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4421
4422 } // ExeDomain = SSEPackedInt
4423
4424 //===---------------------------------------------------------------------===//
4425 // SSE2 - Packed Mask Creation
4426 //===---------------------------------------------------------------------===//
4427
4428 let ExeDomain = SSEPackedInt in {
4429
4430 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4431 "pmovmskb\t{$src, $dst|$dst, $src}",
4432 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4433 IIC_SSE_MOVMSK>, VEX;
4434 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4435 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4436
4437 let Predicates = [HasAVX2] in {
4438 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4439 "pmovmskb\t{$src, $dst|$dst, $src}",
4440 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4441 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4442 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4443 }
4444
4445 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4446 "pmovmskb\t{$src, $dst|$dst, $src}",
4447 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4448 IIC_SSE_MOVMSK>;
4449
4450 } // ExeDomain = SSEPackedInt
4451
4452 //===---------------------------------------------------------------------===//
4453 // SSE2 - Conditional Store
4454 //===---------------------------------------------------------------------===//
4455
4456 let ExeDomain = SSEPackedInt in {
4457
4458 let Uses = [EDI] in
4459 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4460 (ins VR128:$src, VR128:$mask),
4461 "maskmovdqu\t{$mask, $src|$src, $mask}",
4462 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4463 IIC_SSE_MASKMOV>, VEX;
4464 let Uses = [RDI] in
4465 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4466 (ins VR128:$src, VR128:$mask),
4467 "maskmovdqu\t{$mask, $src|$src, $mask}",
4468 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4469 IIC_SSE_MASKMOV>, VEX;
4470
4471 let Uses = [EDI] in
4472 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4473 "maskmovdqu\t{$mask, $src|$src, $mask}",
4474 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4475 IIC_SSE_MASKMOV>;
4476 let Uses = [RDI] in
4477 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4478 "maskmovdqu\t{$mask, $src|$src, $mask}",
4479 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4480 IIC_SSE_MASKMOV>;
4481
4482 } // ExeDomain = SSEPackedInt
4483
4484 //===---------------------------------------------------------------------===//
4485 // SSE2 - Move Doubleword
4486 //===---------------------------------------------------------------------===//
4487
4488 //===---------------------------------------------------------------------===//
4489 // Move Int Doubleword to Packed Double Int
4490 //
4491 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4492 "movd\t{$src, $dst|$dst, $src}",
4493 [(set VR128:$dst,
4494 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4495 VEX;
4496 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4497 "movd\t{$src, $dst|$dst, $src}",
4498 [(set VR128:$dst,
4499 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4500 IIC_SSE_MOVDQ>,
4501 VEX;
4502 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4503 "mov{d|q}\t{$src, $dst|$dst, $src}",
4504 [(set VR128:$dst,
4505 (v2i64 (scalar_to_vector GR64:$src)))],
4506 IIC_SSE_MOVDQ>, VEX;
4507 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4508 "mov{d|q}\t{$src, $dst|$dst, $src}",
4509 [(set FR64:$dst, (bitconvert GR64:$src))],
4510 IIC_SSE_MOVDQ>, VEX;
4511
4512 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4513 "movd\t{$src, $dst|$dst, $src}",
4514 [(set VR128:$dst,
4515 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4516 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4517 "movd\t{$src, $dst|$dst, $src}",
4518 [(set VR128:$dst,
4519 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4520 IIC_SSE_MOVDQ>;
4521 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4522 "mov{d|q}\t{$src, $dst|$dst, $src}",
4523 [(set VR128:$dst,
4524 (v2i64 (scalar_to_vector GR64:$src)))],
4525 IIC_SSE_MOVDQ>;
4526 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4527 "mov{d|q}\t{$src, $dst|$dst, $src}",
4528 [(set FR64:$dst, (bitconvert GR64:$src))],
4529 IIC_SSE_MOVDQ>;
4530
4531 //===---------------------------------------------------------------------===//
4532 // Move Int Doubleword to Single Scalar
4533 //
4534 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4535 "movd\t{$src, $dst|$dst, $src}",
4536 [(set FR32:$dst, (bitconvert GR32:$src))],
4537 IIC_SSE_MOVDQ>, VEX;
4538
4539 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4540 "movd\t{$src, $dst|$dst, $src}",
4541 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4542 IIC_SSE_MOVDQ>,
4543 VEX;
4544 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4545 "movd\t{$src, $dst|$dst, $src}",
4546 [(set FR32:$dst, (bitconvert GR32:$src))],
4547 IIC_SSE_MOVDQ>;
4548
4549 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4550 "movd\t{$src, $dst|$dst, $src}",
4551 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4552 IIC_SSE_MOVDQ>;
4553
4554 //===---------------------------------------------------------------------===//
4555 // Move Packed Doubleword Int to Packed Double Int
4556 //
4557 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4558 "movd\t{$src, $dst|$dst, $src}",
4559 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4560 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4561 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4562 (ins i32mem:$dst, VR128:$src),
4563 "movd\t{$src, $dst|$dst, $src}",
4564 [(store (i32 (vector_extract (v4i32 VR128:$src),
4565 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4566 VEX;
4567 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4568 "movd\t{$src, $dst|$dst, $src}",
4569 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4570 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4571 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4572 "movd\t{$src, $dst|$dst, $src}",
4573 [(store (i32 (vector_extract (v4i32 VR128:$src),
4574 (iPTR 0))), addr:$dst)],
4575 IIC_SSE_MOVDQ>;
4576
4577 //===---------------------------------------------------------------------===//
4578 // Move Packed Doubleword Int first element to Doubleword Int
4579 //
4580 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4581 "vmov{d|q}\t{$src, $dst|$dst, $src}",
4582 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4583 (iPTR 0)))],
4584 IIC_SSE_MOVD_ToGP>,
4585 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4586
4587 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4588 "mov{d|q}\t{$src, $dst|$dst, $src}",
4589 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4590 (iPTR 0)))],
4591 IIC_SSE_MOVD_ToGP>;
4592
4593 //===---------------------------------------------------------------------===//
4594 // Bitcast FR64 <-> GR64
4595 //
4596 let Predicates = [HasAVX] in
4597 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4598 "vmovq\t{$src, $dst|$dst, $src}",
4599 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4600 VEX;
4601 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4602 "mov{d|q}\t{$src, $dst|$dst, $src}",
4603 [(set GR64:$dst, (bitconvert FR64:$src))],
4604 IIC_SSE_MOVDQ>, VEX;
4605 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4606 "movq\t{$src, $dst|$dst, $src}",
4607 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4608 IIC_SSE_MOVDQ>, VEX;
4609
4610 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4611 "movq\t{$src, $dst|$dst, $src}",
4612 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4613 IIC_SSE_MOVDQ>;
4614 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4615 "mov{d|q}\t{$src, $dst|$dst, $src}",
4616 [(set GR64:$dst, (bitconvert FR64:$src))],
4617 IIC_SSE_MOVD_ToGP>;
4618 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4619 "movq\t{$src, $dst|$dst, $src}",
4620 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4621 IIC_SSE_MOVDQ>;
4622
4623 //===---------------------------------------------------------------------===//
4624 // Move Scalar Single to Double Int
4625 //
4626 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4627 "movd\t{$src, $dst|$dst, $src}",
4628 [(set GR32:$dst, (bitconvert FR32:$src))],
4629 IIC_SSE_MOVD_ToGP>, VEX;
4630 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4631 "movd\t{$src, $dst|$dst, $src}",
4632 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4633 IIC_SSE_MOVDQ>, VEX;
4634 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4635 "movd\t{$src, $dst|$dst, $src}",
4636 [(set GR32:$dst, (bitconvert FR32:$src))],
4637 IIC_SSE_MOVD_ToGP>;
4638 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4639 "movd\t{$src, $dst|$dst, $src}",
4640 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4641 IIC_SSE_MOVDQ>;
4642
4643 //===---------------------------------------------------------------------===//
4644 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4645 //
4646 let AddedComplexity = 15 in {
4647 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4648 "movd\t{$src, $dst|$dst, $src}",
4649 [(set VR128:$dst, (v4i32 (X86vzmovl
4650 (v4i32 (scalar_to_vector GR32:$src)))))],
4651 IIC_SSE_MOVDQ>, VEX;
4652 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4653 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4654 [(set VR128:$dst, (v2i64 (X86vzmovl
4655 (v2i64 (scalar_to_vector GR64:$src)))))],
4656 IIC_SSE_MOVDQ>,
4657 VEX, VEX_W;
4658 }
4659 let AddedComplexity = 15 in {
4660 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4661 "movd\t{$src, $dst|$dst, $src}",
4662 [(set VR128:$dst, (v4i32 (X86vzmovl
4663 (v4i32 (scalar_to_vector GR32:$src)))))],
4664 IIC_SSE_MOVDQ>;
4665 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4666 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4667 [(set VR128:$dst, (v2i64 (X86vzmovl
4668 (v2i64 (scalar_to_vector GR64:$src)))))],
4669 IIC_SSE_MOVDQ>;
4670 }
4671
4672 let AddedComplexity = 20 in {
4673 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4674 "movd\t{$src, $dst|$dst, $src}",
4675 [(set VR128:$dst,
4676 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4677 (loadi32 addr:$src))))))],
4678 IIC_SSE_MOVDQ>, VEX;
4679 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4680 "movd\t{$src, $dst|$dst, $src}",
4681 [(set VR128:$dst,
4682 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4683 (loadi32 addr:$src))))))],
4684 IIC_SSE_MOVDQ>;
4685 }
4686
4687 let Predicates = [HasAVX] in {
4688 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4689 let AddedComplexity = 20 in {
4690 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4691 (VMOVZDI2PDIrm addr:$src)>;
4692 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4693 (VMOVZDI2PDIrm addr:$src)>;
4694 }
4695 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4696 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4697 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4698 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4699 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4700 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4701 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4702 }
4703
4704 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4705 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4706 (MOVZDI2PDIrm addr:$src)>;
4707 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4708 (MOVZDI2PDIrm addr:$src)>;
4709 }
4710
4711 // These are the correct encodings of the instructions so that we know how to
4712 // read correct assembly, even though we continue to emit the wrong ones for
4713 // compatibility with Darwin's buggy assembler.
4714 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4715 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4716 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4717 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4718 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4719 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4720 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4721 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4722 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4723 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4724 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4725 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4726
4727 //===---------------------------------------------------------------------===//
4728 // SSE2 - Move Quadword
4729 //===---------------------------------------------------------------------===//
4730
4731 //===---------------------------------------------------------------------===//
4732 // Move Quadword Int to Packed Quadword Int
4733 //
4734 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4735 "vmovq\t{$src, $dst|$dst, $src}",
4736 [(set VR128:$dst,
4737 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4738 VEX, Requires<[HasAVX]>;
4739 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4740 "movq\t{$src, $dst|$dst, $src}",
4741 [(set VR128:$dst,
4742 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4743 IIC_SSE_MOVDQ>, XS,
4744 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4745
4746 //===---------------------------------------------------------------------===//
4747 // Move Packed Quadword Int to Quadword Int
4748 //
4749 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4750 "movq\t{$src, $dst|$dst, $src}",
4751 [(store (i64 (vector_extract (v2i64 VR128:$src),
4752 (iPTR 0))), addr:$dst)],
4753 IIC_SSE_MOVDQ>, VEX;
4754 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4755 "movq\t{$src, $dst|$dst, $src}",
4756 [(store (i64 (vector_extract (v2i64 VR128:$src),
4757 (iPTR 0))), addr:$dst)],
4758 IIC_SSE_MOVDQ>;
4759
4760 //===---------------------------------------------------------------------===//
4761 // Store / copy lower 64-bits of a XMM register.
4762 //
4763 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4764 "movq\t{$src, $dst|$dst, $src}",
4765 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4766 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4767 "movq\t{$src, $dst|$dst, $src}",
4768 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4769 IIC_SSE_MOVDQ>;
4770
4771 let AddedComplexity = 20 in
4772 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4773 "vmovq\t{$src, $dst|$dst, $src}",
4774 [(set VR128:$dst,
4775 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4776 (loadi64 addr:$src))))))],
4777 IIC_SSE_MOVDQ>,
4778 XS, VEX, Requires<[HasAVX]>;
4779
4780 let AddedComplexity = 20 in
4781 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4782 "movq\t{$src, $dst|$dst, $src}",
4783 [(set VR128:$dst,
4784 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4785 (loadi64 addr:$src))))))],
4786 IIC_SSE_MOVDQ>,
4787 XS, Requires<[UseSSE2]>;
4788
4789 let Predicates = [HasAVX], AddedComplexity = 20 in {
4790 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4791 (VMOVZQI2PQIrm addr:$src)>;
4792 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4793 (VMOVZQI2PQIrm addr:$src)>;
4794 def : Pat<(v2i64 (X86vzload addr:$src)),
4795 (VMOVZQI2PQIrm addr:$src)>;
4796 }
4797
4798 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4799 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4800 (MOVZQI2PQIrm addr:$src)>;
4801 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4802 (MOVZQI2PQIrm addr:$src)>;
4803 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4804 }
4805
4806 let Predicates = [HasAVX] in {
4807 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4808 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4809 def : Pat<(v4i64 (X86vzload addr:$src)),
4810 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4811 }
4812
4813 //===---------------------------------------------------------------------===//
4814 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4815 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4816 //
4817 let AddedComplexity = 15 in
4818 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4819 "vmovq\t{$src, $dst|$dst, $src}",
4820 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4821 IIC_SSE_MOVQ_RR>,
4822 XS, VEX, Requires<[HasAVX]>;
4823 let AddedComplexity = 15 in
4824 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4825 "movq\t{$src, $dst|$dst, $src}",
4826 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4827 IIC_SSE_MOVQ_RR>,
4828 XS, Requires<[UseSSE2]>;
4829
4830 let AddedComplexity = 20 in
4831 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4832 "vmovq\t{$src, $dst|$dst, $src}",
4833 [(set VR128:$dst, (v2i64 (X86vzmovl
4834 (loadv2i64 addr:$src))))],
4835 IIC_SSE_MOVDQ>,
4836 XS, VEX, Requires<[HasAVX]>;
4837 let AddedComplexity = 20 in {
4838 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4839 "movq\t{$src, $dst|$dst, $src}",
4840 [(set VR128:$dst, (v2i64 (X86vzmovl
4841 (loadv2i64 addr:$src))))],
4842 IIC_SSE_MOVDQ>,
4843 XS, Requires<[UseSSE2]>;
4844 }
4845
4846 let AddedComplexity = 20 in {
4847 let Predicates = [HasAVX] in {
4848 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4849 (VMOVZPQILo2PQIrm addr:$src)>;
4850 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4851 (VMOVZPQILo2PQIrr VR128:$src)>;
4852 }
4853 let Predicates = [UseSSE2] in {
4854 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4855 (MOVZPQILo2PQIrm addr:$src)>;
4856 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4857 (MOVZPQILo2PQIrr VR128:$src)>;
4858 }
4859 }
4860
4861 // Instructions to match in the assembler
4862 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4863 "movq\t{$src, $dst|$dst, $src}", [],
4864 IIC_SSE_MOVDQ>, VEX, VEX_W;
4865 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4866 "movq\t{$src, $dst|$dst, $src}", [],
4867 IIC_SSE_MOVDQ>, VEX, VEX_W;
4868 // Recognize "movd" with GR64 destination, but encode as a "movq"
4869 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4870 "movd\t{$src, $dst|$dst, $src}", [],
4871 IIC_SSE_MOVDQ>, VEX, VEX_W;
4872
4873 // Instructions for the disassembler
4874 // xr = XMM register
4875 // xm = mem64
4876
4877 let Predicates = [HasAVX] in
4878 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4879 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4880 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4881 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4882
4883 //===---------------------------------------------------------------------===//
4884 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4885 //===---------------------------------------------------------------------===//
4886 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4887 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4888 X86MemOperand x86memop> {
4889 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4890 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4891 [(set RC:$dst, (vt (OpNode RC:$src)))],
4892 IIC_SSE_MOV_LH>;
4893 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4894 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4895 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4896 IIC_SSE_MOV_LH>;
4897 }
4898
4899 let Predicates = [HasAVX] in {
4900 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4901 v4f32, VR128, memopv4f32, f128mem>, VEX;
4902 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4903 v4f32, VR128, memopv4f32, f128mem>, VEX;
4904 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4905 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4906 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4907 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4908 }
4909 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4910 memopv4f32, f128mem>;
4911 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4912 memopv4f32, f128mem>;
4913
4914 let Predicates = [HasAVX] in {
4915 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4916 (VMOVSHDUPrr VR128:$src)>;
4917 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4918 (VMOVSHDUPrm addr:$src)>;
4919 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4920 (VMOVSLDUPrr VR128:$src)>;
4921 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4922 (VMOVSLDUPrm addr:$src)>;
4923 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4924 (VMOVSHDUPYrr VR256:$src)>;
4925 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4926 (VMOVSHDUPYrm addr:$src)>;
4927 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4928 (VMOVSLDUPYrr VR256:$src)>;
4929 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4930 (VMOVSLDUPYrm addr:$src)>;
4931 }
4932
4933 let Predicates = [UseSSE3] in {
4934 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4935 (MOVSHDUPrr VR128:$src)>;
4936 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4937 (MOVSHDUPrm addr:$src)>;
4938 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4939 (MOVSLDUPrr VR128:$src)>;
4940 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4941 (MOVSLDUPrm addr:$src)>;
4942 }
4943
4944 //===---------------------------------------------------------------------===//
4945 // SSE3 - Replicate Double FP - MOVDDUP
4946 //===---------------------------------------------------------------------===//
4947
4948 multiclass sse3_replicate_dfp<string OpcodeStr> {
4949 let neverHasSideEffects = 1 in
4950 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4951 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4952 [], IIC_SSE_MOV_LH>;
4953 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4954 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4955 [(set VR128:$dst,
4956 (v2f64 (X86Movddup
4957 (scalar_to_vector (loadf64 addr:$src)))))],
4958 IIC_SSE_MOV_LH>;
4959 }
4960
4961 // FIXME: Merge with above classe when there're patterns for the ymm version
4962 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4963 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4964 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4965 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4966 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4967 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4968 [(set VR256:$dst,
4969 (v4f64 (X86Movddup
4970 (scalar_to_vector (loadf64 addr:$src)))))]>;
4971 }
4972
4973 let Predicates = [HasAVX] in {
4974 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4975 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4976 }
4977
4978 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4979
4980 let Predicates = [HasAVX] in {
4981 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4982 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4983 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4984 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4985 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4986 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4987 def : Pat<(X86Movddup (bc_v2f64
4988 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4989 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4990
4991 // 256-bit version
4992 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4993 (VMOVDDUPYrm addr:$src)>;
4994 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4995 (VMOVDDUPYrm addr:$src)>;
4996 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4997 (VMOVDDUPYrm addr:$src)>;
4998 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4999 (VMOVDDUPYrr VR256:$src)>;
5000 }
5001
5002 let Predicates = [UseSSE3] in {
5003 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5004 (MOVDDUPrm addr:$src)>;
5005 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5006 (MOVDDUPrm addr:$src)>;
5007 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5008 (MOVDDUPrm addr:$src)>;
5009 def : Pat<(X86Movddup (bc_v2f64
5010 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5011 (MOVDDUPrm addr:$src)>;
5012 }
5013
5014 //===---------------------------------------------------------------------===//
5015 // SSE3 - Move Unaligned Integer
5016 //===---------------------------------------------------------------------===//
5017
5018 let Predicates = [HasAVX] in {
5019 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5020 "vlddqu\t{$src, $dst|$dst, $src}",
5021 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5022 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5023 "vlddqu\t{$src, $dst|$dst, $src}",
5024 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5025 VEX, VEX_L;
5026 }
5027 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5028 "lddqu\t{$src, $dst|$dst, $src}",
5029 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5030 IIC_SSE_LDDQU>;
5031
5032 //===---------------------------------------------------------------------===//
5033 // SSE3 - Arithmetic
5034 //===---------------------------------------------------------------------===//
5035
5036 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5037 X86MemOperand x86memop, OpndItins itins,
5038 bit Is2Addr = 1> {
5039 def rr : I<0xD0, MRMSrcReg,
5040 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5041 !if(Is2Addr,
5042 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5044 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5045 def rm : I<0xD0, MRMSrcMem,
5046 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5047 !if(Is2Addr,
5048 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5050 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5051 }
5052
5053 let Predicates = [HasAVX] in {
5054 let ExeDomain = SSEPackedSingle in {
5055 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5056 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5057 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5058 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
5059 }
5060 let ExeDomain = SSEPackedDouble in {
5061 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5062 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5063 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5064 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
5065 }
5066 }
5067 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5068 let ExeDomain = SSEPackedSingle in
5069 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5070 f128mem, SSE_ALU_F32P>, TB, XD;
5071 let ExeDomain = SSEPackedDouble in
5072 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5073 f128mem, SSE_ALU_F64P>, TB, OpSize;
5074 }
5075
5076 //===---------------------------------------------------------------------===//
5077 // SSE3 Instructions
5078 //===---------------------------------------------------------------------===//
5079
5080 // Horizontal ops
5081 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5082 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5083 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5084 !if(Is2Addr,
5085 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5086 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5087 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5088
5089 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5090 !if(Is2Addr,
5091 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5092 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5093 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5094 IIC_SSE_HADDSUB_RM>;
5095 }
5096 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5097 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5098 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5099 !if(Is2Addr,
5100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5101 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5102 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5103
5104 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5105 !if(Is2Addr,
5106 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5107 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5108 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5109 IIC_SSE_HADDSUB_RM>;
5110 }
5111
5112 let Predicates = [HasAVX] in {
5113 let ExeDomain = SSEPackedSingle in {
5114 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5115 X86fhadd, 0>, VEX_4V;
5116 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5117 X86fhsub, 0>, VEX_4V;
5118 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5119 X86fhadd, 0>, VEX_4V, VEX_L;
5120 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5121 X86fhsub, 0>, VEX_4V, VEX_L;
5122 }
5123 let ExeDomain = SSEPackedDouble in {
5124 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5125 X86fhadd, 0>, VEX_4V;
5126 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5127 X86fhsub, 0>, VEX_4V;
5128 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5129 X86fhadd, 0>, VEX_4V, VEX_L;
5130 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5131 X86fhsub, 0>, VEX_4V, VEX_L;
5132 }
5133 }
5134
5135 let Constraints = "$src1 = $dst" in {
5136 let ExeDomain = SSEPackedSingle in {
5137 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5138 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5139 }
5140 let ExeDomain = SSEPackedDouble in {
5141 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5142 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5143 }
5144 }
5145
5146 //===---------------------------------------------------------------------===//
5147 // SSSE3 - Packed Absolute Instructions
5148 //===---------------------------------------------------------------------===//
5149
5150
5151 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5152 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5153 Intrinsic IntId128> {
5154 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5155 (ins VR128:$src),
5156 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5157 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5158 OpSize;
5159
5160 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5161 (ins i128mem:$src),
5162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5163 [(set VR128:$dst,
5164 (IntId128
5165 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5166 OpSize;
5167 }
5168
5169 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5170 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5171 Intrinsic IntId256> {
5172 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5173 (ins VR256:$src),
5174 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5175 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5176 OpSize;
5177
5178 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5179 (ins i256mem:$src),
5180 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5181 [(set VR256:$dst,
5182 (IntId256
5183 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5184 }
5185
5186 let Predicates = [HasAVX] in {
5187 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5188 int_x86_ssse3_pabs_b_128>, VEX;
5189 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5190 int_x86_ssse3_pabs_w_128>, VEX;
5191 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5192 int_x86_ssse3_pabs_d_128>, VEX;
5193 }
5194
5195 let Predicates = [HasAVX2] in {
5196 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5197 int_x86_avx2_pabs_b>, VEX, VEX_L;
5198 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5199 int_x86_avx2_pabs_w>, VEX, VEX_L;
5200 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5201 int_x86_avx2_pabs_d>, VEX, VEX_L;
5202 }
5203
5204 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5205 int_x86_ssse3_pabs_b_128>;
5206 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5207 int_x86_ssse3_pabs_w_128>;
5208 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5209 int_x86_ssse3_pabs_d_128>;
5210
5211 //===---------------------------------------------------------------------===//
5212 // SSSE3 - Packed Binary Operator Instructions
5213 //===---------------------------------------------------------------------===//
5214
5215 def SSE_PHADDSUBD : OpndItins<
5216 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5217 >;
5218 def SSE_PHADDSUBSW : OpndItins<
5219 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5220 >;
5221 def SSE_PHADDSUBW : OpndItins<
5222 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5223 >;
5224 def SSE_PSHUFB : OpndItins<
5225 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5226 >;
5227 def SSE_PSIGN : OpndItins<
5228 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5229 >;
5230 def SSE_PMULHRSW : OpndItins<
5231 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5232 >;
5233
5234 /// SS3I_binop_rm - Simple SSSE3 bin op
5235 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5236 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5237 X86MemOperand x86memop, OpndItins itins,
5238 bit Is2Addr = 1> {
5239 let isCommutable = 1 in
5240 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5241 (ins RC:$src1, RC:$src2),
5242 !if(Is2Addr,
5243 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5245 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5246 OpSize;
5247 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5248 (ins RC:$src1, x86memop:$src2),
5249 !if(Is2Addr,
5250 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5251 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5252 [(set RC:$dst,
5253 (OpVT (OpNode RC:$src1,
5254 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5255 }
5256
5257 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5258 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5259 Intrinsic IntId128, OpndItins itins,
5260 bit Is2Addr = 1> {
5261 let isCommutable = 1 in
5262 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5263 (ins VR128:$src1, VR128:$src2),
5264 !if(Is2Addr,
5265 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5267 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5268 OpSize;
5269 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5270 (ins VR128:$src1, i128mem:$src2),
5271 !if(Is2Addr,
5272 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5273 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5274 [(set VR128:$dst,
5275 (IntId128 VR128:$src1,
5276 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5277 }
5278
5279 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5280 Intrinsic IntId256> {
5281 let isCommutable = 1 in
5282 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5283 (ins VR256:$src1, VR256:$src2),
5284 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5285 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5286 OpSize;
5287 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5288 (ins VR256:$src1, i256mem:$src2),
5289 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5290 [(set VR256:$dst,
5291 (IntId256 VR256:$src1,
5292 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5293 }
5294
5295 let ImmT = NoImm, Predicates = [HasAVX] in {
5296 let isCommutable = 0 in {
5297 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5298 memopv2i64, i128mem,
5299 SSE_PHADDSUBW, 0>, VEX_4V;
5300 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5301 memopv2i64, i128mem,
5302 SSE_PHADDSUBD, 0>, VEX_4V;
5303 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5304 memopv2i64, i128mem,
5305 SSE_PHADDSUBW, 0>, VEX_4V;
5306 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5307 memopv2i64, i128mem,
5308 SSE_PHADDSUBD, 0>, VEX_4V;
5309 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5310 memopv2i64, i128mem,
5311 SSE_PSIGN, 0>, VEX_4V;
5312 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5313 memopv2i64, i128mem,
5314 SSE_PSIGN, 0>, VEX_4V;
5315 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5316 memopv2i64, i128mem,
5317 SSE_PSIGN, 0>, VEX_4V;
5318 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5319 memopv2i64, i128mem,
5320 SSE_PSHUFB, 0>, VEX_4V;
5321 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5322 int_x86_ssse3_phadd_sw_128,
5323 SSE_PHADDSUBSW, 0>, VEX_4V;
5324 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5325 int_x86_ssse3_phsub_sw_128,
5326 SSE_PHADDSUBSW, 0>, VEX_4V;
5327 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5328 int_x86_ssse3_pmadd_ub_sw_128,
5329 SSE_PMADD, 0>, VEX_4V;
5330 }
5331 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5332 int_x86_ssse3_pmul_hr_sw_128,
5333 SSE_PMULHRSW, 0>, VEX_4V;
5334 }
5335
5336 let ImmT = NoImm, Predicates = [HasAVX2] in {
5337 let isCommutable = 0 in {
5338 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5339 memopv4i64, i256mem,
5340 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5341 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5342 memopv4i64, i256mem,
5343 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5344 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5345 memopv4i64, i256mem,
5346 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5347 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5348 memopv4i64, i256mem,
5349 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5350 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5351 memopv4i64, i256mem,
5352 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5353 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5354 memopv4i64, i256mem,
5355 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5356 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5357 memopv4i64, i256mem,
5358 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5359 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5360 memopv4i64, i256mem,
5361 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5362 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5363 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5364 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5365 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5366 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5367 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5368 }
5369 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5370 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5371 }
5372
5373 // None of these have i8 immediate fields.
5374 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5375 let isCommutable = 0 in {
5376 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5377 memopv2i64, i128mem, SSE_PHADDSUBW>;
5378 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5379 memopv2i64, i128mem, SSE_PHADDSUBD>;
5380 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5381 memopv2i64, i128mem, SSE_PHADDSUBW>;
5382 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5383 memopv2i64, i128mem, SSE_PHADDSUBD>;
5384 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5385 memopv2i64, i128mem, SSE_PSIGN>;
5386 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5387 memopv2i64, i128mem, SSE_PSIGN>;
5388 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5389 memopv2i64, i128mem, SSE_PSIGN>;
5390 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5391 memopv2i64, i128mem, SSE_PSHUFB>;
5392 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5393 int_x86_ssse3_phadd_sw_128,
5394 SSE_PHADDSUBSW>;
5395 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5396 int_x86_ssse3_phsub_sw_128,
5397 SSE_PHADDSUBSW>;
5398 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5399 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5400 }
5401 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5402 int_x86_ssse3_pmul_hr_sw_128,
5403 SSE_PMULHRSW>;
5404 }
5405
5406 //===---------------------------------------------------------------------===//
5407 // SSSE3 - Packed Align Instruction Patterns
5408 //===---------------------------------------------------------------------===//
5409
5410 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5411 let neverHasSideEffects = 1 in {
5412 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5413 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5414 !if(Is2Addr,
5415 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5416 !strconcat(asm,
5417 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5418 [], IIC_SSE_PALIGNR>, OpSize;
5419 let mayLoad = 1 in
5420 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5421 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5422 !if(Is2Addr,
5423 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5424 !strconcat(asm,
5425 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5426 [], IIC_SSE_PALIGNR>, OpSize;
5427 }
5428 }
5429
5430 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5431 let neverHasSideEffects = 1 in {
5432 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5433 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5434 !strconcat(asm,
5435 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5436 []>, OpSize;
5437 let mayLoad = 1 in
5438 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5439 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5440 !strconcat(asm,
5441 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5442 []>, OpSize;
5443 }
5444 }
5445
5446 let Predicates = [HasAVX] in
5447 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5448 let Predicates = [HasAVX2] in
5449 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V, VEX_L;
5450 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5451 defm PALIGN : ssse3_palign<"palignr">;
5452
5453 let Predicates = [HasAVX2] in {
5454 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5455 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5456 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5457 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5458 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5459 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5460 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5461 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5462 }
5463
5464 let Predicates = [HasAVX] in {
5465 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5466 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5467 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5468 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5469 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5470 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5471 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5472 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5473 }
5474
5475 let Predicates = [UseSSSE3] in {
5476 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5477 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5478 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5479 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5480 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5481 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5482 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5483 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5484 }
5485
5486 //===---------------------------------------------------------------------===//
5487 // SSSE3 - Thread synchronization
5488 //===---------------------------------------------------------------------===//
5489
5490 let usesCustomInserter = 1 in {
5491 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5492 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5493 Requires<[HasSSE3]>;
5494 }
5495
5496 let Uses = [EAX, ECX, EDX] in
5497 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5498 TB, Requires<[HasSSE3]>;
5499 let Uses = [ECX, EAX] in
5500 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5501 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5502 TB, Requires<[HasSSE3]>;
5503
5504 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5505 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5506
5507 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5508 Requires<[In32BitMode]>;
5509 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5510 Requires<[In64BitMode]>;
5511
5512 //===----------------------------------------------------------------------===//
5513 // SSE4.1 - Packed Move with Sign/Zero Extend
5514 //===----------------------------------------------------------------------===//
5515
5516 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5517 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5519 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5520
5521 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5522 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5523 [(set VR128:$dst,
5524 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5525 OpSize;
5526 }
5527
5528 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5529 Intrinsic IntId> {
5530 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5531 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5532 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5533
5534 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5535 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5536 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5537 }
5538
5539 let Predicates = [HasAVX] in {
5540 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5541 VEX;
5542 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5543 VEX;
5544 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5545 VEX;
5546 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5547 VEX;
5548 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5549 VEX;
5550 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5551 VEX;
5552 }
5553
5554 let Predicates = [HasAVX2] in {
5555 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5556 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5557 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5558 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5559 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5560 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5561 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5562 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5563 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5564 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5565 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5566 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5567 }
5568
5569 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5570 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5571 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5572 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5573 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5574 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5575
5576 let Predicates = [HasAVX] in {
5577 // Common patterns involving scalar load.
5578 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5579 (VPMOVSXBWrm addr:$src)>;
5580 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5581 (VPMOVSXBWrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5583 (VPMOVSXBWrm addr:$src)>;
5584
5585 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5586 (VPMOVSXWDrm addr:$src)>;
5587 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5588 (VPMOVSXWDrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5590 (VPMOVSXWDrm addr:$src)>;
5591
5592 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5593 (VPMOVSXDQrm addr:$src)>;
5594 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5595 (VPMOVSXDQrm addr:$src)>;
5596 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5597 (VPMOVSXDQrm addr:$src)>;
5598
5599 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5600 (VPMOVZXBWrm addr:$src)>;
5601 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5602 (VPMOVZXBWrm addr:$src)>;
5603 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5604 (VPMOVZXBWrm addr:$src)>;
5605
5606 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5607 (VPMOVZXWDrm addr:$src)>;
5608 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5609 (VPMOVZXWDrm addr:$src)>;
5610 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5611 (VPMOVZXWDrm addr:$src)>;
5612
5613 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5614 (VPMOVZXDQrm addr:$src)>;
5615 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5616 (VPMOVZXDQrm addr:$src)>;
5617 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5618 (VPMOVZXDQrm addr:$src)>;
5619 }
5620
5621 let Predicates = [UseSSE41] in {
5622 // Common patterns involving scalar load.
5623 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5624 (PMOVSXBWrm addr:$src)>;
5625 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5626 (PMOVSXBWrm addr:$src)>;
5627 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5628 (PMOVSXBWrm addr:$src)>;
5629
5630 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5631 (PMOVSXWDrm addr:$src)>;
5632 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5633 (PMOVSXWDrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5635 (PMOVSXWDrm addr:$src)>;
5636
5637 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5638 (PMOVSXDQrm addr:$src)>;
5639 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5640 (PMOVSXDQrm addr:$src)>;
5641 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5642 (PMOVSXDQrm addr:$src)>;
5643
5644 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5645 (PMOVZXBWrm addr:$src)>;
5646 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5647 (PMOVZXBWrm addr:$src)>;
5648 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5649 (PMOVZXBWrm addr:$src)>;
5650
5651 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5652 (PMOVZXWDrm addr:$src)>;
5653 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5654 (PMOVZXWDrm addr:$src)>;
5655 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5656 (PMOVZXWDrm addr:$src)>;
5657
5658 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5659 (PMOVZXDQrm addr:$src)>;
5660 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5661 (PMOVZXDQrm addr:$src)>;
5662 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5663 (PMOVZXDQrm addr:$src)>;
5664 }
5665
5666 let Predicates = [HasAVX2] in {
5667 let AddedComplexity = 15 in {
5668 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5669 (VPMOVZXDQYrr VR128:$src)>;
5670 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5671 (VPMOVZXWDYrr VR128:$src)>;
5672 }
5673
5674 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5675 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5676 }
5677
5678 let Predicates = [HasAVX] in {
5679 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5680 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5681 }
5682
5683 let Predicates = [UseSSE41] in {
5684 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5685 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5686 }
5687
5688
5689 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5690 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5691 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5692 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5693
5694 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5695 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5696 [(set VR128:$dst,
5697 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5698 OpSize;
5699 }
5700
5701 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5702 Intrinsic IntId> {
5703 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5704 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5705 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5706
5707 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5709 [(set VR256:$dst,
5710 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5711 OpSize;
5712 }
5713
5714 let Predicates = [HasAVX] in {
5715 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5716 VEX;
5717 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5718 VEX;
5719 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5720 VEX;
5721 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5722 VEX;
5723 }
5724
5725 let Predicates = [HasAVX2] in {
5726 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5727 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5728 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5729 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5730 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5731 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5732 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5733 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5734 }
5735
5736 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5737 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5738 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5739 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5740
5741 let Predicates = [HasAVX] in {
5742 // Common patterns involving scalar load
5743 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5744 (VPMOVSXBDrm addr:$src)>;
5745 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5746 (VPMOVSXWQrm addr:$src)>;
5747
5748 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5749 (VPMOVZXBDrm addr:$src)>;
5750 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5751 (VPMOVZXWQrm addr:$src)>;
5752 }
5753
5754 let Predicates = [UseSSE41] in {
5755 // Common patterns involving scalar load
5756 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5757 (PMOVSXBDrm addr:$src)>;
5758 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5759 (PMOVSXWQrm addr:$src)>;
5760
5761 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5762 (PMOVZXBDrm addr:$src)>;
5763 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5764 (PMOVZXWQrm addr:$src)>;
5765 }
5766
5767 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5768 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5769 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5770 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5771
5772 // Expecting a i16 load any extended to i32 value.
5773 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5775 [(set VR128:$dst, (IntId (bitconvert
5776 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5777 OpSize;
5778 }
5779
5780 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5781 Intrinsic IntId> {
5782 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5783 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5784 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5785
5786 // Expecting a i16 load any extended to i32 value.
5787 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5788 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5789 [(set VR256:$dst, (IntId (bitconvert
5790 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5791 OpSize;
5792 }
5793
5794 let Predicates = [HasAVX] in {
5795 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5796 VEX;
5797 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5798 VEX;
5799 }
5800 let Predicates = [HasAVX2] in {
5801 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5802 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5803 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5804 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5805 }
5806 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5807 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5808
5809 let Predicates = [HasAVX] in {
5810 // Common patterns involving scalar load
5811 def : Pat<(int_x86_sse41_pmovsxbq
5812 (bitconvert (v4i32 (X86vzmovl
5813 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5814 (VPMOVSXBQrm addr:$src)>;
5815
5816 def : Pat<(int_x86_sse41_pmovzxbq
5817 (bitconvert (v4i32 (X86vzmovl
5818 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5819 (VPMOVZXBQrm addr:$src)>;
5820 }
5821
5822 let Predicates = [UseSSE41] in {
5823 // Common patterns involving scalar load
5824 def : Pat<(int_x86_sse41_pmovsxbq
5825 (bitconvert (v4i32 (X86vzmovl
5826 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5827 (PMOVSXBQrm addr:$src)>;
5828
5829 def : Pat<(int_x86_sse41_pmovzxbq
5830 (bitconvert (v4i32 (X86vzmovl
5831 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5832 (PMOVZXBQrm addr:$src)>;
5833 }
5834
5835 //===----------------------------------------------------------------------===//
5836 // SSE4.1 - Extract Instructions
5837 //===----------------------------------------------------------------------===//
5838
5839 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5840 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5841 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5842 (ins VR128:$src1, i32i8imm:$src2),
5843 !strconcat(OpcodeStr,
5844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5845 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5846 OpSize;
5847 let neverHasSideEffects = 1, mayStore = 1 in
5848 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5849 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5850 !strconcat(OpcodeStr,
5851 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5852 []>, OpSize;
5853 // FIXME:
5854 // There's an AssertZext in the way of writing the store pattern
5855 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5856 }
5857
5858 let Predicates = [HasAVX] in {
5859 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5860 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5861 (ins VR128:$src1, i32i8imm:$src2),
5862 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5863 }
5864
5865 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5866
5867
5868 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5869 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5870 let neverHasSideEffects = 1, mayStore = 1 in
5871 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5872 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5873 !strconcat(OpcodeStr,
5874 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5875 []>, OpSize;
5876 // FIXME:
5877 // There's an AssertZext in the way of writing the store pattern
5878 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5879 }
5880
5881 let Predicates = [HasAVX] in
5882 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5883
5884 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5885
5886
5887 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5888 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5889 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5890 (ins VR128:$src1, i32i8imm:$src2),
5891 !strconcat(OpcodeStr,
5892 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5893 [(set GR32:$dst,
5894 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5895 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5896 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5897 !strconcat(OpcodeStr,
5898 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5899 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5900 addr:$dst)]>, OpSize;
5901 }
5902
5903 let Predicates = [HasAVX] in
5904 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5905
5906 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5907
5908 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5909 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5910 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5911 (ins VR128:$src1, i32i8imm:$src2),
5912 !strconcat(OpcodeStr,
5913 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5914 [(set GR64:$dst,
5915 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5916 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5917 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5918 !strconcat(OpcodeStr,
5919 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5920 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5921 addr:$dst)]>, OpSize, REX_W;
5922 }
5923
5924 let Predicates = [HasAVX] in
5925 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5926
5927 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5928
5929 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5930 /// destination
5931 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5932 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5933 (ins VR128:$src1, i32i8imm:$src2),
5934 !strconcat(OpcodeStr,
5935 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5936 [(set GR32:$dst,
5937 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5938 OpSize;
5939 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5940 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5941 !strconcat(OpcodeStr,
5942 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5943 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5944 addr:$dst)]>, OpSize;
5945 }
5946
5947 let ExeDomain = SSEPackedSingle in {
5948 let Predicates = [HasAVX] in {
5949 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5950 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5951 (ins VR128:$src1, i32i8imm:$src2),
5952 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5953 []>, OpSize, VEX;
5954 }
5955 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5956 }
5957
5958 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5959 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5960 imm:$src2))),
5961 addr:$dst),
5962 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5963 Requires<[HasAVX]>;
5964 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5965 imm:$src2))),
5966 addr:$dst),
5967 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5968 Requires<[UseSSE41]>;
5969
5970 //===----------------------------------------------------------------------===//
5971 // SSE4.1 - Insert Instructions
5972 //===----------------------------------------------------------------------===//
5973
5974 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5975 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5976 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5977 !if(Is2Addr,
5978 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5979 !strconcat(asm,
5980 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5981 [(set VR128:$dst,
5982 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5983 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5984 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5985 !if(Is2Addr,
5986 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5987 !strconcat(asm,
5988 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5989 [(set VR128:$dst,
5990 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5991 imm:$src3))]>, OpSize;
5992 }
5993
5994 let Predicates = [HasAVX] in
5995 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5996 let Constraints = "$src1 = $dst" in
5997 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5998
5999 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6000 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6001 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6002 !if(Is2Addr,
6003 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6004 !strconcat(asm,
6005 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6006 [(set VR128:$dst,
6007 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6008 OpSize;
6009 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6010 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6011 !if(Is2Addr,
6012 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6013 !strconcat(asm,
6014 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6015 [(set VR128:$dst,
6016 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6017 imm:$src3)))]>, OpSize;
6018 }
6019
6020 let Predicates = [HasAVX] in
6021 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6022 let Constraints = "$src1 = $dst" in
6023 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6024
6025 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6026 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6027 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6028 !if(Is2Addr,
6029 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6030 !strconcat(asm,
6031 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6032 [(set VR128:$dst,
6033 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6034 OpSize;
6035 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6036 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6037 !if(Is2Addr,
6038 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6039 !strconcat(asm,
6040 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6041 [(set VR128:$dst,
6042 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6043 imm:$src3)))]>, OpSize;
6044 }
6045
6046 let Predicates = [HasAVX] in
6047 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6048 let Constraints = "$src1 = $dst" in
6049 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6050
6051 // insertps has a few different modes, there's the first two here below which
6052 // are optimized inserts that won't zero arbitrary elements in the destination
6053 // vector. The next one matches the intrinsic and could zero arbitrary elements
6054 // in the target vector.
6055 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6056 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6057 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6058 !if(Is2Addr,
6059 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6060 !strconcat(asm,
6061 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6062 [(set VR128:$dst,
6063 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6064 OpSize;
6065 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6066 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6067 !if(Is2Addr,
6068 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6069 !strconcat(asm,
6070 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6071 [(set VR128:$dst,
6072 (X86insrtps VR128:$src1,
6073 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6074 imm:$src3))]>, OpSize;
6075 }
6076
6077 let ExeDomain = SSEPackedSingle in {
6078 let Predicates = [HasAVX] in
6079 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6080 let Constraints = "$src1 = $dst" in
6081 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6082 }
6083
6084 //===----------------------------------------------------------------------===//
6085 // SSE4.1 - Round Instructions
6086 //===----------------------------------------------------------------------===//
6087
6088 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6089 X86MemOperand x86memop, RegisterClass RC,
6090 PatFrag mem_frag32, PatFrag mem_frag64,
6091 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6092 let ExeDomain = SSEPackedSingle in {
6093 // Intrinsic operation, reg.
6094 // Vector intrinsic operation, reg
6095 def PSr : SS4AIi8<opcps, MRMSrcReg,
6096 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6097 !strconcat(OpcodeStr,
6098 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6099 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6100 OpSize;
6101
6102 // Vector intrinsic operation, mem
6103 def PSm : SS4AIi8<opcps, MRMSrcMem,
6104 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6105 !strconcat(OpcodeStr,
6106 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6107 [(set RC:$dst,
6108 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6109 OpSize;
6110 } // ExeDomain = SSEPackedSingle
6111
6112 let ExeDomain = SSEPackedDouble in {
6113 // Vector intrinsic operation, reg
6114 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6115 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6116 !strconcat(OpcodeStr,
6117 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6118 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6119 OpSize;
6120
6121 // Vector intrinsic operation, mem
6122 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6123 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6124 !strconcat(OpcodeStr,
6125 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6126 [(set RC:$dst,
6127 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6128 OpSize;
6129 } // ExeDomain = SSEPackedDouble
6130 }
6131
6132 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6133 string OpcodeStr,
6134 Intrinsic F32Int,
6135 Intrinsic F64Int, bit Is2Addr = 1> {
6136 let ExeDomain = GenericDomain in {
6137 // Operation, reg.
6138 def SSr : SS4AIi8<opcss, MRMSrcReg,
6139 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6140 !if(Is2Addr,
6141 !strconcat(OpcodeStr,
6142 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6143 !strconcat(OpcodeStr,
6144 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6145 []>, OpSize;
6146
6147 // Intrinsic operation, reg.
6148 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6149 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6150 !if(Is2Addr,
6151 !strconcat(OpcodeStr,
6152 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6153 !strconcat(OpcodeStr,
6154 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6155 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6156 OpSize;
6157
6158 // Intrinsic operation, mem.
6159 def SSm : SS4AIi8<opcss, MRMSrcMem,
6160 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6161 !if(Is2Addr,
6162 !strconcat(OpcodeStr,
6163 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6164 !strconcat(OpcodeStr,
6165 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6166 [(set VR128:$dst,
6167 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6168 OpSize;
6169
6170 // Operation, reg.
6171 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6172 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6173 !if(Is2Addr,
6174 !strconcat(OpcodeStr,
6175 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6176 !strconcat(OpcodeStr,
6177 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6178 []>, OpSize;
6179
6180 // Intrinsic operation, reg.
6181 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6182 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6183 !if(Is2Addr,
6184 !strconcat(OpcodeStr,
6185 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6186 !strconcat(OpcodeStr,
6187 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6188 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6189 OpSize;
6190
6191 // Intrinsic operation, mem.
6192 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6193 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6194 !if(Is2Addr,
6195 !strconcat(OpcodeStr,
6196 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6197 !strconcat(OpcodeStr,
6198 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6199 [(set VR128:$dst,
6200 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6201 OpSize;
6202 } // ExeDomain = GenericDomain
6203 }
6204
6205 // FP round - roundss, roundps, roundsd, roundpd
6206 let Predicates = [HasAVX] in {
6207 // Intrinsic form
6208 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6209 memopv4f32, memopv2f64,
6210 int_x86_sse41_round_ps,
6211 int_x86_sse41_round_pd>, VEX;
6212 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6213 memopv8f32, memopv4f64,
6214 int_x86_avx_round_ps_256,
6215 int_x86_avx_round_pd_256>, VEX, VEX_L;
6216 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6217 int_x86_sse41_round_ss,
6218 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6219
6220 def : Pat<(ffloor FR32:$src),
6221 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6222 def : Pat<(f64 (ffloor FR64:$src)),
6223 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6224 def : Pat<(f32 (fnearbyint FR32:$src)),
6225 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6226 def : Pat<(f64 (fnearbyint FR64:$src)),
6227 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6228 def : Pat<(f32 (fceil FR32:$src)),
6229 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6230 def : Pat<(f64 (fceil FR64:$src)),
6231 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6232 def : Pat<(f32 (frint FR32:$src)),
6233 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6234 def : Pat<(f64 (frint FR64:$src)),
6235 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6236 def : Pat<(f32 (ftrunc FR32:$src)),
6237 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6238 def : Pat<(f64 (ftrunc FR64:$src)),
6239 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6240
6241 def : Pat<(v4f32 (ffloor VR128:$src)),
6242 (VROUNDPSr VR128:$src, (i32 0x1))>;
6243 def : Pat<(v2f64 (ffloor VR128:$src)),
6244 (VROUNDPDr VR128:$src, (i32 0x1))>;
6245 def : Pat<(v8f32 (ffloor VR256:$src)),
6246 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6247 def : Pat<(v4f64 (ffloor VR256:$src)),
6248 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6249 }
6250
6251 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6252 memopv4f32, memopv2f64,
6253 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6254 let Constraints = "$src1 = $dst" in
6255 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6256 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6257
6258 let Predicates = [UseSSE41] in {
6259 def : Pat<(ffloor FR32:$src),
6260 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6261 def : Pat<(f64 (ffloor FR64:$src)),
6262 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6263 def : Pat<(f32 (fnearbyint FR32:$src)),
6264 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6265 def : Pat<(f64 (fnearbyint FR64:$src)),
6266 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6267 def : Pat<(f32 (fceil FR32:$src)),
6268 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6269 def : Pat<(f64 (fceil FR64:$src)),
6270 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6271 def : Pat<(f32 (frint FR32:$src)),
6272 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6273 def : Pat<(f64 (frint FR64:$src)),
6274 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6275 def : Pat<(f32 (ftrunc FR32:$src)),
6276 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6277 def : Pat<(f64 (ftrunc FR64:$src)),
6278 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6279
6280 def : Pat<(v4f32 (ffloor VR128:$src)),
6281 (ROUNDPSr VR128:$src, (i32 0x1))>;
6282 def : Pat<(v2f64 (ffloor VR128:$src)),
6283 (ROUNDPDr VR128:$src, (i32 0x1))>;
6284 }
6285
6286 //===----------------------------------------------------------------------===//
6287 // SSE4.1 - Packed Bit Test
6288 //===----------------------------------------------------------------------===//
6289
6290 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6291 // the intel intrinsic that corresponds to this.
6292 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6293 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6294 "vptest\t{$src2, $src1|$src1, $src2}",
6295 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6296 OpSize, VEX;
6297 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6298 "vptest\t{$src2, $src1|$src1, $src2}",
6299 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6300 OpSize, VEX;
6301
6302 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6303 "vptest\t{$src2, $src1|$src1, $src2}",
6304 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6305 OpSize, VEX, VEX_L;
6306 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6307 "vptest\t{$src2, $src1|$src1, $src2}",
6308 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6309 OpSize, VEX, VEX_L;
6310 }
6311
6312 let Defs = [EFLAGS] in {
6313 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6314 "ptest\t{$src2, $src1|$src1, $src2}",
6315 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6316 OpSize;
6317 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6318 "ptest\t{$src2, $src1|$src1, $src2}",
6319 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6320 OpSize;
6321 }
6322
6323 // The bit test instructions below are AVX only
6324 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6325 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6326 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6327 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6328 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6329 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6330 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6331 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6332 OpSize, VEX;
6333 }
6334
6335 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6336 let ExeDomain = SSEPackedSingle in {
6337 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6338 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6339 VEX_L;
6340 }
6341 let ExeDomain = SSEPackedDouble in {
6342 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6343 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6344 VEX_L;
6345 }
6346 }
6347
6348 //===----------------------------------------------------------------------===//
6349 // SSE4.1 - Misc Instructions
6350 //===----------------------------------------------------------------------===//
6351
6352 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6353 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6354 "popcnt{w}\t{$src, $dst|$dst, $src}",
6355 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6356 OpSize, XS;
6357 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6358 "popcnt{w}\t{$src, $dst|$dst, $src}",
6359 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6360 (implicit EFLAGS)]>, OpSize, XS;
6361
6362 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6363 "popcnt{l}\t{$src, $dst|$dst, $src}",
6364 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6365 XS;
6366 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6367 "popcnt{l}\t{$src, $dst|$dst, $src}",
6368 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6369 (implicit EFLAGS)]>, XS;
6370
6371 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6372 "popcnt{q}\t{$src, $dst|$dst, $src}",
6373 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6374 XS;
6375 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6376 "popcnt{q}\t{$src, $dst|$dst, $src}",
6377 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6378 (implicit EFLAGS)]>, XS;
6379 }
6380
6381
6382
6383 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6384 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6385 Intrinsic IntId128> {
6386 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6387 (ins VR128:$src),
6388 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6389 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6390 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6391 (ins i128mem:$src),
6392 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6393 [(set VR128:$dst,
6394 (IntId128
6395 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6396 }
6397
6398 let Predicates = [HasAVX] in
6399 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6400 int_x86_sse41_phminposuw>, VEX;
6401 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6402 int_x86_sse41_phminposuw>;
6403
6404 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6405 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6406 Intrinsic IntId128, bit Is2Addr = 1> {
6407 let isCommutable = 1 in
6408 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6409 (ins VR128:$src1, VR128:$src2),
6410 !if(Is2Addr,
6411 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6412 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6413 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6414 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6415 (ins VR128:$src1, i128mem:$src2),
6416 !if(Is2Addr,
6417 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6419 [(set VR128:$dst,
6420 (IntId128 VR128:$src1,
6421 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6422 }
6423
6424 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6425 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6426 Intrinsic IntId256> {
6427 let isCommutable = 1 in
6428 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6429 (ins VR256:$src1, VR256:$src2),
6430 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6431 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6432 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6433 (ins VR256:$src1, i256mem:$src2),
6434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6435 [(set VR256:$dst,
6436 (IntId256 VR256:$src1,
6437 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6438 }
6439
6440 let Predicates = [HasAVX] in {
6441 let isCommutable = 0 in
6442 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6443 0>, VEX_4V;
6444 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6445 0>, VEX_4V;
6446 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6447 0>, VEX_4V;
6448 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6449 0>, VEX_4V;
6450 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6451 0>, VEX_4V;
6452 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6453 0>, VEX_4V;
6454 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6455 0>, VEX_4V;
6456 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6457 0>, VEX_4V;
6458 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6459 0>, VEX_4V;
6460 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6461 0>, VEX_4V;
6462 }
6463
6464 let Predicates = [HasAVX2] in {
6465 let isCommutable = 0 in
6466 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6467 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6468 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6469 int_x86_avx2_pmins_b>, VEX_4V, VEX_L;
6470 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6471 int_x86_avx2_pmins_d>, VEX_4V, VEX_L;
6472 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6473 int_x86_avx2_pminu_d>, VEX_4V, VEX_L;
6474 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6475 int_x86_avx2_pminu_w>, VEX_4V, VEX_L;
6476 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6477 int_x86_avx2_pmaxs_b>, VEX_4V, VEX_L;
6478 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6479 int_x86_avx2_pmaxs_d>, VEX_4V, VEX_L;
6480 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6481 int_x86_avx2_pmaxu_d>, VEX_4V, VEX_L;
6482 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6483 int_x86_avx2_pmaxu_w>, VEX_4V, VEX_L;
6484 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6485 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6486 }
6487
6488 let Constraints = "$src1 = $dst" in {
6489 let isCommutable = 0 in
6490 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6491 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6492 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6493 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6494 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6495 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6496 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6497 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6498 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6499 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6500 }
6501
6502 /// SS48I_binop_rm - Simple SSE41 binary operator.
6503 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6504 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6505 X86MemOperand x86memop, bit Is2Addr = 1> {
6506 let isCommutable = 1 in
6507 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6508 (ins RC:$src1, RC:$src2),
6509 !if(Is2Addr,
6510 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6511 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6512 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6513 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6514 (ins RC:$src1, x86memop:$src2),
6515 !if(Is2Addr,
6516 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6518 [(set RC:$dst,
6519 (OpVT (OpNode RC:$src1,
6520 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6521 }
6522
6523 let Predicates = [HasAVX] in {
6524 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6525 memopv2i64, i128mem, 0>, VEX_4V;
6526 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6527 memopv2i64, i128mem, 0>, VEX_4V;
6528 }
6529 let Predicates = [HasAVX2] in {
6530 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6531 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6532 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6533 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6534 }
6535
6536 let Constraints = "$src1 = $dst" in {
6537 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6538 memopv2i64, i128mem>;
6539 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6540 memopv2i64, i128mem>;
6541 }
6542
6543 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6544 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6545 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6546 X86MemOperand x86memop, bit Is2Addr = 1> {
6547 let isCommutable = 1 in
6548 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6549 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6550 !if(Is2Addr,
6551 !strconcat(OpcodeStr,
6552 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6553 !strconcat(OpcodeStr,
6554 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6555 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6556 OpSize;
6557 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6558 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6559 !if(Is2Addr,
6560 !strconcat(OpcodeStr,
6561 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6562 !strconcat(OpcodeStr,
6563 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6564 [(set RC:$dst,
6565 (IntId RC:$src1,
6566 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6567 OpSize;
6568 }
6569
6570 let Predicates = [HasAVX] in {
6571 let isCommutable = 0 in {
6572 let ExeDomain = SSEPackedSingle in {
6573 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6574 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6575 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6576 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6577 f256mem, 0>, VEX_4V, VEX_L;
6578 }
6579 let ExeDomain = SSEPackedDouble in {
6580 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6581 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6582 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6583 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6584 f256mem, 0>, VEX_4V, VEX_L;
6585 }
6586 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6587 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6588 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6589 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6590 }
6591 let ExeDomain = SSEPackedSingle in
6592 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6593 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6594 let ExeDomain = SSEPackedDouble in
6595 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6596 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6597 let ExeDomain = SSEPackedSingle in
6598 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6599 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6600 }
6601
6602 let Predicates = [HasAVX2] in {
6603 let isCommutable = 0 in {
6604 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6605 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6606 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6607 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6608 }
6609 }
6610
6611 let Constraints = "$src1 = $dst" in {
6612 let isCommutable = 0 in {
6613 let ExeDomain = SSEPackedSingle in
6614 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6615 VR128, memopv4f32, f128mem>;
6616 let ExeDomain = SSEPackedDouble in
6617 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6618 VR128, memopv2f64, f128mem>;
6619 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6620 VR128, memopv2i64, i128mem>;
6621 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6622 VR128, memopv2i64, i128mem>;
6623 }
6624 let ExeDomain = SSEPackedSingle in
6625 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6626 VR128, memopv4f32, f128mem>;
6627 let ExeDomain = SSEPackedDouble in
6628 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6629 VR128, memopv2f64, f128mem>;
6630 }
6631
6632 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6633 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6634 RegisterClass RC, X86MemOperand x86memop,
6635 PatFrag mem_frag, Intrinsic IntId> {
6636 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6637 (ins RC:$src1, RC:$src2, RC:$src3),
6638 !strconcat(OpcodeStr,
6639 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6640 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6641 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6642
6643 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6644 (ins RC:$src1, x86memop:$src2, RC:$src3),
6645 !strconcat(OpcodeStr,
6646 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6647 [(set RC:$dst,
6648 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6649 RC:$src3))],
6650 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6651 }
6652
6653 let Predicates = [HasAVX] in {
6654 let ExeDomain = SSEPackedDouble in {
6655 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6656 memopv2f64, int_x86_sse41_blendvpd>;
6657 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6658 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6659 } // ExeDomain = SSEPackedDouble
6660 let ExeDomain = SSEPackedSingle in {
6661 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6662 memopv4f32, int_x86_sse41_blendvps>;
6663 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6664 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6665 } // ExeDomain = SSEPackedSingle
6666 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6667 memopv2i64, int_x86_sse41_pblendvb>;
6668 }
6669
6670 let Predicates = [HasAVX2] in {
6671 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6672 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6673 }
6674
6675 let Predicates = [HasAVX] in {
6676 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6677 (v16i8 VR128:$src2))),
6678 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6679 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6680 (v4i32 VR128:$src2))),
6681 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6682 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6683 (v4f32 VR128:$src2))),
6684 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6685 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6686 (v2i64 VR128:$src2))),
6687 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6688 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6689 (v2f64 VR128:$src2))),
6690 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6691 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6692 (v8i32 VR256:$src2))),
6693 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6694 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6695 (v8f32 VR256:$src2))),
6696 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6697 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6698 (v4i64 VR256:$src2))),
6699 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6700 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6701 (v4f64 VR256:$src2))),
6702 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6703
6704 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6705 (imm:$mask))),
6706 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6707 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6708 (imm:$mask))),
6709 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6710
6711 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6712 (imm:$mask))),
6713 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6714 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6715 (imm:$mask))),
6716 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6717 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6718 (imm:$mask))),
6719 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6720 }
6721
6722 let Predicates = [HasAVX2] in {
6723 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6724 (v32i8 VR256:$src2))),
6725 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6726 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6727 (imm:$mask))),
6728 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6729 }
6730
6731 /// SS41I_ternary_int - SSE 4.1 ternary operator
6732 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6733 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6734 X86MemOperand x86memop, Intrinsic IntId> {
6735 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6736 (ins VR128:$src1, VR128:$src2),
6737 !strconcat(OpcodeStr,
6738 "\t{$src2, $dst|$dst, $src2}"),
6739 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6740 OpSize;
6741
6742 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6743 (ins VR128:$src1, x86memop:$src2),
6744 !strconcat(OpcodeStr,
6745 "\t{$src2, $dst|$dst, $src2}"),
6746 [(set VR128:$dst,
6747 (IntId VR128:$src1,
6748 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6749 }
6750 }
6751
6752 let ExeDomain = SSEPackedDouble in
6753 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
6754 int_x86_sse41_blendvpd>;
6755 let ExeDomain = SSEPackedSingle in
6756 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
6757 int_x86_sse41_blendvps>;
6758 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
6759 int_x86_sse41_pblendvb>;
6760
6761 // Aliases with the implicit xmm0 argument
6762 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6763 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
6764 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6765 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
6766 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6767 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
6768 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6769 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
6770 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6771 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
6772 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}",
6773 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
6774
6775 let Predicates = [UseSSE41] in {
6776 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6777 (v16i8 VR128:$src2))),
6778 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6779 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6780 (v4i32 VR128:$src2))),
6781 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6782 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6783 (v4f32 VR128:$src2))),
6784 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6785 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6786 (v2i64 VR128:$src2))),
6787 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6788 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6789 (v2f64 VR128:$src2))),
6790 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6791
6792 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6793 (imm:$mask))),
6794 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6795 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6796 (imm:$mask))),
6797 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6798 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6799 (imm:$mask))),
6800 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6801
6802 }
6803
6804 let Predicates = [HasAVX] in
6805 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6806 "vmovntdqa\t{$src, $dst|$dst, $src}",
6807 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6808 OpSize, VEX;
6809 let Predicates = [HasAVX2] in
6810 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6811 "vmovntdqa\t{$src, $dst|$dst, $src}",
6812 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6813 OpSize, VEX, VEX_L;
6814 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6815 "movntdqa\t{$src, $dst|$dst, $src}",
6816 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6817 OpSize;
6818
6819 //===----------------------------------------------------------------------===//
6820 // SSE4.2 - Compare Instructions
6821 //===----------------------------------------------------------------------===//
6822
6823 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6824 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6825 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6826 X86MemOperand x86memop, bit Is2Addr = 1> {
6827 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6828 (ins RC:$src1, RC:$src2),
6829 !if(Is2Addr,
6830 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6831 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6832 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6833 OpSize;
6834 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6835 (ins RC:$src1, x86memop:$src2),
6836 !if(Is2Addr,
6837 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6839 [(set RC:$dst,
6840 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6841 }
6842
6843 let Predicates = [HasAVX] in
6844 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6845 memopv2i64, i128mem, 0>, VEX_4V;
6846
6847 let Predicates = [HasAVX2] in
6848 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6849 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6850
6851 let Constraints = "$src1 = $dst" in
6852 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6853 memopv2i64, i128mem>;
6854
6855 //===----------------------------------------------------------------------===//
6856 // SSE4.2 - String/text Processing Instructions
6857 //===----------------------------------------------------------------------===//
6858
6859 // Packed Compare Implicit Length Strings, Return Mask
6860 multiclass pseudo_pcmpistrm<string asm> {
6861 def REG : PseudoI<(outs VR128:$dst),
6862 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6863 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6864 imm:$src3))]>;
6865 def MEM : PseudoI<(outs VR128:$dst),
6866 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6867 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6868 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6869 }
6870
6871 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6872 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6873 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
6874 }
6875
6876 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6877 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6878 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6879 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6880 let mayLoad = 1 in
6881 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6882 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6883 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6884 }
6885
6886 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6887 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6888 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6889 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6890 let mayLoad = 1 in
6891 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6892 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6893 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6894 }
6895
6896 // Packed Compare Explicit Length Strings, Return Mask
6897 multiclass pseudo_pcmpestrm<string asm> {
6898 def REG : PseudoI<(outs VR128:$dst),
6899 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6900 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6901 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6902 def MEM : PseudoI<(outs VR128:$dst),
6903 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6904 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6905 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6906 }
6907
6908 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6909 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6910 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
6911 }
6912
6913 let Predicates = [HasAVX],
6914 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6915 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6916 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6917 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6918 let mayLoad = 1 in
6919 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6920 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6921 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6922 }
6923
6924 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6925 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6926 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6927 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6928 let mayLoad = 1 in
6929 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6930 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6931 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6932 }
6933
6934 // Packed Compare Implicit Length Strings, Return Index
6935 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
6936 multiclass SS42AI_pcmpistri<string asm> {
6937 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6938 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6939 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6940 []>, OpSize;
6941 let mayLoad = 1 in
6942 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6943 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6944 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6945 []>, OpSize;
6946 }
6947 }
6948
6949 let Predicates = [HasAVX] in
6950 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
6951 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
6952
6953 // Packed Compare Explicit Length Strings, Return Index
6954 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6955 multiclass SS42AI_pcmpestri<string asm> {
6956 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6957 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6958 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6959 []>, OpSize;
6960 let mayLoad = 1 in
6961 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6962 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6963 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6964 []>, OpSize;
6965 }
6966 }
6967
6968 let Predicates = [HasAVX] in
6969 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
6970 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
6971
6972 //===----------------------------------------------------------------------===//
6973 // SSE4.2 - CRC Instructions
6974 //===----------------------------------------------------------------------===//
6975
6976 // No CRC instructions have AVX equivalents
6977
6978 // crc intrinsic instruction
6979 // This set of instructions are only rm, the only difference is the size
6980 // of r and m.
6981 let Constraints = "$src1 = $dst" in {
6982 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6983 (ins GR32:$src1, i8mem:$src2),
6984 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6985 [(set GR32:$dst,
6986 (int_x86_sse42_crc32_32_8 GR32:$src1,
6987 (load addr:$src2)))]>;
6988 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6989 (ins GR32:$src1, GR8:$src2),
6990 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6991 [(set GR32:$dst,
6992 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6993 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6994 (ins GR32:$src1, i16mem:$src2),
6995 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6996 [(set GR32:$dst,
6997 (int_x86_sse42_crc32_32_16 GR32:$src1,
6998 (load addr:$src2)))]>,
6999 OpSize;
7000 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7001 (ins GR32:$src1, GR16:$src2),
7002 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7003 [(set GR32:$dst,
7004 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7005 OpSize;
7006 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7007 (ins GR32:$src1, i32mem:$src2),
7008 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7009 [(set GR32:$dst,
7010 (int_x86_sse42_crc32_32_32 GR32:$src1,
7011 (load addr:$src2)))]>;
7012 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7013 (ins GR32:$src1, GR32:$src2),
7014 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7015 [(set GR32:$dst,
7016 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7017 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7018 (ins GR64:$src1, i8mem:$src2),
7019 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7020 [(set GR64:$dst,
7021 (int_x86_sse42_crc32_64_8 GR64:$src1,
7022 (load addr:$src2)))]>,
7023 REX_W;
7024 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7025 (ins GR64:$src1, GR8:$src2),
7026 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7027 [(set GR64:$dst,
7028 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7029 REX_W;
7030 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7031 (ins GR64:$src1, i64mem:$src2),
7032 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7033 [(set GR64:$dst,
7034 (int_x86_sse42_crc32_64_64 GR64:$src1,
7035 (load addr:$src2)))]>,
7036 REX_W;
7037 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7038 (ins GR64:$src1, GR64:$src2),
7039 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7040 [(set GR64:$dst,
7041 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7042 REX_W;
7043 }
7044
7045 //===----------------------------------------------------------------------===//
7046 // AES-NI Instructions
7047 //===----------------------------------------------------------------------===//
7048
7049 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7050 Intrinsic IntId128, bit Is2Addr = 1> {
7051 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7052 (ins VR128:$src1, VR128:$src2),
7053 !if(Is2Addr,
7054 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7055 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7056 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7057 OpSize;
7058 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7059 (ins VR128:$src1, i128mem:$src2),
7060 !if(Is2Addr,
7061 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7062 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7063 [(set VR128:$dst,
7064 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7065 }
7066
7067 // Perform One Round of an AES Encryption/Decryption Flow
7068 let Predicates = [HasAVX, HasAES] in {
7069 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7070 int_x86_aesni_aesenc, 0>, VEX_4V;
7071 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7072 int_x86_aesni_aesenclast, 0>, VEX_4V;
7073 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7074 int_x86_aesni_aesdec, 0>, VEX_4V;
7075 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7076 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7077 }
7078
7079 let Constraints = "$src1 = $dst" in {
7080 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7081 int_x86_aesni_aesenc>;
7082 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7083 int_x86_aesni_aesenclast>;
7084 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7085 int_x86_aesni_aesdec>;
7086 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7087 int_x86_aesni_aesdeclast>;
7088 }
7089
7090 // Perform the AES InvMixColumn Transformation
7091 let Predicates = [HasAVX, HasAES] in {
7092 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7093 (ins VR128:$src1),
7094 "vaesimc\t{$src1, $dst|$dst, $src1}",
7095 [(set VR128:$dst,
7096 (int_x86_aesni_aesimc VR128:$src1))]>,
7097 OpSize, VEX;
7098 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7099 (ins i128mem:$src1),
7100 "vaesimc\t{$src1, $dst|$dst, $src1}",
7101 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7102 OpSize, VEX;
7103 }
7104 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7105 (ins VR128:$src1),
7106 "aesimc\t{$src1, $dst|$dst, $src1}",
7107 [(set VR128:$dst,
7108 (int_x86_aesni_aesimc VR128:$src1))]>,
7109 OpSize;
7110 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7111 (ins i128mem:$src1),
7112 "aesimc\t{$src1, $dst|$dst, $src1}",
7113 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7114 OpSize;
7115
7116 // AES Round Key Generation Assist
7117 let Predicates = [HasAVX, HasAES] in {
7118 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7119 (ins VR128:$src1, i8imm:$src2),
7120 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7121 [(set VR128:$dst,
7122 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7123 OpSize, VEX;
7124 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7125 (ins i128mem:$src1, i8imm:$src2),
7126 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7127 [(set VR128:$dst,
7128 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7129 OpSize, VEX;
7130 }
7131 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7132 (ins VR128:$src1, i8imm:$src2),
7133 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7134 [(set VR128:$dst,
7135 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7136 OpSize;
7137 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7138 (ins i128mem:$src1, i8imm:$src2),
7139 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7140 [(set VR128:$dst,
7141 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7142 OpSize;
7143
7144 //===----------------------------------------------------------------------===//
7145 // PCLMUL Instructions
7146 //===----------------------------------------------------------------------===//
7147
7148 // AVX carry-less Multiplication instructions
7149 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7150 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7151 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7152 [(set VR128:$dst,
7153 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7154
7155 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7156 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7157 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7158 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7159 (memopv2i64 addr:$src2), imm:$src3))]>;
7160
7161 // Carry-less Multiplication instructions
7162 let Constraints = "$src1 = $dst" in {
7163 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7164 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7165 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7166 [(set VR128:$dst,
7167 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7168
7169 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7170 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7171 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7172 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7173 (memopv2i64 addr:$src2), imm:$src3))]>;
7174 } // Constraints = "$src1 = $dst"
7175
7176
7177 multiclass pclmul_alias<string asm, int immop> {
7178 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7179 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7180
7181 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7182 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7183
7184 def : InstAlias<!strconcat("vpclmul", asm,
7185 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7186 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7187
7188 def : InstAlias<!strconcat("vpclmul", asm,
7189 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7190 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7191 }
7192 defm : pclmul_alias<"hqhq", 0x11>;
7193 defm : pclmul_alias<"hqlq", 0x01>;
7194 defm : pclmul_alias<"lqhq", 0x10>;
7195 defm : pclmul_alias<"lqlq", 0x00>;
7196
7197 //===----------------------------------------------------------------------===//
7198 // SSE4A Instructions
7199 //===----------------------------------------------------------------------===//
7200
7201 let Predicates = [HasSSE4A] in {
7202
7203 let Constraints = "$src = $dst" in {
7204 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7205 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7206 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7207 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7208 imm:$idx))]>, TB, OpSize;
7209 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7210 (ins VR128:$src, VR128:$mask),
7211 "extrq\t{$mask, $src|$src, $mask}",
7212 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7213 VR128:$mask))]>, TB, OpSize;
7214
7215 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7216 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7217 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7218 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7219 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7220 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7221 (ins VR128:$src, VR128:$mask),
7222 "insertq\t{$mask, $src|$src, $mask}",
7223 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7224 VR128:$mask))]>, XD;
7225 }
7226
7227 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7228 "movntss\t{$src, $dst|$dst, $src}",
7229 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7230
7231 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7232 "movntsd\t{$src, $dst|$dst, $src}",
7233 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7234 }
7235
7236 //===----------------------------------------------------------------------===//
7237 // AVX Instructions
7238 //===----------------------------------------------------------------------===//
7239
7240 //===----------------------------------------------------------------------===//
7241 // VBROADCAST - Load from memory and broadcast to all elements of the
7242 // destination operand
7243 //
7244 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7245 X86MemOperand x86memop, Intrinsic Int> :
7246 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7247 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7248 [(set RC:$dst, (Int addr:$src))]>, VEX;
7249
7250 // AVX2 adds register forms
7251 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7252 Intrinsic Int> :
7253 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7254 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7255 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7256
7257 let ExeDomain = SSEPackedSingle in {
7258 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7259 int_x86_avx_vbroadcast_ss>;
7260 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7261 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7262 }
7263 let ExeDomain = SSEPackedDouble in
7264 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7265 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7266 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7267 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7268
7269 let ExeDomain = SSEPackedSingle in {
7270 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7271 int_x86_avx2_vbroadcast_ss_ps>;
7272 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7273 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7274 }
7275 let ExeDomain = SSEPackedDouble in
7276 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7277 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7278
7279 let Predicates = [HasAVX2] in
7280 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7281 int_x86_avx2_vbroadcasti128>, VEX_L;
7282
7283 let Predicates = [HasAVX] in
7284 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7285 (VBROADCASTF128 addr:$src)>;
7286
7287
7288 //===----------------------------------------------------------------------===//
7289 // VINSERTF128 - Insert packed floating-point values
7290 //
7291 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7292 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7293 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7294 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7295 []>, VEX_4V, VEX_L;
7296 let mayLoad = 1 in
7297 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7298 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7299 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7300 []>, VEX_4V, VEX_L;
7301 }
7302
7303 let Predicates = [HasAVX] in {
7304 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7305 (iPTR imm)),
7306 (VINSERTF128rr VR256:$src1, VR128:$src2,
7307 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7308 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7309 (iPTR imm)),
7310 (VINSERTF128rr VR256:$src1, VR128:$src2,
7311 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7312
7313 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7314 (iPTR imm)),
7315 (VINSERTF128rm VR256:$src1, addr:$src2,
7316 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7317 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7318 (iPTR imm)),
7319 (VINSERTF128rm VR256:$src1, addr:$src2,
7320 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7321 }
7322
7323 let Predicates = [HasAVX1Only] in {
7324 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7325 (iPTR imm)),
7326 (VINSERTF128rr VR256:$src1, VR128:$src2,
7327 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7328 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7329 (iPTR imm)),
7330 (VINSERTF128rr VR256:$src1, VR128:$src2,
7331 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7332 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7333 (iPTR imm)),
7334 (VINSERTF128rr VR256:$src1, VR128:$src2,
7335 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7336 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7337 (iPTR imm)),
7338 (VINSERTF128rr VR256:$src1, VR128:$src2,
7339 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7340
7341 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7342 (iPTR imm)),
7343 (VINSERTF128rm VR256:$src1, addr:$src2,
7344 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7345 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7346 (bc_v4i32 (memopv2i64 addr:$src2)),
7347 (iPTR imm)),
7348 (VINSERTF128rm VR256:$src1, addr:$src2,
7349 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7350 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7351 (bc_v16i8 (memopv2i64 addr:$src2)),
7352 (iPTR imm)),
7353 (VINSERTF128rm VR256:$src1, addr:$src2,
7354 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7355 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7356 (bc_v8i16 (memopv2i64 addr:$src2)),
7357 (iPTR imm)),
7358 (VINSERTF128rm VR256:$src1, addr:$src2,
7359 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7360 }
7361
7362 //===----------------------------------------------------------------------===//
7363 // VEXTRACTF128 - Extract packed floating-point values
7364 //
7365 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7366 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7367 (ins VR256:$src1, i8imm:$src2),
7368 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7369 []>, VEX, VEX_L;
7370 let mayStore = 1 in
7371 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7372 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7373 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7374 []>, VEX, VEX_L;
7375 }
7376
7377 // AVX1 patterns
7378 let Predicates = [HasAVX] in {
7379 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7380 (v4f32 (VEXTRACTF128rr
7381 (v8f32 VR256:$src1),
7382 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7383 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7384 (v2f64 (VEXTRACTF128rr
7385 (v4f64 VR256:$src1),
7386 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7387
7388 def : Pat<(alignedstore (v4f32 (vextractf128_extract:$ext (v8f32 VR256:$src1),
7389 (iPTR imm))), addr:$dst),
7390 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7391 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7392 def : Pat<(alignedstore (v2f64 (vextractf128_extract:$ext (v4f64 VR256:$src1),
7393 (iPTR imm))), addr:$dst),
7394 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7395 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7396 }
7397
7398 let Predicates = [HasAVX1Only] in {
7399 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7400 (v2i64 (VEXTRACTF128rr
7401 (v4i64 VR256:$src1),
7402 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7403 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7404 (v4i32 (VEXTRACTF128rr
7405 (v8i32 VR256:$src1),
7406 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7407 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7408 (v8i16 (VEXTRACTF128rr
7409 (v16i16 VR256:$src1),
7410 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7411 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7412 (v16i8 (VEXTRACTF128rr
7413 (v32i8 VR256:$src1),
7414 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7415
7416 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7417 (iPTR imm))), addr:$dst),
7418 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7419 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7420 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7421 (iPTR imm))), addr:$dst),
7422 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7423 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7424 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7425 (iPTR imm))), addr:$dst),
7426 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7427 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7428 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7429 (iPTR imm))), addr:$dst),
7430 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7431 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7432 }
7433
7434 //===----------------------------------------------------------------------===//
7435 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7436 //
7437 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7438 Intrinsic IntLd, Intrinsic IntLd256,
7439 Intrinsic IntSt, Intrinsic IntSt256> {
7440 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7441 (ins VR128:$src1, f128mem:$src2),
7442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7443 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7444 VEX_4V;
7445 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7446 (ins VR256:$src1, f256mem:$src2),
7447 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7448 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7449 VEX_4V, VEX_L;
7450 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7451 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7452 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7453 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7454 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7455 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7456 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7457 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7458 }
7459
7460 let ExeDomain = SSEPackedSingle in
7461 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7462 int_x86_avx_maskload_ps,
7463 int_x86_avx_maskload_ps_256,
7464 int_x86_avx_maskstore_ps,
7465 int_x86_avx_maskstore_ps_256>;
7466 let ExeDomain = SSEPackedDouble in
7467 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7468 int_x86_avx_maskload_pd,
7469 int_x86_avx_maskload_pd_256,
7470 int_x86_avx_maskstore_pd,
7471 int_x86_avx_maskstore_pd_256>;
7472
7473 //===----------------------------------------------------------------------===//
7474 // VPERMIL - Permute Single and Double Floating-Point Values
7475 //
7476 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7477 RegisterClass RC, X86MemOperand x86memop_f,
7478 X86MemOperand x86memop_i, PatFrag i_frag,
7479 Intrinsic IntVar, ValueType vt> {
7480 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7481 (ins RC:$src1, RC:$src2),
7482 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7483 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7484 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7485 (ins RC:$src1, x86memop_i:$src2),
7486 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7487 [(set RC:$dst, (IntVar RC:$src1,
7488 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7489
7490 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7491 (ins RC:$src1, i8imm:$src2),
7492 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7493 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7494 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7495 (ins x86memop_f:$src1, i8imm:$src2),
7496 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7497 [(set RC:$dst,
7498 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7499 }
7500
7501 let ExeDomain = SSEPackedSingle in {
7502 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7503 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7504 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7505 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7506 }
7507 let ExeDomain = SSEPackedDouble in {
7508 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7509 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7510 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7511 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7512 }
7513
7514 let Predicates = [HasAVX] in {
7515 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7516 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7517 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7518 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7519 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7520 (i8 imm:$imm))),
7521 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7522 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7523 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7524
7525 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7526 (VPERMILPDri VR128:$src1, imm:$imm)>;
7527 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7528 (VPERMILPDmi addr:$src1, imm:$imm)>;
7529 }
7530
7531 //===----------------------------------------------------------------------===//
7532 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7533 //
7534 let ExeDomain = SSEPackedSingle in {
7535 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7536 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7537 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7538 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7539 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7540 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7541 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7542 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7543 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7544 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7545 }
7546
7547 let Predicates = [HasAVX] in {
7548 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7549 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7550 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7551 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7552 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7553 }
7554
7555 let Predicates = [HasAVX1Only] in {
7556 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7557 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7558 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7559 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7560 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7561 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7562 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7563 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7564
7565 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7566 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7567 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7568 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7569 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7570 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7571 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7572 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7573 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7574 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7575 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7576 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7577 }
7578
7579 //===----------------------------------------------------------------------===//
7580 // VZERO - Zero YMM registers
7581 //
7582 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7583 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7584 // Zero All YMM registers
7585 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7586 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7587
7588 // Zero Upper bits of YMM registers
7589 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7590 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7591 }
7592
7593 //===----------------------------------------------------------------------===//
7594 // Half precision conversion instructions
7595 //===----------------------------------------------------------------------===//
7596 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7597 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7598 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7599 [(set RC:$dst, (Int VR128:$src))]>,
7600 T8, OpSize, VEX;
7601 let neverHasSideEffects = 1, mayLoad = 1 in
7602 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7603 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7604 }
7605
7606 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7607 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7608 (ins RC:$src1, i32i8imm:$src2),
7609 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7610 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7611 TA, OpSize, VEX;
7612 let neverHasSideEffects = 1, mayStore = 1 in
7613 def mr : Ii8<0x1D, MRMDestMem, (outs),
7614 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7615 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7616 TA, OpSize, VEX;
7617 }
7618
7619 let Predicates = [HasAVX, HasF16C] in {
7620 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7621 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7622 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7623 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7624 }
7625
7626 //===----------------------------------------------------------------------===//
7627 // AVX2 Instructions
7628 //===----------------------------------------------------------------------===//
7629
7630 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7631 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7632 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7633 X86MemOperand x86memop> {
7634 let isCommutable = 1 in
7635 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7636 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7637 !strconcat(OpcodeStr,
7638 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7639 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7640 VEX_4V;
7641 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7642 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7643 !strconcat(OpcodeStr,
7644 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7645 [(set RC:$dst,
7646 (IntId RC:$src1,
7647 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7648 VEX_4V;
7649 }
7650
7651 let isCommutable = 0 in {
7652 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7653 VR128, memopv2i64, i128mem>;
7654 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7655 VR256, memopv4i64, i256mem>, VEX_L;
7656 }
7657
7658 //===----------------------------------------------------------------------===//
7659 // VPBROADCAST - Load from memory and broadcast to all elements of the
7660 // destination operand
7661 //
7662 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7663 X86MemOperand x86memop, PatFrag ld_frag,
7664 Intrinsic Int128, Intrinsic Int256> {
7665 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7666 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7667 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7668 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7669 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7670 [(set VR128:$dst,
7671 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7672 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7673 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7674 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7675 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7676 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7677 [(set VR256:$dst,
7678 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7679 VEX, VEX_L;
7680 }
7681
7682 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7683 int_x86_avx2_pbroadcastb_128,
7684 int_x86_avx2_pbroadcastb_256>;
7685 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7686 int_x86_avx2_pbroadcastw_128,
7687 int_x86_avx2_pbroadcastw_256>;
7688 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7689 int_x86_avx2_pbroadcastd_128,
7690 int_x86_avx2_pbroadcastd_256>;
7691 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7692 int_x86_avx2_pbroadcastq_128,
7693 int_x86_avx2_pbroadcastq_256>;
7694
7695 let Predicates = [HasAVX2] in {
7696 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7697 (VPBROADCASTBrm addr:$src)>;
7698 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7699 (VPBROADCASTBYrm addr:$src)>;
7700 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7701 (VPBROADCASTWrm addr:$src)>;
7702 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7703 (VPBROADCASTWYrm addr:$src)>;
7704 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7705 (VPBROADCASTDrm addr:$src)>;
7706 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7707 (VPBROADCASTDYrm addr:$src)>;
7708 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7709 (VPBROADCASTQrm addr:$src)>;
7710 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7711 (VPBROADCASTQYrm addr:$src)>;
7712
7713 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
7714 (VPBROADCASTBrr VR128:$src)>;
7715 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
7716 (VPBROADCASTBYrr VR128:$src)>;
7717 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
7718 (VPBROADCASTWrr VR128:$src)>;
7719 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
7720 (VPBROADCASTWYrr VR128:$src)>;
7721 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
7722 (VPBROADCASTDrr VR128:$src)>;
7723 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
7724 (VPBROADCASTDYrr VR128:$src)>;
7725 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
7726 (VPBROADCASTQrr VR128:$src)>;
7727 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
7728 (VPBROADCASTQYrr VR128:$src)>;
7729 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
7730 (VBROADCASTSSrr VR128:$src)>;
7731 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
7732 (VBROADCASTSSYrr VR128:$src)>;
7733 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
7734 (VPBROADCASTQrr VR128:$src)>;
7735 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
7736 (VBROADCASTSDYrr VR128:$src)>;
7737
7738 // Provide fallback in case the load node that is used in the patterns above
7739 // is used by additional users, which prevents the pattern selection.
7740 let AddedComplexity = 20 in {
7741 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7742 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7743 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7744 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
7745 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7746 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
7747
7748 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7749 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7750 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7751 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
7752 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7753 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
7754 }
7755 }
7756
7757 // AVX1 broadcast patterns
7758 let Predicates = [HasAVX1Only] in {
7759 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7760 (VBROADCASTSSYrm addr:$src)>;
7761 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7762 (VBROADCASTSDYrm addr:$src)>;
7763 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7764 (VBROADCASTSSrm addr:$src)>;
7765 }
7766
7767 let Predicates = [HasAVX] in {
7768 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7769 (VBROADCASTSSYrm addr:$src)>;
7770 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7771 (VBROADCASTSDYrm addr:$src)>;
7772 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7773 (VBROADCASTSSrm addr:$src)>;
7774
7775 // Provide fallback in case the load node that is used in the patterns above
7776 // is used by additional users, which prevents the pattern selection.
7777 let AddedComplexity = 20 in {
7778 // 128bit broadcasts:
7779 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7780 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
7781 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7782 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7783 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
7784 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
7785 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7786 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7787 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
7788 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
7789
7790 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7791 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
7792 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7793 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7794 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
7795 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
7796 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7797 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7798 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
7799 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
7800 }
7801 }
7802
7803 //===----------------------------------------------------------------------===//
7804 // VPERM - Permute instructions
7805 //
7806
7807 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7808 ValueType OpVT> {
7809 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7810 (ins VR256:$src1, VR256:$src2),
7811 !strconcat(OpcodeStr,
7812 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7813 [(set VR256:$dst,
7814 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
7815 VEX_4V, VEX_L;
7816 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7817 (ins VR256:$src1, i256mem:$src2),
7818 !strconcat(OpcodeStr,
7819 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7820 [(set VR256:$dst,
7821 (OpVT (X86VPermv VR256:$src1,
7822 (bitconvert (mem_frag addr:$src2)))))]>,
7823 VEX_4V, VEX_L;
7824 }
7825
7826 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7827 let ExeDomain = SSEPackedSingle in
7828 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7829
7830 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7831 ValueType OpVT> {
7832 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7833 (ins VR256:$src1, i8imm:$src2),
7834 !strconcat(OpcodeStr,
7835 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7836 [(set VR256:$dst,
7837 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
7838 VEX, VEX_L;
7839 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7840 (ins i256mem:$src1, i8imm:$src2),
7841 !strconcat(OpcodeStr,
7842 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7843 [(set VR256:$dst,
7844 (OpVT (X86VPermi (mem_frag addr:$src1),
7845 (i8 imm:$src2))))]>, VEX, VEX_L;
7846 }
7847
7848 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7849 let ExeDomain = SSEPackedDouble in
7850 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7851
7852 //===----------------------------------------------------------------------===//
7853 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7854 //
7855 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7856 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7857 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7858 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7859 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7860 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7861 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7862 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7863 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7864 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7865
7866 let Predicates = [HasAVX2] in {
7867 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7868 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7869 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7870 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7871 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7872 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7873
7874 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7875 (i8 imm:$imm))),
7876 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7877 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7878 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7879 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7880 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7881 (i8 imm:$imm))),
7882 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7883 }
7884
7885
7886 //===----------------------------------------------------------------------===//
7887 // VINSERTI128 - Insert packed integer values
7888 //
7889 let neverHasSideEffects = 1 in {
7890 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7891 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7892 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7893 []>, VEX_4V, VEX_L;
7894 let mayLoad = 1 in
7895 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7896 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7897 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7898 []>, VEX_4V, VEX_L;
7899 }
7900
7901 let Predicates = [HasAVX2] in {
7902 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7903 (iPTR imm)),
7904 (VINSERTI128rr VR256:$src1, VR128:$src2,
7905 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7906 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7907 (iPTR imm)),
7908 (VINSERTI128rr VR256:$src1, VR128:$src2,
7909 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7910 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7911 (iPTR imm)),
7912 (VINSERTI128rr VR256:$src1, VR128:$src2,
7913 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7914 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7915 (iPTR imm)),
7916 (VINSERTI128rr VR256:$src1, VR128:$src2,
7917 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7918
7919 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7920 (iPTR imm)),
7921 (VINSERTI128rm VR256:$src1, addr:$src2,
7922 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7923 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1),
7924 (bc_v4i32 (memopv2i64 addr:$src2)),
7925 (iPTR imm)),
7926 (VINSERTI128rm VR256:$src1, addr:$src2,
7927 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7928 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1),
7929 (bc_v16i8 (memopv2i64 addr:$src2)),
7930 (iPTR imm)),
7931 (VINSERTI128rm VR256:$src1, addr:$src2,
7932 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7933 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1),
7934 (bc_v8i16 (memopv2i64 addr:$src2)),
7935 (iPTR imm)),
7936 (VINSERTI128rm VR256:$src1, addr:$src2,
7937 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7938 }
7939
7940 //===----------------------------------------------------------------------===//
7941 // VEXTRACTI128 - Extract packed integer values
7942 //
7943 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7944 (ins VR256:$src1, i8imm:$src2),
7945 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7946 [(set VR128:$dst,
7947 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7948 VEX, VEX_L;
7949 let neverHasSideEffects = 1, mayStore = 1 in
7950 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7951 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7952 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7953 VEX, VEX_L;
7954
7955 let Predicates = [HasAVX2] in {
7956 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7957 (v2i64 (VEXTRACTI128rr
7958 (v4i64 VR256:$src1),
7959 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7960 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7961 (v4i32 (VEXTRACTI128rr
7962 (v8i32 VR256:$src1),
7963 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7964 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7965 (v8i16 (VEXTRACTI128rr
7966 (v16i16 VR256:$src1),
7967 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7968 def : Pat<(vextractf128_extract:$ext VR256:$src1, (iPTR imm)),
7969 (v16i8 (VEXTRACTI128rr
7970 (v32i8 VR256:$src1),
7971 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7972
7973 def : Pat<(alignedstore (v2i64 (vextractf128_extract:$ext (v4i64 VR256:$src1),
7974 (iPTR imm))), addr:$dst),
7975 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7976 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7977 def : Pat<(alignedstore (v4i32 (vextractf128_extract:$ext (v8i32 VR256:$src1),
7978 (iPTR imm))), addr:$dst),
7979 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7980 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7981 def : Pat<(alignedstore (v8i16 (vextractf128_extract:$ext (v16i16 VR256:$src1),
7982 (iPTR imm))), addr:$dst),
7983 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7984 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7985 def : Pat<(alignedstore (v16i8 (vextractf128_extract:$ext (v32i8 VR256:$src1),
7986 (iPTR imm))), addr:$dst),
7987 (VEXTRACTI128mr addr:$dst, VR256:$src1,
7988 (EXTRACT_get_vextractf128_imm VR128:$ext))>;
7989 }
7990
7991 //===----------------------------------------------------------------------===//
7992 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7993 //
7994 multiclass avx2_pmovmask<string OpcodeStr,
7995 Intrinsic IntLd128, Intrinsic IntLd256,
7996 Intrinsic IntSt128, Intrinsic IntSt256> {
7997 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7998 (ins VR128:$src1, i128mem:$src2),
7999 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8000 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8001 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8002 (ins VR256:$src1, i256mem:$src2),
8003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8004 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8005 VEX_4V, VEX_L;
8006 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8007 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8009 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8010 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8011 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8012 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8013 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8014 }
8015
8016 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8017 int_x86_avx2_maskload_d,
8018 int_x86_avx2_maskload_d_256,
8019 int_x86_avx2_maskstore_d,
8020 int_x86_avx2_maskstore_d_256>;
8021 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8022 int_x86_avx2_maskload_q,
8023 int_x86_avx2_maskload_q_256,
8024 int_x86_avx2_maskstore_q,
8025 int_x86_avx2_maskstore_q_256>, VEX_W;
8026
8027
8028 //===----------------------------------------------------------------------===//
8029 // Variable Bit Shifts
8030 //
8031 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8032 ValueType vt128, ValueType vt256> {
8033 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8034 (ins VR128:$src1, VR128:$src2),
8035 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8036 [(set VR128:$dst,
8037 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8038 VEX_4V;
8039 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8040 (ins VR128:$src1, i128mem:$src2),
8041 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8042 [(set VR128:$dst,
8043 (vt128 (OpNode VR128:$src1,
8044 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8045 VEX_4V;
8046 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8047 (ins VR256:$src1, VR256:$src2),
8048 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8049 [(set VR256:$dst,
8050 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8051 VEX_4V, VEX_L;
8052 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8053 (ins VR256:$src1, i256mem:$src2),
8054 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8055 [(set VR256:$dst,
8056 (vt256 (OpNode VR256:$src1,
8057 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8058 VEX_4V, VEX_L;
8059 }
8060
8061 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8062 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8063 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8064 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8065 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8066
8067 //===----------------------------------------------------------------------===//
8068 // VGATHER - GATHER Operations
8069 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8070 X86MemOperand memop128, X86MemOperand memop256> {
8071 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8072 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8073 !strconcat(OpcodeStr,
8074 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8075 []>, VEX_4VOp3;
8076 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8077 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8078 !strconcat(OpcodeStr,
8079 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8080 []>, VEX_4VOp3, VEX_L;
8081 }
8082
8083 let mayLoad = 1, Constraints = "$src1 = $dst, $mask = $mask_wb" in {
8084 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8085 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8086 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8087 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8088 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8089 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8090 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8091 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8092 }
backport for Debian buster