2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 #include "hw/registerfields.h"
29 #include "tcg/tcg-gvec-desc.h"
32 /* register banks for CPU modes */
42 static inline bool excp_is_internal(int excp
)
44 /* Return true if this exception number represents a QEMU-internal
45 * exception that will not be passed to the guest.
47 return excp
== EXCP_INTERRUPT
50 || excp
== EXCP_HALTED
51 || excp
== EXCP_EXCEPTION_EXIT
52 || excp
== EXCP_KERNEL_TRAP
53 || excp
== EXCP_SEMIHOST
;
56 /* Scale factor for generic timers, ie number of ns per tick.
57 * This gives a 62.5MHz timer.
59 #define GTIMER_SCALE 16
61 /* Bit definitions for the v7M CONTROL register */
62 FIELD(V7M_CONTROL
, NPRIV
, 0, 1)
63 FIELD(V7M_CONTROL
, SPSEL
, 1, 1)
64 FIELD(V7M_CONTROL
, FPCA
, 2, 1)
65 FIELD(V7M_CONTROL
, SFPA
, 3, 1)
67 /* Bit definitions for v7M exception return payload */
68 FIELD(V7M_EXCRET
, ES
, 0, 1)
69 FIELD(V7M_EXCRET
, RES0
, 1, 1)
70 FIELD(V7M_EXCRET
, SPSEL
, 2, 1)
71 FIELD(V7M_EXCRET
, MODE
, 3, 1)
72 FIELD(V7M_EXCRET
, FTYPE
, 4, 1)
73 FIELD(V7M_EXCRET
, DCRS
, 5, 1)
74 FIELD(V7M_EXCRET
, S
, 6, 1)
75 FIELD(V7M_EXCRET
, RES1
, 7, 25) /* including the must-be-1 prefix */
77 /* Minimum value which is a magic number for exception return */
78 #define EXC_RETURN_MIN_MAGIC 0xff000000
79 /* Minimum number which is a magic number for function or exception return
80 * when using v8M security extension
82 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
84 /* Bit definitions for DBGWCRn and DBGWCRn_EL1 */
85 FIELD(DBGWCR
, E
, 0, 1)
86 FIELD(DBGWCR
, PAC
, 1, 2)
87 FIELD(DBGWCR
, LSC
, 3, 2)
88 FIELD(DBGWCR
, BAS
, 5, 8)
89 FIELD(DBGWCR
, HMC
, 13, 1)
90 FIELD(DBGWCR
, SSC
, 14, 2)
91 FIELD(DBGWCR
, LBN
, 16, 4)
92 FIELD(DBGWCR
, WT
, 20, 1)
93 FIELD(DBGWCR
, MASK
, 24, 5)
94 FIELD(DBGWCR
, SSCE
, 29, 1)
96 /* We use a few fake FSR values for internal purposes in M profile.
97 * M profile cores don't have A/R format FSRs, but currently our
98 * get_phys_addr() code assumes A/R profile and reports failures via
99 * an A/R format FSR value. We then translate that into the proper
100 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
101 * Mostly the FSR values we use for this are those defined for v7PMSA,
102 * since we share some of that codepath. A few kinds of fault are
103 * only for M profile and have no A/R equivalent, though, so we have
104 * to pick a value from the reserved range (which we never otherwise
105 * generate) to use for these.
106 * These values will never be visible to the guest.
108 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
109 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
112 * raise_exception: Raise the specified exception.
113 * Raise a guest exception with the specified value, syndrome register
114 * and target exception level. This should be called from helper functions,
115 * and never returns because we will longjump back up to the CPU main loop.
117 G_NORETURN
void raise_exception(CPUARMState
*env
, uint32_t excp
,
118 uint32_t syndrome
, uint32_t target_el
);
121 * Similarly, but also use unwinding to restore cpu state.
123 G_NORETURN
void raise_exception_ra(CPUARMState
*env
, uint32_t excp
,
124 uint32_t syndrome
, uint32_t target_el
,
128 * For AArch64, map a given EL to an index in the banked_spsr array.
129 * Note that this mapping and the AArch32 mapping defined in bank_number()
130 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
131 * mandated mapping between each other.
133 static inline unsigned int aarch64_banked_spsr_index(unsigned int el
)
135 static const unsigned int map
[4] = {
136 [1] = BANK_SVC
, /* EL1. */
137 [2] = BANK_HYP
, /* EL2. */
138 [3] = BANK_MON
, /* EL3. */
140 assert(el
>= 1 && el
<= 3);
144 /* Map CPU modes onto saved register banks. */
145 static inline int bank_number(int mode
)
148 case ARM_CPU_MODE_USR
:
149 case ARM_CPU_MODE_SYS
:
151 case ARM_CPU_MODE_SVC
:
153 case ARM_CPU_MODE_ABT
:
155 case ARM_CPU_MODE_UND
:
157 case ARM_CPU_MODE_IRQ
:
159 case ARM_CPU_MODE_FIQ
:
161 case ARM_CPU_MODE_HYP
:
163 case ARM_CPU_MODE_MON
:
166 g_assert_not_reached();
170 * r14_bank_number: Map CPU mode onto register bank for r14
172 * Given an AArch32 CPU mode, return the index into the saved register
173 * banks to use for the R14 (LR) in that mode. This is the same as
174 * bank_number(), except for the special case of Hyp mode, where
175 * R14 is shared with USR and SYS, unlike its R13 and SPSR.
176 * This should be used as the index into env->banked_r14[], and
177 * bank_number() used for the index into env->banked_r13[] and
178 * env->banked_spsr[].
180 static inline int r14_bank_number(int mode
)
182 return (mode
== ARM_CPU_MODE_HYP
) ? BANK_USRSYS
: bank_number(mode
);
185 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
);
186 void arm_translate_init(void);
188 void arm_restore_state_to_opc(CPUState
*cs
,
189 const TranslationBlock
*tb
,
190 const uint64_t *data
);
193 void arm_cpu_synchronize_from_tb(CPUState
*cs
, const TranslationBlock
*tb
);
194 #endif /* CONFIG_TCG */
196 enum arm_fprounding
{
205 int arm_rmode_to_sf(int rmode
);
207 static inline void aarch64_save_sp(CPUARMState
*env
, int el
)
209 if (env
->pstate
& PSTATE_SP
) {
210 env
->sp_el
[el
] = env
->xregs
[31];
212 env
->sp_el
[0] = env
->xregs
[31];
216 static inline void aarch64_restore_sp(CPUARMState
*env
, int el
)
218 if (env
->pstate
& PSTATE_SP
) {
219 env
->xregs
[31] = env
->sp_el
[el
];
221 env
->xregs
[31] = env
->sp_el
[0];
225 static inline void update_spsel(CPUARMState
*env
, uint32_t imm
)
227 unsigned int cur_el
= arm_current_el(env
);
228 /* Update PSTATE SPSel bit; this requires us to update the
229 * working stack pointer in xregs[31].
231 if (!((imm
^ env
->pstate
) & PSTATE_SP
)) {
234 aarch64_save_sp(env
, cur_el
);
235 env
->pstate
= deposit32(env
->pstate
, 0, 1, imm
);
237 /* We rely on illegal updates to SPsel from EL0 to get trapped
238 * at translation time.
240 assert(cur_el
>= 1 && cur_el
<= 3);
241 aarch64_restore_sp(env
, cur_el
);
248 * Returns the implementation defined bit-width of physical addresses.
249 * The ARMv8 reference manuals refer to this as PAMax().
251 unsigned int arm_pamax(ARMCPU
*cpu
);
253 /* Return true if extended addresses are enabled.
254 * This is always the case if our translation regime is 64 bit,
255 * but depends on TTBCR.EAE for 32 bit.
257 static inline bool extended_addresses_enabled(CPUARMState
*env
)
259 uint64_t tcr
= env
->cp15
.tcr_el
[arm_is_secure(env
) ? 3 : 1];
260 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
261 arm_feature(env
, ARM_FEATURE_V8
)) {
264 return arm_el_is_aa64(env
, 1) ||
265 (arm_feature(env
, ARM_FEATURE_LPAE
) && (tcr
& TTBCR_EAE
));
268 /* Update a QEMU watchpoint based on the information the guest has set in the
269 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
271 void hw_watchpoint_update(ARMCPU
*cpu
, int n
);
272 /* Update the QEMU watchpoints for every guest watchpoint. This does a
273 * complete delete-and-reinstate of the QEMU watchpoint list and so is
274 * suitable for use after migration or on reset.
276 void hw_watchpoint_update_all(ARMCPU
*cpu
);
277 /* Update a QEMU breakpoint based on the information the guest has set in the
278 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
280 void hw_breakpoint_update(ARMCPU
*cpu
, int n
);
281 /* Update the QEMU breakpoints for every guest breakpoint. This does a
282 * complete delete-and-reinstate of the QEMU breakpoint list and so is
283 * suitable for use after migration or on reset.
285 void hw_breakpoint_update_all(ARMCPU
*cpu
);
287 /* Callback function for checking if a breakpoint should trigger. */
288 bool arm_debug_check_breakpoint(CPUState
*cs
);
290 /* Callback function for checking if a watchpoint should trigger. */
291 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
);
293 /* Adjust addresses (in BE32 mode) before testing against watchpoint
296 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
);
298 /* Callback function for when a watchpoint or breakpoint triggers. */
299 void arm_debug_excp_handler(CPUState
*cs
);
301 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
302 static inline bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
)
306 static inline void arm_handle_psci_call(ARMCPU
*cpu
)
308 g_assert_not_reached();
311 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
312 bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
);
313 /* Actually handle a PSCI call */
314 void arm_handle_psci_call(ARMCPU
*cpu
);
318 * arm_clear_exclusive: clear the exclusive monitor
320 * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
322 static inline void arm_clear_exclusive(CPUARMState
*env
)
324 env
->exclusive_addr
= -1;
328 * ARMFaultType: type of an ARM MMU fault
329 * This corresponds to the v8A pseudocode's Fault enumeration,
330 * with extensions for QEMU internal conditions.
332 typedef enum ARMFaultType
{
339 ARMFault_Translation
,
340 ARMFault_AddressSize
,
341 ARMFault_SyncExternal
,
342 ARMFault_SyncExternalOnWalk
,
344 ARMFault_SyncParityOnWalk
,
345 ARMFault_AsyncParity
,
346 ARMFault_AsyncExternal
,
348 ARMFault_TLBConflict
,
349 ARMFault_UnsuppAtomicUpdate
,
352 ARMFault_ICacheMaint
,
353 ARMFault_QEMU_NSCExec
, /* v8M: NS executing in S&NSC memory */
354 ARMFault_QEMU_SFault
, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
358 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
359 * @type: Type of fault
360 * @level: Table walk level (for translation, access flag and permission faults)
361 * @domain: Domain of the fault address (for non-LPAE CPUs only)
362 * @s2addr: Address that caused a fault at stage 2
363 * @stage2: True if we faulted at stage 2
364 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
365 * @s1ns: True if we faulted on a non-secure IPA while in secure state
366 * @ea: True if we should set the EA (external abort type) bit in syndrome
368 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo
;
369 struct ARMMMUFaultInfo
{
381 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
382 * Compare pseudocode EncodeSDFSC(), though unlike that function
383 * we set up a whole FSR-format code including domain field and
384 * putting the high bit of the FSC into bit 10.
386 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo
*fi
)
393 case ARMFault_AccessFlag
:
394 fsc
= fi
->level
== 1 ? 0x3 : 0x6;
396 case ARMFault_Alignment
:
399 case ARMFault_Permission
:
400 fsc
= fi
->level
== 1 ? 0xd : 0xf;
402 case ARMFault_Domain
:
403 fsc
= fi
->level
== 1 ? 0x9 : 0xb;
405 case ARMFault_Translation
:
406 fsc
= fi
->level
== 1 ? 0x5 : 0x7;
408 case ARMFault_SyncExternal
:
409 fsc
= 0x8 | (fi
->ea
<< 12);
411 case ARMFault_SyncExternalOnWalk
:
412 fsc
= fi
->level
== 1 ? 0xc : 0xe;
413 fsc
|= (fi
->ea
<< 12);
415 case ARMFault_SyncParity
:
418 case ARMFault_SyncParityOnWalk
:
419 fsc
= fi
->level
== 1 ? 0x40c : 0x40e;
421 case ARMFault_AsyncParity
:
424 case ARMFault_AsyncExternal
:
425 fsc
= 0x406 | (fi
->ea
<< 12);
430 case ARMFault_TLBConflict
:
433 case ARMFault_Lockdown
:
436 case ARMFault_Exclusive
:
439 case ARMFault_ICacheMaint
:
442 case ARMFault_Background
:
445 case ARMFault_QEMU_NSCExec
:
446 fsc
= M_FAKE_FSR_NSC_EXEC
;
448 case ARMFault_QEMU_SFault
:
449 fsc
= M_FAKE_FSR_SFAULT
;
452 /* Other faults can't occur in a context that requires a
453 * short-format status code.
455 g_assert_not_reached();
458 fsc
|= (fi
->domain
<< 4);
463 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
464 * Compare pseudocode EncodeLDFSC(), though unlike that function
465 * we fill in also the LPAE bit 9 of a DFSR format.
467 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo
*fi
)
474 case ARMFault_AddressSize
:
475 assert(fi
->level
>= -1 && fi
->level
<= 3);
482 case ARMFault_AccessFlag
:
483 assert(fi
->level
>= 0 && fi
->level
<= 3);
484 fsc
= 0b001000 | fi
->level
;
486 case ARMFault_Permission
:
487 assert(fi
->level
>= 0 && fi
->level
<= 3);
488 fsc
= 0b001100 | fi
->level
;
490 case ARMFault_Translation
:
491 assert(fi
->level
>= -1 && fi
->level
<= 3);
495 fsc
= 0b000100 | fi
->level
;
498 case ARMFault_SyncExternal
:
499 fsc
= 0x10 | (fi
->ea
<< 12);
501 case ARMFault_SyncExternalOnWalk
:
502 assert(fi
->level
>= -1 && fi
->level
<= 3);
506 fsc
= 0b010100 | fi
->level
;
510 case ARMFault_SyncParity
:
513 case ARMFault_SyncParityOnWalk
:
514 assert(fi
->level
>= -1 && fi
->level
<= 3);
518 fsc
= 0b011100 | fi
->level
;
521 case ARMFault_AsyncParity
:
524 case ARMFault_AsyncExternal
:
525 fsc
= 0x11 | (fi
->ea
<< 12);
527 case ARMFault_Alignment
:
533 case ARMFault_TLBConflict
:
536 case ARMFault_UnsuppAtomicUpdate
:
539 case ARMFault_Lockdown
:
542 case ARMFault_Exclusive
:
546 /* Other faults can't occur in a context that requires a
547 * long-format status code.
549 g_assert_not_reached();
556 static inline bool arm_extabort_type(MemTxResult result
)
558 /* The EA bit in syndromes and fault status registers is an
559 * IMPDEF classification of external aborts. ARM implementations
560 * usually use this to indicate AXI bus Decode error (0) or
561 * Slave error (1); in QEMU we follow that.
563 return result
!= MEMTX_DECODE_ERROR
;
566 #ifdef CONFIG_USER_ONLY
567 void arm_cpu_record_sigsegv(CPUState
*cpu
, vaddr addr
,
568 MMUAccessType access_type
,
569 bool maperr
, uintptr_t ra
);
570 void arm_cpu_record_sigbus(CPUState
*cpu
, vaddr addr
,
571 MMUAccessType access_type
, uintptr_t ra
);
573 bool arm_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
574 MMUAccessType access_type
, int mmu_idx
,
575 bool probe
, uintptr_t retaddr
);
578 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx
)
580 return mmu_idx
& ARM_MMU_IDX_COREIDX_MASK
;
583 static inline ARMMMUIdx
core_to_arm_mmu_idx(CPUARMState
*env
, int mmu_idx
)
585 if (arm_feature(env
, ARM_FEATURE_M
)) {
586 return mmu_idx
| ARM_MMU_IDX_M
;
588 return mmu_idx
| ARM_MMU_IDX_A
;
592 static inline ARMMMUIdx
core_to_aa64_mmu_idx(int mmu_idx
)
594 /* AArch64 is always a-profile. */
595 return mmu_idx
| ARM_MMU_IDX_A
;
598 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
);
600 /* Return the MMU index for a v7M CPU in the specified security state */
601 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
);
603 /* Return true if the translation regime is using LPAE format page tables */
604 bool regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
607 * Return true if the stage 1 translation regime is using LPAE
610 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
612 /* Raise a data fault alignment exception for the specified virtual address */
613 G_NORETURN
void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
614 MMUAccessType access_type
,
615 int mmu_idx
, uintptr_t retaddr
);
617 /* arm_cpu_do_transaction_failed: handle a memory system error response
618 * (eg "no device/memory present at address") by raising an external abort
621 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
622 vaddr addr
, unsigned size
,
623 MMUAccessType access_type
,
624 int mmu_idx
, MemTxAttrs attrs
,
625 MemTxResult response
, uintptr_t retaddr
);
627 /* Call any registered EL change hooks */
628 static inline void arm_call_pre_el_change_hook(ARMCPU
*cpu
)
630 ARMELChangeHook
*hook
, *next
;
631 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
632 hook
->hook(cpu
, hook
->opaque
);
635 static inline void arm_call_el_change_hook(ARMCPU
*cpu
)
637 ARMELChangeHook
*hook
, *next
;
638 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
639 hook
->hook(cpu
, hook
->opaque
);
643 /* Return true if this address translation regime has two ranges. */
644 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx
)
647 case ARMMMUIdx_Stage1_E0
:
648 case ARMMMUIdx_Stage1_E1
:
649 case ARMMMUIdx_Stage1_E1_PAN
:
650 case ARMMMUIdx_E10_0
:
651 case ARMMMUIdx_E10_1
:
652 case ARMMMUIdx_E10_1_PAN
:
653 case ARMMMUIdx_E20_0
:
654 case ARMMMUIdx_E20_2
:
655 case ARMMMUIdx_E20_2_PAN
:
662 static inline bool regime_is_pan(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
665 case ARMMMUIdx_Stage1_E1_PAN
:
666 case ARMMMUIdx_E10_1_PAN
:
667 case ARMMMUIdx_E20_2_PAN
:
674 static inline bool regime_is_stage2(ARMMMUIdx mmu_idx
)
676 return mmu_idx
== ARMMMUIdx_Stage2
|| mmu_idx
== ARMMMUIdx_Stage2_S
;
679 /* Return the exception level which controls this address translation regime */
680 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
683 case ARMMMUIdx_E20_0
:
684 case ARMMMUIdx_E20_2
:
685 case ARMMMUIdx_E20_2_PAN
:
686 case ARMMMUIdx_Stage2
:
687 case ARMMMUIdx_Stage2_S
:
692 case ARMMMUIdx_E10_0
:
693 case ARMMMUIdx_Stage1_E0
:
694 return arm_el_is_aa64(env
, 3) || !arm_is_secure_below_el3(env
) ? 1 : 3;
695 case ARMMMUIdx_Stage1_E1
:
696 case ARMMMUIdx_Stage1_E1_PAN
:
697 case ARMMMUIdx_E10_1
:
698 case ARMMMUIdx_E10_1_PAN
:
699 case ARMMMUIdx_MPrivNegPri
:
700 case ARMMMUIdx_MUserNegPri
:
701 case ARMMMUIdx_MPriv
:
702 case ARMMMUIdx_MUser
:
703 case ARMMMUIdx_MSPrivNegPri
:
704 case ARMMMUIdx_MSUserNegPri
:
705 case ARMMMUIdx_MSPriv
:
706 case ARMMMUIdx_MSUser
:
709 g_assert_not_reached();
713 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
716 case ARMMMUIdx_E20_0
:
717 case ARMMMUIdx_Stage1_E0
:
718 case ARMMMUIdx_MUser
:
719 case ARMMMUIdx_MSUser
:
720 case ARMMMUIdx_MUserNegPri
:
721 case ARMMMUIdx_MSUserNegPri
:
725 case ARMMMUIdx_E10_0
:
726 case ARMMMUIdx_E10_1
:
727 case ARMMMUIdx_E10_1_PAN
:
728 g_assert_not_reached();
732 /* Return the SCTLR value which controls this address translation regime */
733 static inline uint64_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
735 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
739 * These are the fields in VTCR_EL2 which affect both the Secure stage 2
740 * and the Non-Secure stage 2 translation regimes (and hence which are
741 * not present in VSTCR_EL2).
743 #define VTCR_SHARED_FIELD_MASK \
744 (R_VTCR_IRGN0_MASK | R_VTCR_ORGN0_MASK | R_VTCR_SH0_MASK | \
745 R_VTCR_PS_MASK | R_VTCR_VS_MASK | R_VTCR_HA_MASK | R_VTCR_HD_MASK | \
748 /* Return the value of the TCR controlling this translation regime */
749 static inline uint64_t regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
751 if (mmu_idx
== ARMMMUIdx_Stage2
) {
752 return env
->cp15
.vtcr_el2
;
754 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
756 * Secure stage 2 shares fields from VTCR_EL2. We merge those
757 * in with the VSTCR_EL2 value to synthesize a single VTCR_EL2 format
758 * value so the callers don't need to special case this.
760 * If a future architecture change defines bits in VSTCR_EL2 that
761 * overlap with these VTCR_EL2 fields we may need to revisit this.
763 uint64_t v
= env
->cp15
.vstcr_el2
& ~VTCR_SHARED_FIELD_MASK
;
764 v
|= env
->cp15
.vtcr_el2
& VTCR_SHARED_FIELD_MASK
;
767 return env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
771 * arm_num_brps: Return number of implemented breakpoints.
772 * Note that the ID register BRPS field is "number of bps - 1",
773 * and we return the actual number of breakpoints.
775 static inline int arm_num_brps(ARMCPU
*cpu
)
777 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
778 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, BRPS
) + 1;
780 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, BRPS
) + 1;
785 * arm_num_wrps: Return number of implemented watchpoints.
786 * Note that the ID register WRPS field is "number of wps - 1",
787 * and we return the actual number of watchpoints.
789 static inline int arm_num_wrps(ARMCPU
*cpu
)
791 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
792 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, WRPS
) + 1;
794 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, WRPS
) + 1;
799 * arm_num_ctx_cmps: Return number of implemented context comparators.
800 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
801 * and we return the actual number of comparators.
803 static inline int arm_num_ctx_cmps(ARMCPU
*cpu
)
805 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
806 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, CTX_CMPS
) + 1;
808 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, CTX_CMPS
) + 1;
813 * v7m_using_psp: Return true if using process stack pointer
814 * Return true if the CPU is currently using the process stack
815 * pointer, or false if it is using the main stack pointer.
817 static inline bool v7m_using_psp(CPUARMState
*env
)
819 /* Handler mode always uses the main stack; for thread mode
820 * the CONTROL.SPSEL bit determines the answer.
821 * Note that in v7M it is not possible to be in Handler mode with
822 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
824 return !arm_v7m_is_handler_mode(env
) &&
825 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
829 * v7m_sp_limit: Return SP limit for current CPU state
830 * Return the SP limit value for the current CPU security state
833 static inline uint32_t v7m_sp_limit(CPUARMState
*env
)
835 if (v7m_using_psp(env
)) {
836 return env
->v7m
.psplim
[env
->v7m
.secure
];
838 return env
->v7m
.msplim
[env
->v7m
.secure
];
844 * Return true if the v7M CPACR permits access to the FPU for the specified
845 * security state and privilege level.
847 static inline bool v7m_cpacr_pass(CPUARMState
*env
,
848 bool is_secure
, bool is_priv
)
850 switch (extract32(env
->v7m
.cpacr
[is_secure
], 20, 2)) {
852 case 2: /* UNPREDICTABLE: we treat like 0 */
859 g_assert_not_reached();
864 * aarch32_mode_name(): Return name of the AArch32 CPU mode
865 * @psr: Program Status Register indicating CPU mode
867 * Returns, for debug logging purposes, a printable representation
868 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
869 * the low bits of the specified PSR.
871 static inline const char *aarch32_mode_name(uint32_t psr
)
873 static const char cpu_mode_names
[16][4] = {
874 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
875 "???", "???", "hyp", "und", "???", "???", "???", "sys"
878 return cpu_mode_names
[psr
& 0xf];
882 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request
884 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following
885 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit.
886 * Must be called with the iothread lock held.
888 void arm_cpu_update_virq(ARMCPU
*cpu
);
891 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request
893 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following
894 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit.
895 * Must be called with the iothread lock held.
897 void arm_cpu_update_vfiq(ARMCPU
*cpu
);
900 * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
902 * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
903 * following a change to the HCR_EL2.VSE bit.
905 void arm_cpu_update_vserr(ARMCPU
*cpu
);
909 * @env: The cpu environment
910 * @el: The EL to use.
912 * Return the full ARMMMUIdx for the translation regime for EL.
914 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
);
918 * @env: The cpu environment
920 * Return the full ARMMMUIdx for the current translation regime.
922 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
);
925 * arm_stage1_mmu_idx:
926 * @env: The cpu environment
928 * Return the ARMMMUIdx for the stage1 traversal for the current regime.
930 #ifdef CONFIG_USER_ONLY
931 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
933 return ARMMMUIdx_Stage1_E0
;
935 static inline ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
937 return ARMMMUIdx_Stage1_E0
;
940 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
);
941 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
);
945 * arm_mmu_idx_is_stage1_of_2:
946 * @mmu_idx: The ARMMMUIdx to test
948 * Return true if @mmu_idx is a NOTLB mmu_idx that is the
949 * first stage of a two stage regime.
951 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx
)
954 case ARMMMUIdx_Stage1_E0
:
955 case ARMMMUIdx_Stage1_E1
:
956 case ARMMMUIdx_Stage1_E1_PAN
:
963 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features
,
964 const ARMISARegisters
*id
)
966 uint32_t valid
= CPSR_M
| CPSR_AIF
| CPSR_IL
| CPSR_NZCV
;
968 if ((features
>> ARM_FEATURE_V4T
) & 1) {
971 if ((features
>> ARM_FEATURE_V5
) & 1) {
972 valid
|= CPSR_Q
; /* V5TE in reality*/
974 if ((features
>> ARM_FEATURE_V6
) & 1) {
975 valid
|= CPSR_E
| CPSR_GE
;
977 if ((features
>> ARM_FEATURE_THUMB2
) & 1) {
980 if (isar_feature_aa32_jazelle(id
)) {
983 if (isar_feature_aa32_pan(id
)) {
986 if (isar_feature_aa32_dit(id
)) {
989 if (isar_feature_aa32_ssbs(id
)) {
996 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters
*id
)
1000 valid
= PSTATE_M
| PSTATE_DAIF
| PSTATE_IL
| PSTATE_SS
| PSTATE_NZCV
;
1001 if (isar_feature_aa64_bti(id
)) {
1002 valid
|= PSTATE_BTYPE
;
1004 if (isar_feature_aa64_pan(id
)) {
1005 valid
|= PSTATE_PAN
;
1007 if (isar_feature_aa64_uao(id
)) {
1008 valid
|= PSTATE_UAO
;
1010 if (isar_feature_aa64_dit(id
)) {
1011 valid
|= PSTATE_DIT
;
1013 if (isar_feature_aa64_ssbs(id
)) {
1014 valid
|= PSTATE_SSBS
;
1016 if (isar_feature_aa64_mte(id
)) {
1017 valid
|= PSTATE_TCO
;
1023 /* Granule size (i.e. page size) */
1024 typedef enum ARMGranuleSize
{
1025 /* Same order as TG0 encoding */
1033 * arm_granule_bits: Return address size of the granule in bits
1035 * Return the address size of the granule in bits. This corresponds
1036 * to the pseudocode TGxGranuleBits().
1038 static inline int arm_granule_bits(ARMGranuleSize gran
)
1048 g_assert_not_reached();
1053 * Parameters of a given virtual address, as extracted from the
1054 * translation control register (TCR) for a given regime.
1056 typedef struct ARMVAParameters
{
1060 unsigned select
: 1;
1064 bool tsz_oob
: 1; /* tsz has been clamped to legal range */
1068 ARMGranuleSize gran
: 2;
1071 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
1072 ARMMMUIdx mmu_idx
, bool data
);
1074 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
);
1075 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
);
1077 /* Determine if allocation tags are available. */
1078 static inline bool allocation_tag_access_enabled(CPUARMState
*env
, int el
,
1082 && arm_feature(env
, ARM_FEATURE_EL3
)
1083 && !(env
->cp15
.scr_el3
& SCR_ATA
)) {
1086 if (el
< 2 && arm_is_el2_enabled(env
)) {
1087 uint64_t hcr
= arm_hcr_el2_eff(env
);
1088 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
1092 sctlr
&= (el
== 0 ? SCTLR_ATA0
: SCTLR_ATA
);
1096 #ifndef CONFIG_USER_ONLY
1098 /* Security attributes for an address, as returned by v8m_security_lookup. */
1099 typedef struct V8M_SAttributes
{
1100 bool subpage
; /* true if these attrs don't cover the whole TARGET_PAGE */
1109 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
1110 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1111 bool secure
, V8M_SAttributes
*sattrs
);
1113 /* Cacheability and shareability attributes for a memory access */
1114 typedef struct ARMCacheAttrs
{
1116 * If is_s2_format is true, attrs is the S2 descriptor bits [5:2]
1117 * Otherwise, attrs is the same as the MAIR_EL1 8-bit format
1119 unsigned int attrs
:8;
1120 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
1121 bool is_s2_format
:1;
1122 bool guarded
:1; /* guarded bit of the v8-64 PTE */
1125 /* Fields that are valid upon success. */
1126 typedef struct GetPhysAddrResult
{
1128 ARMCacheAttrs cacheattrs
;
1129 } GetPhysAddrResult
;
1132 * get_phys_addr_with_secure: get the physical address for a virtual address
1134 * @address: virtual address to get physical address for
1135 * @access_type: 0 for read, 1 for write, 2 for execute
1136 * @mmu_idx: MMU index indicating required translation regime
1137 * @is_secure: security state for the access
1138 * @result: set on translation success.
1139 * @fi: set to fault info if the translation fails
1141 * Find the physical address corresponding to the given virtual address,
1142 * by doing a translation table walk on MMU based systems or using the
1143 * MPU state on MPU based systems.
1145 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
1146 * prot and page_size may not be filled in, and the populated fsr value provides
1147 * information on why the translation aborted, in the format of a
1148 * DFSR/IFSR fault register, with the following caveats:
1149 * * we honour the short vs long DFSR format differences.
1150 * * the WnR bit is never set (the caller must do this).
1151 * * for PSMAv5 based systems we don't bother to return a full FSR format
1154 bool get_phys_addr_with_secure(CPUARMState
*env
, target_ulong address
,
1155 MMUAccessType access_type
,
1156 ARMMMUIdx mmu_idx
, bool is_secure
,
1157 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1158 __attribute__((nonnull
));
1161 * get_phys_addr: get the physical address for a virtual address
1163 * @address: virtual address to get physical address for
1164 * @access_type: 0 for read, 1 for write, 2 for execute
1165 * @mmu_idx: MMU index indicating required translation regime
1166 * @result: set on translation success.
1167 * @fi: set to fault info if the translation fails
1169 * Similarly, but use the security regime of @mmu_idx.
1171 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
1172 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1173 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1174 __attribute__((nonnull
));
1176 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
1177 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1178 bool is_secure
, GetPhysAddrResult
*result
,
1179 ARMMMUFaultInfo
*fi
, uint32_t *mregion
);
1181 void arm_log_exception(CPUState
*cs
);
1183 #endif /* !CONFIG_USER_ONLY */
1186 * The log2 of the words in the tag block, for GMID_EL1.BS.
1187 * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
1189 #define GMID_EL1_BS 6
1192 * SVE predicates are 1/8 the size of SVE vectors, and cannot use
1193 * the same simd_desc() encoding due to restrictions on size.
1194 * Use these instead.
1196 FIELD(PREDDESC
, OPRSZ
, 0, 6)
1197 FIELD(PREDDESC
, ESZ
, 6, 2)
1198 FIELD(PREDDESC
, DATA
, 8, 24)
1201 * The SVE simd_data field, for memory ops, contains either
1202 * rd (5 bits) or a shift count (2 bits).
1204 #define SVE_MTEDESC_SHIFT 5
1206 /* Bits within a descriptor passed to the helper_mte_check* functions. */
1207 FIELD(MTEDESC
, MIDX
, 0, 4)
1208 FIELD(MTEDESC
, TBI
, 4, 2)
1209 FIELD(MTEDESC
, TCMA
, 6, 2)
1210 FIELD(MTEDESC
, WRITE
, 8, 1)
1211 FIELD(MTEDESC
, SIZEM1
, 9, SIMD_DATA_BITS
- 9) /* size - 1 */
1213 bool mte_probe(CPUARMState
*env
, uint32_t desc
, uint64_t ptr
);
1214 uint64_t mte_check(CPUARMState
*env
, uint32_t desc
, uint64_t ptr
, uintptr_t ra
);
1216 static inline int allocation_tag_from_addr(uint64_t ptr
)
1218 return extract64(ptr
, 56, 4);
1221 static inline uint64_t address_with_allocation_tag(uint64_t ptr
, int rtag
)
1223 return deposit64(ptr
, 56, 4, rtag
);
1226 /* Return true if tbi bits mean that the access is checked. */
1227 static inline bool tbi_check(uint32_t desc
, int bit55
)
1229 return (desc
>> (R_MTEDESC_TBI_SHIFT
+ bit55
)) & 1;
1232 /* Return true if tcma bits mean that the access is unchecked. */
1233 static inline bool tcma_check(uint32_t desc
, int bit55
, int ptr_tag
)
1236 * We had extracted bit55 and ptr_tag for other reasons, so fold
1237 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test.
1239 bool match
= ((ptr_tag
+ bit55
) & 0xf) == 0;
1240 bool tcma
= (desc
>> (R_MTEDESC_TCMA_SHIFT
+ bit55
)) & 1;
1241 return tcma
&& match
;
1245 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
1246 * for the tag to be present in the FAR_ELx register. But for user-only
1247 * mode, we do not have a TLB with which to implement this, so we must
1248 * remove the top byte.
1250 static inline uint64_t useronly_clean_ptr(uint64_t ptr
)
1252 #ifdef CONFIG_USER_ONLY
1253 /* TBI0 is known to be enabled, while TBI1 is disabled. */
1254 ptr
&= sextract64(ptr
, 0, 56);
1259 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc
, uint64_t ptr
)
1261 #ifdef CONFIG_USER_ONLY
1262 int64_t clean_ptr
= sextract64(ptr
, 0, 56);
1263 if (tbi_check(desc
, clean_ptr
< 0)) {
1270 /* Values for M-profile PSR.ECI for MVE insns */
1272 ECI_NONE
= 0, /* No completed beats */
1273 ECI_A0
= 1, /* Completed: A0 */
1274 ECI_A0A1
= 2, /* Completed: A0, A1 */
1276 ECI_A0A1A2
= 4, /* Completed: A0, A1, A2 */
1277 ECI_A0A1A2B0
= 5, /* Completed: A0, A1, A2, B0 */
1278 /* All other values reserved */
1281 /* Definitions for the PMU registers */
1282 #define PMCRN_MASK 0xf800
1283 #define PMCRN_SHIFT 11
1293 * Mask of PMCR bits writable by guest (not including WO bits like C, P,
1294 * which can be written as 1 to trigger behaviour but which stay RAZ).
1296 #define PMCR_WRITABLE_MASK (PMCRLP | PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1298 #define PMXEVTYPER_P 0x80000000
1299 #define PMXEVTYPER_U 0x40000000
1300 #define PMXEVTYPER_NSK 0x20000000
1301 #define PMXEVTYPER_NSU 0x10000000
1302 #define PMXEVTYPER_NSH 0x08000000
1303 #define PMXEVTYPER_M 0x04000000
1304 #define PMXEVTYPER_MT 0x02000000
1305 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1306 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1307 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1308 PMXEVTYPER_M | PMXEVTYPER_MT | \
1309 PMXEVTYPER_EVTCOUNT)
1311 #define PMCCFILTR 0xf8000000
1312 #define PMCCFILTR_M PMXEVTYPER_M
1313 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1315 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1317 ARMCPU
*cpu
= env_archcpu(env
);
1319 return (cpu
->isar
.reset_pmcr_el0
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1322 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1323 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1325 return (1ULL << 31) | ((1ULL << pmu_num_counters(env
)) - 1);
1328 #ifdef TARGET_AARCH64
1329 int arm_gdb_get_svereg(CPUARMState
*env
, GByteArray
*buf
, int reg
);
1330 int arm_gdb_set_svereg(CPUARMState
*env
, uint8_t *buf
, int reg
);
1331 int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
);
1332 int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
);
1333 void arm_cpu_sve_finalize(ARMCPU
*cpu
, Error
**errp
);
1334 void arm_cpu_sme_finalize(ARMCPU
*cpu
, Error
**errp
);
1335 void arm_cpu_pauth_finalize(ARMCPU
*cpu
, Error
**errp
);
1336 void arm_cpu_lpa2_finalize(ARMCPU
*cpu
, Error
**errp
);
1339 #ifdef CONFIG_USER_ONLY
1340 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU
*cpu
) { }
1342 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU
*cpu
);
1345 bool el_is_in_host(CPUARMState
*env
, int el
);
1347 void aa32_max_features(ARMCPU
*cpu
);
1348 int exception_target_el(CPUARMState
*env
);
1349 bool arm_singlestep_active(CPUARMState
*env
);
1350 bool arm_generate_debug_exceptions(CPUARMState
*env
);
1352 /* Add the cpreg definitions for debug related system registers */
1353 void define_debug_regs(ARMCPU
*cpu
);
1355 /* Effective value of MDCR_EL2 */
1356 static inline uint64_t arm_mdcr_el2_eff(CPUARMState
*env
)
1358 return arm_is_el2_enabled(env
) ? env
->cp15
.mdcr_el2
: 0;
1361 /* Powers of 2 for sve_vq_map et al. */
1362 #define SVE_VQ_POW2_MAP \
1363 ((1 << (1 - 1)) | (1 << (2 - 1)) | \
1364 (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
1367 * Return true if it is possible to take a fine-grained-trap to EL2.
1369 static inline bool arm_fgt_active(CPUARMState
*env
, int el
)
1372 * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
1373 * that can affect EL0, but it is harmless to do the test also for
1374 * traps on registers that are only accessible at EL1 because if the test
1375 * returns true then we can't be executing at EL1 anyway.
1376 * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
1377 * traps from AArch32 only happen for the EL0 is AArch32 case.
1379 return cpu_isar_feature(aa64_fgt
, env_archcpu(env
)) &&
1380 el
< 2 && arm_is_el2_enabled(env
) &&
1381 arm_el_is_aa64(env
, 1) &&
1382 (arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
) &&
1383 (!arm_feature(env
, ARM_FEATURE_EL3
) || (env
->cp15
.scr_el3
& SCR_FGTEN
));