1 #include "qemu/osdep.h"
2 #include "qemu-common.h"
6 #include "qemu/error-report.h"
7 #include "sysemu/kvm.h"
10 #include "migration/cpu.h"
12 static bool vfp_needed(void *opaque
)
15 CPUARMState
*env
= &cpu
->env
;
17 return arm_feature(env
, ARM_FEATURE_VFP
);
20 static int get_fpscr(QEMUFile
*f
, void *opaque
, size_t size
,
24 CPUARMState
*env
= &cpu
->env
;
25 uint32_t val
= qemu_get_be32(f
);
27 vfp_set_fpscr(env
, val
);
31 static int put_fpscr(QEMUFile
*f
, void *opaque
, size_t size
,
32 VMStateField
*field
, QJSON
*vmdesc
)
35 CPUARMState
*env
= &cpu
->env
;
37 qemu_put_be32(f
, vfp_get_fpscr(env
));
41 static const VMStateInfo vmstate_fpscr
= {
47 static const VMStateDescription vmstate_vfp
= {
50 .minimum_version_id
= 3,
52 .fields
= (VMStateField
[]) {
53 /* For compatibility, store Qn out of Zn here. */
54 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[0].d
, ARMCPU
, 0, 2),
55 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[1].d
, ARMCPU
, 0, 2),
56 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[2].d
, ARMCPU
, 0, 2),
57 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[3].d
, ARMCPU
, 0, 2),
58 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[4].d
, ARMCPU
, 0, 2),
59 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[5].d
, ARMCPU
, 0, 2),
60 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[6].d
, ARMCPU
, 0, 2),
61 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[7].d
, ARMCPU
, 0, 2),
62 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[8].d
, ARMCPU
, 0, 2),
63 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[9].d
, ARMCPU
, 0, 2),
64 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[10].d
, ARMCPU
, 0, 2),
65 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[11].d
, ARMCPU
, 0, 2),
66 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[12].d
, ARMCPU
, 0, 2),
67 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[13].d
, ARMCPU
, 0, 2),
68 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[14].d
, ARMCPU
, 0, 2),
69 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[15].d
, ARMCPU
, 0, 2),
70 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[16].d
, ARMCPU
, 0, 2),
71 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[17].d
, ARMCPU
, 0, 2),
72 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[18].d
, ARMCPU
, 0, 2),
73 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[19].d
, ARMCPU
, 0, 2),
74 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[20].d
, ARMCPU
, 0, 2),
75 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[21].d
, ARMCPU
, 0, 2),
76 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[22].d
, ARMCPU
, 0, 2),
77 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[23].d
, ARMCPU
, 0, 2),
78 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[24].d
, ARMCPU
, 0, 2),
79 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[25].d
, ARMCPU
, 0, 2),
80 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[26].d
, ARMCPU
, 0, 2),
81 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[27].d
, ARMCPU
, 0, 2),
82 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[28].d
, ARMCPU
, 0, 2),
83 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[29].d
, ARMCPU
, 0, 2),
84 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[30].d
, ARMCPU
, 0, 2),
85 VMSTATE_UINT64_SUB_ARRAY(env
.vfp
.zregs
[31].d
, ARMCPU
, 0, 2),
87 /* The xregs array is a little awkward because element 1 (FPSCR)
88 * requires a specific accessor, so we have to split it up in
91 VMSTATE_UINT32(env
.vfp
.xregs
[0], ARMCPU
),
92 VMSTATE_UINT32_SUB_ARRAY(env
.vfp
.xregs
, ARMCPU
, 2, 14),
96 .size
= sizeof(uint32_t),
97 .info
= &vmstate_fpscr
,
101 VMSTATE_END_OF_LIST()
105 static bool iwmmxt_needed(void *opaque
)
107 ARMCPU
*cpu
= opaque
;
108 CPUARMState
*env
= &cpu
->env
;
110 return arm_feature(env
, ARM_FEATURE_IWMMXT
);
113 static const VMStateDescription vmstate_iwmmxt
= {
114 .name
= "cpu/iwmmxt",
116 .minimum_version_id
= 1,
117 .needed
= iwmmxt_needed
,
118 .fields
= (VMStateField
[]) {
119 VMSTATE_UINT64_ARRAY(env
.iwmmxt
.regs
, ARMCPU
, 16),
120 VMSTATE_UINT32_ARRAY(env
.iwmmxt
.cregs
, ARMCPU
, 16),
121 VMSTATE_END_OF_LIST()
125 #ifdef TARGET_AARCH64
126 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build,
127 * and ARMPredicateReg is actively empty. This triggers errors
128 * in the expansion of the VMSTATE macros.
131 static bool sve_needed(void *opaque
)
133 ARMCPU
*cpu
= opaque
;
134 CPUARMState
*env
= &cpu
->env
;
136 return arm_feature(env
, ARM_FEATURE_SVE
);
139 /* The first two words of each Zreg is stored in VFP state. */
140 static const VMStateDescription vmstate_zreg_hi_reg
= {
141 .name
= "cpu/sve/zreg_hi",
143 .minimum_version_id
= 1,
144 .fields
= (VMStateField
[]) {
145 VMSTATE_UINT64_SUB_ARRAY(d
, ARMVectorReg
, 2, ARM_MAX_VQ
- 2),
146 VMSTATE_END_OF_LIST()
150 static const VMStateDescription vmstate_preg_reg
= {
151 .name
= "cpu/sve/preg",
153 .minimum_version_id
= 1,
154 .fields
= (VMStateField
[]) {
155 VMSTATE_UINT64_ARRAY(p
, ARMPredicateReg
, 2 * ARM_MAX_VQ
/ 8),
156 VMSTATE_END_OF_LIST()
160 static const VMStateDescription vmstate_sve
= {
163 .minimum_version_id
= 1,
164 .needed
= sve_needed
,
165 .fields
= (VMStateField
[]) {
166 VMSTATE_STRUCT_ARRAY(env
.vfp
.zregs
, ARMCPU
, 32, 0,
167 vmstate_zreg_hi_reg
, ARMVectorReg
),
168 VMSTATE_STRUCT_ARRAY(env
.vfp
.pregs
, ARMCPU
, 17, 0,
169 vmstate_preg_reg
, ARMPredicateReg
),
170 VMSTATE_END_OF_LIST()
175 static bool m_needed(void *opaque
)
177 ARMCPU
*cpu
= opaque
;
178 CPUARMState
*env
= &cpu
->env
;
180 return arm_feature(env
, ARM_FEATURE_M
);
183 static const VMStateDescription vmstate_m_faultmask_primask
= {
184 .name
= "cpu/m/faultmask-primask",
186 .minimum_version_id
= 1,
187 .fields
= (VMStateField
[]) {
188 VMSTATE_UINT32(env
.v7m
.faultmask
[M_REG_NS
], ARMCPU
),
189 VMSTATE_UINT32(env
.v7m
.primask
[M_REG_NS
], ARMCPU
),
190 VMSTATE_END_OF_LIST()
194 static const VMStateDescription vmstate_m
= {
197 .minimum_version_id
= 4,
199 .fields
= (VMStateField
[]) {
200 VMSTATE_UINT32(env
.v7m
.vecbase
[M_REG_NS
], ARMCPU
),
201 VMSTATE_UINT32(env
.v7m
.basepri
[M_REG_NS
], ARMCPU
),
202 VMSTATE_UINT32(env
.v7m
.control
[M_REG_NS
], ARMCPU
),
203 VMSTATE_UINT32(env
.v7m
.ccr
[M_REG_NS
], ARMCPU
),
204 VMSTATE_UINT32(env
.v7m
.cfsr
[M_REG_NS
], ARMCPU
),
205 VMSTATE_UINT32(env
.v7m
.hfsr
, ARMCPU
),
206 VMSTATE_UINT32(env
.v7m
.dfsr
, ARMCPU
),
207 VMSTATE_UINT32(env
.v7m
.mmfar
[M_REG_NS
], ARMCPU
),
208 VMSTATE_UINT32(env
.v7m
.bfar
, ARMCPU
),
209 VMSTATE_UINT32(env
.v7m
.mpu_ctrl
[M_REG_NS
], ARMCPU
),
210 VMSTATE_INT32(env
.v7m
.exception
, ARMCPU
),
211 VMSTATE_END_OF_LIST()
213 .subsections
= (const VMStateDescription
*[]) {
214 &vmstate_m_faultmask_primask
,
219 static bool thumb2ee_needed(void *opaque
)
221 ARMCPU
*cpu
= opaque
;
222 CPUARMState
*env
= &cpu
->env
;
224 return arm_feature(env
, ARM_FEATURE_THUMB2EE
);
227 static const VMStateDescription vmstate_thumb2ee
= {
228 .name
= "cpu/thumb2ee",
230 .minimum_version_id
= 1,
231 .needed
= thumb2ee_needed
,
232 .fields
= (VMStateField
[]) {
233 VMSTATE_UINT32(env
.teecr
, ARMCPU
),
234 VMSTATE_UINT32(env
.teehbr
, ARMCPU
),
235 VMSTATE_END_OF_LIST()
239 static bool pmsav7_needed(void *opaque
)
241 ARMCPU
*cpu
= opaque
;
242 CPUARMState
*env
= &cpu
->env
;
244 return arm_feature(env
, ARM_FEATURE_PMSA
) &&
245 arm_feature(env
, ARM_FEATURE_V7
) &&
246 !arm_feature(env
, ARM_FEATURE_V8
);
249 static bool pmsav7_rgnr_vmstate_validate(void *opaque
, int version_id
)
251 ARMCPU
*cpu
= opaque
;
253 return cpu
->env
.pmsav7
.rnr
[M_REG_NS
] < cpu
->pmsav7_dregion
;
256 static const VMStateDescription vmstate_pmsav7
= {
257 .name
= "cpu/pmsav7",
259 .minimum_version_id
= 1,
260 .needed
= pmsav7_needed
,
261 .fields
= (VMStateField
[]) {
262 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drbar
, ARMCPU
, pmsav7_dregion
, 0,
263 vmstate_info_uint32
, uint32_t),
264 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drsr
, ARMCPU
, pmsav7_dregion
, 0,
265 vmstate_info_uint32
, uint32_t),
266 VMSTATE_VARRAY_UINT32(env
.pmsav7
.dracr
, ARMCPU
, pmsav7_dregion
, 0,
267 vmstate_info_uint32
, uint32_t),
268 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate
),
269 VMSTATE_END_OF_LIST()
273 static bool pmsav7_rnr_needed(void *opaque
)
275 ARMCPU
*cpu
= opaque
;
276 CPUARMState
*env
= &cpu
->env
;
278 /* For R profile cores pmsav7.rnr is migrated via the cpreg
279 * "RGNR" definition in helper.h. For M profile we have to
280 * migrate it separately.
282 return arm_feature(env
, ARM_FEATURE_M
);
285 static const VMStateDescription vmstate_pmsav7_rnr
= {
286 .name
= "cpu/pmsav7-rnr",
288 .minimum_version_id
= 1,
289 .needed
= pmsav7_rnr_needed
,
290 .fields
= (VMStateField
[]) {
291 VMSTATE_UINT32(env
.pmsav7
.rnr
[M_REG_NS
], ARMCPU
),
292 VMSTATE_END_OF_LIST()
296 static bool pmsav8_needed(void *opaque
)
298 ARMCPU
*cpu
= opaque
;
299 CPUARMState
*env
= &cpu
->env
;
301 return arm_feature(env
, ARM_FEATURE_PMSA
) &&
302 arm_feature(env
, ARM_FEATURE_V8
);
305 static const VMStateDescription vmstate_pmsav8
= {
306 .name
= "cpu/pmsav8",
308 .minimum_version_id
= 1,
309 .needed
= pmsav8_needed
,
310 .fields
= (VMStateField
[]) {
311 VMSTATE_VARRAY_UINT32(env
.pmsav8
.rbar
[M_REG_NS
], ARMCPU
, pmsav7_dregion
,
312 0, vmstate_info_uint32
, uint32_t),
313 VMSTATE_VARRAY_UINT32(env
.pmsav8
.rlar
[M_REG_NS
], ARMCPU
, pmsav7_dregion
,
314 0, vmstate_info_uint32
, uint32_t),
315 VMSTATE_UINT32(env
.pmsav8
.mair0
[M_REG_NS
], ARMCPU
),
316 VMSTATE_UINT32(env
.pmsav8
.mair1
[M_REG_NS
], ARMCPU
),
317 VMSTATE_END_OF_LIST()
321 static bool s_rnr_vmstate_validate(void *opaque
, int version_id
)
323 ARMCPU
*cpu
= opaque
;
325 return cpu
->env
.pmsav7
.rnr
[M_REG_S
] < cpu
->pmsav7_dregion
;
328 static bool sau_rnr_vmstate_validate(void *opaque
, int version_id
)
330 ARMCPU
*cpu
= opaque
;
332 return cpu
->env
.sau
.rnr
< cpu
->sau_sregion
;
335 static bool m_security_needed(void *opaque
)
337 ARMCPU
*cpu
= opaque
;
338 CPUARMState
*env
= &cpu
->env
;
340 return arm_feature(env
, ARM_FEATURE_M_SECURITY
);
343 static const VMStateDescription vmstate_m_security
= {
344 .name
= "cpu/m-security",
346 .minimum_version_id
= 1,
347 .needed
= m_security_needed
,
348 .fields
= (VMStateField
[]) {
349 VMSTATE_UINT32(env
.v7m
.secure
, ARMCPU
),
350 VMSTATE_UINT32(env
.v7m
.other_ss_msp
, ARMCPU
),
351 VMSTATE_UINT32(env
.v7m
.other_ss_psp
, ARMCPU
),
352 VMSTATE_UINT32(env
.v7m
.basepri
[M_REG_S
], ARMCPU
),
353 VMSTATE_UINT32(env
.v7m
.primask
[M_REG_S
], ARMCPU
),
354 VMSTATE_UINT32(env
.v7m
.faultmask
[M_REG_S
], ARMCPU
),
355 VMSTATE_UINT32(env
.v7m
.control
[M_REG_S
], ARMCPU
),
356 VMSTATE_UINT32(env
.v7m
.vecbase
[M_REG_S
], ARMCPU
),
357 VMSTATE_UINT32(env
.pmsav8
.mair0
[M_REG_S
], ARMCPU
),
358 VMSTATE_UINT32(env
.pmsav8
.mair1
[M_REG_S
], ARMCPU
),
359 VMSTATE_VARRAY_UINT32(env
.pmsav8
.rbar
[M_REG_S
], ARMCPU
, pmsav7_dregion
,
360 0, vmstate_info_uint32
, uint32_t),
361 VMSTATE_VARRAY_UINT32(env
.pmsav8
.rlar
[M_REG_S
], ARMCPU
, pmsav7_dregion
,
362 0, vmstate_info_uint32
, uint32_t),
363 VMSTATE_UINT32(env
.pmsav7
.rnr
[M_REG_S
], ARMCPU
),
364 VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate
),
365 VMSTATE_UINT32(env
.v7m
.mpu_ctrl
[M_REG_S
], ARMCPU
),
366 VMSTATE_UINT32(env
.v7m
.ccr
[M_REG_S
], ARMCPU
),
367 VMSTATE_UINT32(env
.v7m
.mmfar
[M_REG_S
], ARMCPU
),
368 VMSTATE_UINT32(env
.v7m
.cfsr
[M_REG_S
], ARMCPU
),
369 VMSTATE_UINT32(env
.v7m
.sfsr
, ARMCPU
),
370 VMSTATE_UINT32(env
.v7m
.sfar
, ARMCPU
),
371 VMSTATE_VARRAY_UINT32(env
.sau
.rbar
, ARMCPU
, sau_sregion
, 0,
372 vmstate_info_uint32
, uint32_t),
373 VMSTATE_VARRAY_UINT32(env
.sau
.rlar
, ARMCPU
, sau_sregion
, 0,
374 vmstate_info_uint32
, uint32_t),
375 VMSTATE_UINT32(env
.sau
.rnr
, ARMCPU
),
376 VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate
),
377 VMSTATE_UINT32(env
.sau
.ctrl
, ARMCPU
),
378 VMSTATE_END_OF_LIST()
382 static int get_cpsr(QEMUFile
*f
, void *opaque
, size_t size
,
385 ARMCPU
*cpu
= opaque
;
386 CPUARMState
*env
= &cpu
->env
;
387 uint32_t val
= qemu_get_be32(f
);
389 if (arm_feature(env
, ARM_FEATURE_M
)) {
390 if (val
& XPSR_EXCP
) {
391 /* This is a CPSR format value from an older QEMU. (We can tell
392 * because values transferred in XPSR format always have zero
393 * for the EXCP field, and CPSR format will always have bit 4
394 * set in CPSR_M.) Rearrange it into XPSR format. The significant
395 * differences are that the T bit is not in the same place, the
396 * primask/faultmask info may be in the CPSR I and F bits, and
397 * we do not want the mode bits.
398 * We know that this cleanup happened before v8M, so there
399 * is no complication with banked primask/faultmask.
401 uint32_t newval
= val
;
403 assert(!arm_feature(env
, ARM_FEATURE_M_SECURITY
));
405 newval
&= (CPSR_NZCV
| CPSR_Q
| CPSR_IT
| CPSR_GE
);
409 /* If the I or F bits are set then this is a migration from
410 * an old QEMU which still stored the M profile FAULTMASK
411 * and PRIMASK in env->daif. For a new QEMU, the data is
412 * transferred using the vmstate_m_faultmask_primask subsection.
415 env
->v7m
.faultmask
[M_REG_NS
] = 1;
418 env
->v7m
.primask
[M_REG_NS
] = 1;
422 /* Ignore the low bits, they are handled by vmstate_m. */
423 xpsr_write(env
, val
, ~XPSR_EXCP
);
427 env
->aarch64
= ((val
& PSTATE_nRW
) == 0);
430 pstate_write(env
, val
);
434 cpsr_write(env
, val
, 0xffffffff, CPSRWriteRaw
);
438 static int put_cpsr(QEMUFile
*f
, void *opaque
, size_t size
,
439 VMStateField
*field
, QJSON
*vmdesc
)
441 ARMCPU
*cpu
= opaque
;
442 CPUARMState
*env
= &cpu
->env
;
445 if (arm_feature(env
, ARM_FEATURE_M
)) {
446 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */
447 val
= xpsr_read(env
) & ~XPSR_EXCP
;
448 } else if (is_a64(env
)) {
449 val
= pstate_read(env
);
451 val
= cpsr_read(env
);
454 qemu_put_be32(f
, val
);
458 static const VMStateInfo vmstate_cpsr
= {
464 static int get_power(QEMUFile
*f
, void *opaque
, size_t size
,
467 ARMCPU
*cpu
= opaque
;
468 bool powered_off
= qemu_get_byte(f
);
469 cpu
->power_state
= powered_off
? PSCI_OFF
: PSCI_ON
;
473 static int put_power(QEMUFile
*f
, void *opaque
, size_t size
,
474 VMStateField
*field
, QJSON
*vmdesc
)
476 ARMCPU
*cpu
= opaque
;
478 /* Migration should never happen while we transition power states */
480 if (cpu
->power_state
== PSCI_ON
||
481 cpu
->power_state
== PSCI_OFF
) {
482 bool powered_off
= (cpu
->power_state
== PSCI_OFF
) ? true : false;
483 qemu_put_byte(f
, powered_off
);
490 static const VMStateInfo vmstate_powered_off
= {
491 .name
= "powered_off",
496 static int cpu_pre_save(void *opaque
)
498 ARMCPU
*cpu
= opaque
;
501 if (!write_kvmstate_to_list(cpu
)) {
502 /* This should never fail */
506 if (!write_cpustate_to_list(cpu
)) {
507 /* This should never fail. */
512 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
513 memcpy(cpu
->cpreg_vmstate_indexes
, cpu
->cpreg_indexes
,
514 cpu
->cpreg_array_len
* sizeof(uint64_t));
515 memcpy(cpu
->cpreg_vmstate_values
, cpu
->cpreg_values
,
516 cpu
->cpreg_array_len
* sizeof(uint64_t));
521 static int cpu_post_load(void *opaque
, int version_id
)
523 ARMCPU
*cpu
= opaque
;
526 /* Update the values list from the incoming migration data.
527 * Anything in the incoming data which we don't know about is
528 * a migration failure; anything we know about but the incoming
529 * data doesn't specify retains its current (reset) value.
530 * The indexes list remains untouched -- we only inspect the
531 * incoming migration index list so we can match the values array
532 * entries with the right slots in our own values array.
535 for (i
= 0, v
= 0; i
< cpu
->cpreg_array_len
536 && v
< cpu
->cpreg_vmstate_array_len
; i
++) {
537 if (cpu
->cpreg_vmstate_indexes
[v
] > cpu
->cpreg_indexes
[i
]) {
538 /* register in our list but not incoming : skip it */
541 if (cpu
->cpreg_vmstate_indexes
[v
] < cpu
->cpreg_indexes
[i
]) {
542 /* register in their list but not ours: fail migration */
545 /* matching register, copy the value over */
546 cpu
->cpreg_values
[i
] = cpu
->cpreg_vmstate_values
[v
];
551 if (!write_list_to_kvmstate(cpu
, KVM_PUT_FULL_STATE
)) {
554 /* Note that it's OK for the TCG side not to know about
555 * every register in the list; KVM is authoritative if
558 write_list_to_cpustate(cpu
);
560 if (!write_list_to_cpustate(cpu
)) {
565 hw_breakpoint_update_all(cpu
);
566 hw_watchpoint_update_all(cpu
);
571 const VMStateDescription vmstate_arm_cpu
= {
574 .minimum_version_id
= 22,
575 .pre_save
= cpu_pre_save
,
576 .post_load
= cpu_post_load
,
577 .fields
= (VMStateField
[]) {
578 VMSTATE_UINT32_ARRAY(env
.regs
, ARMCPU
, 16),
579 VMSTATE_UINT64_ARRAY(env
.xregs
, ARMCPU
, 32),
580 VMSTATE_UINT64(env
.pc
, ARMCPU
),
584 .size
= sizeof(uint32_t),
585 .info
= &vmstate_cpsr
,
589 VMSTATE_UINT32(env
.spsr
, ARMCPU
),
590 VMSTATE_UINT64_ARRAY(env
.banked_spsr
, ARMCPU
, 8),
591 VMSTATE_UINT32_ARRAY(env
.banked_r13
, ARMCPU
, 8),
592 VMSTATE_UINT32_ARRAY(env
.banked_r14
, ARMCPU
, 8),
593 VMSTATE_UINT32_ARRAY(env
.usr_regs
, ARMCPU
, 5),
594 VMSTATE_UINT32_ARRAY(env
.fiq_regs
, ARMCPU
, 5),
595 VMSTATE_UINT64_ARRAY(env
.elr_el
, ARMCPU
, 4),
596 VMSTATE_UINT64_ARRAY(env
.sp_el
, ARMCPU
, 4),
597 /* The length-check must come before the arrays to avoid
598 * incoming data possibly overflowing the array.
600 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len
, ARMCPU
),
601 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes
, ARMCPU
,
602 cpreg_vmstate_array_len
,
603 0, vmstate_info_uint64
, uint64_t),
604 VMSTATE_VARRAY_INT32(cpreg_vmstate_values
, ARMCPU
,
605 cpreg_vmstate_array_len
,
606 0, vmstate_info_uint64
, uint64_t),
607 VMSTATE_UINT64(env
.exclusive_addr
, ARMCPU
),
608 VMSTATE_UINT64(env
.exclusive_val
, ARMCPU
),
609 VMSTATE_UINT64(env
.exclusive_high
, ARMCPU
),
610 VMSTATE_UINT64(env
.features
, ARMCPU
),
611 VMSTATE_UINT32(env
.exception
.syndrome
, ARMCPU
),
612 VMSTATE_UINT32(env
.exception
.fsr
, ARMCPU
),
613 VMSTATE_UINT64(env
.exception
.vaddress
, ARMCPU
),
614 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_PHYS
], ARMCPU
),
615 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_VIRT
], ARMCPU
),
617 .name
= "power_state",
619 .size
= sizeof(bool),
620 .info
= &vmstate_powered_off
,
624 VMSTATE_END_OF_LIST()
626 .subsections
= (const VMStateDescription
*[]) {
631 /* pmsav7_rnr must come before pmsav7 so that we have the
632 * region number before we test it in the VMSTATE_VALIDATE
639 #ifdef TARGET_AARCH64