1 #include "qemu/osdep.h"
2 #include "qemu-common.h"
6 #include "qemu/error-report.h"
7 #include "sysemu/kvm.h"
10 #include "migration/cpu.h"
12 static bool vfp_needed(void *opaque
)
15 CPUARMState
*env
= &cpu
->env
;
17 return arm_feature(env
, ARM_FEATURE_VFP
);
20 static int get_fpscr(QEMUFile
*f
, void *opaque
, size_t size
,
24 CPUARMState
*env
= &cpu
->env
;
25 uint32_t val
= qemu_get_be32(f
);
27 vfp_set_fpscr(env
, val
);
31 static int put_fpscr(QEMUFile
*f
, void *opaque
, size_t size
,
32 VMStateField
*field
, QJSON
*vmdesc
)
35 CPUARMState
*env
= &cpu
->env
;
37 qemu_put_be32(f
, vfp_get_fpscr(env
));
41 static const VMStateInfo vmstate_fpscr
= {
47 static const VMStateDescription vmstate_vfp
= {
50 .minimum_version_id
= 3,
52 .fields
= (VMStateField
[]) {
53 VMSTATE_FLOAT64_ARRAY(env
.vfp
.regs
, ARMCPU
, 64),
54 /* The xregs array is a little awkward because element 1 (FPSCR)
55 * requires a specific accessor, so we have to split it up in
58 VMSTATE_UINT32(env
.vfp
.xregs
[0], ARMCPU
),
59 VMSTATE_UINT32_SUB_ARRAY(env
.vfp
.xregs
, ARMCPU
, 2, 14),
63 .size
= sizeof(uint32_t),
64 .info
= &vmstate_fpscr
,
72 static bool iwmmxt_needed(void *opaque
)
75 CPUARMState
*env
= &cpu
->env
;
77 return arm_feature(env
, ARM_FEATURE_IWMMXT
);
80 static const VMStateDescription vmstate_iwmmxt
= {
83 .minimum_version_id
= 1,
84 .needed
= iwmmxt_needed
,
85 .fields
= (VMStateField
[]) {
86 VMSTATE_UINT64_ARRAY(env
.iwmmxt
.regs
, ARMCPU
, 16),
87 VMSTATE_UINT32_ARRAY(env
.iwmmxt
.cregs
, ARMCPU
, 16),
92 static bool m_needed(void *opaque
)
95 CPUARMState
*env
= &cpu
->env
;
97 return arm_feature(env
, ARM_FEATURE_M
);
100 static const VMStateDescription vmstate_m_faultmask_primask
= {
101 .name
= "cpu/m/faultmask-primask",
103 .minimum_version_id
= 1,
104 .fields
= (VMStateField
[]) {
105 VMSTATE_UINT32(env
.v7m
.faultmask
, ARMCPU
),
106 VMSTATE_UINT32(env
.v7m
.primask
, ARMCPU
),
107 VMSTATE_END_OF_LIST()
111 static const VMStateDescription vmstate_m
= {
114 .minimum_version_id
= 4,
116 .fields
= (VMStateField
[]) {
117 VMSTATE_UINT32(env
.v7m
.vecbase
, ARMCPU
),
118 VMSTATE_UINT32(env
.v7m
.basepri
, ARMCPU
),
119 VMSTATE_UINT32(env
.v7m
.control
, ARMCPU
),
120 VMSTATE_UINT32(env
.v7m
.ccr
, ARMCPU
),
121 VMSTATE_UINT32(env
.v7m
.cfsr
, ARMCPU
),
122 VMSTATE_UINT32(env
.v7m
.hfsr
, ARMCPU
),
123 VMSTATE_UINT32(env
.v7m
.dfsr
, ARMCPU
),
124 VMSTATE_UINT32(env
.v7m
.mmfar
, ARMCPU
),
125 VMSTATE_UINT32(env
.v7m
.bfar
, ARMCPU
),
126 VMSTATE_UINT32(env
.v7m
.mpu_ctrl
, ARMCPU
),
127 VMSTATE_INT32(env
.v7m
.exception
, ARMCPU
),
128 VMSTATE_END_OF_LIST()
130 .subsections
= (const VMStateDescription
*[]) {
131 &vmstate_m_faultmask_primask
,
136 static bool thumb2ee_needed(void *opaque
)
138 ARMCPU
*cpu
= opaque
;
139 CPUARMState
*env
= &cpu
->env
;
141 return arm_feature(env
, ARM_FEATURE_THUMB2EE
);
144 static const VMStateDescription vmstate_thumb2ee
= {
145 .name
= "cpu/thumb2ee",
147 .minimum_version_id
= 1,
148 .needed
= thumb2ee_needed
,
149 .fields
= (VMStateField
[]) {
150 VMSTATE_UINT32(env
.teecr
, ARMCPU
),
151 VMSTATE_UINT32(env
.teehbr
, ARMCPU
),
152 VMSTATE_END_OF_LIST()
156 static bool pmsav7_needed(void *opaque
)
158 ARMCPU
*cpu
= opaque
;
159 CPUARMState
*env
= &cpu
->env
;
161 return arm_feature(env
, ARM_FEATURE_PMSA
) &&
162 arm_feature(env
, ARM_FEATURE_V7
);
165 static bool pmsav7_rgnr_vmstate_validate(void *opaque
, int version_id
)
167 ARMCPU
*cpu
= opaque
;
169 return cpu
->env
.pmsav7
.rnr
< cpu
->pmsav7_dregion
;
172 static const VMStateDescription vmstate_pmsav7
= {
173 .name
= "cpu/pmsav7",
175 .minimum_version_id
= 1,
176 .needed
= pmsav7_needed
,
177 .fields
= (VMStateField
[]) {
178 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drbar
, ARMCPU
, pmsav7_dregion
, 0,
179 vmstate_info_uint32
, uint32_t),
180 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drsr
, ARMCPU
, pmsav7_dregion
, 0,
181 vmstate_info_uint32
, uint32_t),
182 VMSTATE_VARRAY_UINT32(env
.pmsav7
.dracr
, ARMCPU
, pmsav7_dregion
, 0,
183 vmstate_info_uint32
, uint32_t),
184 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate
),
185 VMSTATE_END_OF_LIST()
189 static bool pmsav7_rnr_needed(void *opaque
)
191 ARMCPU
*cpu
= opaque
;
192 CPUARMState
*env
= &cpu
->env
;
194 /* For R profile cores pmsav7.rnr is migrated via the cpreg
195 * "RGNR" definition in helper.h. For M profile we have to
196 * migrate it separately.
198 return arm_feature(env
, ARM_FEATURE_M
);
201 static const VMStateDescription vmstate_pmsav7_rnr
= {
202 .name
= "cpu/pmsav7-rnr",
204 .minimum_version_id
= 1,
205 .needed
= pmsav7_rnr_needed
,
206 .fields
= (VMStateField
[]) {
207 VMSTATE_UINT32(env
.pmsav7
.rnr
, ARMCPU
),
208 VMSTATE_END_OF_LIST()
212 static int get_cpsr(QEMUFile
*f
, void *opaque
, size_t size
,
215 ARMCPU
*cpu
= opaque
;
216 CPUARMState
*env
= &cpu
->env
;
217 uint32_t val
= qemu_get_be32(f
);
219 if (arm_feature(env
, ARM_FEATURE_M
)) {
220 if (val
& XPSR_EXCP
) {
221 /* This is a CPSR format value from an older QEMU. (We can tell
222 * because values transferred in XPSR format always have zero
223 * for the EXCP field, and CPSR format will always have bit 4
224 * set in CPSR_M.) Rearrange it into XPSR format. The significant
225 * differences are that the T bit is not in the same place, the
226 * primask/faultmask info may be in the CPSR I and F bits, and
227 * we do not want the mode bits.
229 uint32_t newval
= val
;
231 newval
&= (CPSR_NZCV
| CPSR_Q
| CPSR_IT
| CPSR_GE
);
235 /* If the I or F bits are set then this is a migration from
236 * an old QEMU which still stored the M profile FAULTMASK
237 * and PRIMASK in env->daif. For a new QEMU, the data is
238 * transferred using the vmstate_m_faultmask_primask subsection.
241 env
->v7m
.faultmask
= 1;
244 env
->v7m
.primask
= 1;
248 /* Ignore the low bits, they are handled by vmstate_m. */
249 xpsr_write(env
, val
, ~XPSR_EXCP
);
253 env
->aarch64
= ((val
& PSTATE_nRW
) == 0);
256 pstate_write(env
, val
);
260 cpsr_write(env
, val
, 0xffffffff, CPSRWriteRaw
);
264 static int put_cpsr(QEMUFile
*f
, void *opaque
, size_t size
,
265 VMStateField
*field
, QJSON
*vmdesc
)
267 ARMCPU
*cpu
= opaque
;
268 CPUARMState
*env
= &cpu
->env
;
271 if (arm_feature(env
, ARM_FEATURE_M
)) {
272 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */
273 val
= xpsr_read(env
) & ~XPSR_EXCP
;
274 } else if (is_a64(env
)) {
275 val
= pstate_read(env
);
277 val
= cpsr_read(env
);
280 qemu_put_be32(f
, val
);
284 static const VMStateInfo vmstate_cpsr
= {
290 static int get_power(QEMUFile
*f
, void *opaque
, size_t size
,
293 ARMCPU
*cpu
= opaque
;
294 bool powered_off
= qemu_get_byte(f
);
295 cpu
->power_state
= powered_off
? PSCI_OFF
: PSCI_ON
;
299 static int put_power(QEMUFile
*f
, void *opaque
, size_t size
,
300 VMStateField
*field
, QJSON
*vmdesc
)
302 ARMCPU
*cpu
= opaque
;
304 /* Migration should never happen while we transition power states */
306 if (cpu
->power_state
== PSCI_ON
||
307 cpu
->power_state
== PSCI_OFF
) {
308 bool powered_off
= (cpu
->power_state
== PSCI_OFF
) ? true : false;
309 qemu_put_byte(f
, powered_off
);
316 static const VMStateInfo vmstate_powered_off
= {
317 .name
= "powered_off",
322 static void cpu_pre_save(void *opaque
)
324 ARMCPU
*cpu
= opaque
;
327 if (!write_kvmstate_to_list(cpu
)) {
328 /* This should never fail */
332 if (!write_cpustate_to_list(cpu
)) {
333 /* This should never fail. */
338 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
339 memcpy(cpu
->cpreg_vmstate_indexes
, cpu
->cpreg_indexes
,
340 cpu
->cpreg_array_len
* sizeof(uint64_t));
341 memcpy(cpu
->cpreg_vmstate_values
, cpu
->cpreg_values
,
342 cpu
->cpreg_array_len
* sizeof(uint64_t));
345 static int cpu_post_load(void *opaque
, int version_id
)
347 ARMCPU
*cpu
= opaque
;
350 /* Update the values list from the incoming migration data.
351 * Anything in the incoming data which we don't know about is
352 * a migration failure; anything we know about but the incoming
353 * data doesn't specify retains its current (reset) value.
354 * The indexes list remains untouched -- we only inspect the
355 * incoming migration index list so we can match the values array
356 * entries with the right slots in our own values array.
359 for (i
= 0, v
= 0; i
< cpu
->cpreg_array_len
360 && v
< cpu
->cpreg_vmstate_array_len
; i
++) {
361 if (cpu
->cpreg_vmstate_indexes
[v
] > cpu
->cpreg_indexes
[i
]) {
362 /* register in our list but not incoming : skip it */
365 if (cpu
->cpreg_vmstate_indexes
[v
] < cpu
->cpreg_indexes
[i
]) {
366 /* register in their list but not ours: fail migration */
369 /* matching register, copy the value over */
370 cpu
->cpreg_values
[i
] = cpu
->cpreg_vmstate_values
[v
];
375 if (!write_list_to_kvmstate(cpu
, KVM_PUT_FULL_STATE
)) {
378 /* Note that it's OK for the TCG side not to know about
379 * every register in the list; KVM is authoritative if
382 write_list_to_cpustate(cpu
);
384 if (!write_list_to_cpustate(cpu
)) {
389 hw_breakpoint_update_all(cpu
);
390 hw_watchpoint_update_all(cpu
);
395 const VMStateDescription vmstate_arm_cpu
= {
398 .minimum_version_id
= 22,
399 .pre_save
= cpu_pre_save
,
400 .post_load
= cpu_post_load
,
401 .fields
= (VMStateField
[]) {
402 VMSTATE_UINT32_ARRAY(env
.regs
, ARMCPU
, 16),
403 VMSTATE_UINT64_ARRAY(env
.xregs
, ARMCPU
, 32),
404 VMSTATE_UINT64(env
.pc
, ARMCPU
),
408 .size
= sizeof(uint32_t),
409 .info
= &vmstate_cpsr
,
413 VMSTATE_UINT32(env
.spsr
, ARMCPU
),
414 VMSTATE_UINT64_ARRAY(env
.banked_spsr
, ARMCPU
, 8),
415 VMSTATE_UINT32_ARRAY(env
.banked_r13
, ARMCPU
, 8),
416 VMSTATE_UINT32_ARRAY(env
.banked_r14
, ARMCPU
, 8),
417 VMSTATE_UINT32_ARRAY(env
.usr_regs
, ARMCPU
, 5),
418 VMSTATE_UINT32_ARRAY(env
.fiq_regs
, ARMCPU
, 5),
419 VMSTATE_UINT64_ARRAY(env
.elr_el
, ARMCPU
, 4),
420 VMSTATE_UINT64_ARRAY(env
.sp_el
, ARMCPU
, 4),
421 /* The length-check must come before the arrays to avoid
422 * incoming data possibly overflowing the array.
424 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len
, ARMCPU
),
425 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes
, ARMCPU
,
426 cpreg_vmstate_array_len
,
427 0, vmstate_info_uint64
, uint64_t),
428 VMSTATE_VARRAY_INT32(cpreg_vmstate_values
, ARMCPU
,
429 cpreg_vmstate_array_len
,
430 0, vmstate_info_uint64
, uint64_t),
431 VMSTATE_UINT64(env
.exclusive_addr
, ARMCPU
),
432 VMSTATE_UINT64(env
.exclusive_val
, ARMCPU
),
433 VMSTATE_UINT64(env
.exclusive_high
, ARMCPU
),
434 VMSTATE_UINT64(env
.features
, ARMCPU
),
435 VMSTATE_UINT32(env
.exception
.syndrome
, ARMCPU
),
436 VMSTATE_UINT32(env
.exception
.fsr
, ARMCPU
),
437 VMSTATE_UINT64(env
.exception
.vaddress
, ARMCPU
),
438 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_PHYS
], ARMCPU
),
439 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_VIRT
], ARMCPU
),
441 .name
= "power_state",
443 .size
= sizeof(bool),
444 .info
= &vmstate_powered_off
,
448 VMSTATE_END_OF_LIST()
450 .subsections
= (const VMStateDescription
*[]) {
455 /* pmsav7_rnr must come before pmsav7 so that we have the
456 * region number before we test it in the VMSTATE_VALIDATE