2 * ARM page table walking.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/range.h"
12 #include "qemu/main-loop.h"
13 #include "exec/exec-all.h"
15 #include "internals.h"
19 typedef struct S1Translate
{
32 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
34 MMUAccessType access_type
, bool s1_is_el0
,
35 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
36 __attribute__((nonnull
));
38 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
40 MMUAccessType access_type
,
41 GetPhysAddrResult
*result
,
43 __attribute__((nonnull
));
45 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
46 static const uint8_t pamax_map
[] = {
56 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
57 unsigned int arm_pamax(ARMCPU
*cpu
)
59 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
60 unsigned int parange
=
61 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
64 * id_aa64mmfr0 is a read-only register so values outside of the
65 * supported mappings can be considered an implementation error.
67 assert(parange
< ARRAY_SIZE(pamax_map
));
68 return pamax_map
[parange
];
72 * In machvirt_init, we call arm_pamax on a cpu that is not fully
73 * initialized, so we can't rely on the propagation done in realize.
75 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
) ||
76 arm_feature(&cpu
->env
, ARM_FEATURE_V7VE
)) {
85 * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
87 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
91 return ARMMMUIdx_Stage1_E0
;
93 return ARMMMUIdx_Stage1_E1
;
94 case ARMMMUIdx_E10_1_PAN
:
95 return ARMMMUIdx_Stage1_E1_PAN
;
101 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
103 return stage_1_mmu_idx(arm_mmu_idx(env
));
106 static bool regime_translation_big_endian(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
108 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
111 /* Return the TTBR associated with this translation regime */
112 static uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ttbrn
)
114 if (mmu_idx
== ARMMMUIdx_Stage2
) {
115 return env
->cp15
.vttbr_el2
;
117 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
118 return env
->cp15
.vsttbr_el2
;
121 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
123 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
127 /* Return true if the specified stage of address translation is disabled */
128 static bool regime_translation_disabled(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
133 if (arm_feature(env
, ARM_FEATURE_M
)) {
134 switch (env
->v7m
.mpu_ctrl
[is_secure
] &
135 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
136 case R_V7M_MPU_CTRL_ENABLE_MASK
:
137 /* Enabled, but not for HardFault and NMI */
138 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
139 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
140 /* Enabled for all cases */
145 * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
146 * we warned about that in armv7m_nvic.c when the guest set it.
152 hcr_el2
= arm_hcr_el2_eff_secstate(env
, is_secure
);
155 case ARMMMUIdx_Stage2
:
156 case ARMMMUIdx_Stage2_S
:
157 /* HCR.DC means HCR.VM behaves as 1 */
158 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
160 case ARMMMUIdx_E10_0
:
161 case ARMMMUIdx_E10_1
:
162 case ARMMMUIdx_E10_1_PAN
:
163 /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
164 if (hcr_el2
& HCR_TGE
) {
169 case ARMMMUIdx_Stage1_E0
:
170 case ARMMMUIdx_Stage1_E1
:
171 case ARMMMUIdx_Stage1_E1_PAN
:
172 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
173 if (hcr_el2
& HCR_DC
) {
178 case ARMMMUIdx_E20_0
:
179 case ARMMMUIdx_E20_2
:
180 case ARMMMUIdx_E20_2_PAN
:
185 case ARMMMUIdx_Phys_NS
:
186 case ARMMMUIdx_Phys_S
:
187 /* No translation for physical address spaces. */
191 g_assert_not_reached();
194 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
197 static bool S2_attrs_are_device(uint64_t hcr
, uint8_t attrs
)
200 * For an S1 page table walk, the stage 1 attributes are always
201 * some form of "this is Normal memory". The combined S1+S2
202 * attributes are therefore only Device if stage 2 specifies Device.
203 * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
204 * ie when cacheattrs.attrs bits [3:2] are 0b00.
205 * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
206 * when cacheattrs.attrs bit [2] is 0.
209 return (attrs
& 0x4) == 0;
211 return (attrs
& 0xc) == 0;
215 /* Translate a S1 pagetable walk through S2 if needed. */
216 static bool S1_ptw_translate(CPUARMState
*env
, S1Translate
*ptw
,
217 hwaddr addr
, ARMMMUFaultInfo
*fi
)
219 bool is_secure
= ptw
->in_secure
;
220 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
221 ARMMMUIdx s2_mmu_idx
= ptw
->in_ptw_idx
;
225 ptw
->out_virt
= addr
;
227 if (unlikely(ptw
->in_debug
)) {
229 * From gdbstub, do not use softmmu so that we don't modify the
230 * state of the cpu at all, including softmmu tlb contents.
232 if (regime_is_stage2(s2_mmu_idx
)) {
233 S1Translate s2ptw
= {
234 .in_mmu_idx
= s2_mmu_idx
,
235 .in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
,
236 .in_secure
= is_secure
,
239 GetPhysAddrResult s2
= { };
241 if (!get_phys_addr_lpae(env
, &s2ptw
, addr
, MMU_DATA_LOAD
,
245 ptw
->out_phys
= s2
.f
.phys_addr
;
246 pte_attrs
= s2
.cacheattrs
.attrs
;
247 pte_secure
= s2
.f
.attrs
.secure
;
249 /* Regime is physical. */
250 ptw
->out_phys
= addr
;
252 pte_secure
= is_secure
;
254 ptw
->out_host
= NULL
;
257 CPUTLBEntryFull
*full
;
261 flags
= probe_access_full(env
, addr
, MMU_DATA_LOAD
,
262 arm_to_core_mmu_idx(s2_mmu_idx
),
263 true, &ptw
->out_host
, &full
, 0);
266 if (unlikely(flags
& TLB_INVALID_MASK
)) {
269 ptw
->out_phys
= full
->phys_addr
;
270 ptw
->out_rw
= full
->prot
& PAGE_WRITE
;
271 pte_attrs
= full
->pte_attrs
;
272 pte_secure
= full
->attrs
.secure
;
275 if (regime_is_stage2(s2_mmu_idx
)) {
276 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
278 if ((hcr
& HCR_PTW
) && S2_attrs_are_device(hcr
, pte_attrs
)) {
280 * PTW set and S1 walk touched S2 Device memory:
281 * generate Permission fault.
283 fi
->type
= ARMFault_Permission
;
287 fi
->s1ns
= !is_secure
;
292 /* Check if page table walk is to secure or non-secure PA space. */
293 ptw
->out_secure
= (is_secure
295 ? env
->cp15
.vstcr_el2
& VSTCR_SW
296 : env
->cp15
.vtcr_el2
& VTCR_NSW
));
297 ptw
->out_be
= regime_translation_big_endian(env
, mmu_idx
);
301 assert(fi
->type
!= ARMFault_None
);
305 fi
->s1ns
= !is_secure
;
309 /* All loads done in the course of a page table walk go through here. */
310 static uint32_t arm_ldl_ptw(CPUARMState
*env
, S1Translate
*ptw
,
313 CPUState
*cs
= env_cpu(env
);
314 void *host
= ptw
->out_host
;
318 /* Page tables are in RAM, and we have the host address. */
319 data
= qatomic_read((uint32_t *)host
);
321 data
= be32_to_cpu(data
);
323 data
= le32_to_cpu(data
);
326 /* Page tables are in MMIO. */
327 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
328 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
329 MemTxResult result
= MEMTX_OK
;
332 data
= address_space_ldl_be(as
, ptw
->out_phys
, attrs
, &result
);
334 data
= address_space_ldl_le(as
, ptw
->out_phys
, attrs
, &result
);
336 if (unlikely(result
!= MEMTX_OK
)) {
337 fi
->type
= ARMFault_SyncExternalOnWalk
;
338 fi
->ea
= arm_extabort_type(result
);
345 static uint64_t arm_ldq_ptw(CPUARMState
*env
, S1Translate
*ptw
,
348 CPUState
*cs
= env_cpu(env
);
349 void *host
= ptw
->out_host
;
353 /* Page tables are in RAM, and we have the host address. */
354 #ifdef CONFIG_ATOMIC64
355 data
= qatomic_read__nocheck((uint64_t *)host
);
357 data
= be64_to_cpu(data
);
359 data
= le64_to_cpu(data
);
363 data
= ldq_be_p(host
);
365 data
= ldq_le_p(host
);
369 /* Page tables are in MMIO. */
370 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
371 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
372 MemTxResult result
= MEMTX_OK
;
375 data
= address_space_ldq_be(as
, ptw
->out_phys
, attrs
, &result
);
377 data
= address_space_ldq_le(as
, ptw
->out_phys
, attrs
, &result
);
379 if (unlikely(result
!= MEMTX_OK
)) {
380 fi
->type
= ARMFault_SyncExternalOnWalk
;
381 fi
->ea
= arm_extabort_type(result
);
388 static uint64_t arm_casq_ptw(CPUARMState
*env
, uint64_t old_val
,
389 uint64_t new_val
, S1Translate
*ptw
,
393 void *host
= ptw
->out_host
;
395 if (unlikely(!host
)) {
396 fi
->type
= ARMFault_UnsuppAtomicUpdate
;
402 * Raising a stage2 Protection fault for an atomic update to a read-only
403 * page is delayed until it is certain that there is a change to make.
405 if (unlikely(!ptw
->out_rw
)) {
410 flags
= probe_access_flags(env
, ptw
->out_virt
, MMU_DATA_STORE
,
411 arm_to_core_mmu_idx(ptw
->in_ptw_idx
),
415 if (unlikely(flags
& TLB_INVALID_MASK
)) {
416 assert(fi
->type
!= ARMFault_None
);
417 fi
->s2addr
= ptw
->out_virt
;
420 fi
->s1ns
= !ptw
->in_secure
;
424 /* In case CAS mismatches and we loop, remember writability. */
428 #ifdef CONFIG_ATOMIC64
430 old_val
= cpu_to_be64(old_val
);
431 new_val
= cpu_to_be64(new_val
);
432 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
433 cur_val
= be64_to_cpu(cur_val
);
435 old_val
= cpu_to_le64(old_val
);
436 new_val
= cpu_to_le64(new_val
);
437 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
438 cur_val
= le64_to_cpu(cur_val
);
442 * We can't support the full 64-bit atomic cmpxchg on the host.
443 * Because this is only used for FEAT_HAFDBS, which is only for AA64,
444 * we know that TCG_OVERSIZED_GUEST is set, which means that we are
445 * running in round-robin mode and could only race with dma i/o.
447 #ifndef TCG_OVERSIZED_GUEST
448 # error "Unexpected configuration"
450 bool locked
= qemu_mutex_iothread_locked();
452 qemu_mutex_lock_iothread();
455 cur_val
= ldq_be_p(host
);
456 if (cur_val
== old_val
) {
457 stq_be_p(host
, new_val
);
460 cur_val
= ldq_le_p(host
);
461 if (cur_val
== old_val
) {
462 stq_le_p(host
, new_val
);
466 qemu_mutex_unlock_iothread();
473 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
474 uint32_t *table
, uint32_t address
)
476 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
477 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
478 int maskshift
= extract32(tcr
, 0, 3);
479 uint32_t mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
482 if (address
& mask
) {
483 if (tcr
& TTBCR_PD1
) {
484 /* Translation table walk disabled for TTBR1 */
487 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
489 if (tcr
& TTBCR_PD0
) {
490 /* Translation table walk disabled for TTBR0 */
493 base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
494 *table
= regime_ttbr(env
, mmu_idx
, 0) & base_mask
;
496 *table
|= (address
>> 18) & 0x3ffc;
501 * Translate section/page access permissions to page R/W protection flags
503 * @mmu_idx: MMU index indicating required translation regime
504 * @ap: The 3-bit access permissions (AP[2:0])
505 * @domain_prot: The 2-bit domain access permissions
507 static int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
508 int ap
, int domain_prot
)
510 bool is_user
= regime_is_user(env
, mmu_idx
);
512 if (domain_prot
== 3) {
513 return PAGE_READ
| PAGE_WRITE
;
518 if (arm_feature(env
, ARM_FEATURE_V7
)) {
521 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
523 return is_user
? 0 : PAGE_READ
;
530 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
535 return PAGE_READ
| PAGE_WRITE
;
538 return PAGE_READ
| PAGE_WRITE
;
539 case 4: /* Reserved. */
542 return is_user
? 0 : PAGE_READ
;
546 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
551 g_assert_not_reached();
556 * Translate section/page access permissions to page R/W protection flags.
557 * @ap: The 2-bit simple AP (AP[2:1])
558 * @is_user: TRUE if accessing from PL0
560 static int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
564 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
566 return PAGE_READ
| PAGE_WRITE
;
568 return is_user
? 0 : PAGE_READ
;
572 g_assert_not_reached();
576 static int simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
578 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
581 static bool get_phys_addr_v5(CPUARMState
*env
, S1Translate
*ptw
,
582 uint32_t address
, MMUAccessType access_type
,
583 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
595 /* Pagetable walk. */
596 /* Lookup l1 descriptor. */
597 if (!get_level1_table_address(env
, ptw
->in_mmu_idx
, &table
, address
)) {
598 /* Section translation fault if page walk is disabled by PD0 or PD1 */
599 fi
->type
= ARMFault_Translation
;
602 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
605 desc
= arm_ldl_ptw(env
, ptw
, fi
);
606 if (fi
->type
!= ARMFault_None
) {
610 domain
= (desc
>> 5) & 0x0f;
611 if (regime_el(env
, ptw
->in_mmu_idx
) == 1) {
612 dacr
= env
->cp15
.dacr_ns
;
614 dacr
= env
->cp15
.dacr_s
;
616 domain_prot
= (dacr
>> (domain
* 2)) & 3;
618 /* Section translation fault. */
619 fi
->type
= ARMFault_Translation
;
625 if (domain_prot
== 0 || domain_prot
== 2) {
626 fi
->type
= ARMFault_Domain
;
631 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
632 ap
= (desc
>> 10) & 3;
633 result
->f
.lg_page_size
= 20; /* 1MB */
635 /* Lookup l2 entry. */
637 /* Coarse pagetable. */
638 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
640 /* Fine pagetable. */
641 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
643 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
646 desc
= arm_ldl_ptw(env
, ptw
, fi
);
647 if (fi
->type
!= ARMFault_None
) {
651 case 0: /* Page translation fault. */
652 fi
->type
= ARMFault_Translation
;
654 case 1: /* 64k page. */
655 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
656 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
657 result
->f
.lg_page_size
= 16;
659 case 2: /* 4k page. */
660 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
661 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
662 result
->f
.lg_page_size
= 12;
664 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
666 /* ARMv6/XScale extended small page format */
667 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
668 || arm_feature(env
, ARM_FEATURE_V6
)) {
669 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
670 result
->f
.lg_page_size
= 12;
673 * UNPREDICTABLE in ARMv5; we choose to take a
674 * page translation fault.
676 fi
->type
= ARMFault_Translation
;
680 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
681 result
->f
.lg_page_size
= 10;
683 ap
= (desc
>> 4) & 3;
686 /* Never happens, but compiler isn't smart enough to tell. */
687 g_assert_not_reached();
690 result
->f
.prot
= ap_to_rw_prot(env
, ptw
->in_mmu_idx
, ap
, domain_prot
);
691 result
->f
.prot
|= result
->f
.prot
? PAGE_EXEC
: 0;
692 if (!(result
->f
.prot
& (1 << access_type
))) {
693 /* Access permission fault. */
694 fi
->type
= ARMFault_Permission
;
697 result
->f
.phys_addr
= phys_addr
;
705 static bool get_phys_addr_v6(CPUARMState
*env
, S1Translate
*ptw
,
706 uint32_t address
, MMUAccessType access_type
,
707 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
709 ARMCPU
*cpu
= env_archcpu(env
);
710 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
724 /* Pagetable walk. */
725 /* Lookup l1 descriptor. */
726 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
727 /* Section translation fault if page walk is disabled by PD0 or PD1 */
728 fi
->type
= ARMFault_Translation
;
731 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
734 desc
= arm_ldl_ptw(env
, ptw
, fi
);
735 if (fi
->type
!= ARMFault_None
) {
739 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
740 /* Section translation fault, or attempt to use the encoding
741 * which is Reserved on implementations without PXN.
743 fi
->type
= ARMFault_Translation
;
746 if ((type
== 1) || !(desc
& (1 << 18))) {
747 /* Page or Section. */
748 domain
= (desc
>> 5) & 0x0f;
750 if (regime_el(env
, mmu_idx
) == 1) {
751 dacr
= env
->cp15
.dacr_ns
;
753 dacr
= env
->cp15
.dacr_s
;
758 domain_prot
= (dacr
>> (domain
* 2)) & 3;
759 if (domain_prot
== 0 || domain_prot
== 2) {
760 /* Section or Page domain fault */
761 fi
->type
= ARMFault_Domain
;
765 if (desc
& (1 << 18)) {
767 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
768 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
769 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
770 result
->f
.lg_page_size
= 24; /* 16MB */
773 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
774 result
->f
.lg_page_size
= 20; /* 1MB */
776 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
777 xn
= desc
& (1 << 4);
779 ns
= extract32(desc
, 19, 1);
781 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
782 pxn
= (desc
>> 2) & 1;
784 ns
= extract32(desc
, 3, 1);
785 /* Lookup l2 entry. */
786 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
787 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
790 desc
= arm_ldl_ptw(env
, ptw
, fi
);
791 if (fi
->type
!= ARMFault_None
) {
794 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
796 case 0: /* Page translation fault. */
797 fi
->type
= ARMFault_Translation
;
799 case 1: /* 64k page. */
800 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
801 xn
= desc
& (1 << 15);
802 result
->f
.lg_page_size
= 16;
804 case 2: case 3: /* 4k page. */
805 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
807 result
->f
.lg_page_size
= 12;
810 /* Never happens, but compiler isn't smart enough to tell. */
811 g_assert_not_reached();
814 if (domain_prot
== 3) {
815 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
817 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
820 if (xn
&& access_type
== MMU_INST_FETCH
) {
821 fi
->type
= ARMFault_Permission
;
825 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
826 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
827 /* The simplified model uses AP[0] as an access control bit. */
829 /* Access flag fault. */
830 fi
->type
= ARMFault_AccessFlag
;
833 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
835 result
->f
.prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
837 if (result
->f
.prot
&& !xn
) {
838 result
->f
.prot
|= PAGE_EXEC
;
840 if (!(result
->f
.prot
& (1 << access_type
))) {
841 /* Access permission fault. */
842 fi
->type
= ARMFault_Permission
;
847 /* The NS bit will (as required by the architecture) have no effect if
848 * the CPU doesn't support TZ or this is a non-secure translation
849 * regime, because the attribute will already be non-secure.
851 result
->f
.attrs
.secure
= false;
853 result
->f
.phys_addr
= phys_addr
;
862 * Translate S2 section/page access permissions to protection flags
864 * @s2ap: The 2-bit stage2 access permissions (S2AP)
865 * @xn: XN (execute-never) bits
866 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
868 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
879 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
897 g_assert_not_reached();
900 if (!extract32(xn
, 1, 1)) {
901 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
910 * Translate section/page access permissions to protection flags
912 * @mmu_idx: MMU index indicating required translation regime
913 * @is_aa64: TRUE if AArch64
914 * @ap: The 2-bit simple AP (AP[2:1])
915 * @ns: NS (non-secure) bit
916 * @xn: XN (execute-never) bit
917 * @pxn: PXN (privileged execute-never) bit
919 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
920 int ap
, int ns
, int xn
, int pxn
)
922 bool is_user
= regime_is_user(env
, mmu_idx
);
923 int prot_rw
, user_rw
;
927 assert(!regime_is_stage2(mmu_idx
));
929 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
933 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
934 /* PAN forbids data accesses but doesn't affect insn fetch */
937 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
941 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
945 /* TODO have_wxn should be replaced with
946 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
947 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
948 * compatible processors have EL2, which is required for [U]WXN.
950 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
953 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
957 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
958 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
960 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
961 switch (regime_el(env
, mmu_idx
)) {
965 xn
= xn
|| !(user_rw
& PAGE_READ
);
969 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
971 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
972 (uwxn
&& (user_rw
& PAGE_WRITE
));
982 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
985 return prot_rw
| PAGE_EXEC
;
988 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
991 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
992 uint32_t el
= regime_el(env
, mmu_idx
);
996 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
998 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1000 bool sext
= extract32(tcr
, 4, 1);
1001 bool sign
= extract32(tcr
, 3, 1);
1004 * If the sign-extend bit is not the same as t0sz[3], the result
1005 * is unpredictable. Flag this as a guest error.
1008 qemu_log_mask(LOG_GUEST_ERROR
,
1009 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
1011 tsz
= sextract32(tcr
, 0, 4) + 8;
1015 } else if (el
== 2) {
1017 tsz
= extract32(tcr
, 0, 3);
1019 hpd
= extract64(tcr
, 24, 1);
1022 int t0sz
= extract32(tcr
, 0, 3);
1023 int t1sz
= extract32(tcr
, 16, 3);
1026 select
= va
> (0xffffffffu
>> t0sz
);
1028 /* Note that we will detect errors later. */
1029 select
= va
>= ~(0xffffffffu
>> t1sz
);
1033 epd
= extract32(tcr
, 7, 1);
1034 hpd
= extract64(tcr
, 41, 1);
1037 epd
= extract32(tcr
, 23, 1);
1038 hpd
= extract64(tcr
, 42, 1);
1040 /* For aarch32, hpd0 is not enabled without t2e as well. */
1041 hpd
&= extract32(tcr
, 6, 1);
1044 return (ARMVAParameters
) {
1053 * check_s2_mmu_setup
1055 * @is_aa64: True if the translation regime is in AArch64 state
1056 * @startlevel: Suggested starting level
1057 * @inputsize: Bitsize of IPAs
1058 * @stride: Page-table stride (See the ARM ARM)
1060 * Returns true if the suggested S2 translation parameters are OK and
1063 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
1064 int inputsize
, int stride
, int outputsize
)
1066 const int grainsize
= stride
+ 3;
1070 * Negative levels are usually not allowed...
1071 * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
1072 * begins with level -1. Note that previous feature tests will have
1073 * eliminated this combination if it is not enabled.
1075 if (level
< (inputsize
== 52 && stride
== 9 ? -1 : 0)) {
1079 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
1080 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
1086 case 13: /* 64KB Pages. */
1087 if (level
== 0 || (level
== 1 && outputsize
<= 42)) {
1091 case 11: /* 16KB Pages. */
1092 if (level
== 0 || (level
== 1 && outputsize
<= 40)) {
1096 case 9: /* 4KB Pages. */
1097 if (level
== 0 && outputsize
<= 42) {
1102 g_assert_not_reached();
1105 /* Inputsize checks. */
1106 if (inputsize
> outputsize
&&
1107 (arm_el_is_aa64(&cpu
->env
, 1) || inputsize
> 40)) {
1108 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
1112 /* AArch32 only supports 4KB pages. Assert on that. */
1113 assert(stride
== 9);
1123 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
1125 * Returns false if the translation was successful. Otherwise, phys_ptr,
1126 * attrs, prot and page_size may not be filled in, and the populated fsr
1127 * value provides information on why the translation aborted, in the format
1128 * of a long-format DFSR/IFSR fault register, with the following caveat:
1129 * the WnR bit is never set (the caller must do this).
1132 * @ptw: Current and next stage parameters for the walk.
1133 * @address: virtual address to get physical address for
1134 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
1135 * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
1136 * (so this is a stage 2 page table walk),
1137 * must be true if this is stage 2 of a stage 1+2
1138 * walk for an EL0 access. If @mmu_idx is anything else,
1139 * @s1_is_el0 is ignored.
1140 * @result: set on translation success,
1141 * @fi: set to fault info if the translation fails
1143 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
1145 MMUAccessType access_type
, bool s1_is_el0
,
1146 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1148 ARMCPU
*cpu
= env_archcpu(env
);
1149 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1150 bool is_secure
= ptw
->in_secure
;
1152 ARMVAParameters param
;
1154 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
1155 uint32_t tableattrs
;
1156 target_ulong page_size
;
1159 int addrsize
, inputsize
, outputsize
;
1160 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1161 int ap
, ns
, xn
, pxn
;
1162 uint32_t el
= regime_el(env
, mmu_idx
);
1163 uint64_t descaddrmask
;
1164 bool aarch64
= arm_el_is_aa64(env
, el
);
1165 uint64_t descriptor
, new_descriptor
;
1168 /* TODO: This code does not support shareability levels. */
1172 param
= aa64_va_parameters(env
, address
, mmu_idx
,
1173 access_type
!= MMU_INST_FETCH
);
1177 * If TxSZ is programmed to a value larger than the maximum,
1178 * or smaller than the effective minimum, it is IMPLEMENTATION
1179 * DEFINED whether we behave as if the field were programmed
1180 * within bounds, or if a level 0 Translation fault is generated.
1182 * With FEAT_LVA, fault on less than minimum becomes required,
1183 * so our choice is to always raise the fault.
1185 if (param
.tsz_oob
) {
1186 goto do_translation_fault
;
1189 addrsize
= 64 - 8 * param
.tbi
;
1190 inputsize
= 64 - param
.tsz
;
1193 * Bound PS by PARANGE to find the effective output address size.
1194 * ID_AA64MMFR0 is a read-only register so values outside of the
1195 * supported mappings can be considered an implementation error.
1197 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
1198 ps
= MIN(ps
, param
.ps
);
1199 assert(ps
< ARRAY_SIZE(pamax_map
));
1200 outputsize
= pamax_map
[ps
];
1202 param
= aa32_va_parameters(env
, address
, mmu_idx
);
1204 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
1205 inputsize
= addrsize
- param
.tsz
;
1210 * We determined the region when collecting the parameters, but we
1211 * have not yet validated that the address is valid for the region.
1212 * Extract the top bits and verify that they all match select.
1214 * For aa32, if inputsize == addrsize, then we have selected the
1215 * region by exclusion in aa32_va_parameters and there is no more
1216 * validation to do here.
1218 if (inputsize
< addrsize
) {
1219 target_ulong top_bits
= sextract64(address
, inputsize
,
1220 addrsize
- inputsize
);
1221 if (-top_bits
!= param
.select
) {
1222 /* The gap between the two regions is a Translation fault */
1223 goto do_translation_fault
;
1227 stride
= arm_granule_bits(param
.gran
) - 3;
1230 * Note that QEMU ignores shareability and cacheability attributes,
1231 * so we don't need to do anything with the SH, ORGN, IRGN fields
1232 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
1233 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
1234 * implement any ASID-like capability so we can ignore it (instead
1235 * we will always flush the TLB any time the ASID is changed).
1237 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
1240 * Here we should have set up all the parameters for the translation:
1241 * inputsize, ttbr, epd, stride, tbi
1246 * Translation table walk disabled => Translation fault on TLB miss
1247 * Note: This is always 0 on 64-bit EL2 and EL3.
1249 goto do_translation_fault
;
1252 if (!regime_is_stage2(mmu_idx
)) {
1254 * The starting level depends on the virtual address size (which can
1255 * be up to 48 bits) and the translation granule size. It indicates
1256 * the number of strides (stride bits at a time) needed to
1257 * consume the bits of the input address. In the pseudocode this is:
1258 * level = 4 - RoundUp((inputsize - grainsize) / stride)
1259 * where their 'inputsize' is our 'inputsize', 'grainsize' is
1260 * our 'stride + 3' and 'stride' is our 'stride'.
1261 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
1262 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
1263 * = 4 - (inputsize - 4) / stride;
1265 level
= 4 - (inputsize
- 4) / stride
;
1268 * For stage 2 translations the starting level is specified by the
1269 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
1271 uint32_t sl0
= extract32(tcr
, 6, 2);
1272 uint32_t sl2
= extract64(tcr
, 33, 1);
1273 uint32_t startlevel
;
1276 /* SL2 is RES0 unless DS=1 & 4kb granule. */
1277 if (param
.ds
&& stride
== 9 && sl2
) {
1280 goto do_translation_fault
;
1283 } else if (!aarch64
|| stride
== 9) {
1284 /* AArch32 or 4KB pages */
1285 startlevel
= 2 - sl0
;
1287 if (cpu_isar_feature(aa64_st
, cpu
)) {
1291 /* 16KB or 64KB pages */
1292 startlevel
= 3 - sl0
;
1295 /* Check that the starting level is valid. */
1296 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
1297 inputsize
, stride
, outputsize
);
1299 goto do_translation_fault
;
1304 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
1305 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
1307 /* Now we can extract the actual base address from the TTBR */
1308 descaddr
= extract64(ttbr
, 0, 48);
1311 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
1313 * Otherwise, if the base address is out of range, raise AddressSizeFault.
1314 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
1315 * but we've just cleared the bits above 47, so simplify the test.
1317 if (outputsize
> 48) {
1318 descaddr
|= extract64(ttbr
, 2, 4) << 48;
1319 } else if (descaddr
>> outputsize
) {
1321 fi
->type
= ARMFault_AddressSize
;
1326 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
1327 * and also to mask out CnP (bit 0) which could validly be non-zero.
1329 descaddr
&= ~indexmask
;
1332 * For AArch32, the address field in the descriptor goes up to bit 39
1333 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
1334 * or an AddressSize fault is raised. So for v8 we extract those SBZ
1335 * bits as part of the address, which will be checked via outputsize.
1336 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
1337 * the highest bits of a 52-bit output are placed elsewhere.
1340 descaddrmask
= MAKE_64BIT_MASK(0, 50);
1341 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
1342 descaddrmask
= MAKE_64BIT_MASK(0, 48);
1344 descaddrmask
= MAKE_64BIT_MASK(0, 40);
1346 descaddrmask
&= ~indexmask_grainsize
;
1349 * Secure accesses start with the page table in secure memory and
1350 * can be downgraded to non-secure at any step. Non-secure accesses
1351 * remain non-secure. We implement this by just ORing in the NSTable/NS
1352 * bits at each step.
1354 tableattrs
= is_secure
? 0 : (1 << 4);
1357 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
1359 nstable
= extract32(tableattrs
, 4, 1);
1362 * Stage2_S -> Stage2 or Phys_S -> Phys_NS
1363 * Assert that the non-secure idx are even, and relative order.
1365 QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS
& 1) != 0);
1366 QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2
& 1) != 0);
1367 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS
+ 1 != ARMMMUIdx_Phys_S
);
1368 QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2
+ 1 != ARMMMUIdx_Stage2_S
);
1369 ptw
->in_ptw_idx
&= ~1;
1370 ptw
->in_secure
= false;
1372 if (!S1_ptw_translate(env
, ptw
, descaddr
, fi
)) {
1375 descriptor
= arm_ldq_ptw(env
, ptw
, fi
);
1376 if (fi
->type
!= ARMFault_None
) {
1379 new_descriptor
= descriptor
;
1381 restart_atomic_update
:
1382 if (!(descriptor
& 1) || (!(descriptor
& 2) && (level
== 3))) {
1383 /* Invalid, or the Reserved level 3 encoding */
1384 goto do_translation_fault
;
1387 descaddr
= descriptor
& descaddrmask
;
1390 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
1391 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
1392 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
1393 * raise AddressSizeFault.
1395 if (outputsize
> 48) {
1397 descaddr
|= extract64(descriptor
, 8, 2) << 50;
1399 descaddr
|= extract64(descriptor
, 12, 4) << 48;
1401 } else if (descaddr
>> outputsize
) {
1402 fi
->type
= ARMFault_AddressSize
;
1406 if ((descriptor
& 2) && (level
< 3)) {
1408 * Table entry. The top five bits are attributes which may
1409 * propagate down through lower levels of the table (and
1410 * which are all arranged so that 0 means "no effect", so
1411 * we can gather them up by ORing in the bits at each level).
1413 tableattrs
|= extract64(descriptor
, 59, 5);
1415 indexmask
= indexmask_grainsize
;
1420 * Block entry at level 1 or 2, or page entry at level 3.
1421 * These are basically the same thing, although the number
1422 * of bits we pull in from the vaddr varies. Note that although
1423 * descaddrmask masks enough of the low bits of the descriptor
1424 * to give a correct page or table address, the address field
1425 * in a block descriptor is smaller; so we need to explicitly
1426 * clear the lower bits here before ORing in the low vaddr bits.
1428 * Afterward, descaddr is the final physical address.
1430 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
1431 descaddr
&= ~(hwaddr
)(page_size
- 1);
1432 descaddr
|= (address
& (page_size
- 1));
1434 if (likely(!ptw
->in_debug
)) {
1437 * If HA is enabled, prepare to update the descriptor below.
1438 * Otherwise, pass the access fault on to software.
1440 if (!(descriptor
& (1 << 10))) {
1442 new_descriptor
|= 1 << 10; /* AF */
1444 fi
->type
= ARMFault_AccessFlag
;
1451 * Extract attributes from the (modified) descriptor, and apply
1452 * table descriptors. Stage 2 table descriptors do not include
1453 * any attribute fields. HPD disables all the table attributes
1456 attrs
= new_descriptor
& (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
1457 if (!regime_is_stage2(mmu_idx
)) {
1458 attrs
|= nstable
<< 5; /* NS */
1460 attrs
|= extract64(tableattrs
, 0, 2) << 53; /* XN, PXN */
1462 * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
1463 * means "force PL1 access only", which means forcing AP[1] to 0.
1465 attrs
&= ~(extract64(tableattrs
, 2, 1) << 6); /* !APT[0] => AP[1] */
1466 attrs
|= extract32(tableattrs
, 3, 1) << 7; /* APT[1] => AP[2] */
1470 ap
= extract32(attrs
, 6, 2);
1471 if (regime_is_stage2(mmu_idx
)) {
1472 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1473 xn
= extract64(attrs
, 53, 2);
1474 result
->f
.prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
1476 ns
= extract32(attrs
, 5, 1);
1477 xn
= extract64(attrs
, 54, 1);
1478 pxn
= extract64(attrs
, 53, 1);
1479 result
->f
.prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
1482 if (!(result
->f
.prot
& (1 << access_type
))) {
1483 fi
->type
= ARMFault_Permission
;
1487 /* If FEAT_HAFDBS has made changes, update the PTE. */
1488 if (new_descriptor
!= descriptor
) {
1489 new_descriptor
= arm_casq_ptw(env
, descriptor
, new_descriptor
, ptw
, fi
);
1490 if (fi
->type
!= ARMFault_None
) {
1494 * I_YZSVV says that if the in-memory descriptor has changed,
1495 * then we must use the information in that new value
1496 * (which might include a different output address, different
1497 * attributes, or generate a fault).
1498 * Restart the handling of the descriptor value from scratch.
1500 if (new_descriptor
!= descriptor
) {
1501 descriptor
= new_descriptor
;
1502 goto restart_atomic_update
;
1508 * The NS bit will (as required by the architecture) have no effect if
1509 * the CPU doesn't support TZ or this is a non-secure translation
1510 * regime, because the attribute will already be non-secure.
1512 result
->f
.attrs
.secure
= false;
1515 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
1516 if (aarch64
&& cpu_isar_feature(aa64_bti
, cpu
)) {
1517 result
->f
.guarded
= extract64(attrs
, 50, 1); /* GP */
1520 if (regime_is_stage2(mmu_idx
)) {
1521 result
->cacheattrs
.is_s2_format
= true;
1522 result
->cacheattrs
.attrs
= extract32(attrs
, 2, 4);
1524 /* Index into MAIR registers for cache attributes */
1525 uint8_t attrindx
= extract32(attrs
, 2, 3);
1526 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
1527 assert(attrindx
<= 7);
1528 result
->cacheattrs
.is_s2_format
= false;
1529 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
1533 * For FEAT_LPA2 and effective DS, the SH field in the attributes
1534 * was re-purposed for output address bits. The SH attribute in
1535 * that case comes from TCR_ELx, which we extracted earlier.
1538 result
->cacheattrs
.shareability
= param
.sh
;
1540 result
->cacheattrs
.shareability
= extract32(attrs
, 8, 2);
1543 result
->f
.phys_addr
= descaddr
;
1544 result
->f
.lg_page_size
= ctz64(page_size
);
1547 do_translation_fault
:
1548 fi
->type
= ARMFault_Translation
;
1551 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
1552 fi
->stage2
= fi
->s1ptw
|| regime_is_stage2(mmu_idx
);
1553 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1557 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
1558 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1559 bool is_secure
, GetPhysAddrResult
*result
,
1560 ARMMMUFaultInfo
*fi
)
1565 bool is_user
= regime_is_user(env
, mmu_idx
);
1567 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
1569 result
->f
.phys_addr
= address
;
1570 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1574 result
->f
.phys_addr
= address
;
1575 for (n
= 7; n
>= 0; n
--) {
1576 base
= env
->cp15
.c6_region
[n
];
1577 if ((base
& 1) == 0) {
1580 mask
= 1 << ((base
>> 1) & 0x1f);
1581 /* Keep this shift separate from the above to avoid an
1582 (undefined) << 32. */
1583 mask
= (mask
<< 1) - 1;
1584 if (((base
^ address
) & ~mask
) == 0) {
1589 fi
->type
= ARMFault_Background
;
1593 if (access_type
== MMU_INST_FETCH
) {
1594 mask
= env
->cp15
.pmsav5_insn_ap
;
1596 mask
= env
->cp15
.pmsav5_data_ap
;
1598 mask
= (mask
>> (n
* 4)) & 0xf;
1601 fi
->type
= ARMFault_Permission
;
1606 fi
->type
= ARMFault_Permission
;
1610 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1613 result
->f
.prot
= PAGE_READ
;
1615 result
->f
.prot
|= PAGE_WRITE
;
1619 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1623 fi
->type
= ARMFault_Permission
;
1627 result
->f
.prot
= PAGE_READ
;
1630 result
->f
.prot
= PAGE_READ
;
1633 /* Bad permission. */
1634 fi
->type
= ARMFault_Permission
;
1638 result
->f
.prot
|= PAGE_EXEC
;
1642 static void get_phys_addr_pmsav7_default(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1643 int32_t address
, uint8_t *prot
)
1645 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1646 *prot
= PAGE_READ
| PAGE_WRITE
;
1648 case 0xF0000000 ... 0xFFFFFFFF:
1649 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
1650 /* hivecs execing is ok */
1654 case 0x00000000 ... 0x7FFFFFFF:
1659 /* Default system address map for M profile cores.
1660 * The architecture specifies which regions are execute-never;
1661 * at the MPU level no other checks are defined.
1664 case 0x00000000 ... 0x1fffffff: /* ROM */
1665 case 0x20000000 ... 0x3fffffff: /* SRAM */
1666 case 0x60000000 ... 0x7fffffff: /* RAM */
1667 case 0x80000000 ... 0x9fffffff: /* RAM */
1668 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1670 case 0x40000000 ... 0x5fffffff: /* Peripheral */
1671 case 0xa0000000 ... 0xbfffffff: /* Device */
1672 case 0xc0000000 ... 0xdfffffff: /* Device */
1673 case 0xe0000000 ... 0xffffffff: /* System */
1674 *prot
= PAGE_READ
| PAGE_WRITE
;
1677 g_assert_not_reached();
1682 static bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
1684 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
1685 return arm_feature(env
, ARM_FEATURE_M
) &&
1686 extract32(address
, 20, 12) == 0xe00;
1689 static bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
1692 * True if address is in the M profile system region
1693 * 0xe0000000 - 0xffffffff
1695 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
1698 static bool pmsav7_use_background_region(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
1699 bool is_secure
, bool is_user
)
1702 * Return true if we should use the default memory map as a
1703 * "background" region if there are no hits against any MPU regions.
1705 CPUARMState
*env
= &cpu
->env
;
1711 if (arm_feature(env
, ARM_FEATURE_M
)) {
1712 return env
->v7m
.mpu_ctrl
[is_secure
] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
1714 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
1718 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
1719 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1720 bool secure
, GetPhysAddrResult
*result
,
1721 ARMMMUFaultInfo
*fi
)
1723 ARMCPU
*cpu
= env_archcpu(env
);
1725 bool is_user
= regime_is_user(env
, mmu_idx
);
1727 result
->f
.phys_addr
= address
;
1728 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1731 if (regime_translation_disabled(env
, mmu_idx
, secure
) ||
1732 m_is_ppb_region(env
, address
)) {
1734 * MPU disabled or M profile PPB access: use default memory map.
1735 * The other case which uses the default memory map in the
1736 * v7M ARM ARM pseudocode is exception vector reads from the vector
1737 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
1738 * which always does a direct read using address_space_ldl(), rather
1739 * than going via this function, so we don't need to check that here.
1741 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
1742 } else { /* MPU enabled */
1743 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1745 uint32_t base
= env
->pmsav7
.drbar
[n
];
1746 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
1750 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
1755 qemu_log_mask(LOG_GUEST_ERROR
,
1756 "DRSR[%d]: Rsize field cannot be 0\n", n
);
1760 rmask
= (1ull << rsize
) - 1;
1763 qemu_log_mask(LOG_GUEST_ERROR
,
1764 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
1765 "to DRSR region size, mask = 0x%" PRIx32
"\n",
1770 if (address
< base
|| address
> base
+ rmask
) {
1772 * Address not in this region. We must check whether the
1773 * region covers addresses in the same page as our address.
1774 * In that case we must not report a size that covers the
1775 * whole page for a subsequent hit against a different MPU
1776 * region or the background region, because it would result in
1777 * incorrect TLB hits for subsequent accesses to addresses that
1778 * are in this MPU region.
1780 if (ranges_overlap(base
, rmask
,
1781 address
& TARGET_PAGE_MASK
,
1782 TARGET_PAGE_SIZE
)) {
1783 result
->f
.lg_page_size
= 0;
1788 /* Region matched */
1790 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
1792 uint32_t srdis_mask
;
1794 rsize
-= 3; /* sub region size (power of 2) */
1795 snd
= ((address
- base
) >> rsize
) & 0x7;
1796 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
1798 srdis_mask
= srdis
? 0x3 : 0x0;
1799 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
1801 * This will check in groups of 2, 4 and then 8, whether
1802 * the subregion bits are consistent. rsize is incremented
1803 * back up to give the region size, considering consistent
1804 * adjacent subregions as one region. Stop testing if rsize
1805 * is already big enough for an entire QEMU page.
1807 int snd_rounded
= snd
& ~(i
- 1);
1808 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
1809 snd_rounded
+ 8, i
);
1810 if (srdis_mask
^ srdis_multi
) {
1813 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
1820 if (rsize
< TARGET_PAGE_BITS
) {
1821 result
->f
.lg_page_size
= rsize
;
1826 if (n
== -1) { /* no hits */
1827 if (!pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1828 /* background fault */
1829 fi
->type
= ARMFault_Background
;
1832 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
,
1834 } else { /* a MPU hit! */
1835 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
1836 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
1838 if (m_is_system_region(env
, address
)) {
1839 /* System space is always execute never */
1843 if (is_user
) { /* User mode AP bit decoding */
1848 break; /* no access */
1850 result
->f
.prot
|= PAGE_WRITE
;
1854 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1857 /* for v7M, same as 6; for R profile a reserved value */
1858 if (arm_feature(env
, ARM_FEATURE_M
)) {
1859 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1864 qemu_log_mask(LOG_GUEST_ERROR
,
1865 "DRACR[%d]: Bad value for AP bits: 0x%"
1866 PRIx32
"\n", n
, ap
);
1868 } else { /* Priv. mode AP bits decoding */
1871 break; /* no access */
1875 result
->f
.prot
|= PAGE_WRITE
;
1879 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1882 /* for v7M, same as 6; for R profile a reserved value */
1883 if (arm_feature(env
, ARM_FEATURE_M
)) {
1884 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1889 qemu_log_mask(LOG_GUEST_ERROR
,
1890 "DRACR[%d]: Bad value for AP bits: 0x%"
1891 PRIx32
"\n", n
, ap
);
1897 result
->f
.prot
&= ~PAGE_EXEC
;
1902 fi
->type
= ARMFault_Permission
;
1904 return !(result
->f
.prot
& (1 << access_type
));
1907 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
1908 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1909 bool secure
, GetPhysAddrResult
*result
,
1910 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
1913 * Perform a PMSAv8 MPU lookup (without also doing the SAU check
1914 * that a full phys-to-virt translation does).
1915 * mregion is (if not NULL) set to the region number which matched,
1916 * or -1 if no region number is returned (MPU off, address did not
1917 * hit a region, address hit in multiple regions).
1918 * If the region hit doesn't cover the entire TARGET_PAGE the address
1919 * is within, then we set the result page_size to 1 to force the
1920 * memory system to use a subpage.
1922 ARMCPU
*cpu
= env_archcpu(env
);
1923 bool is_user
= regime_is_user(env
, mmu_idx
);
1925 int matchregion
= -1;
1927 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
1928 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
1930 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1931 result
->f
.phys_addr
= address
;
1938 * Unlike the ARM ARM pseudocode, we don't need to check whether this
1939 * was an exception vector read from the vector table (which is always
1940 * done using the default system address map), because those accesses
1941 * are done in arm_v7m_load_vector(), which always does a direct
1942 * read using address_space_ldl(), rather than going via this function.
1944 if (regime_translation_disabled(env
, mmu_idx
, secure
)) { /* MPU disabled */
1946 } else if (m_is_ppb_region(env
, address
)) {
1949 if (pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1953 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1956 * Note that the base address is bits [31:5] from the register
1957 * with bits [4:0] all zeroes, but the limit address is bits
1958 * [31:5] from the register with bits [4:0] all ones.
1960 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
1961 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
1963 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
1964 /* Region disabled */
1968 if (address
< base
|| address
> limit
) {
1970 * Address not in this region. We must check whether the
1971 * region covers addresses in the same page as our address.
1972 * In that case we must not report a size that covers the
1973 * whole page for a subsequent hit against a different MPU
1974 * region or the background region, because it would result in
1975 * incorrect TLB hits for subsequent accesses to addresses that
1976 * are in this MPU region.
1978 if (limit
>= base
&&
1979 ranges_overlap(base
, limit
- base
+ 1,
1981 TARGET_PAGE_SIZE
)) {
1982 result
->f
.lg_page_size
= 0;
1987 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
1988 result
->f
.lg_page_size
= 0;
1991 if (matchregion
!= -1) {
1993 * Multiple regions match -- always a failure (unlike
1994 * PMSAv7 where highest-numbered-region wins)
1996 fi
->type
= ARMFault_Permission
;
2007 /* background fault */
2008 fi
->type
= ARMFault_Background
;
2012 if (matchregion
== -1) {
2013 /* hit using the background region */
2014 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
2016 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
2017 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
2020 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
2021 pxn
= extract32(env
->pmsav8
.rlar
[secure
][matchregion
], 4, 1);
2024 if (m_is_system_region(env
, address
)) {
2025 /* System space is always execute never */
2029 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
2030 if (result
->f
.prot
&& !xn
&& !(pxn
&& !is_user
)) {
2031 result
->f
.prot
|= PAGE_EXEC
;
2034 * We don't need to look the attribute up in the MAIR0/MAIR1
2035 * registers because that only tells us about cacheability.
2038 *mregion
= matchregion
;
2042 fi
->type
= ARMFault_Permission
;
2044 return !(result
->f
.prot
& (1 << access_type
));
2047 static bool v8m_is_sau_exempt(CPUARMState
*env
,
2048 uint32_t address
, MMUAccessType access_type
)
2051 * The architecture specifies that certain address ranges are
2052 * exempt from v8M SAU/IDAU checks.
2055 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
2056 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
2057 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
2058 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
2059 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
2060 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
2063 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
2064 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2065 bool is_secure
, V8M_SAttributes
*sattrs
)
2068 * Look up the security attributes for this address. Compare the
2069 * pseudocode SecurityCheck() function.
2070 * We assume the caller has zero-initialized *sattrs.
2072 ARMCPU
*cpu
= env_archcpu(env
);
2074 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
2075 int idau_region
= IREGION_NOTVALID
;
2076 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2077 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2080 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
2081 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
2083 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
2087 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
2088 /* 0xf0000000..0xffffffff is always S for insn fetches */
2092 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
2093 sattrs
->ns
= !is_secure
;
2097 if (idau_region
!= IREGION_NOTVALID
) {
2098 sattrs
->irvalid
= true;
2099 sattrs
->iregion
= idau_region
;
2102 switch (env
->sau
.ctrl
& 3) {
2103 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
2105 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
2108 default: /* SAU.ENABLE == 1 */
2109 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
2110 if (env
->sau
.rlar
[r
] & 1) {
2111 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
2112 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
2114 if (base
<= address
&& limit
>= address
) {
2115 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2116 sattrs
->subpage
= true;
2118 if (sattrs
->srvalid
) {
2120 * If we hit in more than one region then we must report
2121 * as Secure, not NS-Callable, with no valid region
2125 sattrs
->nsc
= false;
2126 sattrs
->sregion
= 0;
2127 sattrs
->srvalid
= false;
2130 if (env
->sau
.rlar
[r
] & 2) {
2135 sattrs
->srvalid
= true;
2136 sattrs
->sregion
= r
;
2140 * Address not in this region. We must check whether the
2141 * region covers addresses in the same page as our address.
2142 * In that case we must not report a size that covers the
2143 * whole page for a subsequent hit against a different MPU
2144 * region or the background region, because it would result
2145 * in incorrect TLB hits for subsequent accesses to
2146 * addresses that are in this MPU region.
2148 if (limit
>= base
&&
2149 ranges_overlap(base
, limit
- base
+ 1,
2151 TARGET_PAGE_SIZE
)) {
2152 sattrs
->subpage
= true;
2161 * The IDAU will override the SAU lookup results if it specifies
2162 * higher security than the SAU does.
2165 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
2167 sattrs
->nsc
= idau_nsc
;
2172 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
2173 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2174 bool secure
, GetPhysAddrResult
*result
,
2175 ARMMMUFaultInfo
*fi
)
2177 V8M_SAttributes sattrs
= {};
2180 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2181 v8m_security_lookup(env
, address
, access_type
, mmu_idx
,
2183 if (access_type
== MMU_INST_FETCH
) {
2185 * Instruction fetches always use the MMU bank and the
2186 * transaction attribute determined by the fetch address,
2187 * regardless of CPU state. This is painful for QEMU
2188 * to handle, because it would mean we need to encode
2189 * into the mmu_idx not just the (user, negpri) information
2190 * for the current security state but also that for the
2191 * other security state, which would balloon the number
2192 * of mmu_idx values needed alarmingly.
2193 * Fortunately we can avoid this because it's not actually
2194 * possible to arbitrarily execute code from memory with
2195 * the wrong security attribute: it will always generate
2196 * an exception of some kind or another, apart from the
2197 * special case of an NS CPU executing an SG instruction
2198 * in S&NSC memory. So we always just fail the translation
2199 * here and sort things out in the exception handler
2200 * (including possibly emulating an SG instruction).
2202 if (sattrs
.ns
!= !secure
) {
2204 fi
->type
= ARMFault_QEMU_NSCExec
;
2206 fi
->type
= ARMFault_QEMU_SFault
;
2208 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2209 result
->f
.phys_addr
= address
;
2215 * For data accesses we always use the MMU bank indicated
2216 * by the current CPU state, but the security attributes
2217 * might downgrade a secure access to nonsecure.
2220 result
->f
.attrs
.secure
= false;
2221 } else if (!secure
) {
2223 * NS access to S memory must fault.
2224 * Architecturally we should first check whether the
2225 * MPU information for this address indicates that we
2226 * are doing an unaligned access to Device memory, which
2227 * should generate a UsageFault instead. QEMU does not
2228 * currently check for that kind of unaligned access though.
2229 * If we added it we would need to do so as a special case
2230 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
2232 fi
->type
= ARMFault_QEMU_SFault
;
2233 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2234 result
->f
.phys_addr
= address
;
2241 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, secure
,
2243 if (sattrs
.subpage
) {
2244 result
->f
.lg_page_size
= 0;
2250 * Translate from the 4-bit stage 2 representation of
2251 * memory attributes (without cache-allocation hints) to
2252 * the 8-bit representation of the stage 1 MAIR registers
2253 * (which includes allocation hints).
2255 * ref: shared/translation/attrs/S2AttrDecode()
2256 * .../S2ConvertAttrsHints()
2258 static uint8_t convert_stage2_attrs(uint64_t hcr
, uint8_t s2attrs
)
2260 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
2261 uint8_t loattr
= extract32(s2attrs
, 0, 2);
2262 uint8_t hihint
= 0, lohint
= 0;
2264 if (hiattr
!= 0) { /* normal memory */
2265 if (hcr
& HCR_CD
) { /* cache disabled */
2266 hiattr
= loattr
= 1; /* non-cacheable */
2268 if (hiattr
!= 1) { /* Write-through or write-back */
2269 hihint
= 3; /* RW allocate */
2271 if (loattr
!= 1) { /* Write-through or write-back */
2272 lohint
= 3; /* RW allocate */
2277 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
2281 * Combine either inner or outer cacheability attributes for normal
2282 * memory, according to table D4-42 and pseudocode procedure
2283 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
2285 * NB: only stage 1 includes allocation hints (RW bits), leading to
2288 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
2290 if (s1
== 4 || s2
== 4) {
2291 /* non-cacheable has precedence */
2293 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
2294 /* stage 1 write-through takes precedence */
2296 } else if (extract32(s2
, 2, 2) == 2) {
2297 /* stage 2 write-through takes precedence, but the allocation hint
2298 * is still taken from stage 1
2300 return (2 << 2) | extract32(s1
, 0, 2);
2301 } else { /* write-back */
2307 * Combine the memory type and cacheability attributes of
2308 * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
2309 * combined attributes in MAIR_EL1 format.
2311 static uint8_t combined_attrs_nofwb(uint64_t hcr
,
2312 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2314 uint8_t s1lo
, s2lo
, s1hi
, s2hi
, s2_mair_attrs
, ret_attrs
;
2316 s2_mair_attrs
= convert_stage2_attrs(hcr
, s2
.attrs
);
2318 s1lo
= extract32(s1
.attrs
, 0, 4);
2319 s2lo
= extract32(s2_mair_attrs
, 0, 4);
2320 s1hi
= extract32(s1
.attrs
, 4, 4);
2321 s2hi
= extract32(s2_mair_attrs
, 4, 4);
2323 /* Combine memory type and cacheability attributes */
2324 if (s1hi
== 0 || s2hi
== 0) {
2325 /* Device has precedence over normal */
2326 if (s1lo
== 0 || s2lo
== 0) {
2327 /* nGnRnE has precedence over anything */
2329 } else if (s1lo
== 4 || s2lo
== 4) {
2330 /* non-Reordering has precedence over Reordering */
2331 ret_attrs
= 4; /* nGnRE */
2332 } else if (s1lo
== 8 || s2lo
== 8) {
2333 /* non-Gathering has precedence over Gathering */
2334 ret_attrs
= 8; /* nGRE */
2336 ret_attrs
= 0xc; /* GRE */
2338 } else { /* Normal memory */
2339 /* Outer/inner cacheability combine independently */
2340 ret_attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
2341 | combine_cacheattr_nibble(s1lo
, s2lo
);
2346 static uint8_t force_cacheattr_nibble_wb(uint8_t attr
)
2349 * Given the 4 bits specifying the outer or inner cacheability
2350 * in MAIR format, return a value specifying Normal Write-Back,
2351 * with the allocation and transient hints taken from the input
2352 * if the input specified some kind of cacheable attribute.
2354 if (attr
== 0 || attr
== 4) {
2356 * 0 == an UNPREDICTABLE encoding
2357 * 4 == Non-cacheable
2358 * Either way, force Write-Back RW allocate non-transient
2362 /* Change WriteThrough to WriteBack, keep allocation and transient hints */
2367 * Combine the memory type and cacheability attributes of
2368 * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
2369 * combined attributes in MAIR_EL1 format.
2371 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2375 /* Use stage 1 attributes */
2379 * Force Normal Write-Back. Note that if S1 is Normal cacheable
2380 * then we take the allocation hints from it; otherwise it is
2381 * RW allocate, non-transient.
2383 if ((s1
.attrs
& 0xf0) == 0) {
2387 /* Need to check the Inner and Outer nibbles separately */
2388 return force_cacheattr_nibble_wb(s1
.attrs
& 0xf) |
2389 force_cacheattr_nibble_wb(s1
.attrs
>> 4) << 4;
2391 /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
2392 if ((s1
.attrs
& 0xf0) == 0) {
2397 /* Force Device, of subtype specified by S2 */
2398 return s2
.attrs
<< 2;
2401 * RESERVED values (including RES0 descriptor bit [5] being nonzero);
2402 * arbitrarily force Device.
2409 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
2410 * and CombineS1S2Desc()
2413 * @s1: Attributes from stage 1 walk
2414 * @s2: Attributes from stage 2 walk
2416 static ARMCacheAttrs
combine_cacheattrs(uint64_t hcr
,
2417 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2420 bool tagged
= false;
2422 assert(s2
.is_s2_format
&& !s1
.is_s2_format
);
2423 ret
.is_s2_format
= false;
2425 if (s1
.attrs
== 0xf0) {
2430 /* Combine shareability attributes (table D4-43) */
2431 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
2432 /* if either are outer-shareable, the result is outer-shareable */
2433 ret
.shareability
= 2;
2434 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
2435 /* if either are inner-shareable, the result is inner-shareable */
2436 ret
.shareability
= 3;
2438 /* both non-shareable */
2439 ret
.shareability
= 0;
2442 /* Combine memory type and cacheability attributes */
2443 if (hcr
& HCR_FWB
) {
2444 ret
.attrs
= combined_attrs_fwb(s1
, s2
);
2446 ret
.attrs
= combined_attrs_nofwb(hcr
, s1
, s2
);
2450 * Any location for which the resultant memory type is any
2451 * type of Device memory is always treated as Outer Shareable.
2452 * Any location for which the resultant memory type is Normal
2453 * Inner Non-cacheable, Outer Non-cacheable is always treated
2454 * as Outer Shareable.
2455 * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
2457 if ((ret
.attrs
& 0xf0) == 0 || ret
.attrs
== 0x44) {
2458 ret
.shareability
= 2;
2461 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
2462 if (tagged
&& ret
.attrs
== 0xff) {
2470 * MMU disabled. S1 addresses within aa64 translation regimes are
2471 * still checked for bounds -- see AArch64.S1DisabledOutput().
2473 static bool get_phys_addr_disabled(CPUARMState
*env
, target_ulong address
,
2474 MMUAccessType access_type
,
2475 ARMMMUIdx mmu_idx
, bool is_secure
,
2476 GetPhysAddrResult
*result
,
2477 ARMMMUFaultInfo
*fi
)
2479 uint8_t memattr
= 0x00; /* Device nGnRnE */
2480 uint8_t shareability
= 0; /* non-sharable */
2484 case ARMMMUIdx_Stage2
:
2485 case ARMMMUIdx_Stage2_S
:
2486 case ARMMMUIdx_Phys_NS
:
2487 case ARMMMUIdx_Phys_S
:
2491 r_el
= regime_el(env
, mmu_idx
);
2492 if (arm_el_is_aa64(env
, r_el
)) {
2493 int pamax
= arm_pamax(env_archcpu(env
));
2494 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
];
2497 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
2498 if (access_type
== MMU_INST_FETCH
) {
2499 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
2501 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
2502 addrtop
= (tbi
? 55 : 63);
2504 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
2505 fi
->type
= ARMFault_AddressSize
;
2512 * When TBI is disabled, we've just validated that all of the
2513 * bits above PAMax are zero, so logically we only need to
2514 * clear the top byte for TBI. But it's clearer to follow
2515 * the pseudocode set of addrdesc.paddress.
2517 address
= extract64(address
, 0, 52);
2520 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
2522 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2524 if (hcr
& HCR_DCT
) {
2525 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
2527 memattr
= 0xff; /* Normal, WB, RWA */
2531 if (memattr
== 0 && access_type
== MMU_INST_FETCH
) {
2532 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
2533 memattr
= 0xee; /* Normal, WT, RA, NT */
2535 memattr
= 0x44; /* Normal, NC, No */
2537 shareability
= 2; /* outer sharable */
2539 result
->cacheattrs
.is_s2_format
= false;
2543 result
->f
.phys_addr
= address
;
2544 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2545 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2546 result
->cacheattrs
.shareability
= shareability
;
2547 result
->cacheattrs
.attrs
= memattr
;
2551 static bool get_phys_addr_twostage(CPUARMState
*env
, S1Translate
*ptw
,
2552 target_ulong address
,
2553 MMUAccessType access_type
,
2554 GetPhysAddrResult
*result
,
2555 ARMMMUFaultInfo
*fi
)
2559 bool is_secure
= ptw
->in_secure
;
2560 bool ret
, ipa_secure
, s2walk_secure
;
2561 ARMCacheAttrs cacheattrs1
;
2565 ret
= get_phys_addr_with_struct(env
, ptw
, address
, access_type
, result
, fi
);
2567 /* If S1 fails or S2 is disabled, return early. */
2568 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_Stage2
, is_secure
)) {
2572 ipa
= result
->f
.phys_addr
;
2573 ipa_secure
= result
->f
.attrs
.secure
;
2575 /* Select TCR based on the NS bit from the S1 walk. */
2576 s2walk_secure
= !(ipa_secure
2577 ? env
->cp15
.vstcr_el2
& VSTCR_SW
2578 : env
->cp15
.vtcr_el2
& VTCR_NSW
);
2580 assert(!ipa_secure
);
2581 s2walk_secure
= false;
2584 is_el0
= ptw
->in_mmu_idx
== ARMMMUIdx_Stage1_E0
;
2585 ptw
->in_mmu_idx
= s2walk_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2586 ptw
->in_ptw_idx
= s2walk_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2587 ptw
->in_secure
= s2walk_secure
;
2590 * S1 is done, now do S2 translation.
2591 * Save the stage1 results so that we may merge prot and cacheattrs later.
2593 s1_prot
= result
->f
.prot
;
2594 cacheattrs1
= result
->cacheattrs
;
2595 memset(result
, 0, sizeof(*result
));
2597 ret
= get_phys_addr_lpae(env
, ptw
, ipa
, access_type
, is_el0
, result
, fi
);
2600 /* Combine the S1 and S2 perms. */
2601 result
->f
.prot
&= s1_prot
;
2603 /* If S2 fails, return early. */
2608 /* Combine the S1 and S2 cache attributes. */
2609 hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2612 * HCR.DC forces the first stage attributes to
2613 * Normal Non-Shareable,
2614 * Inner Write-Back Read-Allocate Write-Allocate,
2615 * Outer Write-Back Read-Allocate Write-Allocate.
2616 * Do not overwrite Tagged within attrs.
2618 if (cacheattrs1
.attrs
!= 0xf0) {
2619 cacheattrs1
.attrs
= 0xff;
2621 cacheattrs1
.shareability
= 0;
2623 result
->cacheattrs
= combine_cacheattrs(hcr
, cacheattrs1
,
2624 result
->cacheattrs
);
2627 * Check if IPA translates to secure or non-secure PA space.
2628 * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
2630 result
->f
.attrs
.secure
=
2632 && !(env
->cp15
.vstcr_el2
& (VSTCR_SA
| VSTCR_SW
))
2634 || !(env
->cp15
.vtcr_el2
& (VTCR_NSA
| VTCR_NSW
))));
2639 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
2640 target_ulong address
,
2641 MMUAccessType access_type
,
2642 GetPhysAddrResult
*result
,
2643 ARMMMUFaultInfo
*fi
)
2645 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2646 bool is_secure
= ptw
->in_secure
;
2647 ARMMMUIdx s1_mmu_idx
;
2650 case ARMMMUIdx_Phys_S
:
2651 case ARMMMUIdx_Phys_NS
:
2652 /* Checking Phys early avoids special casing later vs regime_el. */
2653 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2654 is_secure
, result
, fi
);
2656 case ARMMMUIdx_Stage1_E0
:
2657 case ARMMMUIdx_Stage1_E1
:
2658 case ARMMMUIdx_Stage1_E1_PAN
:
2659 /* First stage lookup uses second stage for ptw. */
2660 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2663 case ARMMMUIdx_E10_0
:
2664 s1_mmu_idx
= ARMMMUIdx_Stage1_E0
;
2666 case ARMMMUIdx_E10_1
:
2667 s1_mmu_idx
= ARMMMUIdx_Stage1_E1
;
2669 case ARMMMUIdx_E10_1_PAN
:
2670 s1_mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
2673 * Call ourselves recursively to do the stage 1 and then stage 2
2674 * translations if mmu_idx is a two-stage regime, and EL2 present.
2675 * Otherwise, a stage1+stage2 translation is just stage 1.
2677 ptw
->in_mmu_idx
= mmu_idx
= s1_mmu_idx
;
2678 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2679 return get_phys_addr_twostage(env
, ptw
, address
, access_type
,
2685 /* Single stage and second stage uses physical for ptw. */
2686 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2691 * The page table entries may downgrade secure to non-secure, but
2692 * cannot upgrade an non-secure translation regime's attributes
2695 result
->f
.attrs
.secure
= is_secure
;
2696 result
->f
.attrs
.user
= regime_is_user(env
, mmu_idx
);
2699 * Fast Context Switch Extension. This doesn't exist at all in v8.
2700 * In v7 and earlier it affects all stage 1 translations.
2702 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
2703 && !arm_feature(env
, ARM_FEATURE_V8
)) {
2704 if (regime_el(env
, mmu_idx
) == 3) {
2705 address
+= env
->cp15
.fcseidr_s
;
2707 address
+= env
->cp15
.fcseidr_ns
;
2711 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2713 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2715 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2717 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
2718 is_secure
, result
, fi
);
2719 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2721 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
2722 is_secure
, result
, fi
);
2725 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
2726 is_secure
, result
, fi
);
2728 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
2729 " mmu_idx %u -> %s (prot %c%c%c)\n",
2730 access_type
== MMU_DATA_LOAD
? "reading" :
2731 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
2732 (uint32_t)address
, mmu_idx
,
2733 ret
? "Miss" : "Hit",
2734 result
->f
.prot
& PAGE_READ
? 'r' : '-',
2735 result
->f
.prot
& PAGE_WRITE
? 'w' : '-',
2736 result
->f
.prot
& PAGE_EXEC
? 'x' : '-');
2741 /* Definitely a real MMU, not an MPU */
2743 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
2744 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2745 is_secure
, result
, fi
);
2748 if (regime_using_lpae_format(env
, mmu_idx
)) {
2749 return get_phys_addr_lpae(env
, ptw
, address
, access_type
, false,
2751 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
2752 return get_phys_addr_v6(env
, ptw
, address
, access_type
, result
, fi
);
2754 return get_phys_addr_v5(env
, ptw
, address
, access_type
, result
, fi
);
2758 bool get_phys_addr_with_secure(CPUARMState
*env
, target_ulong address
,
2759 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2760 bool is_secure
, GetPhysAddrResult
*result
,
2761 ARMMMUFaultInfo
*fi
)
2764 .in_mmu_idx
= mmu_idx
,
2765 .in_secure
= is_secure
,
2767 return get_phys_addr_with_struct(env
, &ptw
, address
, access_type
,
2771 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
2772 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2773 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
2778 case ARMMMUIdx_E10_0
:
2779 case ARMMMUIdx_E10_1
:
2780 case ARMMMUIdx_E10_1_PAN
:
2781 case ARMMMUIdx_E20_0
:
2782 case ARMMMUIdx_E20_2
:
2783 case ARMMMUIdx_E20_2_PAN
:
2784 case ARMMMUIdx_Stage1_E0
:
2785 case ARMMMUIdx_Stage1_E1
:
2786 case ARMMMUIdx_Stage1_E1_PAN
:
2788 is_secure
= arm_is_secure_below_el3(env
);
2790 case ARMMMUIdx_Stage2
:
2791 case ARMMMUIdx_Phys_NS
:
2792 case ARMMMUIdx_MPrivNegPri
:
2793 case ARMMMUIdx_MUserNegPri
:
2794 case ARMMMUIdx_MPriv
:
2795 case ARMMMUIdx_MUser
:
2799 case ARMMMUIdx_Stage2_S
:
2800 case ARMMMUIdx_Phys_S
:
2801 case ARMMMUIdx_MSPrivNegPri
:
2802 case ARMMMUIdx_MSUserNegPri
:
2803 case ARMMMUIdx_MSPriv
:
2804 case ARMMMUIdx_MSUser
:
2808 g_assert_not_reached();
2810 return get_phys_addr_with_secure(env
, address
, access_type
, mmu_idx
,
2811 is_secure
, result
, fi
);
2814 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
2817 ARMCPU
*cpu
= ARM_CPU(cs
);
2818 CPUARMState
*env
= &cpu
->env
;
2820 .in_mmu_idx
= arm_mmu_idx(env
),
2821 .in_secure
= arm_is_secure(env
),
2824 GetPhysAddrResult res
= {};
2825 ARMMMUFaultInfo fi
= {};
2828 ret
= get_phys_addr_with_struct(env
, &ptw
, addr
, MMU_DATA_LOAD
, &res
, &fi
);
2829 *attrs
= res
.f
.attrs
;
2834 return res
.f
.phys_addr
;