2 * ARM page table walking.
4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
11 #include "qemu/range.h"
12 #include "qemu/main-loop.h"
13 #include "exec/exec-all.h"
15 #include "internals.h"
19 typedef struct S1Translate
{
32 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
34 MMUAccessType access_type
, bool s1_is_el0
,
35 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
36 __attribute__((nonnull
));
38 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
40 MMUAccessType access_type
,
41 GetPhysAddrResult
*result
,
43 __attribute__((nonnull
));
45 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
46 static const uint8_t pamax_map
[] = {
56 /* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
57 unsigned int arm_pamax(ARMCPU
*cpu
)
59 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
60 unsigned int parange
=
61 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
64 * id_aa64mmfr0 is a read-only register so values outside of the
65 * supported mappings can be considered an implementation error.
67 assert(parange
< ARRAY_SIZE(pamax_map
));
68 return pamax_map
[parange
];
72 * In machvirt_init, we call arm_pamax on a cpu that is not fully
73 * initialized, so we can't rely on the propagation done in realize.
75 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
) ||
76 arm_feature(&cpu
->env
, ARM_FEATURE_V7VE
)) {
85 * Convert a possible stage1+2 MMU index into the appropriate stage 1 MMU index
87 ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
91 return ARMMMUIdx_Stage1_E0
;
93 return ARMMMUIdx_Stage1_E1
;
94 case ARMMMUIdx_E10_1_PAN
:
95 return ARMMMUIdx_Stage1_E1_PAN
;
101 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
103 return stage_1_mmu_idx(arm_mmu_idx(env
));
106 static bool regime_translation_big_endian(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
108 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
111 /* Return the TTBR associated with this translation regime */
112 static uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ttbrn
)
114 if (mmu_idx
== ARMMMUIdx_Stage2
) {
115 return env
->cp15
.vttbr_el2
;
117 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
118 return env
->cp15
.vsttbr_el2
;
121 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
123 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
127 /* Return true if the specified stage of address translation is disabled */
128 static bool regime_translation_disabled(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
133 if (arm_feature(env
, ARM_FEATURE_M
)) {
134 switch (env
->v7m
.mpu_ctrl
[is_secure
] &
135 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
136 case R_V7M_MPU_CTRL_ENABLE_MASK
:
137 /* Enabled, but not for HardFault and NMI */
138 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
139 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
140 /* Enabled for all cases */
145 * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
146 * we warned about that in armv7m_nvic.c when the guest set it.
152 hcr_el2
= arm_hcr_el2_eff_secstate(env
, is_secure
);
155 case ARMMMUIdx_Stage2
:
156 case ARMMMUIdx_Stage2_S
:
157 /* HCR.DC means HCR.VM behaves as 1 */
158 return (hcr_el2
& (HCR_DC
| HCR_VM
)) == 0;
160 case ARMMMUIdx_E10_0
:
161 case ARMMMUIdx_E10_1
:
162 case ARMMMUIdx_E10_1_PAN
:
163 /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
164 if (hcr_el2
& HCR_TGE
) {
169 case ARMMMUIdx_Stage1_E0
:
170 case ARMMMUIdx_Stage1_E1
:
171 case ARMMMUIdx_Stage1_E1_PAN
:
172 /* HCR.DC means SCTLR_EL1.M behaves as 0 */
173 if (hcr_el2
& HCR_DC
) {
178 case ARMMMUIdx_E20_0
:
179 case ARMMMUIdx_E20_2
:
180 case ARMMMUIdx_E20_2_PAN
:
185 case ARMMMUIdx_Phys_NS
:
186 case ARMMMUIdx_Phys_S
:
187 /* No translation for physical address spaces. */
191 g_assert_not_reached();
194 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
197 static bool S2_attrs_are_device(uint64_t hcr
, uint8_t attrs
)
200 * For an S1 page table walk, the stage 1 attributes are always
201 * some form of "this is Normal memory". The combined S1+S2
202 * attributes are therefore only Device if stage 2 specifies Device.
203 * With HCR_EL2.FWB == 0 this is when descriptor bits [5:4] are 0b00,
204 * ie when cacheattrs.attrs bits [3:2] are 0b00.
205 * With HCR_EL2.FWB == 1 this is when descriptor bit [4] is 0, ie
206 * when cacheattrs.attrs bit [2] is 0.
209 return (attrs
& 0x4) == 0;
211 return (attrs
& 0xc) == 0;
215 /* Translate a S1 pagetable walk through S2 if needed. */
216 static bool S1_ptw_translate(CPUARMState
*env
, S1Translate
*ptw
,
217 hwaddr addr
, ARMMMUFaultInfo
*fi
)
219 bool is_secure
= ptw
->in_secure
;
220 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
221 ARMMMUIdx s2_mmu_idx
= ptw
->in_ptw_idx
;
225 ptw
->out_virt
= addr
;
227 if (unlikely(ptw
->in_debug
)) {
229 * From gdbstub, do not use softmmu so that we don't modify the
230 * state of the cpu at all, including softmmu tlb contents.
232 if (regime_is_stage2(s2_mmu_idx
)) {
233 S1Translate s2ptw
= {
234 .in_mmu_idx
= s2_mmu_idx
,
235 .in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
,
236 .in_secure
= is_secure
,
239 GetPhysAddrResult s2
= { };
241 if (get_phys_addr_lpae(env
, &s2ptw
, addr
, MMU_DATA_LOAD
,
245 ptw
->out_phys
= s2
.f
.phys_addr
;
246 pte_attrs
= s2
.cacheattrs
.attrs
;
247 pte_secure
= s2
.f
.attrs
.secure
;
249 /* Regime is physical. */
250 ptw
->out_phys
= addr
;
252 pte_secure
= is_secure
;
254 ptw
->out_host
= NULL
;
258 CPUTLBEntryFull
*full
;
262 flags
= probe_access_full(env
, addr
, 0, MMU_DATA_LOAD
,
263 arm_to_core_mmu_idx(s2_mmu_idx
),
264 true, &ptw
->out_host
, &full
, 0);
267 if (unlikely(flags
& TLB_INVALID_MASK
)) {
270 ptw
->out_phys
= full
->phys_addr
| (addr
& ~TARGET_PAGE_MASK
);
271 ptw
->out_rw
= full
->prot
& PAGE_WRITE
;
272 pte_attrs
= full
->pte_attrs
;
273 pte_secure
= full
->attrs
.secure
;
275 g_assert_not_reached();
279 if (regime_is_stage2(s2_mmu_idx
)) {
280 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
282 if ((hcr
& HCR_PTW
) && S2_attrs_are_device(hcr
, pte_attrs
)) {
284 * PTW set and S1 walk touched S2 Device memory:
285 * generate Permission fault.
287 fi
->type
= ARMFault_Permission
;
291 fi
->s1ns
= !is_secure
;
296 /* Check if page table walk is to secure or non-secure PA space. */
297 ptw
->out_secure
= (is_secure
299 ? env
->cp15
.vstcr_el2
& VSTCR_SW
300 : env
->cp15
.vtcr_el2
& VTCR_NSW
));
301 ptw
->out_be
= regime_translation_big_endian(env
, mmu_idx
);
305 assert(fi
->type
!= ARMFault_None
);
309 fi
->s1ns
= !is_secure
;
313 /* All loads done in the course of a page table walk go through here. */
314 static uint32_t arm_ldl_ptw(CPUARMState
*env
, S1Translate
*ptw
,
317 CPUState
*cs
= env_cpu(env
);
318 void *host
= ptw
->out_host
;
322 /* Page tables are in RAM, and we have the host address. */
323 data
= qatomic_read((uint32_t *)host
);
325 data
= be32_to_cpu(data
);
327 data
= le32_to_cpu(data
);
330 /* Page tables are in MMIO. */
331 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
332 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
333 MemTxResult result
= MEMTX_OK
;
336 data
= address_space_ldl_be(as
, ptw
->out_phys
, attrs
, &result
);
338 data
= address_space_ldl_le(as
, ptw
->out_phys
, attrs
, &result
);
340 if (unlikely(result
!= MEMTX_OK
)) {
341 fi
->type
= ARMFault_SyncExternalOnWalk
;
342 fi
->ea
= arm_extabort_type(result
);
349 static uint64_t arm_ldq_ptw(CPUARMState
*env
, S1Translate
*ptw
,
352 CPUState
*cs
= env_cpu(env
);
353 void *host
= ptw
->out_host
;
357 /* Page tables are in RAM, and we have the host address. */
358 #ifdef CONFIG_ATOMIC64
359 data
= qatomic_read__nocheck((uint64_t *)host
);
361 data
= be64_to_cpu(data
);
363 data
= le64_to_cpu(data
);
367 data
= ldq_be_p(host
);
369 data
= ldq_le_p(host
);
373 /* Page tables are in MMIO. */
374 MemTxAttrs attrs
= { .secure
= ptw
->out_secure
};
375 AddressSpace
*as
= arm_addressspace(cs
, attrs
);
376 MemTxResult result
= MEMTX_OK
;
379 data
= address_space_ldq_be(as
, ptw
->out_phys
, attrs
, &result
);
381 data
= address_space_ldq_le(as
, ptw
->out_phys
, attrs
, &result
);
383 if (unlikely(result
!= MEMTX_OK
)) {
384 fi
->type
= ARMFault_SyncExternalOnWalk
;
385 fi
->ea
= arm_extabort_type(result
);
392 static uint64_t arm_casq_ptw(CPUARMState
*env
, uint64_t old_val
,
393 uint64_t new_val
, S1Translate
*ptw
,
397 void *host
= ptw
->out_host
;
399 if (unlikely(!host
)) {
400 fi
->type
= ARMFault_UnsuppAtomicUpdate
;
406 * Raising a stage2 Protection fault for an atomic update to a read-only
407 * page is delayed until it is certain that there is a change to make.
409 if (unlikely(!ptw
->out_rw
)) {
414 flags
= probe_access_flags(env
, ptw
->out_virt
, 0, MMU_DATA_STORE
,
415 arm_to_core_mmu_idx(ptw
->in_ptw_idx
),
419 if (unlikely(flags
& TLB_INVALID_MASK
)) {
420 assert(fi
->type
!= ARMFault_None
);
421 fi
->s2addr
= ptw
->out_virt
;
424 fi
->s1ns
= !ptw
->in_secure
;
428 /* In case CAS mismatches and we loop, remember writability. */
432 #ifdef CONFIG_ATOMIC64
434 old_val
= cpu_to_be64(old_val
);
435 new_val
= cpu_to_be64(new_val
);
436 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
437 cur_val
= be64_to_cpu(cur_val
);
439 old_val
= cpu_to_le64(old_val
);
440 new_val
= cpu_to_le64(new_val
);
441 cur_val
= qatomic_cmpxchg__nocheck((uint64_t *)host
, old_val
, new_val
);
442 cur_val
= le64_to_cpu(cur_val
);
446 * We can't support the full 64-bit atomic cmpxchg on the host.
447 * Because this is only used for FEAT_HAFDBS, which is only for AA64,
448 * we know that TCG_OVERSIZED_GUEST is set, which means that we are
449 * running in round-robin mode and could only race with dma i/o.
451 #ifndef TCG_OVERSIZED_GUEST
452 # error "Unexpected configuration"
454 bool locked
= qemu_mutex_iothread_locked();
456 qemu_mutex_lock_iothread();
459 cur_val
= ldq_be_p(host
);
460 if (cur_val
== old_val
) {
461 stq_be_p(host
, new_val
);
464 cur_val
= ldq_le_p(host
);
465 if (cur_val
== old_val
) {
466 stq_le_p(host
, new_val
);
470 qemu_mutex_unlock_iothread();
477 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
478 uint32_t *table
, uint32_t address
)
480 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
481 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
482 int maskshift
= extract32(tcr
, 0, 3);
483 uint32_t mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
486 if (address
& mask
) {
487 if (tcr
& TTBCR_PD1
) {
488 /* Translation table walk disabled for TTBR1 */
491 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
493 if (tcr
& TTBCR_PD0
) {
494 /* Translation table walk disabled for TTBR0 */
497 base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
498 *table
= regime_ttbr(env
, mmu_idx
, 0) & base_mask
;
500 *table
|= (address
>> 18) & 0x3ffc;
505 * Translate section/page access permissions to page R/W protection flags
507 * @mmu_idx: MMU index indicating required translation regime
508 * @ap: The 3-bit access permissions (AP[2:0])
509 * @domain_prot: The 2-bit domain access permissions
510 * @is_user: TRUE if accessing from PL0
512 static int ap_to_rw_prot_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
513 int ap
, int domain_prot
, bool is_user
)
515 if (domain_prot
== 3) {
516 return PAGE_READ
| PAGE_WRITE
;
521 if (arm_feature(env
, ARM_FEATURE_V7
)) {
524 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
526 return is_user
? 0 : PAGE_READ
;
533 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
538 return PAGE_READ
| PAGE_WRITE
;
541 return PAGE_READ
| PAGE_WRITE
;
542 case 4: /* Reserved. */
545 return is_user
? 0 : PAGE_READ
;
549 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
554 g_assert_not_reached();
559 * Translate section/page access permissions to page R/W protection flags
561 * @mmu_idx: MMU index indicating required translation regime
562 * @ap: The 3-bit access permissions (AP[2:0])
563 * @domain_prot: The 2-bit domain access permissions
565 static int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
566 int ap
, int domain_prot
)
568 return ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
,
569 regime_is_user(env
, mmu_idx
));
573 * Translate section/page access permissions to page R/W protection flags.
574 * @ap: The 2-bit simple AP (AP[2:1])
575 * @is_user: TRUE if accessing from PL0
577 static int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
581 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
583 return PAGE_READ
| PAGE_WRITE
;
585 return is_user
? 0 : PAGE_READ
;
589 g_assert_not_reached();
593 static int simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
595 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
598 static bool get_phys_addr_v5(CPUARMState
*env
, S1Translate
*ptw
,
599 uint32_t address
, MMUAccessType access_type
,
600 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
612 /* Pagetable walk. */
613 /* Lookup l1 descriptor. */
614 if (!get_level1_table_address(env
, ptw
->in_mmu_idx
, &table
, address
)) {
615 /* Section translation fault if page walk is disabled by PD0 or PD1 */
616 fi
->type
= ARMFault_Translation
;
619 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
622 desc
= arm_ldl_ptw(env
, ptw
, fi
);
623 if (fi
->type
!= ARMFault_None
) {
627 domain
= (desc
>> 5) & 0x0f;
628 if (regime_el(env
, ptw
->in_mmu_idx
) == 1) {
629 dacr
= env
->cp15
.dacr_ns
;
631 dacr
= env
->cp15
.dacr_s
;
633 domain_prot
= (dacr
>> (domain
* 2)) & 3;
635 /* Section translation fault. */
636 fi
->type
= ARMFault_Translation
;
642 if (domain_prot
== 0 || domain_prot
== 2) {
643 fi
->type
= ARMFault_Domain
;
648 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
649 ap
= (desc
>> 10) & 3;
650 result
->f
.lg_page_size
= 20; /* 1MB */
652 /* Lookup l2 entry. */
654 /* Coarse pagetable. */
655 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
657 /* Fine pagetable. */
658 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
660 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
663 desc
= arm_ldl_ptw(env
, ptw
, fi
);
664 if (fi
->type
!= ARMFault_None
) {
668 case 0: /* Page translation fault. */
669 fi
->type
= ARMFault_Translation
;
671 case 1: /* 64k page. */
672 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
673 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
674 result
->f
.lg_page_size
= 16;
676 case 2: /* 4k page. */
677 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
678 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
679 result
->f
.lg_page_size
= 12;
681 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
683 /* ARMv6/XScale extended small page format */
684 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
685 || arm_feature(env
, ARM_FEATURE_V6
)) {
686 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
687 result
->f
.lg_page_size
= 12;
690 * UNPREDICTABLE in ARMv5; we choose to take a
691 * page translation fault.
693 fi
->type
= ARMFault_Translation
;
697 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
698 result
->f
.lg_page_size
= 10;
700 ap
= (desc
>> 4) & 3;
703 /* Never happens, but compiler isn't smart enough to tell. */
704 g_assert_not_reached();
707 result
->f
.prot
= ap_to_rw_prot(env
, ptw
->in_mmu_idx
, ap
, domain_prot
);
708 result
->f
.prot
|= result
->f
.prot
? PAGE_EXEC
: 0;
709 if (!(result
->f
.prot
& (1 << access_type
))) {
710 /* Access permission fault. */
711 fi
->type
= ARMFault_Permission
;
714 result
->f
.phys_addr
= phys_addr
;
722 static bool get_phys_addr_v6(CPUARMState
*env
, S1Translate
*ptw
,
723 uint32_t address
, MMUAccessType access_type
,
724 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
726 ARMCPU
*cpu
= env_archcpu(env
);
727 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
742 /* Pagetable walk. */
743 /* Lookup l1 descriptor. */
744 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
745 /* Section translation fault if page walk is disabled by PD0 or PD1 */
746 fi
->type
= ARMFault_Translation
;
749 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
752 desc
= arm_ldl_ptw(env
, ptw
, fi
);
753 if (fi
->type
!= ARMFault_None
) {
757 if (type
== 0 || (type
== 3 && !cpu_isar_feature(aa32_pxn
, cpu
))) {
758 /* Section translation fault, or attempt to use the encoding
759 * which is Reserved on implementations without PXN.
761 fi
->type
= ARMFault_Translation
;
764 if ((type
== 1) || !(desc
& (1 << 18))) {
765 /* Page or Section. */
766 domain
= (desc
>> 5) & 0x0f;
768 if (regime_el(env
, mmu_idx
) == 1) {
769 dacr
= env
->cp15
.dacr_ns
;
771 dacr
= env
->cp15
.dacr_s
;
776 domain_prot
= (dacr
>> (domain
* 2)) & 3;
777 if (domain_prot
== 0 || domain_prot
== 2) {
778 /* Section or Page domain fault */
779 fi
->type
= ARMFault_Domain
;
783 if (desc
& (1 << 18)) {
785 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
786 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
787 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
788 result
->f
.lg_page_size
= 24; /* 16MB */
791 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
792 result
->f
.lg_page_size
= 20; /* 1MB */
794 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
795 xn
= desc
& (1 << 4);
797 ns
= extract32(desc
, 19, 1);
799 if (cpu_isar_feature(aa32_pxn
, cpu
)) {
800 pxn
= (desc
>> 2) & 1;
802 ns
= extract32(desc
, 3, 1);
803 /* Lookup l2 entry. */
804 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
805 if (!S1_ptw_translate(env
, ptw
, table
, fi
)) {
808 desc
= arm_ldl_ptw(env
, ptw
, fi
);
809 if (fi
->type
!= ARMFault_None
) {
812 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
814 case 0: /* Page translation fault. */
815 fi
->type
= ARMFault_Translation
;
817 case 1: /* 64k page. */
818 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
819 xn
= desc
& (1 << 15);
820 result
->f
.lg_page_size
= 16;
822 case 2: case 3: /* 4k page. */
823 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
825 result
->f
.lg_page_size
= 12;
828 /* Never happens, but compiler isn't smart enough to tell. */
829 g_assert_not_reached();
832 if (domain_prot
== 3) {
833 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
835 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
838 if (xn
&& access_type
== MMU_INST_FETCH
) {
839 fi
->type
= ARMFault_Permission
;
843 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
844 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
845 /* The simplified model uses AP[0] as an access control bit. */
847 /* Access flag fault. */
848 fi
->type
= ARMFault_AccessFlag
;
851 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
852 user_prot
= simple_ap_to_rw_prot_is_user(ap
>> 1, 1);
854 result
->f
.prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
855 user_prot
= ap_to_rw_prot_is_user(env
, mmu_idx
, ap
, domain_prot
, 1);
857 if (result
->f
.prot
&& !xn
) {
858 result
->f
.prot
|= PAGE_EXEC
;
860 if (!(result
->f
.prot
& (1 << access_type
))) {
861 /* Access permission fault. */
862 fi
->type
= ARMFault_Permission
;
865 if (regime_is_pan(env
, mmu_idx
) &&
866 !regime_is_user(env
, mmu_idx
) &&
868 access_type
!= MMU_INST_FETCH
) {
869 /* Privileged Access Never fault */
870 fi
->type
= ARMFault_Permission
;
875 /* The NS bit will (as required by the architecture) have no effect if
876 * the CPU doesn't support TZ or this is a non-secure translation
877 * regime, because the attribute will already be non-secure.
879 result
->f
.attrs
.secure
= false;
881 result
->f
.phys_addr
= phys_addr
;
890 * Translate S2 section/page access permissions to protection flags
892 * @s2ap: The 2-bit stage2 access permissions (S2AP)
893 * @xn: XN (execute-never) bits
894 * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
896 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
, bool s1_is_el0
)
907 if (cpu_isar_feature(any_tts2uxn
, env_archcpu(env
))) {
925 g_assert_not_reached();
928 if (!extract32(xn
, 1, 1)) {
929 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
938 * Translate section/page access permissions to protection flags
940 * @mmu_idx: MMU index indicating required translation regime
941 * @is_aa64: TRUE if AArch64
942 * @ap: The 2-bit simple AP (AP[2:1])
943 * @ns: NS (non-secure) bit
944 * @xn: XN (execute-never) bit
945 * @pxn: PXN (privileged execute-never) bit
947 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
948 int ap
, int ns
, int xn
, int pxn
)
950 bool is_user
= regime_is_user(env
, mmu_idx
);
951 int prot_rw
, user_rw
;
955 assert(!regime_is_stage2(mmu_idx
));
957 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
961 if (user_rw
&& regime_is_pan(env
, mmu_idx
)) {
962 /* PAN forbids data accesses but doesn't affect insn fetch */
965 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
969 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
973 /* TODO have_wxn should be replaced with
974 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
975 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
976 * compatible processors have EL2, which is required for [U]WXN.
978 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
981 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
985 if (regime_has_2_ranges(mmu_idx
) && !is_user
) {
986 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
988 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
989 switch (regime_el(env
, mmu_idx
)) {
993 xn
= xn
|| !(user_rw
& PAGE_READ
);
997 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
999 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
1000 (uwxn
&& (user_rw
& PAGE_WRITE
));
1010 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
1013 return prot_rw
| PAGE_EXEC
;
1016 static ARMVAParameters
aa32_va_parameters(CPUARMState
*env
, uint32_t va
,
1019 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1020 uint32_t el
= regime_el(env
, mmu_idx
);
1024 assert(mmu_idx
!= ARMMMUIdx_Stage2_S
);
1026 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1028 bool sext
= extract32(tcr
, 4, 1);
1029 bool sign
= extract32(tcr
, 3, 1);
1032 * If the sign-extend bit is not the same as t0sz[3], the result
1033 * is unpredictable. Flag this as a guest error.
1036 qemu_log_mask(LOG_GUEST_ERROR
,
1037 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
1039 tsz
= sextract32(tcr
, 0, 4) + 8;
1043 } else if (el
== 2) {
1045 tsz
= extract32(tcr
, 0, 3);
1047 hpd
= extract64(tcr
, 24, 1);
1050 int t0sz
= extract32(tcr
, 0, 3);
1051 int t1sz
= extract32(tcr
, 16, 3);
1054 select
= va
> (0xffffffffu
>> t0sz
);
1056 /* Note that we will detect errors later. */
1057 select
= va
>= ~(0xffffffffu
>> t1sz
);
1061 epd
= extract32(tcr
, 7, 1);
1062 hpd
= extract64(tcr
, 41, 1);
1065 epd
= extract32(tcr
, 23, 1);
1066 hpd
= extract64(tcr
, 42, 1);
1068 /* For aarch32, hpd0 is not enabled without t2e as well. */
1069 hpd
&= extract32(tcr
, 6, 1);
1072 return (ARMVAParameters
) {
1081 * check_s2_mmu_setup
1083 * @is_aa64: True if the translation regime is in AArch64 state
1084 * @tcr: VTCR_EL2 or VSTCR_EL2
1085 * @ds: Effective value of TCR.DS.
1086 * @iasize: Bitsize of IPAs
1087 * @stride: Page-table stride (See the ARM ARM)
1089 * Decode the starting level of the S2 lookup, returning INT_MIN if
1090 * the configuration is invalid.
1092 static int check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, uint64_t tcr
,
1093 bool ds
, int iasize
, int stride
)
1095 int sl0
, sl2
, startlevel
, granulebits
, levels
;
1096 int s1_min_iasize
, s1_max_iasize
;
1098 sl0
= extract32(tcr
, 6, 2);
1101 * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
1102 * get_phys_addr_lpae, that used aa64_va_parameters which apply
1103 * to aarch64. If Stage1 is aarch32, the min_txsz is larger.
1104 * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
1105 * inputsize is 64 - 24 = 40.
1107 if (iasize
< 40 && !arm_el_is_aa64(&cpu
->env
, 1)) {
1112 * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
1113 * so interleave AArch64.S2StartLevel.
1117 /* SL2 is RES0 unless DS=1 & 4KB granule. */
1118 sl2
= extract64(tcr
, 33, 1);
1125 startlevel
= 2 - sl0
;
1128 if (arm_pamax(cpu
) < 44) {
1133 if (!cpu_isar_feature(aa64_st
, cpu
)) {
1144 if (arm_pamax(cpu
) < 42) {
1154 startlevel
= 3 - sl0
;
1159 if (arm_pamax(cpu
) < 44) {
1166 startlevel
= 3 - sl0
;
1169 g_assert_not_reached();
1173 * Things are simpler for AArch32 EL2, with only 4k pages.
1174 * There is no separate S2InvalidSL function, but AArch32.S2Walk
1175 * begins with walkparms.sl0 in {'1x'}.
1177 assert(stride
== 9);
1181 startlevel
= 2 - sl0
;
1184 /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */
1185 levels
= 3 - startlevel
;
1186 granulebits
= stride
+ 3;
1188 s1_min_iasize
= levels
* stride
+ granulebits
+ 1;
1189 s1_max_iasize
= s1_min_iasize
+ (stride
- 1) + 4;
1191 if (iasize
>= s1_min_iasize
&& iasize
<= s1_max_iasize
) {
1200 * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
1202 * Returns false if the translation was successful. Otherwise, phys_ptr,
1203 * attrs, prot and page_size may not be filled in, and the populated fsr
1204 * value provides information on why the translation aborted, in the format
1205 * of a long-format DFSR/IFSR fault register, with the following caveat:
1206 * the WnR bit is never set (the caller must do this).
1209 * @ptw: Current and next stage parameters for the walk.
1210 * @address: virtual address to get physical address for
1211 * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
1212 * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2
1213 * (so this is a stage 2 page table walk),
1214 * must be true if this is stage 2 of a stage 1+2
1215 * walk for an EL0 access. If @mmu_idx is anything else,
1216 * @s1_is_el0 is ignored.
1217 * @result: set on translation success,
1218 * @fi: set to fault info if the translation fails
1220 static bool get_phys_addr_lpae(CPUARMState
*env
, S1Translate
*ptw
,
1222 MMUAccessType access_type
, bool s1_is_el0
,
1223 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
1225 ARMCPU
*cpu
= env_archcpu(env
);
1226 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
1227 bool is_secure
= ptw
->in_secure
;
1229 ARMVAParameters param
;
1231 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
1232 uint32_t tableattrs
;
1233 target_ulong page_size
;
1236 int addrsize
, inputsize
, outputsize
;
1237 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
1238 int ap
, ns
, xn
, pxn
;
1239 uint32_t el
= regime_el(env
, mmu_idx
);
1240 uint64_t descaddrmask
;
1241 bool aarch64
= arm_el_is_aa64(env
, el
);
1242 uint64_t descriptor
, new_descriptor
;
1245 /* TODO: This code does not support shareability levels. */
1249 param
= aa64_va_parameters(env
, address
, mmu_idx
,
1250 access_type
!= MMU_INST_FETCH
);
1254 * If TxSZ is programmed to a value larger than the maximum,
1255 * or smaller than the effective minimum, it is IMPLEMENTATION
1256 * DEFINED whether we behave as if the field were programmed
1257 * within bounds, or if a level 0 Translation fault is generated.
1259 * With FEAT_LVA, fault on less than minimum becomes required,
1260 * so our choice is to always raise the fault.
1262 if (param
.tsz_oob
) {
1263 goto do_translation_fault
;
1266 addrsize
= 64 - 8 * param
.tbi
;
1267 inputsize
= 64 - param
.tsz
;
1270 * Bound PS by PARANGE to find the effective output address size.
1271 * ID_AA64MMFR0 is a read-only register so values outside of the
1272 * supported mappings can be considered an implementation error.
1274 ps
= FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
1275 ps
= MIN(ps
, param
.ps
);
1276 assert(ps
< ARRAY_SIZE(pamax_map
));
1277 outputsize
= pamax_map
[ps
];
1280 * With LPA2, the effective output address (OA) size is at most 48 bits
1281 * unless TCR.DS == 1
1283 if (!param
.ds
&& param
.gran
!= Gran64K
) {
1284 outputsize
= MIN(outputsize
, 48);
1287 param
= aa32_va_parameters(env
, address
, mmu_idx
);
1289 addrsize
= (mmu_idx
== ARMMMUIdx_Stage2
? 40 : 32);
1290 inputsize
= addrsize
- param
.tsz
;
1295 * We determined the region when collecting the parameters, but we
1296 * have not yet validated that the address is valid for the region.
1297 * Extract the top bits and verify that they all match select.
1299 * For aa32, if inputsize == addrsize, then we have selected the
1300 * region by exclusion in aa32_va_parameters and there is no more
1301 * validation to do here.
1303 if (inputsize
< addrsize
) {
1304 target_ulong top_bits
= sextract64(address
, inputsize
,
1305 addrsize
- inputsize
);
1306 if (-top_bits
!= param
.select
) {
1307 /* The gap between the two regions is a Translation fault */
1308 goto do_translation_fault
;
1312 stride
= arm_granule_bits(param
.gran
) - 3;
1315 * Note that QEMU ignores shareability and cacheability attributes,
1316 * so we don't need to do anything with the SH, ORGN, IRGN fields
1317 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
1318 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
1319 * implement any ASID-like capability so we can ignore it (instead
1320 * we will always flush the TLB any time the ASID is changed).
1322 ttbr
= regime_ttbr(env
, mmu_idx
, param
.select
);
1325 * Here we should have set up all the parameters for the translation:
1326 * inputsize, ttbr, epd, stride, tbi
1331 * Translation table walk disabled => Translation fault on TLB miss
1332 * Note: This is always 0 on 64-bit EL2 and EL3.
1334 goto do_translation_fault
;
1337 if (!regime_is_stage2(mmu_idx
)) {
1339 * The starting level depends on the virtual address size (which can
1340 * be up to 48 bits) and the translation granule size. It indicates
1341 * the number of strides (stride bits at a time) needed to
1342 * consume the bits of the input address. In the pseudocode this is:
1343 * level = 4 - RoundUp((inputsize - grainsize) / stride)
1344 * where their 'inputsize' is our 'inputsize', 'grainsize' is
1345 * our 'stride + 3' and 'stride' is our 'stride'.
1346 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
1347 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
1348 * = 4 - (inputsize - 4) / stride;
1350 level
= 4 - (inputsize
- 4) / stride
;
1352 int startlevel
= check_s2_mmu_setup(cpu
, aarch64
, tcr
, param
.ds
,
1354 if (startlevel
== INT_MIN
) {
1356 goto do_translation_fault
;
1361 indexmask_grainsize
= MAKE_64BIT_MASK(0, stride
+ 3);
1362 indexmask
= MAKE_64BIT_MASK(0, inputsize
- (stride
* (4 - level
)));
1364 /* Now we can extract the actual base address from the TTBR */
1365 descaddr
= extract64(ttbr
, 0, 48);
1368 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
1370 * Otherwise, if the base address is out of range, raise AddressSizeFault.
1371 * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
1372 * but we've just cleared the bits above 47, so simplify the test.
1374 if (outputsize
> 48) {
1375 descaddr
|= extract64(ttbr
, 2, 4) << 48;
1376 } else if (descaddr
>> outputsize
) {
1378 fi
->type
= ARMFault_AddressSize
;
1383 * We rely on this masking to clear the RES0 bits at the bottom of the TTBR
1384 * and also to mask out CnP (bit 0) which could validly be non-zero.
1386 descaddr
&= ~indexmask
;
1389 * For AArch32, the address field in the descriptor goes up to bit 39
1390 * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
1391 * or an AddressSize fault is raised. So for v8 we extract those SBZ
1392 * bits as part of the address, which will be checked via outputsize.
1393 * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
1394 * the highest bits of a 52-bit output are placed elsewhere.
1397 descaddrmask
= MAKE_64BIT_MASK(0, 50);
1398 } else if (arm_feature(env
, ARM_FEATURE_V8
)) {
1399 descaddrmask
= MAKE_64BIT_MASK(0, 48);
1401 descaddrmask
= MAKE_64BIT_MASK(0, 40);
1403 descaddrmask
&= ~indexmask_grainsize
;
1406 * Secure accesses start with the page table in secure memory and
1407 * can be downgraded to non-secure at any step. Non-secure accesses
1408 * remain non-secure. We implement this by just ORing in the NSTable/NS
1409 * bits at each step.
1411 tableattrs
= is_secure
? 0 : (1 << 4);
1414 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
1416 nstable
= extract32(tableattrs
, 4, 1);
1419 * Stage2_S -> Stage2 or Phys_S -> Phys_NS
1420 * Assert that the non-secure idx are even, and relative order.
1422 QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS
& 1) != 0);
1423 QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2
& 1) != 0);
1424 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS
+ 1 != ARMMMUIdx_Phys_S
);
1425 QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2
+ 1 != ARMMMUIdx_Stage2_S
);
1426 ptw
->in_ptw_idx
&= ~1;
1427 ptw
->in_secure
= false;
1429 if (!S1_ptw_translate(env
, ptw
, descaddr
, fi
)) {
1432 descriptor
= arm_ldq_ptw(env
, ptw
, fi
);
1433 if (fi
->type
!= ARMFault_None
) {
1436 new_descriptor
= descriptor
;
1438 restart_atomic_update
:
1439 if (!(descriptor
& 1) || (!(descriptor
& 2) && (level
== 3))) {
1440 /* Invalid, or the Reserved level 3 encoding */
1441 goto do_translation_fault
;
1444 descaddr
= descriptor
& descaddrmask
;
1447 * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
1448 * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
1449 * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
1450 * raise AddressSizeFault.
1452 if (outputsize
> 48) {
1454 descaddr
|= extract64(descriptor
, 8, 2) << 50;
1456 descaddr
|= extract64(descriptor
, 12, 4) << 48;
1458 } else if (descaddr
>> outputsize
) {
1459 fi
->type
= ARMFault_AddressSize
;
1463 if ((descriptor
& 2) && (level
< 3)) {
1465 * Table entry. The top five bits are attributes which may
1466 * propagate down through lower levels of the table (and
1467 * which are all arranged so that 0 means "no effect", so
1468 * we can gather them up by ORing in the bits at each level).
1470 tableattrs
|= extract64(descriptor
, 59, 5);
1472 indexmask
= indexmask_grainsize
;
1477 * Block entry at level 1 or 2, or page entry at level 3.
1478 * These are basically the same thing, although the number
1479 * of bits we pull in from the vaddr varies. Note that although
1480 * descaddrmask masks enough of the low bits of the descriptor
1481 * to give a correct page or table address, the address field
1482 * in a block descriptor is smaller; so we need to explicitly
1483 * clear the lower bits here before ORing in the low vaddr bits.
1485 * Afterward, descaddr is the final physical address.
1487 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
1488 descaddr
&= ~(hwaddr
)(page_size
- 1);
1489 descaddr
|= (address
& (page_size
- 1));
1491 if (likely(!ptw
->in_debug
)) {
1494 * If HA is enabled, prepare to update the descriptor below.
1495 * Otherwise, pass the access fault on to software.
1497 if (!(descriptor
& (1 << 10))) {
1499 new_descriptor
|= 1 << 10; /* AF */
1501 fi
->type
= ARMFault_AccessFlag
;
1508 * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP
1509 * bit for writeback. The actual write protection test may still be
1510 * overridden by tableattrs, to be merged below.
1513 && extract64(descriptor
, 51, 1) /* DBM */
1514 && access_type
== MMU_DATA_STORE
) {
1515 if (regime_is_stage2(mmu_idx
)) {
1516 new_descriptor
|= 1ull << 7; /* set S2AP[1] */
1518 new_descriptor
&= ~(1ull << 7); /* clear AP[2] */
1524 * Extract attributes from the (modified) descriptor, and apply
1525 * table descriptors. Stage 2 table descriptors do not include
1526 * any attribute fields. HPD disables all the table attributes
1529 attrs
= new_descriptor
& (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14));
1530 if (!regime_is_stage2(mmu_idx
)) {
1531 attrs
|= nstable
<< 5; /* NS */
1533 attrs
|= extract64(tableattrs
, 0, 2) << 53; /* XN, PXN */
1535 * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
1536 * means "force PL1 access only", which means forcing AP[1] to 0.
1538 attrs
&= ~(extract64(tableattrs
, 2, 1) << 6); /* !APT[0] => AP[1] */
1539 attrs
|= extract32(tableattrs
, 3, 1) << 7; /* APT[1] => AP[2] */
1543 ap
= extract32(attrs
, 6, 2);
1544 if (regime_is_stage2(mmu_idx
)) {
1545 ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1546 xn
= extract64(attrs
, 53, 2);
1547 result
->f
.prot
= get_S2prot(env
, ap
, xn
, s1_is_el0
);
1549 ns
= extract32(attrs
, 5, 1);
1550 xn
= extract64(attrs
, 54, 1);
1551 pxn
= extract64(attrs
, 53, 1);
1552 result
->f
.prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
1555 if (!(result
->f
.prot
& (1 << access_type
))) {
1556 fi
->type
= ARMFault_Permission
;
1560 /* If FEAT_HAFDBS has made changes, update the PTE. */
1561 if (new_descriptor
!= descriptor
) {
1562 new_descriptor
= arm_casq_ptw(env
, descriptor
, new_descriptor
, ptw
, fi
);
1563 if (fi
->type
!= ARMFault_None
) {
1567 * I_YZSVV says that if the in-memory descriptor has changed,
1568 * then we must use the information in that new value
1569 * (which might include a different output address, different
1570 * attributes, or generate a fault).
1571 * Restart the handling of the descriptor value from scratch.
1573 if (new_descriptor
!= descriptor
) {
1574 descriptor
= new_descriptor
;
1575 goto restart_atomic_update
;
1581 * The NS bit will (as required by the architecture) have no effect if
1582 * the CPU doesn't support TZ or this is a non-secure translation
1583 * regime, because the attribute will already be non-secure.
1585 result
->f
.attrs
.secure
= false;
1588 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
1589 if (aarch64
&& cpu_isar_feature(aa64_bti
, cpu
)) {
1590 result
->f
.guarded
= extract64(attrs
, 50, 1); /* GP */
1593 if (regime_is_stage2(mmu_idx
)) {
1594 result
->cacheattrs
.is_s2_format
= true;
1595 result
->cacheattrs
.attrs
= extract32(attrs
, 2, 4);
1597 /* Index into MAIR registers for cache attributes */
1598 uint8_t attrindx
= extract32(attrs
, 2, 3);
1599 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
1600 assert(attrindx
<= 7);
1601 result
->cacheattrs
.is_s2_format
= false;
1602 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
1606 * For FEAT_LPA2 and effective DS, the SH field in the attributes
1607 * was re-purposed for output address bits. The SH attribute in
1608 * that case comes from TCR_ELx, which we extracted earlier.
1611 result
->cacheattrs
.shareability
= param
.sh
;
1613 result
->cacheattrs
.shareability
= extract32(attrs
, 8, 2);
1616 result
->f
.phys_addr
= descaddr
;
1617 result
->f
.lg_page_size
= ctz64(page_size
);
1620 do_translation_fault
:
1621 fi
->type
= ARMFault_Translation
;
1624 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
1625 fi
->stage2
= fi
->s1ptw
|| regime_is_stage2(mmu_idx
);
1626 fi
->s1ns
= mmu_idx
== ARMMMUIdx_Stage2
;
1630 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
1631 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1632 bool is_secure
, GetPhysAddrResult
*result
,
1633 ARMMMUFaultInfo
*fi
)
1638 bool is_user
= regime_is_user(env
, mmu_idx
);
1640 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
1642 result
->f
.phys_addr
= address
;
1643 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1647 result
->f
.phys_addr
= address
;
1648 for (n
= 7; n
>= 0; n
--) {
1649 base
= env
->cp15
.c6_region
[n
];
1650 if ((base
& 1) == 0) {
1653 mask
= 1 << ((base
>> 1) & 0x1f);
1654 /* Keep this shift separate from the above to avoid an
1655 (undefined) << 32. */
1656 mask
= (mask
<< 1) - 1;
1657 if (((base
^ address
) & ~mask
) == 0) {
1662 fi
->type
= ARMFault_Background
;
1666 if (access_type
== MMU_INST_FETCH
) {
1667 mask
= env
->cp15
.pmsav5_insn_ap
;
1669 mask
= env
->cp15
.pmsav5_data_ap
;
1671 mask
= (mask
>> (n
* 4)) & 0xf;
1674 fi
->type
= ARMFault_Permission
;
1679 fi
->type
= ARMFault_Permission
;
1683 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1686 result
->f
.prot
= PAGE_READ
;
1688 result
->f
.prot
|= PAGE_WRITE
;
1692 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
;
1696 fi
->type
= ARMFault_Permission
;
1700 result
->f
.prot
= PAGE_READ
;
1703 result
->f
.prot
= PAGE_READ
;
1706 /* Bad permission. */
1707 fi
->type
= ARMFault_Permission
;
1711 result
->f
.prot
|= PAGE_EXEC
;
1715 static void get_phys_addr_pmsav7_default(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1716 int32_t address
, uint8_t *prot
)
1718 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1719 *prot
= PAGE_READ
| PAGE_WRITE
;
1721 case 0xF0000000 ... 0xFFFFFFFF:
1722 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
1723 /* hivecs execing is ok */
1727 case 0x00000000 ... 0x7FFFFFFF:
1732 /* Default system address map for M profile cores.
1733 * The architecture specifies which regions are execute-never;
1734 * at the MPU level no other checks are defined.
1737 case 0x00000000 ... 0x1fffffff: /* ROM */
1738 case 0x20000000 ... 0x3fffffff: /* SRAM */
1739 case 0x60000000 ... 0x7fffffff: /* RAM */
1740 case 0x80000000 ... 0x9fffffff: /* RAM */
1741 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1743 case 0x40000000 ... 0x5fffffff: /* Peripheral */
1744 case 0xa0000000 ... 0xbfffffff: /* Device */
1745 case 0xc0000000 ... 0xdfffffff: /* Device */
1746 case 0xe0000000 ... 0xffffffff: /* System */
1747 *prot
= PAGE_READ
| PAGE_WRITE
;
1750 g_assert_not_reached();
1755 static bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
1757 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
1758 return arm_feature(env
, ARM_FEATURE_M
) &&
1759 extract32(address
, 20, 12) == 0xe00;
1762 static bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
1765 * True if address is in the M profile system region
1766 * 0xe0000000 - 0xffffffff
1768 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
1771 static bool pmsav7_use_background_region(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
1772 bool is_secure
, bool is_user
)
1775 * Return true if we should use the default memory map as a
1776 * "background" region if there are no hits against any MPU regions.
1778 CPUARMState
*env
= &cpu
->env
;
1784 if (arm_feature(env
, ARM_FEATURE_M
)) {
1785 return env
->v7m
.mpu_ctrl
[is_secure
] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
1788 if (mmu_idx
== ARMMMUIdx_Stage2
) {
1792 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
1795 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
1796 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1797 bool secure
, GetPhysAddrResult
*result
,
1798 ARMMMUFaultInfo
*fi
)
1800 ARMCPU
*cpu
= env_archcpu(env
);
1802 bool is_user
= regime_is_user(env
, mmu_idx
);
1804 result
->f
.phys_addr
= address
;
1805 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
1808 if (regime_translation_disabled(env
, mmu_idx
, secure
) ||
1809 m_is_ppb_region(env
, address
)) {
1811 * MPU disabled or M profile PPB access: use default memory map.
1812 * The other case which uses the default memory map in the
1813 * v7M ARM ARM pseudocode is exception vector reads from the vector
1814 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
1815 * which always does a direct read using address_space_ldl(), rather
1816 * than going via this function, so we don't need to check that here.
1818 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
1819 } else { /* MPU enabled */
1820 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
1822 uint32_t base
= env
->pmsav7
.drbar
[n
];
1823 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
1827 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
1832 qemu_log_mask(LOG_GUEST_ERROR
,
1833 "DRSR[%d]: Rsize field cannot be 0\n", n
);
1837 rmask
= (1ull << rsize
) - 1;
1840 qemu_log_mask(LOG_GUEST_ERROR
,
1841 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
1842 "to DRSR region size, mask = 0x%" PRIx32
"\n",
1847 if (address
< base
|| address
> base
+ rmask
) {
1849 * Address not in this region. We must check whether the
1850 * region covers addresses in the same page as our address.
1851 * In that case we must not report a size that covers the
1852 * whole page for a subsequent hit against a different MPU
1853 * region or the background region, because it would result in
1854 * incorrect TLB hits for subsequent accesses to addresses that
1855 * are in this MPU region.
1857 if (ranges_overlap(base
, rmask
,
1858 address
& TARGET_PAGE_MASK
,
1859 TARGET_PAGE_SIZE
)) {
1860 result
->f
.lg_page_size
= 0;
1865 /* Region matched */
1867 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
1869 uint32_t srdis_mask
;
1871 rsize
-= 3; /* sub region size (power of 2) */
1872 snd
= ((address
- base
) >> rsize
) & 0x7;
1873 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
1875 srdis_mask
= srdis
? 0x3 : 0x0;
1876 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
1878 * This will check in groups of 2, 4 and then 8, whether
1879 * the subregion bits are consistent. rsize is incremented
1880 * back up to give the region size, considering consistent
1881 * adjacent subregions as one region. Stop testing if rsize
1882 * is already big enough for an entire QEMU page.
1884 int snd_rounded
= snd
& ~(i
- 1);
1885 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
1886 snd_rounded
+ 8, i
);
1887 if (srdis_mask
^ srdis_multi
) {
1890 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
1897 if (rsize
< TARGET_PAGE_BITS
) {
1898 result
->f
.lg_page_size
= rsize
;
1903 if (n
== -1) { /* no hits */
1904 if (!pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
1905 /* background fault */
1906 fi
->type
= ARMFault_Background
;
1909 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
,
1911 } else { /* a MPU hit! */
1912 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
1913 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
1915 if (m_is_system_region(env
, address
)) {
1916 /* System space is always execute never */
1920 if (is_user
) { /* User mode AP bit decoding */
1925 break; /* no access */
1927 result
->f
.prot
|= PAGE_WRITE
;
1931 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1934 /* for v7M, same as 6; for R profile a reserved value */
1935 if (arm_feature(env
, ARM_FEATURE_M
)) {
1936 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1941 qemu_log_mask(LOG_GUEST_ERROR
,
1942 "DRACR[%d]: Bad value for AP bits: 0x%"
1943 PRIx32
"\n", n
, ap
);
1945 } else { /* Priv. mode AP bits decoding */
1948 break; /* no access */
1952 result
->f
.prot
|= PAGE_WRITE
;
1956 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1959 /* for v7M, same as 6; for R profile a reserved value */
1960 if (arm_feature(env
, ARM_FEATURE_M
)) {
1961 result
->f
.prot
|= PAGE_READ
| PAGE_EXEC
;
1966 qemu_log_mask(LOG_GUEST_ERROR
,
1967 "DRACR[%d]: Bad value for AP bits: 0x%"
1968 PRIx32
"\n", n
, ap
);
1974 result
->f
.prot
&= ~PAGE_EXEC
;
1979 fi
->type
= ARMFault_Permission
;
1981 return !(result
->f
.prot
& (1 << access_type
));
1984 static uint32_t *regime_rbar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1987 if (regime_el(env
, mmu_idx
) == 2) {
1988 return env
->pmsav8
.hprbar
;
1990 return env
->pmsav8
.rbar
[secure
];
1994 static uint32_t *regime_rlar(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
1997 if (regime_el(env
, mmu_idx
) == 2) {
1998 return env
->pmsav8
.hprlar
;
2000 return env
->pmsav8
.rlar
[secure
];
2004 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
2005 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2006 bool secure
, GetPhysAddrResult
*result
,
2007 ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
2010 * Perform a PMSAv8 MPU lookup (without also doing the SAU check
2011 * that a full phys-to-virt translation does).
2012 * mregion is (if not NULL) set to the region number which matched,
2013 * or -1 if no region number is returned (MPU off, address did not
2014 * hit a region, address hit in multiple regions).
2015 * If the region hit doesn't cover the entire TARGET_PAGE the address
2016 * is within, then we set the result page_size to 1 to force the
2017 * memory system to use a subpage.
2019 ARMCPU
*cpu
= env_archcpu(env
);
2020 bool is_user
= regime_is_user(env
, mmu_idx
);
2022 int matchregion
= -1;
2024 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2025 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2028 if (regime_el(env
, mmu_idx
) == 2) {
2029 region_counter
= cpu
->pmsav8r_hdregion
;
2031 region_counter
= cpu
->pmsav7_dregion
;
2034 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2035 result
->f
.phys_addr
= address
;
2041 if (mmu_idx
== ARMMMUIdx_Stage2
) {
2046 * Unlike the ARM ARM pseudocode, we don't need to check whether this
2047 * was an exception vector read from the vector table (which is always
2048 * done using the default system address map), because those accesses
2049 * are done in arm_v7m_load_vector(), which always does a direct
2050 * read using address_space_ldl(), rather than going via this function.
2052 if (regime_translation_disabled(env
, mmu_idx
, secure
)) { /* MPU disabled */
2054 } else if (m_is_ppb_region(env
, address
)) {
2057 if (pmsav7_use_background_region(cpu
, mmu_idx
, secure
, is_user
)) {
2062 if (arm_feature(env
, ARM_FEATURE_M
)) {
2069 for (n
= region_counter
- 1; n
>= 0; n
--) {
2072 * Note that the base address is bits [31:x] from the register
2073 * with bits [x-1:0] all zeroes, but the limit address is bits
2074 * [31:x] from the register with bits [x:0] all ones. Where x is
2075 * 5 for Cortex-M and 6 for Cortex-R
2077 uint32_t base
= regime_rbar(env
, mmu_idx
, secure
)[n
] & ~bitmask
;
2078 uint32_t limit
= regime_rlar(env
, mmu_idx
, secure
)[n
] | bitmask
;
2080 if (!(regime_rlar(env
, mmu_idx
, secure
)[n
] & 0x1)) {
2081 /* Region disabled */
2085 if (address
< base
|| address
> limit
) {
2087 * Address not in this region. We must check whether the
2088 * region covers addresses in the same page as our address.
2089 * In that case we must not report a size that covers the
2090 * whole page for a subsequent hit against a different MPU
2091 * region or the background region, because it would result in
2092 * incorrect TLB hits for subsequent accesses to addresses that
2093 * are in this MPU region.
2095 if (limit
>= base
&&
2096 ranges_overlap(base
, limit
- base
+ 1,
2098 TARGET_PAGE_SIZE
)) {
2099 result
->f
.lg_page_size
= 0;
2104 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2105 result
->f
.lg_page_size
= 0;
2108 if (matchregion
!= -1) {
2110 * Multiple regions match -- always a failure (unlike
2111 * PMSAv7 where highest-numbered-region wins)
2113 fi
->type
= ARMFault_Permission
;
2114 if (arm_feature(env
, ARM_FEATURE_M
)) {
2126 if (arm_feature(env
, ARM_FEATURE_M
)) {
2127 fi
->type
= ARMFault_Background
;
2129 fi
->type
= ARMFault_Permission
;
2134 if (matchregion
== -1) {
2135 /* hit using the background region */
2136 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, &result
->f
.prot
);
2138 uint32_t matched_rbar
= regime_rbar(env
, mmu_idx
, secure
)[matchregion
];
2139 uint32_t matched_rlar
= regime_rlar(env
, mmu_idx
, secure
)[matchregion
];
2140 uint32_t ap
= extract32(matched_rbar
, 1, 2);
2141 uint32_t xn
= extract32(matched_rbar
, 0, 1);
2144 if (arm_feature(env
, ARM_FEATURE_V8_1M
)) {
2145 pxn
= extract32(matched_rlar
, 4, 1);
2148 if (m_is_system_region(env
, address
)) {
2149 /* System space is always execute never */
2153 if (regime_el(env
, mmu_idx
) == 2) {
2154 result
->f
.prot
= simple_ap_to_rw_prot_is_user(ap
,
2155 mmu_idx
!= ARMMMUIdx_E2
);
2157 result
->f
.prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
2160 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2161 uint8_t attrindx
= extract32(matched_rlar
, 1, 3);
2162 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
2163 uint8_t sh
= extract32(matched_rlar
, 3, 2);
2165 if (regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
&&
2166 result
->f
.prot
& PAGE_WRITE
&& mmu_idx
!= ARMMMUIdx_Stage2
) {
2170 if ((regime_el(env
, mmu_idx
) == 1) &&
2171 regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
&& ap
== 0x1) {
2175 result
->cacheattrs
.is_s2_format
= false;
2176 result
->cacheattrs
.attrs
= extract64(mair
, attrindx
* 8, 8);
2177 result
->cacheattrs
.shareability
= sh
;
2180 if (result
->f
.prot
&& !xn
&& !(pxn
&& !is_user
)) {
2181 result
->f
.prot
|= PAGE_EXEC
;
2185 *mregion
= matchregion
;
2189 fi
->type
= ARMFault_Permission
;
2190 if (arm_feature(env
, ARM_FEATURE_M
)) {
2193 return !(result
->f
.prot
& (1 << access_type
));
2196 static bool v8m_is_sau_exempt(CPUARMState
*env
,
2197 uint32_t address
, MMUAccessType access_type
)
2200 * The architecture specifies that certain address ranges are
2201 * exempt from v8M SAU/IDAU checks.
2204 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
2205 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
2206 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
2207 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
2208 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
2209 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
2212 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
2213 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2214 bool is_secure
, V8M_SAttributes
*sattrs
)
2217 * Look up the security attributes for this address. Compare the
2218 * pseudocode SecurityCheck() function.
2219 * We assume the caller has zero-initialized *sattrs.
2221 ARMCPU
*cpu
= env_archcpu(env
);
2223 bool idau_exempt
= false, idau_ns
= true, idau_nsc
= true;
2224 int idau_region
= IREGION_NOTVALID
;
2225 uint32_t addr_page_base
= address
& TARGET_PAGE_MASK
;
2226 uint32_t addr_page_limit
= addr_page_base
+ (TARGET_PAGE_SIZE
- 1);
2229 IDAUInterfaceClass
*iic
= IDAU_INTERFACE_GET_CLASS(cpu
->idau
);
2230 IDAUInterface
*ii
= IDAU_INTERFACE(cpu
->idau
);
2232 iic
->check(ii
, address
, &idau_region
, &idau_exempt
, &idau_ns
,
2236 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
2237 /* 0xf0000000..0xffffffff is always S for insn fetches */
2241 if (idau_exempt
|| v8m_is_sau_exempt(env
, address
, access_type
)) {
2242 sattrs
->ns
= !is_secure
;
2246 if (idau_region
!= IREGION_NOTVALID
) {
2247 sattrs
->irvalid
= true;
2248 sattrs
->iregion
= idau_region
;
2251 switch (env
->sau
.ctrl
& 3) {
2252 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
2254 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
2257 default: /* SAU.ENABLE == 1 */
2258 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
2259 if (env
->sau
.rlar
[r
] & 1) {
2260 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
2261 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
2263 if (base
<= address
&& limit
>= address
) {
2264 if (base
> addr_page_base
|| limit
< addr_page_limit
) {
2265 sattrs
->subpage
= true;
2267 if (sattrs
->srvalid
) {
2269 * If we hit in more than one region then we must report
2270 * as Secure, not NS-Callable, with no valid region
2274 sattrs
->nsc
= false;
2275 sattrs
->sregion
= 0;
2276 sattrs
->srvalid
= false;
2279 if (env
->sau
.rlar
[r
] & 2) {
2284 sattrs
->srvalid
= true;
2285 sattrs
->sregion
= r
;
2289 * Address not in this region. We must check whether the
2290 * region covers addresses in the same page as our address.
2291 * In that case we must not report a size that covers the
2292 * whole page for a subsequent hit against a different MPU
2293 * region or the background region, because it would result
2294 * in incorrect TLB hits for subsequent accesses to
2295 * addresses that are in this MPU region.
2297 if (limit
>= base
&&
2298 ranges_overlap(base
, limit
- base
+ 1,
2300 TARGET_PAGE_SIZE
)) {
2301 sattrs
->subpage
= true;
2310 * The IDAU will override the SAU lookup results if it specifies
2311 * higher security than the SAU does.
2314 if (sattrs
->ns
|| (!idau_nsc
&& sattrs
->nsc
)) {
2316 sattrs
->nsc
= idau_nsc
;
2321 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
2322 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2323 bool secure
, GetPhysAddrResult
*result
,
2324 ARMMMUFaultInfo
*fi
)
2326 V8M_SAttributes sattrs
= {};
2329 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2330 v8m_security_lookup(env
, address
, access_type
, mmu_idx
,
2332 if (access_type
== MMU_INST_FETCH
) {
2334 * Instruction fetches always use the MMU bank and the
2335 * transaction attribute determined by the fetch address,
2336 * regardless of CPU state. This is painful for QEMU
2337 * to handle, because it would mean we need to encode
2338 * into the mmu_idx not just the (user, negpri) information
2339 * for the current security state but also that for the
2340 * other security state, which would balloon the number
2341 * of mmu_idx values needed alarmingly.
2342 * Fortunately we can avoid this because it's not actually
2343 * possible to arbitrarily execute code from memory with
2344 * the wrong security attribute: it will always generate
2345 * an exception of some kind or another, apart from the
2346 * special case of an NS CPU executing an SG instruction
2347 * in S&NSC memory. So we always just fail the translation
2348 * here and sort things out in the exception handler
2349 * (including possibly emulating an SG instruction).
2351 if (sattrs
.ns
!= !secure
) {
2353 fi
->type
= ARMFault_QEMU_NSCExec
;
2355 fi
->type
= ARMFault_QEMU_SFault
;
2357 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2358 result
->f
.phys_addr
= address
;
2364 * For data accesses we always use the MMU bank indicated
2365 * by the current CPU state, but the security attributes
2366 * might downgrade a secure access to nonsecure.
2369 result
->f
.attrs
.secure
= false;
2370 } else if (!secure
) {
2372 * NS access to S memory must fault.
2373 * Architecturally we should first check whether the
2374 * MPU information for this address indicates that we
2375 * are doing an unaligned access to Device memory, which
2376 * should generate a UsageFault instead. QEMU does not
2377 * currently check for that kind of unaligned access though.
2378 * If we added it we would need to do so as a special case
2379 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
2381 fi
->type
= ARMFault_QEMU_SFault
;
2382 result
->f
.lg_page_size
= sattrs
.subpage
? 0 : TARGET_PAGE_BITS
;
2383 result
->f
.phys_addr
= address
;
2390 ret
= pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, secure
,
2392 if (sattrs
.subpage
) {
2393 result
->f
.lg_page_size
= 0;
2399 * Translate from the 4-bit stage 2 representation of
2400 * memory attributes (without cache-allocation hints) to
2401 * the 8-bit representation of the stage 1 MAIR registers
2402 * (which includes allocation hints).
2404 * ref: shared/translation/attrs/S2AttrDecode()
2405 * .../S2ConvertAttrsHints()
2407 static uint8_t convert_stage2_attrs(uint64_t hcr
, uint8_t s2attrs
)
2409 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
2410 uint8_t loattr
= extract32(s2attrs
, 0, 2);
2411 uint8_t hihint
= 0, lohint
= 0;
2413 if (hiattr
!= 0) { /* normal memory */
2414 if (hcr
& HCR_CD
) { /* cache disabled */
2415 hiattr
= loattr
= 1; /* non-cacheable */
2417 if (hiattr
!= 1) { /* Write-through or write-back */
2418 hihint
= 3; /* RW allocate */
2420 if (loattr
!= 1) { /* Write-through or write-back */
2421 lohint
= 3; /* RW allocate */
2426 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
2430 * Combine either inner or outer cacheability attributes for normal
2431 * memory, according to table D4-42 and pseudocode procedure
2432 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
2434 * NB: only stage 1 includes allocation hints (RW bits), leading to
2437 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
2439 if (s1
== 4 || s2
== 4) {
2440 /* non-cacheable has precedence */
2442 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
2443 /* stage 1 write-through takes precedence */
2445 } else if (extract32(s2
, 2, 2) == 2) {
2446 /* stage 2 write-through takes precedence, but the allocation hint
2447 * is still taken from stage 1
2449 return (2 << 2) | extract32(s1
, 0, 2);
2450 } else { /* write-back */
2456 * Combine the memory type and cacheability attributes of
2457 * s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
2458 * combined attributes in MAIR_EL1 format.
2460 static uint8_t combined_attrs_nofwb(uint64_t hcr
,
2461 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2463 uint8_t s1lo
, s2lo
, s1hi
, s2hi
, s2_mair_attrs
, ret_attrs
;
2465 if (s2
.is_s2_format
) {
2466 s2_mair_attrs
= convert_stage2_attrs(hcr
, s2
.attrs
);
2468 s2_mair_attrs
= s2
.attrs
;
2471 s1lo
= extract32(s1
.attrs
, 0, 4);
2472 s2lo
= extract32(s2_mair_attrs
, 0, 4);
2473 s1hi
= extract32(s1
.attrs
, 4, 4);
2474 s2hi
= extract32(s2_mair_attrs
, 4, 4);
2476 /* Combine memory type and cacheability attributes */
2477 if (s1hi
== 0 || s2hi
== 0) {
2478 /* Device has precedence over normal */
2479 if (s1lo
== 0 || s2lo
== 0) {
2480 /* nGnRnE has precedence over anything */
2482 } else if (s1lo
== 4 || s2lo
== 4) {
2483 /* non-Reordering has precedence over Reordering */
2484 ret_attrs
= 4; /* nGnRE */
2485 } else if (s1lo
== 8 || s2lo
== 8) {
2486 /* non-Gathering has precedence over Gathering */
2487 ret_attrs
= 8; /* nGRE */
2489 ret_attrs
= 0xc; /* GRE */
2491 } else { /* Normal memory */
2492 /* Outer/inner cacheability combine independently */
2493 ret_attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
2494 | combine_cacheattr_nibble(s1lo
, s2lo
);
2499 static uint8_t force_cacheattr_nibble_wb(uint8_t attr
)
2502 * Given the 4 bits specifying the outer or inner cacheability
2503 * in MAIR format, return a value specifying Normal Write-Back,
2504 * with the allocation and transient hints taken from the input
2505 * if the input specified some kind of cacheable attribute.
2507 if (attr
== 0 || attr
== 4) {
2509 * 0 == an UNPREDICTABLE encoding
2510 * 4 == Non-cacheable
2511 * Either way, force Write-Back RW allocate non-transient
2515 /* Change WriteThrough to WriteBack, keep allocation and transient hints */
2520 * Combine the memory type and cacheability attributes of
2521 * s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
2522 * combined attributes in MAIR_EL1 format.
2524 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2526 assert(s2
.is_s2_format
&& !s1
.is_s2_format
);
2530 /* Use stage 1 attributes */
2534 * Force Normal Write-Back. Note that if S1 is Normal cacheable
2535 * then we take the allocation hints from it; otherwise it is
2536 * RW allocate, non-transient.
2538 if ((s1
.attrs
& 0xf0) == 0) {
2542 /* Need to check the Inner and Outer nibbles separately */
2543 return force_cacheattr_nibble_wb(s1
.attrs
& 0xf) |
2544 force_cacheattr_nibble_wb(s1
.attrs
>> 4) << 4;
2546 /* If S1 attrs are Device, use them; otherwise Normal Non-cacheable */
2547 if ((s1
.attrs
& 0xf0) == 0) {
2552 /* Force Device, of subtype specified by S2 */
2553 return s2
.attrs
<< 2;
2556 * RESERVED values (including RES0 descriptor bit [5] being nonzero);
2557 * arbitrarily force Device.
2564 * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
2565 * and CombineS1S2Desc()
2568 * @s1: Attributes from stage 1 walk
2569 * @s2: Attributes from stage 2 walk
2571 static ARMCacheAttrs
combine_cacheattrs(uint64_t hcr
,
2572 ARMCacheAttrs s1
, ARMCacheAttrs s2
)
2575 bool tagged
= false;
2577 assert(!s1
.is_s2_format
);
2578 ret
.is_s2_format
= false;
2580 if (s1
.attrs
== 0xf0) {
2585 /* Combine shareability attributes (table D4-43) */
2586 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
2587 /* if either are outer-shareable, the result is outer-shareable */
2588 ret
.shareability
= 2;
2589 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
2590 /* if either are inner-shareable, the result is inner-shareable */
2591 ret
.shareability
= 3;
2593 /* both non-shareable */
2594 ret
.shareability
= 0;
2597 /* Combine memory type and cacheability attributes */
2598 if (hcr
& HCR_FWB
) {
2599 ret
.attrs
= combined_attrs_fwb(s1
, s2
);
2601 ret
.attrs
= combined_attrs_nofwb(hcr
, s1
, s2
);
2605 * Any location for which the resultant memory type is any
2606 * type of Device memory is always treated as Outer Shareable.
2607 * Any location for which the resultant memory type is Normal
2608 * Inner Non-cacheable, Outer Non-cacheable is always treated
2609 * as Outer Shareable.
2610 * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC
2612 if ((ret
.attrs
& 0xf0) == 0 || ret
.attrs
== 0x44) {
2613 ret
.shareability
= 2;
2616 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
2617 if (tagged
&& ret
.attrs
== 0xff) {
2625 * MMU disabled. S1 addresses within aa64 translation regimes are
2626 * still checked for bounds -- see AArch64.S1DisabledOutput().
2628 static bool get_phys_addr_disabled(CPUARMState
*env
, target_ulong address
,
2629 MMUAccessType access_type
,
2630 ARMMMUIdx mmu_idx
, bool is_secure
,
2631 GetPhysAddrResult
*result
,
2632 ARMMMUFaultInfo
*fi
)
2634 uint8_t memattr
= 0x00; /* Device nGnRnE */
2635 uint8_t shareability
= 0; /* non-sharable */
2639 case ARMMMUIdx_Stage2
:
2640 case ARMMMUIdx_Stage2_S
:
2641 case ARMMMUIdx_Phys_NS
:
2642 case ARMMMUIdx_Phys_S
:
2646 r_el
= regime_el(env
, mmu_idx
);
2647 if (arm_el_is_aa64(env
, r_el
)) {
2648 int pamax
= arm_pamax(env_archcpu(env
));
2649 uint64_t tcr
= env
->cp15
.tcr_el
[r_el
];
2652 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
2653 if (access_type
== MMU_INST_FETCH
) {
2654 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
2656 tbi
= (tbi
>> extract64(address
, 55, 1)) & 1;
2657 addrtop
= (tbi
? 55 : 63);
2659 if (extract64(address
, pamax
, addrtop
- pamax
+ 1) != 0) {
2660 fi
->type
= ARMFault_AddressSize
;
2667 * When TBI is disabled, we've just validated that all of the
2668 * bits above PAMax are zero, so logically we only need to
2669 * clear the top byte for TBI. But it's clearer to follow
2670 * the pseudocode set of addrdesc.paddress.
2672 address
= extract64(address
, 0, 52);
2675 /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
2677 uint64_t hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2679 if (hcr
& HCR_DCT
) {
2680 memattr
= 0xf0; /* Tagged, Normal, WB, RWA */
2682 memattr
= 0xff; /* Normal, WB, RWA */
2686 if (memattr
== 0 && access_type
== MMU_INST_FETCH
) {
2687 if (regime_sctlr(env
, mmu_idx
) & SCTLR_I
) {
2688 memattr
= 0xee; /* Normal, WT, RA, NT */
2690 memattr
= 0x44; /* Normal, NC, No */
2692 shareability
= 2; /* outer sharable */
2694 result
->cacheattrs
.is_s2_format
= false;
2698 result
->f
.phys_addr
= address
;
2699 result
->f
.prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2700 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2701 result
->cacheattrs
.shareability
= shareability
;
2702 result
->cacheattrs
.attrs
= memattr
;
2706 static bool get_phys_addr_twostage(CPUARMState
*env
, S1Translate
*ptw
,
2707 target_ulong address
,
2708 MMUAccessType access_type
,
2709 GetPhysAddrResult
*result
,
2710 ARMMMUFaultInfo
*fi
)
2713 int s1_prot
, s1_lgpgsz
;
2714 bool is_secure
= ptw
->in_secure
;
2715 bool ret
, ipa_secure
, s2walk_secure
;
2716 ARMCacheAttrs cacheattrs1
;
2720 ret
= get_phys_addr_with_struct(env
, ptw
, address
, access_type
, result
, fi
);
2722 /* If S1 fails, return early. */
2727 ipa
= result
->f
.phys_addr
;
2728 ipa_secure
= result
->f
.attrs
.secure
;
2730 /* Select TCR based on the NS bit from the S1 walk. */
2731 s2walk_secure
= !(ipa_secure
2732 ? env
->cp15
.vstcr_el2
& VSTCR_SW
2733 : env
->cp15
.vtcr_el2
& VTCR_NSW
);
2735 assert(!ipa_secure
);
2736 s2walk_secure
= false;
2739 is_el0
= ptw
->in_mmu_idx
== ARMMMUIdx_Stage1_E0
;
2740 ptw
->in_mmu_idx
= s2walk_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2741 ptw
->in_ptw_idx
= s2walk_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2742 ptw
->in_secure
= s2walk_secure
;
2745 * S1 is done, now do S2 translation.
2746 * Save the stage1 results so that we may merge prot and cacheattrs later.
2748 s1_prot
= result
->f
.prot
;
2749 s1_lgpgsz
= result
->f
.lg_page_size
;
2750 cacheattrs1
= result
->cacheattrs
;
2751 memset(result
, 0, sizeof(*result
));
2753 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2754 ret
= get_phys_addr_pmsav8(env
, ipa
, access_type
,
2755 ptw
->in_mmu_idx
, is_secure
, result
, fi
);
2757 ret
= get_phys_addr_lpae(env
, ptw
, ipa
, access_type
,
2758 is_el0
, result
, fi
);
2762 /* Combine the S1 and S2 perms. */
2763 result
->f
.prot
&= s1_prot
;
2765 /* If S2 fails, return early. */
2771 * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
2772 * this means "don't put this in the TLB"; in this case, return a
2773 * result with lg_page_size == 0 to achieve that. Otherwise,
2774 * use the maximum of the S1 & S2 page size, so that invalidation
2775 * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
2776 * we know the combined result permissions etc only cover the minimum
2777 * of the S1 and S2 page size, because we know that the common TLB code
2778 * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
2779 * and passing a larger page size value only affects invalidations.)
2781 if (result
->f
.lg_page_size
< TARGET_PAGE_BITS
||
2782 s1_lgpgsz
< TARGET_PAGE_BITS
) {
2783 result
->f
.lg_page_size
= 0;
2784 } else if (result
->f
.lg_page_size
< s1_lgpgsz
) {
2785 result
->f
.lg_page_size
= s1_lgpgsz
;
2788 /* Combine the S1 and S2 cache attributes. */
2789 hcr
= arm_hcr_el2_eff_secstate(env
, is_secure
);
2792 * HCR.DC forces the first stage attributes to
2793 * Normal Non-Shareable,
2794 * Inner Write-Back Read-Allocate Write-Allocate,
2795 * Outer Write-Back Read-Allocate Write-Allocate.
2796 * Do not overwrite Tagged within attrs.
2798 if (cacheattrs1
.attrs
!= 0xf0) {
2799 cacheattrs1
.attrs
= 0xff;
2801 cacheattrs1
.shareability
= 0;
2803 result
->cacheattrs
= combine_cacheattrs(hcr
, cacheattrs1
,
2804 result
->cacheattrs
);
2807 * Check if IPA translates to secure or non-secure PA space.
2808 * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
2810 result
->f
.attrs
.secure
=
2812 && !(env
->cp15
.vstcr_el2
& (VSTCR_SA
| VSTCR_SW
))
2814 || !(env
->cp15
.vtcr_el2
& (VTCR_NSA
| VTCR_NSW
))));
2819 static bool get_phys_addr_with_struct(CPUARMState
*env
, S1Translate
*ptw
,
2820 target_ulong address
,
2821 MMUAccessType access_type
,
2822 GetPhysAddrResult
*result
,
2823 ARMMMUFaultInfo
*fi
)
2825 ARMMMUIdx mmu_idx
= ptw
->in_mmu_idx
;
2826 bool is_secure
= ptw
->in_secure
;
2827 ARMMMUIdx s1_mmu_idx
;
2830 * The page table entries may downgrade secure to non-secure, but
2831 * cannot upgrade an non-secure translation regime's attributes
2834 result
->f
.attrs
.secure
= is_secure
;
2837 case ARMMMUIdx_Phys_S
:
2838 case ARMMMUIdx_Phys_NS
:
2839 /* Checking Phys early avoids special casing later vs regime_el. */
2840 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2841 is_secure
, result
, fi
);
2843 case ARMMMUIdx_Stage1_E0
:
2844 case ARMMMUIdx_Stage1_E1
:
2845 case ARMMMUIdx_Stage1_E1_PAN
:
2846 /* First stage lookup uses second stage for ptw. */
2847 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Stage2_S
: ARMMMUIdx_Stage2
;
2850 case ARMMMUIdx_E10_0
:
2851 s1_mmu_idx
= ARMMMUIdx_Stage1_E0
;
2853 case ARMMMUIdx_E10_1
:
2854 s1_mmu_idx
= ARMMMUIdx_Stage1_E1
;
2856 case ARMMMUIdx_E10_1_PAN
:
2857 s1_mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
2860 * Call ourselves recursively to do the stage 1 and then stage 2
2861 * translations if mmu_idx is a two-stage regime, and EL2 present.
2862 * Otherwise, a stage1+stage2 translation is just stage 1.
2864 ptw
->in_mmu_idx
= mmu_idx
= s1_mmu_idx
;
2865 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
2866 !regime_translation_disabled(env
, ARMMMUIdx_Stage2
, is_secure
)) {
2867 return get_phys_addr_twostage(env
, ptw
, address
, access_type
,
2873 /* Single stage and second stage uses physical for ptw. */
2874 ptw
->in_ptw_idx
= is_secure
? ARMMMUIdx_Phys_S
: ARMMMUIdx_Phys_NS
;
2878 result
->f
.attrs
.user
= regime_is_user(env
, mmu_idx
);
2881 * Fast Context Switch Extension. This doesn't exist at all in v8.
2882 * In v7 and earlier it affects all stage 1 translations.
2884 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_Stage2
2885 && !arm_feature(env
, ARM_FEATURE_V8
)) {
2886 if (regime_el(env
, mmu_idx
) == 3) {
2887 address
+= env
->cp15
.fcseidr_s
;
2889 address
+= env
->cp15
.fcseidr_ns
;
2893 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
2895 result
->f
.lg_page_size
= TARGET_PAGE_BITS
;
2897 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2899 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
2900 is_secure
, result
, fi
);
2901 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2903 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
2904 is_secure
, result
, fi
);
2907 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
2908 is_secure
, result
, fi
);
2910 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
2911 " mmu_idx %u -> %s (prot %c%c%c)\n",
2912 access_type
== MMU_DATA_LOAD
? "reading" :
2913 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
2914 (uint32_t)address
, mmu_idx
,
2915 ret
? "Miss" : "Hit",
2916 result
->f
.prot
& PAGE_READ
? 'r' : '-',
2917 result
->f
.prot
& PAGE_WRITE
? 'w' : '-',
2918 result
->f
.prot
& PAGE_EXEC
? 'x' : '-');
2923 /* Definitely a real MMU, not an MPU */
2925 if (regime_translation_disabled(env
, mmu_idx
, is_secure
)) {
2926 return get_phys_addr_disabled(env
, address
, access_type
, mmu_idx
,
2927 is_secure
, result
, fi
);
2930 if (regime_using_lpae_format(env
, mmu_idx
)) {
2931 return get_phys_addr_lpae(env
, ptw
, address
, access_type
, false,
2933 } else if (arm_feature(env
, ARM_FEATURE_V7
) ||
2934 regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
2935 return get_phys_addr_v6(env
, ptw
, address
, access_type
, result
, fi
);
2937 return get_phys_addr_v5(env
, ptw
, address
, access_type
, result
, fi
);
2941 bool get_phys_addr_with_secure(CPUARMState
*env
, target_ulong address
,
2942 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2943 bool is_secure
, GetPhysAddrResult
*result
,
2944 ARMMMUFaultInfo
*fi
)
2947 .in_mmu_idx
= mmu_idx
,
2948 .in_secure
= is_secure
,
2950 return get_phys_addr_with_struct(env
, &ptw
, address
, access_type
,
2954 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
2955 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
2956 GetPhysAddrResult
*result
, ARMMMUFaultInfo
*fi
)
2961 case ARMMMUIdx_E10_0
:
2962 case ARMMMUIdx_E10_1
:
2963 case ARMMMUIdx_E10_1_PAN
:
2964 case ARMMMUIdx_E20_0
:
2965 case ARMMMUIdx_E20_2
:
2966 case ARMMMUIdx_E20_2_PAN
:
2967 case ARMMMUIdx_Stage1_E0
:
2968 case ARMMMUIdx_Stage1_E1
:
2969 case ARMMMUIdx_Stage1_E1_PAN
:
2971 is_secure
= arm_is_secure_below_el3(env
);
2973 case ARMMMUIdx_Stage2
:
2974 case ARMMMUIdx_Phys_NS
:
2975 case ARMMMUIdx_MPrivNegPri
:
2976 case ARMMMUIdx_MUserNegPri
:
2977 case ARMMMUIdx_MPriv
:
2978 case ARMMMUIdx_MUser
:
2982 case ARMMMUIdx_Stage2_S
:
2983 case ARMMMUIdx_Phys_S
:
2984 case ARMMMUIdx_MSPrivNegPri
:
2985 case ARMMMUIdx_MSUserNegPri
:
2986 case ARMMMUIdx_MSPriv
:
2987 case ARMMMUIdx_MSUser
:
2991 g_assert_not_reached();
2993 return get_phys_addr_with_secure(env
, address
, access_type
, mmu_idx
,
2994 is_secure
, result
, fi
);
2997 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
3000 ARMCPU
*cpu
= ARM_CPU(cs
);
3001 CPUARMState
*env
= &cpu
->env
;
3003 .in_mmu_idx
= arm_mmu_idx(env
),
3004 .in_secure
= arm_is_secure(env
),
3007 GetPhysAddrResult res
= {};
3008 ARMMMUFaultInfo fi
= {};
3011 ret
= get_phys_addr_with_struct(env
, &ptw
, addr
, MMU_DATA_LOAD
, &res
, &fi
);
3012 *attrs
= res
.f
.attrs
;
3017 return res
.f
.phys_addr
;