4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "translate.h"
22 #include "translate-a64.h"
24 #include "disas/disas.h"
26 #include "semihosting/semihost.h"
29 static TCGv_i64 cpu_X
[32];
30 static TCGv_i64 cpu_pc
;
32 /* Load/store exclusive handling */
33 static TCGv_i64 cpu_exclusive_high
;
35 static const char *regnames
[] = {
36 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
37 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
38 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
39 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
43 A64_SHIFT_TYPE_LSL
= 0,
44 A64_SHIFT_TYPE_LSR
= 1,
45 A64_SHIFT_TYPE_ASR
= 2,
46 A64_SHIFT_TYPE_ROR
= 3
50 * Include the generated decoders.
53 #include "decode-sme-fa64.c.inc"
54 #include "decode-a64.c.inc"
56 /* Table based decoder typedefs - used when the relevant bits for decode
57 * are too awkwardly scattered across the instruction (eg SIMD).
59 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
61 typedef struct AArch64DecodeTable
{
64 AArch64DecodeFn
*disas_fn
;
67 /* initialize TCG globals. */
68 void a64_translate_init(void)
72 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
73 offsetof(CPUARMState
, pc
),
75 for (i
= 0; i
< 32; i
++) {
76 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
77 offsetof(CPUARMState
, xregs
[i
]),
81 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
82 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
86 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
88 static int get_a64_user_mem_index(DisasContext
*s
)
91 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
92 * which is the usual mmu_idx for this cpu state.
94 ARMMMUIdx useridx
= s
->mmu_idx
;
98 * We have pre-computed the condition for AccType_UNPRIV.
99 * Therefore we should never get here with a mmu_idx for
100 * which we do not know the corresponding user mmu_idx.
103 case ARMMMUIdx_E10_1
:
104 case ARMMMUIdx_E10_1_PAN
:
105 useridx
= ARMMMUIdx_E10_0
;
107 case ARMMMUIdx_E20_2
:
108 case ARMMMUIdx_E20_2_PAN
:
109 useridx
= ARMMMUIdx_E20_0
;
112 g_assert_not_reached();
115 return arm_to_core_mmu_idx(useridx
);
118 static void set_btype_raw(int val
)
120 tcg_gen_st_i32(tcg_constant_i32(val
), cpu_env
,
121 offsetof(CPUARMState
, btype
));
124 static void set_btype(DisasContext
*s
, int val
)
126 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
127 tcg_debug_assert(val
>= 1 && val
<= 3);
132 static void reset_btype(DisasContext
*s
)
140 static void gen_pc_plus_diff(DisasContext
*s
, TCGv_i64 dest
, target_long diff
)
142 assert(s
->pc_save
!= -1);
143 if (tb_cflags(s
->base
.tb
) & CF_PCREL
) {
144 tcg_gen_addi_i64(dest
, cpu_pc
, (s
->pc_curr
- s
->pc_save
) + diff
);
146 tcg_gen_movi_i64(dest
, s
->pc_curr
+ diff
);
150 void gen_a64_update_pc(DisasContext
*s
, target_long diff
)
152 gen_pc_plus_diff(s
, cpu_pc
, diff
);
153 s
->pc_save
= s
->pc_curr
+ diff
;
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
184 /* tbi0 but !tbi1: only use the extension if positive */
185 tcg_gen_and_i64(dst
, dst
, src
);
188 /* !tbi0 but tbi1: only use the extension if negative */
189 tcg_gen_or_i64(dst
, dst
, src
);
192 /* tbi0 and tbi1: always use the extension */
195 g_assert_not_reached();
200 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
203 * If address tagging is enabled for instructions via the TCR TBI bits,
204 * then loading an address into the PC will clear out any tag.
206 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
211 * Handle MTE and/or TBI.
213 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
214 * for the tag to be present in the FAR_ELx register. But for user-only
215 * mode we do not have a TLB with which to implement this, so we must
216 * remove the top byte now.
218 * Always return a fresh temporary that we can increment independently
219 * of the write-back address.
222 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
224 TCGv_i64 clean
= tcg_temp_new_i64();
225 #ifdef CONFIG_USER_ONLY
226 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
228 tcg_gen_mov_i64(clean
, addr
);
233 /* Insert a zero tag into src, with the result at dst. */
234 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
236 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
239 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
240 MMUAccessType acc
, int log2_size
)
242 gen_helper_probe_access(cpu_env
, ptr
,
243 tcg_constant_i32(acc
),
244 tcg_constant_i32(get_mem_index(s
)),
245 tcg_constant_i32(1 << log2_size
));
249 * For MTE, check a single logical or atomic access. This probes a single
250 * address, the exact one specified. The size and alignment of the access
251 * is not relevant to MTE, per se, but watchpoints do require the size,
252 * and we want to recognize those before making any other changes to state.
254 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
255 bool is_write
, bool tag_checked
,
256 int log2_size
, bool is_unpriv
,
259 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
263 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
264 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
265 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
266 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
267 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << log2_size
) - 1);
269 ret
= tcg_temp_new_i64();
270 gen_helper_mte_check(ret
, cpu_env
, tcg_constant_i32(desc
), addr
);
274 return clean_data_tbi(s
, addr
);
277 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
278 bool tag_checked
, int log2_size
)
280 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
281 false, get_mem_index(s
));
285 * For MTE, check multiple logical sequential accesses.
287 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
288 bool tag_checked
, int size
)
290 if (tag_checked
&& s
->mte_active
[0]) {
294 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
295 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
296 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
297 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
298 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, size
- 1);
300 ret
= tcg_temp_new_i64();
301 gen_helper_mte_check(ret
, cpu_env
, tcg_constant_i32(desc
), addr
);
305 return clean_data_tbi(s
, addr
);
308 typedef struct DisasCompare64
{
313 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
317 arm_test_cc(&c32
, cc
);
320 * Sign-extend the 32-bit value so that the GE/LT comparisons work
321 * properly. The NE/EQ comparisons are also fine with this choice.
323 c64
->cond
= c32
.cond
;
324 c64
->value
= tcg_temp_new_i64();
325 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
328 static void gen_rebuild_hflags(DisasContext
*s
)
330 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_constant_i32(s
->current_el
));
333 static void gen_exception_internal(int excp
)
335 assert(excp_is_internal(excp
));
336 gen_helper_exception_internal(cpu_env
, tcg_constant_i32(excp
));
339 static void gen_exception_internal_insn(DisasContext
*s
, int excp
)
341 gen_a64_update_pc(s
, 0);
342 gen_exception_internal(excp
);
343 s
->base
.is_jmp
= DISAS_NORETURN
;
346 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
348 gen_a64_update_pc(s
, 0);
349 gen_helper_exception_bkpt_insn(cpu_env
, tcg_constant_i32(syndrome
));
350 s
->base
.is_jmp
= DISAS_NORETURN
;
353 static void gen_step_complete_exception(DisasContext
*s
)
355 /* We just completed step of an insn. Move from Active-not-pending
356 * to Active-pending, and then also take the swstep exception.
357 * This corresponds to making the (IMPDEF) choice to prioritize
358 * swstep exceptions over asynchronous exceptions taken to an exception
359 * level where debug is disabled. This choice has the advantage that
360 * we do not need to maintain internal state corresponding to the
361 * ISV/EX syndrome bits between completion of the step and generation
362 * of the exception, and our syndrome information is always correct.
365 gen_swstep_exception(s
, 1, s
->is_ldex
);
366 s
->base
.is_jmp
= DISAS_NORETURN
;
369 static inline bool use_goto_tb(DisasContext
*s
, uint64_t dest
)
374 return translator_use_goto_tb(&s
->base
, dest
);
377 static void gen_goto_tb(DisasContext
*s
, int n
, int64_t diff
)
379 if (use_goto_tb(s
, s
->pc_curr
+ diff
)) {
381 * For pcrel, the pc must always be up-to-date on entry to
382 * the linked TB, so that it can use simple additions for all
383 * further adjustments. For !pcrel, the linked TB is compiled
384 * to know its full virtual address, so we can delay the
385 * update to pc to the unlinked path. A long chain of links
386 * can thus avoid many updates to the PC.
388 if (tb_cflags(s
->base
.tb
) & CF_PCREL
) {
389 gen_a64_update_pc(s
, diff
);
393 gen_a64_update_pc(s
, diff
);
395 tcg_gen_exit_tb(s
->base
.tb
, n
);
396 s
->base
.is_jmp
= DISAS_NORETURN
;
398 gen_a64_update_pc(s
, diff
);
400 gen_step_complete_exception(s
);
402 tcg_gen_lookup_and_goto_ptr();
403 s
->base
.is_jmp
= DISAS_NORETURN
;
409 * Register access functions
411 * These functions are used for directly accessing a register in where
412 * changes to the final register value are likely to be made. If you
413 * need to use a register for temporary calculation (e.g. index type
414 * operations) use the read_* form.
416 * B1.2.1 Register mappings
418 * In instruction register encoding 31 can refer to ZR (zero register) or
419 * the SP (stack pointer) depending on context. In QEMU's case we map SP
420 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
421 * This is the point of the _sp forms.
423 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
426 TCGv_i64 t
= tcg_temp_new_i64();
427 tcg_gen_movi_i64(t
, 0);
434 /* register access for when 31 == SP */
435 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
440 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
441 * representing the register contents. This TCGv is an auto-freed
442 * temporary so it need not be explicitly freed, and may be modified.
444 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
446 TCGv_i64 v
= tcg_temp_new_i64();
449 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
451 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
454 tcg_gen_movi_i64(v
, 0);
459 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
461 TCGv_i64 v
= tcg_temp_new_i64();
463 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
465 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
470 /* Return the offset into CPUARMState of a slice (from
471 * the least significant end) of FP register Qn (ie
473 * (Note that this is not the same mapping as for A32; see cpu.h)
475 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
477 return vec_reg_offset(s
, regno
, 0, size
);
480 /* Offset of the high half of the 128 bit vector Qn */
481 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
483 return vec_reg_offset(s
, regno
, 1, MO_64
);
486 /* Convenience accessors for reading and writing single and double
487 * FP registers. Writing clears the upper parts of the associated
488 * 128 bit vector register, as required by the architecture.
489 * Note that unlike the GP register accessors, the values returned
490 * by the read functions must be manually freed.
492 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
494 TCGv_i64 v
= tcg_temp_new_i64();
496 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
500 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
502 TCGv_i32 v
= tcg_temp_new_i32();
504 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
508 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
510 TCGv_i32 v
= tcg_temp_new_i32();
512 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
516 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
517 * If SVE is not enabled, then there are only 128 bits in the vector.
519 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
521 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
522 unsigned vsz
= vec_full_reg_size(s
);
524 /* Nop move, with side effect of clearing the tail. */
525 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
528 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
530 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
532 tcg_gen_st_i64(v
, cpu_env
, ofs
);
533 clear_vec_high(s
, false, reg
);
536 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
538 TCGv_i64 tmp
= tcg_temp_new_i64();
540 tcg_gen_extu_i32_i64(tmp
, v
);
541 write_fp_dreg(s
, reg
, tmp
);
544 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
545 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
546 GVecGen2Fn
*gvec_fn
, int vece
)
548 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
549 is_q
? 16 : 8, vec_full_reg_size(s
));
552 /* Expand a 2-operand + immediate AdvSIMD vector operation using
553 * an expander function.
555 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
556 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
558 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
559 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
562 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
563 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
564 GVecGen3Fn
*gvec_fn
, int vece
)
566 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
567 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
570 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
571 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
572 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
574 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
575 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
576 is_q
? 16 : 8, vec_full_reg_size(s
));
579 /* Expand a 2-operand operation using an out-of-line helper. */
580 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
581 int rn
, int data
, gen_helper_gvec_2
*fn
)
583 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
584 vec_full_reg_offset(s
, rn
),
585 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
588 /* Expand a 3-operand operation using an out-of-line helper. */
589 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
590 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
592 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
593 vec_full_reg_offset(s
, rn
),
594 vec_full_reg_offset(s
, rm
),
595 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
598 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
599 * an out-of-line helper.
601 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
602 int rm
, bool is_fp16
, int data
,
603 gen_helper_gvec_3_ptr
*fn
)
605 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
606 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
607 vec_full_reg_offset(s
, rn
),
608 vec_full_reg_offset(s
, rm
), fpst
,
609 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
612 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
613 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
614 int rm
, gen_helper_gvec_3_ptr
*fn
)
616 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
618 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
619 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
620 vec_full_reg_offset(s
, rn
),
621 vec_full_reg_offset(s
, rm
), qc_ptr
,
622 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
625 /* Expand a 4-operand operation using an out-of-line helper. */
626 static void gen_gvec_op4_ool(DisasContext
*s
, bool is_q
, int rd
, int rn
,
627 int rm
, int ra
, int data
, gen_helper_gvec_4
*fn
)
629 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
630 vec_full_reg_offset(s
, rn
),
631 vec_full_reg_offset(s
, rm
),
632 vec_full_reg_offset(s
, ra
),
633 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
637 * Expand a 4-operand + fpstatus pointer + simd data value operation using
638 * an out-of-line helper.
640 static void gen_gvec_op4_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
641 int rm
, int ra
, bool is_fp16
, int data
,
642 gen_helper_gvec_4_ptr
*fn
)
644 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
645 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
646 vec_full_reg_offset(s
, rn
),
647 vec_full_reg_offset(s
, rm
),
648 vec_full_reg_offset(s
, ra
), fpst
,
649 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
652 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
653 * than the 32 bit equivalent.
655 static inline void gen_set_NZ64(TCGv_i64 result
)
657 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
658 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
661 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
662 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
665 gen_set_NZ64(result
);
667 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
668 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
670 tcg_gen_movi_i32(cpu_CF
, 0);
671 tcg_gen_movi_i32(cpu_VF
, 0);
674 /* dest = T0 + T1; compute C, N, V and Z flags */
675 static void gen_add64_CC(TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
677 TCGv_i64 result
, flag
, tmp
;
678 result
= tcg_temp_new_i64();
679 flag
= tcg_temp_new_i64();
680 tmp
= tcg_temp_new_i64();
682 tcg_gen_movi_i64(tmp
, 0);
683 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
685 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
687 gen_set_NZ64(result
);
689 tcg_gen_xor_i64(flag
, result
, t0
);
690 tcg_gen_xor_i64(tmp
, t0
, t1
);
691 tcg_gen_andc_i64(flag
, flag
, tmp
);
692 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
694 tcg_gen_mov_i64(dest
, result
);
697 static void gen_add32_CC(TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
699 TCGv_i32 t0_32
= tcg_temp_new_i32();
700 TCGv_i32 t1_32
= tcg_temp_new_i32();
701 TCGv_i32 tmp
= tcg_temp_new_i32();
703 tcg_gen_movi_i32(tmp
, 0);
704 tcg_gen_extrl_i64_i32(t0_32
, t0
);
705 tcg_gen_extrl_i64_i32(t1_32
, t1
);
706 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
707 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
708 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
709 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
710 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
711 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
714 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
717 gen_add64_CC(dest
, t0
, t1
);
719 gen_add32_CC(dest
, t0
, t1
);
723 /* dest = T0 - T1; compute C, N, V and Z flags */
724 static void gen_sub64_CC(TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
726 /* 64 bit arithmetic */
727 TCGv_i64 result
, flag
, tmp
;
729 result
= tcg_temp_new_i64();
730 flag
= tcg_temp_new_i64();
731 tcg_gen_sub_i64(result
, t0
, t1
);
733 gen_set_NZ64(result
);
735 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
736 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
738 tcg_gen_xor_i64(flag
, result
, t0
);
739 tmp
= tcg_temp_new_i64();
740 tcg_gen_xor_i64(tmp
, t0
, t1
);
741 tcg_gen_and_i64(flag
, flag
, tmp
);
742 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
743 tcg_gen_mov_i64(dest
, result
);
746 static void gen_sub32_CC(TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
748 /* 32 bit arithmetic */
749 TCGv_i32 t0_32
= tcg_temp_new_i32();
750 TCGv_i32 t1_32
= tcg_temp_new_i32();
753 tcg_gen_extrl_i64_i32(t0_32
, t0
);
754 tcg_gen_extrl_i64_i32(t1_32
, t1
);
755 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
756 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
757 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
758 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
759 tmp
= tcg_temp_new_i32();
760 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
761 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
762 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
765 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
768 gen_sub64_CC(dest
, t0
, t1
);
770 gen_sub32_CC(dest
, t0
, t1
);
774 /* dest = T0 + T1 + CF; do not compute flags. */
775 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
777 TCGv_i64 flag
= tcg_temp_new_i64();
778 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
779 tcg_gen_add_i64(dest
, t0
, t1
);
780 tcg_gen_add_i64(dest
, dest
, flag
);
783 tcg_gen_ext32u_i64(dest
, dest
);
787 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
788 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
791 TCGv_i64 result
= tcg_temp_new_i64();
792 TCGv_i64 cf_64
= tcg_temp_new_i64();
793 TCGv_i64 vf_64
= tcg_temp_new_i64();
794 TCGv_i64 tmp
= tcg_temp_new_i64();
795 TCGv_i64 zero
= tcg_constant_i64(0);
797 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
798 tcg_gen_add2_i64(result
, cf_64
, t0
, zero
, cf_64
, zero
);
799 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, zero
);
800 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
801 gen_set_NZ64(result
);
803 tcg_gen_xor_i64(vf_64
, result
, t0
);
804 tcg_gen_xor_i64(tmp
, t0
, t1
);
805 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
806 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
808 tcg_gen_mov_i64(dest
, result
);
810 TCGv_i32 t0_32
= tcg_temp_new_i32();
811 TCGv_i32 t1_32
= tcg_temp_new_i32();
812 TCGv_i32 tmp
= tcg_temp_new_i32();
813 TCGv_i32 zero
= tcg_constant_i32(0);
815 tcg_gen_extrl_i64_i32(t0_32
, t0
);
816 tcg_gen_extrl_i64_i32(t1_32
, t1
);
817 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, zero
, cpu_CF
, zero
);
818 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, zero
);
820 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
821 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
822 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
823 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
824 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
829 * Load/Store generators
833 * Store from GPR register to memory.
835 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
836 TCGv_i64 tcg_addr
, MemOp memop
, int memidx
,
838 unsigned int iss_srt
,
839 bool iss_sf
, bool iss_ar
)
841 memop
= finalize_memop(s
, memop
);
842 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, memop
);
847 syn
= syn_data_abort_with_iss(0,
853 0, 0, 0, 0, 0, false);
854 disas_set_insn_syndrome(s
, syn
);
858 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
859 TCGv_i64 tcg_addr
, MemOp memop
,
861 unsigned int iss_srt
,
862 bool iss_sf
, bool iss_ar
)
864 do_gpr_st_memidx(s
, source
, tcg_addr
, memop
, get_mem_index(s
),
865 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
869 * Load from memory to GPR register
871 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
872 MemOp memop
, bool extend
, int memidx
,
873 bool iss_valid
, unsigned int iss_srt
,
874 bool iss_sf
, bool iss_ar
)
876 memop
= finalize_memop(s
, memop
);
877 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
879 if (extend
&& (memop
& MO_SIGN
)) {
880 g_assert((memop
& MO_SIZE
) <= MO_32
);
881 tcg_gen_ext32u_i64(dest
, dest
);
887 syn
= syn_data_abort_with_iss(0,
889 (memop
& MO_SIGN
) != 0,
893 0, 0, 0, 0, 0, false);
894 disas_set_insn_syndrome(s
, syn
);
898 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
899 MemOp memop
, bool extend
,
900 bool iss_valid
, unsigned int iss_srt
,
901 bool iss_sf
, bool iss_ar
)
903 do_gpr_ld_memidx(s
, dest
, tcg_addr
, memop
, extend
, get_mem_index(s
),
904 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
908 * Store from FP register to memory
910 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
912 /* This writes the bottom N bits of a 128 bit wide vector to memory */
913 TCGv_i64 tmplo
= tcg_temp_new_i64();
914 MemOp mop
= finalize_memop_asimd(s
, size
);
916 tcg_gen_ld_i64(tmplo
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
919 tcg_gen_qemu_st_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
921 TCGv_i64 tmphi
= tcg_temp_new_i64();
922 TCGv_i128 t16
= tcg_temp_new_i128();
924 tcg_gen_ld_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
925 tcg_gen_concat_i64_i128(t16
, tmplo
, tmphi
);
927 tcg_gen_qemu_st_i128(t16
, tcg_addr
, get_mem_index(s
), mop
);
932 * Load from memory to FP register
934 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
936 /* This always zero-extends and writes to a full 128 bit wide vector */
937 TCGv_i64 tmplo
= tcg_temp_new_i64();
938 TCGv_i64 tmphi
= NULL
;
939 MemOp mop
= finalize_memop_asimd(s
, size
);
942 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
944 TCGv_i128 t16
= tcg_temp_new_i128();
946 tcg_gen_qemu_ld_i128(t16
, tcg_addr
, get_mem_index(s
), mop
);
948 tmphi
= tcg_temp_new_i64();
949 tcg_gen_extr_i128_i64(tmplo
, tmphi
, t16
);
952 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
955 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
957 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
961 * Vector load/store helpers.
963 * The principal difference between this and a FP load is that we don't
964 * zero extend as we are filling a partial chunk of the vector register.
965 * These functions don't support 128 bit loads/stores, which would be
966 * normal load/store operations.
968 * The _i32 versions are useful when operating on 32 bit quantities
969 * (eg for floating point single or using Neon helper functions).
972 /* Get value of an element within a vector register */
973 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
974 int element
, MemOp memop
)
976 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
977 switch ((unsigned)memop
) {
979 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
982 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
985 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
988 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
991 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
994 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
998 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1001 g_assert_not_reached();
1005 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1006 int element
, MemOp memop
)
1008 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1011 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1014 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1017 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1020 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1024 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1027 g_assert_not_reached();
1031 /* Set value of an element within a vector register */
1032 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1033 int element
, MemOp memop
)
1035 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1038 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1041 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1044 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1047 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1050 g_assert_not_reached();
1054 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1055 int destidx
, int element
, MemOp memop
)
1057 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1060 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1063 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1066 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1069 g_assert_not_reached();
1073 /* Store from vector register to memory */
1074 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1075 TCGv_i64 tcg_addr
, MemOp mop
)
1077 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1079 read_vec_element(s
, tcg_tmp
, srcidx
, element
, mop
& MO_SIZE
);
1080 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1083 /* Load from memory to vector register */
1084 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1085 TCGv_i64 tcg_addr
, MemOp mop
)
1087 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1089 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1090 write_vec_element(s
, tcg_tmp
, destidx
, element
, mop
& MO_SIZE
);
1093 /* Check that FP/Neon access is enabled. If it is, return
1094 * true. If not, emit code to generate an appropriate exception,
1095 * and return false; the caller should not emit any code for
1096 * the instruction. Note that this check must happen after all
1097 * unallocated-encoding checks (otherwise the syndrome information
1098 * for the resulting exception will be incorrect).
1100 static bool fp_access_check_only(DisasContext
*s
)
1102 if (s
->fp_excp_el
) {
1103 assert(!s
->fp_access_checked
);
1104 s
->fp_access_checked
= true;
1106 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1107 syn_fp_access_trap(1, 0xe, false, 0),
1111 s
->fp_access_checked
= true;
1115 static bool fp_access_check(DisasContext
*s
)
1117 if (!fp_access_check_only(s
)) {
1120 if (s
->sme_trap_nonstreaming
&& s
->is_nonstreaming
) {
1121 gen_exception_insn(s
, 0, EXCP_UDEF
,
1122 syn_smetrap(SME_ET_Streaming
, false));
1129 * Check that SVE access is enabled. If it is, return true.
1130 * If not, emit code to generate an appropriate exception and return false.
1131 * This function corresponds to CheckSVEEnabled().
1133 bool sve_access_check(DisasContext
*s
)
1135 if (s
->pstate_sm
|| !dc_isar_feature(aa64_sve
, s
)) {
1136 assert(dc_isar_feature(aa64_sme
, s
));
1137 if (!sme_sm_enabled_check(s
)) {
1140 } else if (s
->sve_excp_el
) {
1141 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1142 syn_sve_access_trap(), s
->sve_excp_el
);
1145 s
->sve_access_checked
= true;
1146 return fp_access_check(s
);
1149 /* Assert that we only raise one exception per instruction. */
1150 assert(!s
->sve_access_checked
);
1151 s
->sve_access_checked
= true;
1156 * Check that SME access is enabled, raise an exception if not.
1157 * Note that this function corresponds to CheckSMEAccess and is
1158 * only used directly for cpregs.
1160 static bool sme_access_check(DisasContext
*s
)
1162 if (s
->sme_excp_el
) {
1163 gen_exception_insn_el(s
, 0, EXCP_UDEF
,
1164 syn_smetrap(SME_ET_AccessTrap
, false),
1171 /* This function corresponds to CheckSMEEnabled. */
1172 bool sme_enabled_check(DisasContext
*s
)
1175 * Note that unlike sve_excp_el, we have not constrained sme_excp_el
1176 * to be zero when fp_excp_el has priority. This is because we need
1177 * sme_excp_el by itself for cpregs access checks.
1179 if (!s
->fp_excp_el
|| s
->sme_excp_el
< s
->fp_excp_el
) {
1180 s
->fp_access_checked
= true;
1181 return sme_access_check(s
);
1183 return fp_access_check_only(s
);
1186 /* Common subroutine for CheckSMEAnd*Enabled. */
1187 bool sme_enabled_check_with_svcr(DisasContext
*s
, unsigned req
)
1189 if (!sme_enabled_check(s
)) {
1192 if (FIELD_EX64(req
, SVCR
, SM
) && !s
->pstate_sm
) {
1193 gen_exception_insn(s
, 0, EXCP_UDEF
,
1194 syn_smetrap(SME_ET_NotStreaming
, false));
1197 if (FIELD_EX64(req
, SVCR
, ZA
) && !s
->pstate_za
) {
1198 gen_exception_insn(s
, 0, EXCP_UDEF
,
1199 syn_smetrap(SME_ET_InactiveZA
, false));
1206 * This utility function is for doing register extension with an
1207 * optional shift. You will likely want to pass a temporary for the
1208 * destination register. See DecodeRegExtend() in the ARM ARM.
1210 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1211 int option
, unsigned int shift
)
1213 int extsize
= extract32(option
, 0, 2);
1214 bool is_signed
= extract32(option
, 2, 1);
1219 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1222 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1225 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1228 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1234 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1237 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1240 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1243 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1249 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1253 static inline void gen_check_sp_alignment(DisasContext
*s
)
1255 /* The AArch64 architecture mandates that (if enabled via PSTATE
1256 * or SCTLR bits) there is a check that SP is 16-aligned on every
1257 * SP-relative load or store (with an exception generated if it is not).
1258 * In line with general QEMU practice regarding misaligned accesses,
1259 * we omit these checks for the sake of guest program performance.
1260 * This function is provided as a hook so we can more easily add these
1261 * checks in future (possibly as a "favour catching guest program bugs
1262 * over speed" user selectable option).
1267 * This provides a simple table based table lookup decoder. It is
1268 * intended to be used when the relevant bits for decode are too
1269 * awkwardly placed and switch/if based logic would be confusing and
1270 * deeply nested. Since it's a linear search through the table, tables
1271 * should be kept small.
1273 * It returns the first handler where insn & mask == pattern, or
1274 * NULL if there is no match.
1275 * The table is terminated by an empty mask (i.e. 0)
1277 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1280 const AArch64DecodeTable
*tptr
= table
;
1282 while (tptr
->mask
) {
1283 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1284 return tptr
->disas_fn
;
1292 * The instruction disassembly implemented here matches
1293 * the instruction encoding classifications in chapter C4
1294 * of the ARM Architecture Reference Manual (DDI0487B_a);
1295 * classification names and decode diagrams here should generally
1296 * match up with those in the manual.
1299 static bool trans_B(DisasContext
*s
, arg_i
*a
)
1302 gen_goto_tb(s
, 0, a
->imm
);
1306 static bool trans_BL(DisasContext
*s
, arg_i
*a
)
1308 gen_pc_plus_diff(s
, cpu_reg(s
, 30), curr_insn_len(s
));
1310 gen_goto_tb(s
, 0, a
->imm
);
1315 static bool trans_CBZ(DisasContext
*s
, arg_cbz
*a
)
1320 tcg_cmp
= read_cpu_reg(s
, a
->rt
, a
->sf
);
1323 match
= gen_disas_label(s
);
1324 tcg_gen_brcondi_i64(a
->nz
? TCG_COND_NE
: TCG_COND_EQ
,
1325 tcg_cmp
, 0, match
.label
);
1326 gen_goto_tb(s
, 0, 4);
1327 set_disas_label(s
, match
);
1328 gen_goto_tb(s
, 1, a
->imm
);
1332 static bool trans_TBZ(DisasContext
*s
, arg_tbz
*a
)
1337 tcg_cmp
= tcg_temp_new_i64();
1338 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, a
->rt
), 1ULL << a
->bitpos
);
1342 match
= gen_disas_label(s
);
1343 tcg_gen_brcondi_i64(a
->nz
? TCG_COND_NE
: TCG_COND_EQ
,
1344 tcg_cmp
, 0, match
.label
);
1345 gen_goto_tb(s
, 0, 4);
1346 set_disas_label(s
, match
);
1347 gen_goto_tb(s
, 1, a
->imm
);
1351 static bool trans_B_cond(DisasContext
*s
, arg_B_cond
*a
)
1354 if (a
->cond
< 0x0e) {
1355 /* genuinely conditional branches */
1356 DisasLabel match
= gen_disas_label(s
);
1357 arm_gen_test_cc(a
->cond
, match
.label
);
1358 gen_goto_tb(s
, 0, 4);
1359 set_disas_label(s
, match
);
1360 gen_goto_tb(s
, 1, a
->imm
);
1362 /* 0xe and 0xf are both "always" conditions */
1363 gen_goto_tb(s
, 0, a
->imm
);
1368 static void set_btype_for_br(DisasContext
*s
, int rn
)
1370 if (dc_isar_feature(aa64_bti
, s
)) {
1371 /* BR to {x16,x17} or !guard -> 1, else 3. */
1372 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
1376 static void set_btype_for_blr(DisasContext
*s
)
1378 if (dc_isar_feature(aa64_bti
, s
)) {
1379 /* BLR sets BTYPE to 2, regardless of source guarded page. */
1384 static bool trans_BR(DisasContext
*s
, arg_r
*a
)
1386 gen_a64_set_pc(s
, cpu_reg(s
, a
->rn
));
1387 set_btype_for_br(s
, a
->rn
);
1388 s
->base
.is_jmp
= DISAS_JUMP
;
1392 static bool trans_BLR(DisasContext
*s
, arg_r
*a
)
1394 TCGv_i64 dst
= cpu_reg(s
, a
->rn
);
1395 TCGv_i64 lr
= cpu_reg(s
, 30);
1397 TCGv_i64 tmp
= tcg_temp_new_i64();
1398 tcg_gen_mov_i64(tmp
, dst
);
1401 gen_pc_plus_diff(s
, lr
, curr_insn_len(s
));
1402 gen_a64_set_pc(s
, dst
);
1403 set_btype_for_blr(s
);
1404 s
->base
.is_jmp
= DISAS_JUMP
;
1408 static bool trans_RET(DisasContext
*s
, arg_r
*a
)
1410 gen_a64_set_pc(s
, cpu_reg(s
, a
->rn
));
1411 s
->base
.is_jmp
= DISAS_JUMP
;
1415 static TCGv_i64
auth_branch_target(DisasContext
*s
, TCGv_i64 dst
,
1416 TCGv_i64 modifier
, bool use_key_a
)
1420 * Return the branch target for a BRAA/RETA/etc, which is either
1421 * just the destination dst, or that value with the pauth check
1422 * done and the code removed from the high bits.
1424 if (!s
->pauth_active
) {
1428 truedst
= tcg_temp_new_i64();
1430 gen_helper_autia(truedst
, cpu_env
, dst
, modifier
);
1432 gen_helper_autib(truedst
, cpu_env
, dst
, modifier
);
1437 static bool trans_BRAZ(DisasContext
*s
, arg_braz
*a
)
1441 if (!dc_isar_feature(aa64_pauth
, s
)) {
1445 dst
= auth_branch_target(s
, cpu_reg(s
, a
->rn
), tcg_constant_i64(0), !a
->m
);
1446 gen_a64_set_pc(s
, dst
);
1447 set_btype_for_br(s
, a
->rn
);
1448 s
->base
.is_jmp
= DISAS_JUMP
;
1452 static bool trans_BLRAZ(DisasContext
*s
, arg_braz
*a
)
1456 if (!dc_isar_feature(aa64_pauth
, s
)) {
1460 dst
= auth_branch_target(s
, cpu_reg(s
, a
->rn
), tcg_constant_i64(0), !a
->m
);
1461 lr
= cpu_reg(s
, 30);
1463 TCGv_i64 tmp
= tcg_temp_new_i64();
1464 tcg_gen_mov_i64(tmp
, dst
);
1467 gen_pc_plus_diff(s
, lr
, curr_insn_len(s
));
1468 gen_a64_set_pc(s
, dst
);
1469 set_btype_for_blr(s
);
1470 s
->base
.is_jmp
= DISAS_JUMP
;
1474 static bool trans_RETA(DisasContext
*s
, arg_reta
*a
)
1478 dst
= auth_branch_target(s
, cpu_reg(s
, 30), cpu_X
[31], !a
->m
);
1479 gen_a64_set_pc(s
, dst
);
1480 s
->base
.is_jmp
= DISAS_JUMP
;
1484 static bool trans_BRA(DisasContext
*s
, arg_bra
*a
)
1488 if (!dc_isar_feature(aa64_pauth
, s
)) {
1491 dst
= auth_branch_target(s
, cpu_reg(s
,a
->rn
), cpu_reg_sp(s
, a
->rm
), !a
->m
);
1492 gen_a64_set_pc(s
, dst
);
1493 set_btype_for_br(s
, a
->rn
);
1494 s
->base
.is_jmp
= DISAS_JUMP
;
1498 static bool trans_BLRA(DisasContext
*s
, arg_bra
*a
)
1502 if (!dc_isar_feature(aa64_pauth
, s
)) {
1505 dst
= auth_branch_target(s
, cpu_reg(s
, a
->rn
), cpu_reg_sp(s
, a
->rm
), !a
->m
);
1506 lr
= cpu_reg(s
, 30);
1508 TCGv_i64 tmp
= tcg_temp_new_i64();
1509 tcg_gen_mov_i64(tmp
, dst
);
1512 gen_pc_plus_diff(s
, lr
, curr_insn_len(s
));
1513 gen_a64_set_pc(s
, dst
);
1514 set_btype_for_blr(s
);
1515 s
->base
.is_jmp
= DISAS_JUMP
;
1519 static bool trans_ERET(DisasContext
*s
, arg_ERET
*a
)
1523 if (s
->current_el
== 0) {
1527 gen_exception_insn_el(s
, 0, EXCP_UDEF
, 0, 2);
1530 dst
= tcg_temp_new_i64();
1531 tcg_gen_ld_i64(dst
, cpu_env
,
1532 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
1534 translator_io_start(&s
->base
);
1536 gen_helper_exception_return(cpu_env
, dst
);
1537 /* Must exit loop to check un-masked IRQs */
1538 s
->base
.is_jmp
= DISAS_EXIT
;
1542 static bool trans_ERETA(DisasContext
*s
, arg_reta
*a
)
1546 if (!dc_isar_feature(aa64_pauth
, s
)) {
1549 if (s
->current_el
== 0) {
1552 /* The FGT trap takes precedence over an auth trap. */
1554 gen_exception_insn_el(s
, 0, EXCP_UDEF
, a
->m
? 3 : 2, 2);
1557 dst
= tcg_temp_new_i64();
1558 tcg_gen_ld_i64(dst
, cpu_env
,
1559 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
1561 dst
= auth_branch_target(s
, dst
, cpu_X
[31], !a
->m
);
1563 translator_io_start(&s
->base
);
1565 gen_helper_exception_return(cpu_env
, dst
);
1566 /* Must exit loop to check un-masked IRQs */
1567 s
->base
.is_jmp
= DISAS_EXIT
;
1571 /* HINT instruction group, including various allocated HINTs */
1572 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1573 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1575 unsigned int selector
= crm
<< 3 | op2
;
1578 unallocated_encoding(s
);
1583 case 0b00000: /* NOP */
1585 case 0b00011: /* WFI */
1586 s
->base
.is_jmp
= DISAS_WFI
;
1588 case 0b00001: /* YIELD */
1589 /* When running in MTTCG we don't generate jumps to the yield and
1590 * WFE helpers as it won't affect the scheduling of other vCPUs.
1591 * If we wanted to more completely model WFE/SEV so we don't busy
1592 * spin unnecessarily we would need to do something more involved.
1594 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1595 s
->base
.is_jmp
= DISAS_YIELD
;
1598 case 0b00010: /* WFE */
1599 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1600 s
->base
.is_jmp
= DISAS_WFE
;
1603 case 0b00100: /* SEV */
1604 case 0b00101: /* SEVL */
1605 case 0b00110: /* DGH */
1606 /* we treat all as NOP at least for now */
1608 case 0b00111: /* XPACLRI */
1609 if (s
->pauth_active
) {
1610 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1613 case 0b01000: /* PACIA1716 */
1614 if (s
->pauth_active
) {
1615 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1618 case 0b01010: /* PACIB1716 */
1619 if (s
->pauth_active
) {
1620 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1623 case 0b01100: /* AUTIA1716 */
1624 if (s
->pauth_active
) {
1625 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1628 case 0b01110: /* AUTIB1716 */
1629 if (s
->pauth_active
) {
1630 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1633 case 0b10000: /* ESB */
1634 /* Without RAS, we must implement this as NOP. */
1635 if (dc_isar_feature(aa64_ras
, s
)) {
1637 * QEMU does not have a source of physical SErrors,
1638 * so we are only concerned with virtual SErrors.
1639 * The pseudocode in the ARM for this case is
1640 * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
1641 * AArch64.vESBOperation();
1642 * Most of the condition can be evaluated at translation time.
1643 * Test for EL2 present, and defer test for SEL2 to runtime.
1645 if (s
->current_el
<= 1 && arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
1646 gen_helper_vesb(cpu_env
);
1650 case 0b11000: /* PACIAZ */
1651 if (s
->pauth_active
) {
1652 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1653 tcg_constant_i64(0));
1656 case 0b11001: /* PACIASP */
1657 if (s
->pauth_active
) {
1658 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1661 case 0b11010: /* PACIBZ */
1662 if (s
->pauth_active
) {
1663 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1664 tcg_constant_i64(0));
1667 case 0b11011: /* PACIBSP */
1668 if (s
->pauth_active
) {
1669 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1672 case 0b11100: /* AUTIAZ */
1673 if (s
->pauth_active
) {
1674 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1675 tcg_constant_i64(0));
1678 case 0b11101: /* AUTIASP */
1679 if (s
->pauth_active
) {
1680 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1683 case 0b11110: /* AUTIBZ */
1684 if (s
->pauth_active
) {
1685 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1686 tcg_constant_i64(0));
1689 case 0b11111: /* AUTIBSP */
1690 if (s
->pauth_active
) {
1691 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1695 /* default specified as NOP equivalent */
1700 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1702 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1705 /* CLREX, DSB, DMB, ISB */
1706 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1707 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1712 unallocated_encoding(s
);
1723 case 1: /* MBReqTypes_Reads */
1724 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1726 case 2: /* MBReqTypes_Writes */
1727 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1729 default: /* MBReqTypes_All */
1730 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1736 /* We need to break the TB after this insn to execute
1737 * a self-modified code correctly and also to take
1738 * any pending interrupts immediately.
1741 gen_goto_tb(s
, 0, 4);
1745 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1746 goto do_unallocated
;
1749 * TODO: There is no speculation barrier opcode for TCG;
1750 * MB and end the TB instead.
1752 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1753 gen_goto_tb(s
, 0, 4);
1758 unallocated_encoding(s
);
1763 static void gen_xaflag(void)
1765 TCGv_i32 z
= tcg_temp_new_i32();
1767 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1776 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1777 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1780 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1781 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1783 /* (!C & Z) << 31 -> -(Z & ~C) */
1784 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1785 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1788 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1791 static void gen_axflag(void)
1793 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1794 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1796 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1797 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1799 tcg_gen_movi_i32(cpu_NF
, 0);
1800 tcg_gen_movi_i32(cpu_VF
, 0);
1803 /* MSR (immediate) - move immediate to processor state field */
1804 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1805 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1807 int op
= op1
<< 3 | op2
;
1809 /* End the TB by default, chaining is ok. */
1810 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1813 case 0x00: /* CFINV */
1814 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1815 goto do_unallocated
;
1817 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1818 s
->base
.is_jmp
= DISAS_NEXT
;
1821 case 0x01: /* XAFlag */
1822 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1823 goto do_unallocated
;
1826 s
->base
.is_jmp
= DISAS_NEXT
;
1829 case 0x02: /* AXFlag */
1830 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1831 goto do_unallocated
;
1834 s
->base
.is_jmp
= DISAS_NEXT
;
1837 case 0x03: /* UAO */
1838 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1839 goto do_unallocated
;
1842 set_pstate_bits(PSTATE_UAO
);
1844 clear_pstate_bits(PSTATE_UAO
);
1846 gen_rebuild_hflags(s
);
1849 case 0x04: /* PAN */
1850 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1851 goto do_unallocated
;
1854 set_pstate_bits(PSTATE_PAN
);
1856 clear_pstate_bits(PSTATE_PAN
);
1858 gen_rebuild_hflags(s
);
1861 case 0x05: /* SPSel */
1862 if (s
->current_el
== 0) {
1863 goto do_unallocated
;
1865 gen_helper_msr_i_spsel(cpu_env
, tcg_constant_i32(crm
& PSTATE_SP
));
1868 case 0x19: /* SSBS */
1869 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1870 goto do_unallocated
;
1873 set_pstate_bits(PSTATE_SSBS
);
1875 clear_pstate_bits(PSTATE_SSBS
);
1877 /* Don't need to rebuild hflags since SSBS is a nop */
1880 case 0x1a: /* DIT */
1881 if (!dc_isar_feature(aa64_dit
, s
)) {
1882 goto do_unallocated
;
1885 set_pstate_bits(PSTATE_DIT
);
1887 clear_pstate_bits(PSTATE_DIT
);
1889 /* There's no need to rebuild hflags because DIT is a nop */
1892 case 0x1e: /* DAIFSet */
1893 gen_helper_msr_i_daifset(cpu_env
, tcg_constant_i32(crm
));
1896 case 0x1f: /* DAIFClear */
1897 gen_helper_msr_i_daifclear(cpu_env
, tcg_constant_i32(crm
));
1898 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1899 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1902 case 0x1c: /* TCO */
1903 if (dc_isar_feature(aa64_mte
, s
)) {
1904 /* Full MTE is enabled -- set the TCO bit as directed. */
1906 set_pstate_bits(PSTATE_TCO
);
1908 clear_pstate_bits(PSTATE_TCO
);
1910 gen_rebuild_hflags(s
);
1911 /* Many factors, including TCO, go into MTE_ACTIVE. */
1912 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1913 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1914 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1915 s
->base
.is_jmp
= DISAS_NEXT
;
1917 goto do_unallocated
;
1921 case 0x1b: /* SVCR* */
1922 if (!dc_isar_feature(aa64_sme
, s
) || crm
< 2 || crm
> 7) {
1923 goto do_unallocated
;
1925 if (sme_access_check(s
)) {
1926 int old
= s
->pstate_sm
| (s
->pstate_za
<< 1);
1927 int new = (crm
& 1) * 3;
1928 int msk
= (crm
>> 1) & 3;
1930 if ((old
^ new) & msk
) {
1931 /* At least one bit changes. */
1932 gen_helper_set_svcr(cpu_env
, tcg_constant_i32(new),
1933 tcg_constant_i32(msk
));
1935 s
->base
.is_jmp
= DISAS_NEXT
;
1942 unallocated_encoding(s
);
1947 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1949 TCGv_i32 tmp
= tcg_temp_new_i32();
1950 TCGv_i32 nzcv
= tcg_temp_new_i32();
1952 /* build bit 31, N */
1953 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1954 /* build bit 30, Z */
1955 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1956 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1957 /* build bit 29, C */
1958 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1959 /* build bit 28, V */
1960 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1961 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1962 /* generate result */
1963 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1966 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1968 TCGv_i32 nzcv
= tcg_temp_new_i32();
1970 /* take NZCV from R[t] */
1971 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1974 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1976 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1977 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1979 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1980 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1982 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1983 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1986 static void gen_sysreg_undef(DisasContext
*s
, bool isread
,
1987 uint8_t op0
, uint8_t op1
, uint8_t op2
,
1988 uint8_t crn
, uint8_t crm
, uint8_t rt
)
1991 * Generate code to emit an UNDEF with correct syndrome
1992 * information for a failed system register access.
1993 * This is EC_UNCATEGORIZED (ie a standard UNDEF) in most cases,
1994 * but if FEAT_IDST is implemented then read accesses to registers
1995 * in the feature ID space are reported with the EC_SYSTEMREGISTERTRAP
2000 if (isread
&& dc_isar_feature(aa64_ids
, s
) &&
2001 arm_cpreg_encoding_in_idspace(op0
, op1
, op2
, crn
, crm
)) {
2002 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
2004 syndrome
= syn_uncategorized();
2006 gen_exception_insn(s
, 0, EXCP_UDEF
, syndrome
);
2009 /* MRS - move from system register
2010 * MSR (register) - move to system register
2013 * These are all essentially the same insn in 'read' and 'write'
2014 * versions, with varying op0 fields.
2016 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
2017 unsigned int op0
, unsigned int op1
, unsigned int op2
,
2018 unsigned int crn
, unsigned int crm
, unsigned int rt
)
2020 uint32_t key
= ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
2021 crn
, crm
, op0
, op1
, op2
);
2022 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(s
->cp_regs
, key
);
2023 bool need_exit_tb
= false;
2024 TCGv_ptr tcg_ri
= NULL
;
2028 /* Unknown register; this might be a guest error or a QEMU
2029 * unimplemented feature.
2031 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
2032 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
2033 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
2034 gen_sysreg_undef(s
, isread
, op0
, op1
, op2
, crn
, crm
, rt
);
2038 /* Check access permissions */
2039 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
2040 gen_sysreg_undef(s
, isread
, op0
, op1
, op2
, crn
, crm
, rt
);
2044 if (ri
->accessfn
|| (ri
->fgt
&& s
->fgt_active
)) {
2045 /* Emit code to perform further access permissions checks at
2046 * runtime; this may result in an exception.
2050 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
2051 gen_a64_update_pc(s
, 0);
2052 tcg_ri
= tcg_temp_new_ptr();
2053 gen_helper_access_check_cp_reg(tcg_ri
, cpu_env
,
2054 tcg_constant_i32(key
),
2055 tcg_constant_i32(syndrome
),
2056 tcg_constant_i32(isread
));
2057 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
2059 * The readfn or writefn might raise an exception;
2060 * synchronize the CPU state in case it does.
2062 gen_a64_update_pc(s
, 0);
2065 /* Handle special cases first */
2066 switch (ri
->type
& ARM_CP_SPECIAL_MASK
) {
2072 tcg_rt
= cpu_reg(s
, rt
);
2074 gen_get_nzcv(tcg_rt
);
2076 gen_set_nzcv(tcg_rt
);
2079 case ARM_CP_CURRENTEL
:
2080 /* Reads as current EL value from pstate, which is
2081 * guaranteed to be constant by the tb flags.
2083 tcg_rt
= cpu_reg(s
, rt
);
2084 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
2087 /* Writes clear the aligned block of memory which rt points into. */
2088 if (s
->mte_active
[0]) {
2091 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
2092 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
2093 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
2095 tcg_rt
= tcg_temp_new_i64();
2096 gen_helper_mte_check_zva(tcg_rt
, cpu_env
,
2097 tcg_constant_i32(desc
), cpu_reg(s
, rt
));
2099 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
2101 gen_helper_dc_zva(cpu_env
, tcg_rt
);
2105 TCGv_i64 clean_addr
, tag
;
2108 * DC_GVA, like DC_ZVA, requires that we supply the original
2109 * pointer for an invalid page. Probe that address first.
2111 tcg_rt
= cpu_reg(s
, rt
);
2112 clean_addr
= clean_data_tbi(s
, tcg_rt
);
2113 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
2116 /* Extract the tag from the register to match STZGM. */
2117 tag
= tcg_temp_new_i64();
2118 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
2119 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
2123 case ARM_CP_DC_GZVA
:
2125 TCGv_i64 clean_addr
, tag
;
2127 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
2128 tcg_rt
= cpu_reg(s
, rt
);
2129 clean_addr
= clean_data_tbi(s
, tcg_rt
);
2130 gen_helper_dc_zva(cpu_env
, clean_addr
);
2133 /* Extract the tag from the register to match STZGM. */
2134 tag
= tcg_temp_new_i64();
2135 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
2136 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
2141 g_assert_not_reached();
2143 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check_only(s
)) {
2145 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
2147 } else if ((ri
->type
& ARM_CP_SME
) && !sme_access_check(s
)) {
2151 if (ri
->type
& ARM_CP_IO
) {
2152 /* I/O operations must end the TB here (whether read or write) */
2153 need_exit_tb
= translator_io_start(&s
->base
);
2156 tcg_rt
= cpu_reg(s
, rt
);
2159 if (ri
->type
& ARM_CP_CONST
) {
2160 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
2161 } else if (ri
->readfn
) {
2163 tcg_ri
= gen_lookup_cp_reg(key
);
2165 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tcg_ri
);
2167 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2170 if (ri
->type
& ARM_CP_CONST
) {
2171 /* If not forbidden by access permissions, treat as WI */
2173 } else if (ri
->writefn
) {
2175 tcg_ri
= gen_lookup_cp_reg(key
);
2177 gen_helper_set_cp_reg64(cpu_env
, tcg_ri
, tcg_rt
);
2179 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
2183 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
2185 * A write to any coprocessor regiser that ends a TB
2186 * must rebuild the hflags for the next TB.
2188 gen_rebuild_hflags(s
);
2190 * We default to ending the TB on a coprocessor register write,
2191 * but allow this to be suppressed by the register definition
2192 * (usually only necessary to work around guest bugs).
2194 need_exit_tb
= true;
2197 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2202 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2203 * +---------------------+---+-----+-----+-------+-------+-----+------+
2204 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2205 * +---------------------+---+-----+-----+-------+-------+-----+------+
2207 static void disas_system(DisasContext
*s
, uint32_t insn
)
2209 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2210 l
= extract32(insn
, 21, 1);
2211 op0
= extract32(insn
, 19, 2);
2212 op1
= extract32(insn
, 16, 3);
2213 crn
= extract32(insn
, 12, 4);
2214 crm
= extract32(insn
, 8, 4);
2215 op2
= extract32(insn
, 5, 3);
2216 rt
= extract32(insn
, 0, 5);
2219 if (l
|| rt
!= 31) {
2220 unallocated_encoding(s
);
2224 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2225 handle_hint(s
, insn
, op1
, op2
, crm
);
2227 case 3: /* CLREX, DSB, DMB, ISB */
2228 handle_sync(s
, insn
, op1
, op2
, crm
);
2230 case 4: /* MSR (immediate) */
2231 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2234 unallocated_encoding(s
);
2239 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2242 /* Exception generation
2244 * 31 24 23 21 20 5 4 2 1 0
2245 * +-----------------+-----+------------------------+-----+----+
2246 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2247 * +-----------------------+------------------------+----------+
2249 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2251 int opc
= extract32(insn
, 21, 3);
2252 int op2_ll
= extract32(insn
, 0, 5);
2253 int imm16
= extract32(insn
, 5, 16);
2258 /* For SVC, HVC and SMC we advance the single-step state
2259 * machine before taking the exception. This is architecturally
2260 * mandated, to ensure that single-stepping a system call
2261 * instruction works properly.
2265 syndrome
= syn_aa64_svc(imm16
);
2267 gen_exception_insn_el(s
, 0, EXCP_UDEF
, syndrome
, 2);
2271 gen_exception_insn(s
, 4, EXCP_SWI
, syndrome
);
2274 if (s
->current_el
== 0) {
2275 unallocated_encoding(s
);
2278 /* The pre HVC helper handles cases when HVC gets trapped
2279 * as an undefined insn by runtime configuration.
2281 gen_a64_update_pc(s
, 0);
2282 gen_helper_pre_hvc(cpu_env
);
2284 gen_exception_insn_el(s
, 4, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
2287 if (s
->current_el
== 0) {
2288 unallocated_encoding(s
);
2291 gen_a64_update_pc(s
, 0);
2292 gen_helper_pre_smc(cpu_env
, tcg_constant_i32(syn_aa64_smc(imm16
)));
2294 gen_exception_insn_el(s
, 4, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
2297 unallocated_encoding(s
);
2303 unallocated_encoding(s
);
2307 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2311 unallocated_encoding(s
);
2314 /* HLT. This has two purposes.
2315 * Architecturally, it is an external halting debug instruction.
2316 * Since QEMU doesn't implement external debug, we treat this as
2317 * it is required for halting debug disabled: it will UNDEF.
2318 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2320 if (semihosting_enabled(s
->current_el
== 0) && imm16
== 0xf000) {
2321 gen_exception_internal_insn(s
, EXCP_SEMIHOST
);
2323 unallocated_encoding(s
);
2327 if (op2_ll
< 1 || op2_ll
> 3) {
2328 unallocated_encoding(s
);
2331 /* DCPS1, DCPS2, DCPS3 */
2332 unallocated_encoding(s
);
2335 unallocated_encoding(s
);
2340 /* Branches, exception generating and system instructions */
2341 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2343 switch (extract32(insn
, 25, 7)) {
2344 case 0x6a: /* Exception generation / System */
2345 if (insn
& (1 << 24)) {
2346 if (extract32(insn
, 22, 2) == 0) {
2347 disas_system(s
, insn
);
2349 unallocated_encoding(s
);
2356 unallocated_encoding(s
);
2362 * Load/Store exclusive instructions are implemented by remembering
2363 * the value/address loaded, and seeing if these are the same
2364 * when the store is performed. This is not actually the architecturally
2365 * mandated semantics, but it works for typical guest code sequences
2366 * and avoids having to monitor regular stores.
2368 * The store exclusive uses the atomic cmpxchg primitives to avoid
2369 * races in multi-threaded linux-user and when MTTCG softmmu is
2372 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
, int rn
,
2373 int size
, bool is_pair
)
2375 int idx
= get_mem_index(s
);
2377 TCGv_i64 dirty_addr
, clean_addr
;
2380 dirty_addr
= cpu_reg_sp(s
, rn
);
2381 clean_addr
= gen_mte_check1(s
, dirty_addr
, false, rn
!= 31, size
);
2383 g_assert(size
<= 3);
2385 g_assert(size
>= 2);
2387 /* The pair must be single-copy atomic for the doubleword. */
2388 memop
= finalize_memop(s
, MO_64
| MO_ALIGN
);
2389 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, clean_addr
, idx
, memop
);
2390 if (s
->be_data
== MO_LE
) {
2391 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2392 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2394 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2395 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2399 * The pair must be single-copy atomic for *each* doubleword, not
2400 * the entire quadword, however it must be quadword aligned.
2401 * Expose the complete load to tcg, for ease of tlb lookup,
2402 * but indicate that only 8-byte atomicity is required.
2404 TCGv_i128 t16
= tcg_temp_new_i128();
2406 memop
= finalize_memop_atom(s
, MO_128
| MO_ALIGN_16
,
2407 MO_ATOM_IFALIGN_PAIR
);
2408 tcg_gen_qemu_ld_i128(t16
, clean_addr
, idx
, memop
);
2410 if (s
->be_data
== MO_LE
) {
2411 tcg_gen_extr_i128_i64(cpu_exclusive_val
,
2412 cpu_exclusive_high
, t16
);
2414 tcg_gen_extr_i128_i64(cpu_exclusive_high
,
2415 cpu_exclusive_val
, t16
);
2417 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2418 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2421 memop
= finalize_memop(s
, size
| MO_ALIGN
);
2422 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, clean_addr
, idx
, memop
);
2423 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2425 tcg_gen_mov_i64(cpu_exclusive_addr
, clean_addr
);
2428 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2429 int rn
, int size
, int is_pair
)
2431 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2432 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2435 * [addr + datasize] = {Rt2};
2441 * env->exclusive_addr = -1;
2443 TCGLabel
*fail_label
= gen_new_label();
2444 TCGLabel
*done_label
= gen_new_label();
2445 TCGv_i64 tmp
, dirty_addr
, clean_addr
;
2447 dirty_addr
= cpu_reg_sp(s
, rn
);
2448 clean_addr
= gen_mte_check1(s
, dirty_addr
, true, rn
!= 31, size
);
2450 tcg_gen_brcond_i64(TCG_COND_NE
, clean_addr
, cpu_exclusive_addr
, fail_label
);
2452 tmp
= tcg_temp_new_i64();
2455 if (s
->be_data
== MO_LE
) {
2456 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2458 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2460 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2461 cpu_exclusive_val
, tmp
,
2463 MO_64
| MO_ALIGN
| s
->be_data
);
2464 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2466 TCGv_i128 t16
= tcg_temp_new_i128();
2467 TCGv_i128 c16
= tcg_temp_new_i128();
2470 if (s
->be_data
== MO_LE
) {
2471 tcg_gen_concat_i64_i128(t16
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2472 tcg_gen_concat_i64_i128(c16
, cpu_exclusive_val
,
2473 cpu_exclusive_high
);
2475 tcg_gen_concat_i64_i128(t16
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2476 tcg_gen_concat_i64_i128(c16
, cpu_exclusive_high
,
2480 tcg_gen_atomic_cmpxchg_i128(t16
, cpu_exclusive_addr
, c16
, t16
,
2482 MO_128
| MO_ALIGN
| s
->be_data
);
2484 a
= tcg_temp_new_i64();
2485 b
= tcg_temp_new_i64();
2486 if (s
->be_data
== MO_LE
) {
2487 tcg_gen_extr_i128_i64(a
, b
, t16
);
2489 tcg_gen_extr_i128_i64(b
, a
, t16
);
2492 tcg_gen_xor_i64(a
, a
, cpu_exclusive_val
);
2493 tcg_gen_xor_i64(b
, b
, cpu_exclusive_high
);
2494 tcg_gen_or_i64(tmp
, a
, b
);
2496 tcg_gen_setcondi_i64(TCG_COND_NE
, tmp
, tmp
, 0);
2499 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2500 cpu_reg(s
, rt
), get_mem_index(s
),
2501 size
| MO_ALIGN
| s
->be_data
);
2502 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2504 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2505 tcg_gen_br(done_label
);
2507 gen_set_label(fail_label
);
2508 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2509 gen_set_label(done_label
);
2510 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2513 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2516 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2517 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2518 int memidx
= get_mem_index(s
);
2519 TCGv_i64 clean_addr
;
2522 gen_check_sp_alignment(s
);
2524 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2525 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2526 size
| MO_ALIGN
| s
->be_data
);
2529 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2532 TCGv_i64 s1
= cpu_reg(s
, rs
);
2533 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2534 TCGv_i64 t1
= cpu_reg(s
, rt
);
2535 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2536 TCGv_i64 clean_addr
;
2537 int memidx
= get_mem_index(s
);
2540 gen_check_sp_alignment(s
);
2543 /* This is a single atomic access, despite the "pair". */
2544 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2547 TCGv_i64 cmp
= tcg_temp_new_i64();
2548 TCGv_i64 val
= tcg_temp_new_i64();
2550 if (s
->be_data
== MO_LE
) {
2551 tcg_gen_concat32_i64(val
, t1
, t2
);
2552 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2554 tcg_gen_concat32_i64(val
, t2
, t1
);
2555 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2558 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2559 MO_64
| MO_ALIGN
| s
->be_data
);
2561 if (s
->be_data
== MO_LE
) {
2562 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2564 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2567 TCGv_i128 cmp
= tcg_temp_new_i128();
2568 TCGv_i128 val
= tcg_temp_new_i128();
2570 if (s
->be_data
== MO_LE
) {
2571 tcg_gen_concat_i64_i128(val
, t1
, t2
);
2572 tcg_gen_concat_i64_i128(cmp
, s1
, s2
);
2574 tcg_gen_concat_i64_i128(val
, t2
, t1
);
2575 tcg_gen_concat_i64_i128(cmp
, s2
, s1
);
2578 tcg_gen_atomic_cmpxchg_i128(cmp
, clean_addr
, cmp
, val
, memidx
,
2579 MO_128
| MO_ALIGN
| s
->be_data
);
2581 if (s
->be_data
== MO_LE
) {
2582 tcg_gen_extr_i128_i64(s1
, s2
, cmp
);
2584 tcg_gen_extr_i128_i64(s2
, s1
, cmp
);
2589 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2590 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2592 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2594 int opc0
= extract32(opc
, 0, 1);
2598 regsize
= opc0
? 32 : 64;
2600 regsize
= size
== 3 ? 64 : 32;
2602 return regsize
== 64;
2605 /* Load/store exclusive
2607 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2608 * +-----+-------------+----+---+----+------+----+-------+------+------+
2609 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2610 * +-----+-------------+----+---+----+------+----+-------+------+------+
2612 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2613 * L: 0 -> store, 1 -> load
2614 * o2: 0 -> exclusive, 1 -> not
2615 * o1: 0 -> single register, 1 -> register pair
2616 * o0: 1 -> load-acquire/store-release, 0 -> not
2618 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2620 int rt
= extract32(insn
, 0, 5);
2621 int rn
= extract32(insn
, 5, 5);
2622 int rt2
= extract32(insn
, 10, 5);
2623 int rs
= extract32(insn
, 16, 5);
2624 int is_lasr
= extract32(insn
, 15, 1);
2625 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2626 int size
= extract32(insn
, 30, 2);
2627 TCGv_i64 clean_addr
;
2629 switch (o2_L_o1_o0
) {
2630 case 0x0: /* STXR */
2631 case 0x1: /* STLXR */
2633 gen_check_sp_alignment(s
);
2636 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2638 gen_store_exclusive(s
, rs
, rt
, rt2
, rn
, size
, false);
2641 case 0x4: /* LDXR */
2642 case 0x5: /* LDAXR */
2644 gen_check_sp_alignment(s
);
2646 gen_load_exclusive(s
, rt
, rt2
, rn
, size
, false);
2648 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2652 case 0x8: /* STLLR */
2653 if (!dc_isar_feature(aa64_lor
, s
)) {
2656 /* StoreLORelease is the same as Store-Release for QEMU. */
2658 case 0x9: /* STLR */
2659 /* Generate ISS for non-exclusive accesses including LASR. */
2661 gen_check_sp_alignment(s
);
2663 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2664 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2665 true, rn
!= 31, size
);
2666 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2667 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, true, rt
,
2668 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2671 case 0xc: /* LDLAR */
2672 if (!dc_isar_feature(aa64_lor
, s
)) {
2675 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2677 case 0xd: /* LDAR */
2678 /* Generate ISS for non-exclusive accesses including LASR. */
2680 gen_check_sp_alignment(s
);
2682 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2683 false, rn
!= 31, size
);
2684 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2685 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, false, true,
2686 rt
, disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2687 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2690 case 0x2: case 0x3: /* CASP / STXP */
2691 if (size
& 2) { /* STXP / STLXP */
2693 gen_check_sp_alignment(s
);
2696 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2698 gen_store_exclusive(s
, rs
, rt
, rt2
, rn
, size
, true);
2702 && ((rt
| rs
) & 1) == 0
2703 && dc_isar_feature(aa64_atomics
, s
)) {
2705 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2710 case 0x6: case 0x7: /* CASPA / LDXP */
2711 if (size
& 2) { /* LDXP / LDAXP */
2713 gen_check_sp_alignment(s
);
2715 gen_load_exclusive(s
, rt
, rt2
, rn
, size
, true);
2717 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2722 && ((rt
| rs
) & 1) == 0
2723 && dc_isar_feature(aa64_atomics
, s
)) {
2724 /* CASPA / CASPAL */
2725 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2731 case 0xb: /* CASL */
2732 case 0xe: /* CASA */
2733 case 0xf: /* CASAL */
2734 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2735 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2740 unallocated_encoding(s
);
2744 * Load register (literal)
2746 * 31 30 29 27 26 25 24 23 5 4 0
2747 * +-----+-------+---+-----+-------------------+-------+
2748 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2749 * +-----+-------+---+-----+-------------------+-------+
2751 * V: 1 -> vector (simd/fp)
2752 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2753 * 10-> 32 bit signed, 11 -> prefetch
2754 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2756 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2758 int rt
= extract32(insn
, 0, 5);
2759 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2760 bool is_vector
= extract32(insn
, 26, 1);
2761 int opc
= extract32(insn
, 30, 2);
2762 bool is_signed
= false;
2764 TCGv_i64 tcg_rt
, clean_addr
;
2768 unallocated_encoding(s
);
2772 if (!fp_access_check(s
)) {
2777 /* PRFM (literal) : prefetch */
2780 size
= 2 + extract32(opc
, 0, 1);
2781 is_signed
= extract32(opc
, 1, 1);
2784 tcg_rt
= cpu_reg(s
, rt
);
2786 clean_addr
= tcg_temp_new_i64();
2787 gen_pc_plus_diff(s
, clean_addr
, imm
);
2789 do_fp_ld(s
, rt
, clean_addr
, size
);
2791 /* Only unsigned 32bit loads target 32bit registers. */
2792 bool iss_sf
= opc
!= 0;
2794 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2795 false, true, rt
, iss_sf
, false);
2800 * LDNP (Load Pair - non-temporal hint)
2801 * LDP (Load Pair - non vector)
2802 * LDPSW (Load Pair Signed Word - non vector)
2803 * STNP (Store Pair - non-temporal hint)
2804 * STP (Store Pair - non vector)
2805 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2806 * LDP (Load Pair of SIMD&FP)
2807 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2808 * STP (Store Pair of SIMD&FP)
2810 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2811 * +-----+-------+---+---+-------+---+-----------------------------+
2812 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2813 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2815 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2817 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2818 * V: 0 -> GPR, 1 -> Vector
2819 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2820 * 10 -> signed offset, 11 -> pre-index
2821 * L: 0 -> Store 1 -> Load
2823 * Rt, Rt2 = GPR or SIMD registers to be stored
2824 * Rn = general purpose register containing address
2825 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2827 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2829 int rt
= extract32(insn
, 0, 5);
2830 int rn
= extract32(insn
, 5, 5);
2831 int rt2
= extract32(insn
, 10, 5);
2832 uint64_t offset
= sextract64(insn
, 15, 7);
2833 int index
= extract32(insn
, 23, 2);
2834 bool is_vector
= extract32(insn
, 26, 1);
2835 bool is_load
= extract32(insn
, 22, 1);
2836 int opc
= extract32(insn
, 30, 2);
2838 bool is_signed
= false;
2839 bool postindex
= false;
2841 bool set_tag
= false;
2843 TCGv_i64 clean_addr
, dirty_addr
;
2848 unallocated_encoding(s
);
2854 } else if (opc
== 1 && !is_load
) {
2856 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2857 unallocated_encoding(s
);
2863 size
= 2 + extract32(opc
, 1, 1);
2864 is_signed
= extract32(opc
, 0, 1);
2865 if (!is_load
&& is_signed
) {
2866 unallocated_encoding(s
);
2872 case 1: /* post-index */
2877 /* signed offset with "non-temporal" hint. Since we don't emulate
2878 * caches we don't care about hints to the cache system about
2879 * data access patterns, and handle this identically to plain
2883 /* There is no non-temporal-hint version of LDPSW */
2884 unallocated_encoding(s
);
2889 case 2: /* signed offset, rn not updated */
2892 case 3: /* pre-index */
2898 if (is_vector
&& !fp_access_check(s
)) {
2902 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2905 gen_check_sp_alignment(s
);
2908 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2910 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2916 * TODO: We could rely on the stores below, at least for
2917 * system mode, if we arrange to add MO_ALIGN_16.
2919 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2920 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2921 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2923 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2927 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2928 (wback
|| rn
!= 31) && !set_tag
, 2 << size
);
2932 do_fp_ld(s
, rt
, clean_addr
, size
);
2934 do_fp_st(s
, rt
, clean_addr
, size
);
2936 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2938 do_fp_ld(s
, rt2
, clean_addr
, size
);
2940 do_fp_st(s
, rt2
, clean_addr
, size
);
2943 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2944 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2947 TCGv_i64 tmp
= tcg_temp_new_i64();
2949 /* Do not modify tcg_rt before recognizing any exception
2950 * from the second load.
2952 do_gpr_ld(s
, tmp
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2953 false, false, 0, false, false);
2954 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2955 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2956 false, false, 0, false, false);
2958 tcg_gen_mov_i64(tcg_rt
, tmp
);
2960 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2961 false, 0, false, false);
2962 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2963 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2964 false, 0, false, false);
2970 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2972 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2977 * Load/store (immediate post-indexed)
2978 * Load/store (immediate pre-indexed)
2979 * Load/store (unscaled immediate)
2981 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2982 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2983 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2984 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2986 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2988 * V = 0 -> non-vector
2989 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2990 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2992 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2998 int rn
= extract32(insn
, 5, 5);
2999 int imm9
= sextract32(insn
, 12, 9);
3000 int idx
= extract32(insn
, 10, 2);
3001 bool is_signed
= false;
3002 bool is_store
= false;
3003 bool is_extended
= false;
3004 bool is_unpriv
= (idx
== 2);
3010 TCGv_i64 clean_addr
, dirty_addr
;
3013 size
|= (opc
& 2) << 1;
3014 if (size
> 4 || is_unpriv
) {
3015 unallocated_encoding(s
);
3018 is_store
= ((opc
& 1) == 0);
3019 if (!fp_access_check(s
)) {
3023 if (size
== 3 && opc
== 2) {
3024 /* PRFM - prefetch */
3026 unallocated_encoding(s
);
3031 if (opc
== 3 && size
> 1) {
3032 unallocated_encoding(s
);
3035 is_store
= (opc
== 0);
3036 is_signed
= extract32(opc
, 1, 1);
3037 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3055 g_assert_not_reached();
3058 iss_valid
= !is_vector
&& !writeback
;
3061 gen_check_sp_alignment(s
);
3064 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3066 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3069 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3070 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3071 writeback
|| rn
!= 31,
3072 size
, is_unpriv
, memidx
);
3076 do_fp_st(s
, rt
, clean_addr
, size
);
3078 do_fp_ld(s
, rt
, clean_addr
, size
);
3081 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3082 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3085 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3086 iss_valid
, rt
, iss_sf
, false);
3088 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3089 is_extended
, memidx
,
3090 iss_valid
, rt
, iss_sf
, false);
3095 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3097 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3099 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3104 * Load/store (register offset)
3106 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3107 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3108 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3109 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3112 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3113 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3115 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3116 * opc<0>: 0 -> store, 1 -> load
3117 * V: 1 -> vector/simd
3118 * opt: extend encoding (see DecodeRegExtend)
3119 * S: if S=1 then scale (essentially index by sizeof(size))
3120 * Rt: register to transfer into/out of
3121 * Rn: address register or SP for base
3122 * Rm: offset register or ZR for offset
3124 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3130 int rn
= extract32(insn
, 5, 5);
3131 int shift
= extract32(insn
, 12, 1);
3132 int rm
= extract32(insn
, 16, 5);
3133 int opt
= extract32(insn
, 13, 3);
3134 bool is_signed
= false;
3135 bool is_store
= false;
3136 bool is_extended
= false;
3138 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3140 if (extract32(opt
, 1, 1) == 0) {
3141 unallocated_encoding(s
);
3146 size
|= (opc
& 2) << 1;
3148 unallocated_encoding(s
);
3151 is_store
= !extract32(opc
, 0, 1);
3152 if (!fp_access_check(s
)) {
3156 if (size
== 3 && opc
== 2) {
3157 /* PRFM - prefetch */
3160 if (opc
== 3 && size
> 1) {
3161 unallocated_encoding(s
);
3164 is_store
= (opc
== 0);
3165 is_signed
= extract32(opc
, 1, 1);
3166 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3170 gen_check_sp_alignment(s
);
3172 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3174 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3175 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3177 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3178 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3182 do_fp_st(s
, rt
, clean_addr
, size
);
3184 do_fp_ld(s
, rt
, clean_addr
, size
);
3187 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3188 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3190 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3191 true, rt
, iss_sf
, false);
3193 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3194 is_extended
, true, rt
, iss_sf
, false);
3200 * Load/store (unsigned immediate)
3202 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3203 * +----+-------+---+-----+-----+------------+-------+------+
3204 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3205 * +----+-------+---+-----+-----+------------+-------+------+
3208 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3209 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3211 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3212 * opc<0>: 0 -> store, 1 -> load
3213 * Rn: base address register (inc SP)
3214 * Rt: target register
3216 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3222 int rn
= extract32(insn
, 5, 5);
3223 unsigned int imm12
= extract32(insn
, 10, 12);
3224 unsigned int offset
;
3226 TCGv_i64 clean_addr
, dirty_addr
;
3229 bool is_signed
= false;
3230 bool is_extended
= false;
3233 size
|= (opc
& 2) << 1;
3235 unallocated_encoding(s
);
3238 is_store
= !extract32(opc
, 0, 1);
3239 if (!fp_access_check(s
)) {
3243 if (size
== 3 && opc
== 2) {
3244 /* PRFM - prefetch */
3247 if (opc
== 3 && size
> 1) {
3248 unallocated_encoding(s
);
3251 is_store
= (opc
== 0);
3252 is_signed
= extract32(opc
, 1, 1);
3253 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3257 gen_check_sp_alignment(s
);
3259 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3260 offset
= imm12
<< size
;
3261 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3262 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3266 do_fp_st(s
, rt
, clean_addr
, size
);
3268 do_fp_ld(s
, rt
, clean_addr
, size
);
3271 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3272 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3274 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3275 true, rt
, iss_sf
, false);
3277 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3278 is_extended
, true, rt
, iss_sf
, false);
3283 /* Atomic memory operations
3285 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3286 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3287 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3288 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3290 * Rt: the result register
3291 * Rn: base address or SP
3292 * Rs: the source register for the operation
3293 * V: vector flag (always 0 as of v8.3)
3297 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3298 int size
, int rt
, bool is_vector
)
3300 int rs
= extract32(insn
, 16, 5);
3301 int rn
= extract32(insn
, 5, 5);
3302 int o3_opc
= extract32(insn
, 12, 4);
3303 bool r
= extract32(insn
, 22, 1);
3304 bool a
= extract32(insn
, 23, 1);
3305 TCGv_i64 tcg_rs
, tcg_rt
, clean_addr
;
3306 AtomicThreeOpFn
*fn
= NULL
;
3307 MemOp mop
= s
->be_data
| size
| MO_ALIGN
;
3309 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3310 unallocated_encoding(s
);
3314 case 000: /* LDADD */
3315 fn
= tcg_gen_atomic_fetch_add_i64
;
3317 case 001: /* LDCLR */
3318 fn
= tcg_gen_atomic_fetch_and_i64
;
3320 case 002: /* LDEOR */
3321 fn
= tcg_gen_atomic_fetch_xor_i64
;
3323 case 003: /* LDSET */
3324 fn
= tcg_gen_atomic_fetch_or_i64
;
3326 case 004: /* LDSMAX */
3327 fn
= tcg_gen_atomic_fetch_smax_i64
;
3330 case 005: /* LDSMIN */
3331 fn
= tcg_gen_atomic_fetch_smin_i64
;
3334 case 006: /* LDUMAX */
3335 fn
= tcg_gen_atomic_fetch_umax_i64
;
3337 case 007: /* LDUMIN */
3338 fn
= tcg_gen_atomic_fetch_umin_i64
;
3341 fn
= tcg_gen_atomic_xchg_i64
;
3343 case 014: /* LDAPR, LDAPRH, LDAPRB */
3344 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3345 rs
!= 31 || a
!= 1 || r
!= 0) {
3346 unallocated_encoding(s
);
3351 unallocated_encoding(s
);
3356 gen_check_sp_alignment(s
);
3358 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3360 if (o3_opc
== 014) {
3362 * LDAPR* are a special case because they are a simple load, not a
3363 * fetch-and-do-something op.
3364 * The architectural consistency requirements here are weaker than
3365 * full load-acquire (we only need "load-acquire processor consistent"),
3366 * but we choose to implement them as full LDAQ.
3368 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false,
3369 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3370 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3374 tcg_rs
= read_cpu_reg(s
, rs
, true);
3375 tcg_rt
= cpu_reg(s
, rt
);
3377 if (o3_opc
== 1) { /* LDCLR */
3378 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3381 /* The tcg atomic primitives are all full barriers. Therefore we
3382 * can ignore the Acquire and Release bits of this instruction.
3384 fn(tcg_rt
, clean_addr
, tcg_rs
, get_mem_index(s
), mop
);
3386 if ((mop
& MO_SIGN
) && size
!= MO_64
) {
3387 tcg_gen_ext32u_i64(tcg_rt
, tcg_rt
);
3392 * PAC memory operations
3394 * 31 30 27 26 24 22 21 12 11 10 5 0
3395 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3396 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3397 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3399 * Rt: the result register
3400 * Rn: base address or SP
3401 * V: vector flag (always 0 as of v8.3)
3402 * M: clear for key DA, set for key DB
3403 * W: pre-indexing flag
3406 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3407 int size
, int rt
, bool is_vector
)
3409 int rn
= extract32(insn
, 5, 5);
3410 bool is_wback
= extract32(insn
, 11, 1);
3411 bool use_key_a
= !extract32(insn
, 23, 1);
3413 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3415 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3416 unallocated_encoding(s
);
3421 gen_check_sp_alignment(s
);
3423 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3425 if (s
->pauth_active
) {
3427 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3428 tcg_constant_i64(0));
3430 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3431 tcg_constant_i64(0));
3435 /* Form the 10-bit signed, scaled offset. */
3436 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3437 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3438 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3440 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3441 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3442 is_wback
|| rn
!= 31, size
);
3444 tcg_rt
= cpu_reg(s
, rt
);
3445 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3446 /* extend */ false, /* iss_valid */ !is_wback
,
3447 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3450 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3455 * LDAPR/STLR (unscaled immediate)
3457 * 31 30 24 22 21 12 10 5 0
3458 * +------+-------------+-----+---+--------+-----+----+-----+
3459 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3460 * +------+-------------+-----+---+--------+-----+----+-----+
3462 * Rt: source or destination register
3464 * imm9: unscaled immediate offset
3465 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3466 * size: size of load/store
3468 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3470 int rt
= extract32(insn
, 0, 5);
3471 int rn
= extract32(insn
, 5, 5);
3472 int offset
= sextract32(insn
, 12, 9);
3473 int opc
= extract32(insn
, 22, 2);
3474 int size
= extract32(insn
, 30, 2);
3475 TCGv_i64 clean_addr
, dirty_addr
;
3476 bool is_store
= false;
3477 bool extend
= false;
3481 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3482 unallocated_encoding(s
);
3486 /* TODO: ARMv8.4-LSE SCTLR.nAA */
3487 mop
= size
| MO_ALIGN
;
3490 case 0: /* STLURB */
3493 case 1: /* LDAPUR* */
3495 case 2: /* LDAPURS* 64-bit variant */
3497 unallocated_encoding(s
);
3502 case 3: /* LDAPURS* 32-bit variant */
3504 unallocated_encoding(s
);
3508 extend
= true; /* zero-extend 32->64 after signed load */
3511 g_assert_not_reached();
3514 iss_sf
= disas_ldst_compute_iss_sf(size
, (mop
& MO_SIGN
) != 0, opc
);
3517 gen_check_sp_alignment(s
);
3520 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3521 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3522 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3525 /* Store-Release semantics */
3526 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3527 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, mop
, true, rt
, iss_sf
, true);
3530 * Load-AcquirePC semantics; we implement as the slightly more
3531 * restrictive Load-Acquire.
3533 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, mop
,
3534 extend
, true, rt
, iss_sf
, true);
3535 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3539 /* Load/store register (all forms) */
3540 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3542 int rt
= extract32(insn
, 0, 5);
3543 int opc
= extract32(insn
, 22, 2);
3544 bool is_vector
= extract32(insn
, 26, 1);
3545 int size
= extract32(insn
, 30, 2);
3547 switch (extract32(insn
, 24, 2)) {
3549 if (extract32(insn
, 21, 1) == 0) {
3550 /* Load/store register (unscaled immediate)
3551 * Load/store immediate pre/post-indexed
3552 * Load/store register unprivileged
3554 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3557 switch (extract32(insn
, 10, 2)) {
3559 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3562 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3565 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3570 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3573 unallocated_encoding(s
);
3576 /* AdvSIMD load/store multiple structures
3578 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3579 * +---+---+---------------+---+-------------+--------+------+------+------+
3580 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3581 * +---+---+---------------+---+-------------+--------+------+------+------+
3583 * AdvSIMD load/store multiple structures (post-indexed)
3585 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3586 * +---+---+---------------+---+---+---------+--------+------+------+------+
3587 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3588 * +---+---+---------------+---+---+---------+--------+------+------+------+
3590 * Rt: first (or only) SIMD&FP register to be transferred
3591 * Rn: base address or SP
3592 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3594 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3596 int rt
= extract32(insn
, 0, 5);
3597 int rn
= extract32(insn
, 5, 5);
3598 int rm
= extract32(insn
, 16, 5);
3599 int size
= extract32(insn
, 10, 2);
3600 int opcode
= extract32(insn
, 12, 4);
3601 bool is_store
= !extract32(insn
, 22, 1);
3602 bool is_postidx
= extract32(insn
, 23, 1);
3603 bool is_q
= extract32(insn
, 30, 1);
3604 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3605 MemOp endian
, align
, mop
;
3607 int total
; /* total bytes */
3608 int elements
; /* elements per vector */
3609 int rpt
; /* num iterations */
3610 int selem
; /* structure elements */
3613 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3614 unallocated_encoding(s
);
3618 if (!is_postidx
&& rm
!= 0) {
3619 unallocated_encoding(s
);
3623 /* From the shared decode logic */
3654 unallocated_encoding(s
);
3658 if (size
== 3 && !is_q
&& selem
!= 1) {
3660 unallocated_encoding(s
);
3664 if (!fp_access_check(s
)) {
3669 gen_check_sp_alignment(s
);
3672 /* For our purposes, bytes are always little-endian. */
3673 endian
= s
->be_data
;
3678 total
= rpt
* selem
* (is_q
? 16 : 8);
3679 tcg_rn
= cpu_reg_sp(s
, rn
);
3682 * Issue the MTE check vs the logical repeat count, before we
3683 * promote consecutive little-endian elements below.
3685 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3689 * Consecutive little-endian elements from a single register
3690 * can be promoted to a larger little-endian operation.
3693 if (selem
== 1 && endian
== MO_LE
) {
3694 align
= pow2_align(size
);
3697 if (!s
->align_mem
) {
3700 mop
= endian
| size
| align
;
3702 elements
= (is_q
? 16 : 8) >> size
;
3703 tcg_ebytes
= tcg_constant_i64(1 << size
);
3704 for (r
= 0; r
< rpt
; r
++) {
3706 for (e
= 0; e
< elements
; e
++) {
3708 for (xs
= 0; xs
< selem
; xs
++) {
3709 int tt
= (rt
+ r
+ xs
) % 32;
3711 do_vec_st(s
, tt
, e
, clean_addr
, mop
);
3713 do_vec_ld(s
, tt
, e
, clean_addr
, mop
);
3715 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3721 /* For non-quad operations, setting a slice of the low
3722 * 64 bits of the register clears the high 64 bits (in
3723 * the ARM ARM pseudocode this is implicit in the fact
3724 * that 'rval' is a 64 bit wide variable).
3725 * For quad operations, we might still need to zero the
3728 for (r
= 0; r
< rpt
* selem
; r
++) {
3729 int tt
= (rt
+ r
) % 32;
3730 clear_vec_high(s
, is_q
, tt
);
3736 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3738 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3743 /* AdvSIMD load/store single structure
3745 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3746 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3747 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3748 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3750 * AdvSIMD load/store single structure (post-indexed)
3752 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3753 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3754 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3755 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3757 * Rt: first (or only) SIMD&FP register to be transferred
3758 * Rn: base address or SP
3759 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3760 * index = encoded in Q:S:size dependent on size
3762 * lane_size = encoded in R, opc
3763 * transfer width = encoded in opc, S, size
3765 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3767 int rt
= extract32(insn
, 0, 5);
3768 int rn
= extract32(insn
, 5, 5);
3769 int rm
= extract32(insn
, 16, 5);
3770 int size
= extract32(insn
, 10, 2);
3771 int S
= extract32(insn
, 12, 1);
3772 int opc
= extract32(insn
, 13, 3);
3773 int R
= extract32(insn
, 21, 1);
3774 int is_load
= extract32(insn
, 22, 1);
3775 int is_postidx
= extract32(insn
, 23, 1);
3776 int is_q
= extract32(insn
, 30, 1);
3778 int scale
= extract32(opc
, 1, 2);
3779 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3780 bool replicate
= false;
3781 int index
= is_q
<< 3 | S
<< 2 | size
;
3783 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3786 if (extract32(insn
, 31, 1)) {
3787 unallocated_encoding(s
);
3790 if (!is_postidx
&& rm
!= 0) {
3791 unallocated_encoding(s
);
3797 if (!is_load
|| S
) {
3798 unallocated_encoding(s
);
3807 if (extract32(size
, 0, 1)) {
3808 unallocated_encoding(s
);
3814 if (extract32(size
, 1, 1)) {
3815 unallocated_encoding(s
);
3818 if (!extract32(size
, 0, 1)) {
3822 unallocated_encoding(s
);
3830 g_assert_not_reached();
3833 if (!fp_access_check(s
)) {
3838 gen_check_sp_alignment(s
);
3841 total
= selem
<< scale
;
3842 tcg_rn
= cpu_reg_sp(s
, rn
);
3844 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3846 mop
= finalize_memop(s
, scale
);
3848 tcg_ebytes
= tcg_constant_i64(1 << scale
);
3849 for (xs
= 0; xs
< selem
; xs
++) {
3851 /* Load and replicate to all elements */
3852 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3854 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
, get_mem_index(s
), mop
);
3855 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3856 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3859 /* Load/store one element per register */
3861 do_vec_ld(s
, rt
, index
, clean_addr
, mop
);
3863 do_vec_st(s
, rt
, index
, clean_addr
, mop
);
3866 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3872 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3874 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3880 * Load/Store memory tags
3882 * 31 30 29 24 22 21 12 10 5 0
3883 * +-----+-------------+-----+---+------+-----+------+------+
3884 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3885 * +-----+-------------+-----+---+------+-----+------+------+
3887 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3889 int rt
= extract32(insn
, 0, 5);
3890 int rn
= extract32(insn
, 5, 5);
3891 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3892 int op2
= extract32(insn
, 10, 2);
3893 int op1
= extract32(insn
, 22, 2);
3894 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3896 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3898 /* We checked insn bits [29:24,21] in the caller. */
3899 if (extract32(insn
, 30, 2) != 3) {
3900 goto do_unallocated
;
3904 * @index is a tri-state variable which has 3 states:
3905 * < 0 : post-index, writeback
3906 * = 0 : signed offset
3907 * > 0 : pre-index, writeback
3916 if (s
->current_el
== 0 || offset
!= 0) {
3917 goto do_unallocated
;
3919 is_mult
= is_zero
= true;
3939 if (s
->current_el
== 0 || offset
!= 0) {
3940 goto do_unallocated
;
3948 is_pair
= is_zero
= true;
3952 if (s
->current_el
== 0 || offset
!= 0) {
3953 goto do_unallocated
;
3955 is_mult
= is_load
= true;
3961 unallocated_encoding(s
);
3966 ? !dc_isar_feature(aa64_mte
, s
)
3967 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
3968 goto do_unallocated
;
3972 gen_check_sp_alignment(s
);
3975 addr
= read_cpu_reg_sp(s
, rn
, true);
3977 /* pre-index or signed offset */
3978 tcg_gen_addi_i64(addr
, addr
, offset
);
3982 tcg_rt
= cpu_reg(s
, rt
);
3985 int size
= 4 << s
->dcz_blocksize
;
3988 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
3991 * The non-tags portion of STZGM is mostly like DC_ZVA,
3992 * except the alignment happens before the access.
3994 clean_addr
= clean_data_tbi(s
, addr
);
3995 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
3996 gen_helper_dc_zva(cpu_env
, clean_addr
);
3997 } else if (s
->ata
) {
3999 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4001 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4004 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4005 int size
= 4 << GMID_EL1_BS
;
4007 clean_addr
= clean_data_tbi(s
, addr
);
4008 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4009 gen_probe_access(s
, clean_addr
, acc
, size
);
4012 /* The result tags are zeros. */
4013 tcg_gen_movi_i64(tcg_rt
, 0);
4020 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4021 tcg_rt
= cpu_reg(s
, rt
);
4023 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4025 clean_addr
= clean_data_tbi(s
, addr
);
4026 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4027 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4030 tcg_rt
= cpu_reg_sp(s
, rt
);
4033 * For STG and ST2G, we need to check alignment and probe memory.
4034 * TODO: For STZG and STZ2G, we could rely on the stores below,
4035 * at least for system mode; user-only won't enforce alignment.
4038 gen_helper_st2g_stub(cpu_env
, addr
);
4040 gen_helper_stg_stub(cpu_env
, addr
);
4042 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4044 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4046 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4050 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4052 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4058 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4059 TCGv_i64 zero64
= tcg_constant_i64(0);
4060 TCGv_i128 zero128
= tcg_temp_new_i128();
4061 int mem_index
= get_mem_index(s
);
4062 MemOp mop
= finalize_memop(s
, MO_128
| MO_ALIGN
);
4064 tcg_gen_concat_i64_i128(zero128
, zero64
, zero64
);
4066 /* This is 1 or 2 atomic 16-byte operations. */
4067 tcg_gen_qemu_st_i128(zero128
, clean_addr
, mem_index
, mop
);
4069 tcg_gen_addi_i64(clean_addr
, clean_addr
, 16);
4070 tcg_gen_qemu_st_i128(zero128
, clean_addr
, mem_index
, mop
);
4075 /* pre-index or post-index */
4078 tcg_gen_addi_i64(addr
, addr
, offset
);
4080 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4084 /* Loads and stores */
4085 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4087 switch (extract32(insn
, 24, 6)) {
4088 case 0x08: /* Load/store exclusive */
4089 disas_ldst_excl(s
, insn
);
4091 case 0x18: case 0x1c: /* Load register (literal) */
4092 disas_ld_lit(s
, insn
);
4094 case 0x28: case 0x29:
4095 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4096 disas_ldst_pair(s
, insn
);
4098 case 0x38: case 0x39:
4099 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4100 disas_ldst_reg(s
, insn
);
4102 case 0x0c: /* AdvSIMD load/store multiple structures */
4103 disas_ldst_multiple_struct(s
, insn
);
4105 case 0x0d: /* AdvSIMD load/store single structure */
4106 disas_ldst_single_struct(s
, insn
);
4109 if (extract32(insn
, 21, 1) != 0) {
4110 disas_ldst_tag(s
, insn
);
4111 } else if (extract32(insn
, 10, 2) == 0) {
4112 disas_ldst_ldapr_stlr(s
, insn
);
4114 unallocated_encoding(s
);
4118 unallocated_encoding(s
);
4123 typedef void ArithTwoOp(TCGv_i64
, TCGv_i64
, TCGv_i64
);
4125 static bool gen_rri(DisasContext
*s
, arg_rri_sf
*a
,
4126 bool rd_sp
, bool rn_sp
, ArithTwoOp
*fn
)
4128 TCGv_i64 tcg_rn
= rn_sp
? cpu_reg_sp(s
, a
->rn
) : cpu_reg(s
, a
->rn
);
4129 TCGv_i64 tcg_rd
= rd_sp
? cpu_reg_sp(s
, a
->rd
) : cpu_reg(s
, a
->rd
);
4130 TCGv_i64 tcg_imm
= tcg_constant_i64(a
->imm
);
4132 fn(tcg_rd
, tcg_rn
, tcg_imm
);
4134 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4140 * PC-rel. addressing
4143 static bool trans_ADR(DisasContext
*s
, arg_ri
*a
)
4145 gen_pc_plus_diff(s
, cpu_reg(s
, a
->rd
), a
->imm
);
4149 static bool trans_ADRP(DisasContext
*s
, arg_ri
*a
)
4151 int64_t offset
= (int64_t)a
->imm
<< 12;
4153 /* The page offset is ok for CF_PCREL. */
4154 offset
-= s
->pc_curr
& 0xfff;
4155 gen_pc_plus_diff(s
, cpu_reg(s
, a
->rd
), offset
);
4160 * Add/subtract (immediate)
4162 TRANS(ADD_i
, gen_rri
, a
, 1, 1, tcg_gen_add_i64
)
4163 TRANS(SUB_i
, gen_rri
, a
, 1, 1, tcg_gen_sub_i64
)
4164 TRANS(ADDS_i
, gen_rri
, a
, 0, 1, a
->sf
? gen_add64_CC
: gen_add32_CC
)
4165 TRANS(SUBS_i
, gen_rri
, a
, 0, 1, a
->sf
? gen_sub64_CC
: gen_sub32_CC
)
4168 * Add/subtract (immediate, with tags)
4171 static bool gen_add_sub_imm_with_tags(DisasContext
*s
, arg_rri_tag
*a
,
4174 TCGv_i64 tcg_rn
, tcg_rd
;
4177 imm
= a
->uimm6
<< LOG2_TAG_GRANULE
;
4182 tcg_rn
= cpu_reg_sp(s
, a
->rn
);
4183 tcg_rd
= cpu_reg_sp(s
, a
->rd
);
4186 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
,
4187 tcg_constant_i32(imm
),
4188 tcg_constant_i32(a
->uimm4
));
4190 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4191 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4196 TRANS_FEAT(ADDG_i
, aa64_mte_insn_reg
, gen_add_sub_imm_with_tags
, a
, false)
4197 TRANS_FEAT(SUBG_i
, aa64_mte_insn_reg
, gen_add_sub_imm_with_tags
, a
, true)
4199 /* The input should be a value in the bottom e bits (with higher
4200 * bits zero); returns that value replicated into every element
4201 * of size e in a 64 bit integer.
4203 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4214 * Logical (immediate)
4218 * Simplified variant of pseudocode DecodeBitMasks() for the case where we
4219 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4220 * value (ie should cause a guest UNDEF exception), and true if they are
4221 * valid, in which case the decoded bit pattern is written to result.
4223 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4224 unsigned int imms
, unsigned int immr
)
4227 unsigned e
, levels
, s
, r
;
4230 assert(immn
< 2 && imms
< 64 && immr
< 64);
4232 /* The bit patterns we create here are 64 bit patterns which
4233 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4234 * 64 bits each. Each element contains the same value: a run
4235 * of between 1 and e-1 non-zero bits, rotated within the
4236 * element by between 0 and e-1 bits.
4238 * The element size and run length are encoded into immn (1 bit)
4239 * and imms (6 bits) as follows:
4240 * 64 bit elements: immn = 1, imms = <length of run - 1>
4241 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4242 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4243 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4244 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4245 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4246 * Notice that immn = 0, imms = 11111x is the only combination
4247 * not covered by one of the above options; this is reserved.
4248 * Further, <length of run - 1> all-ones is a reserved pattern.
4250 * In all cases the rotation is by immr % e (and immr is 6 bits).
4253 /* First determine the element size */
4254 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4256 /* This is the immn == 0, imms == 0x11111x case */
4266 /* <length of run - 1> mustn't be all-ones. */
4270 /* Create the value of one element: s+1 set bits rotated
4271 * by r within the element (which is e bits wide)...
4273 mask
= MAKE_64BIT_MASK(0, s
+ 1);
4275 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4276 mask
&= MAKE_64BIT_MASK(0, e
);
4278 /* ...then replicate the element over the whole 64 bit value */
4279 mask
= bitfield_replicate(mask
, e
);
4284 static bool gen_rri_log(DisasContext
*s
, arg_rri_log
*a
, bool set_cc
,
4285 void (*fn
)(TCGv_i64
, TCGv_i64
, int64_t))
4287 TCGv_i64 tcg_rd
, tcg_rn
;
4290 /* Some immediate field values are reserved. */
4291 if (!logic_imm_decode_wmask(&imm
, extract32(a
->dbm
, 12, 1),
4292 extract32(a
->dbm
, 0, 6),
4293 extract32(a
->dbm
, 6, 6))) {
4297 imm
&= 0xffffffffull
;
4300 tcg_rd
= set_cc
? cpu_reg(s
, a
->rd
) : cpu_reg_sp(s
, a
->rd
);
4301 tcg_rn
= cpu_reg(s
, a
->rn
);
4303 fn(tcg_rd
, tcg_rn
, imm
);
4305 gen_logic_CC(a
->sf
, tcg_rd
);
4308 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4313 TRANS(AND_i
, gen_rri_log
, a
, false, tcg_gen_andi_i64
)
4314 TRANS(ORR_i
, gen_rri_log
, a
, false, tcg_gen_ori_i64
)
4315 TRANS(EOR_i
, gen_rri_log
, a
, false, tcg_gen_xori_i64
)
4316 TRANS(ANDS_i
, gen_rri_log
, a
, true, tcg_gen_andi_i64
)
4319 * Move wide (immediate)
4322 static bool trans_MOVZ(DisasContext
*s
, arg_movw
*a
)
4324 int pos
= a
->hw
<< 4;
4325 tcg_gen_movi_i64(cpu_reg(s
, a
->rd
), (uint64_t)a
->imm
<< pos
);
4329 static bool trans_MOVN(DisasContext
*s
, arg_movw
*a
)
4331 int pos
= a
->hw
<< 4;
4332 uint64_t imm
= a
->imm
;
4334 imm
= ~(imm
<< pos
);
4336 imm
= (uint32_t)imm
;
4338 tcg_gen_movi_i64(cpu_reg(s
, a
->rd
), imm
);
4342 static bool trans_MOVK(DisasContext
*s
, arg_movw
*a
)
4344 int pos
= a
->hw
<< 4;
4345 TCGv_i64 tcg_rd
, tcg_im
;
4347 tcg_rd
= cpu_reg(s
, a
->rd
);
4348 tcg_im
= tcg_constant_i64(a
->imm
);
4349 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_im
, pos
, 16);
4351 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4360 static bool trans_SBFM(DisasContext
*s
, arg_SBFM
*a
)
4362 TCGv_i64 tcg_rd
= cpu_reg(s
, a
->rd
);
4363 TCGv_i64 tcg_tmp
= read_cpu_reg(s
, a
->rn
, 1);
4364 unsigned int bitsize
= a
->sf
? 64 : 32;
4365 unsigned int ri
= a
->immr
;
4366 unsigned int si
= a
->imms
;
4367 unsigned int pos
, len
;
4370 /* Wd<s-r:0> = Wn<s:r> */
4371 len
= (si
- ri
) + 1;
4372 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4374 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4377 /* Wd<32+s-r,32-r> = Wn<s:0> */
4379 pos
= (bitsize
- ri
) & (bitsize
- 1);
4383 * Sign extend the destination field from len to fill the
4384 * balance of the word. Let the deposit below insert all
4385 * of those sign bits.
4387 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4392 * We start with zero, and we haven't modified any bits outside
4393 * bitsize, therefore no final zero-extension is unneeded for !sf.
4395 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4400 static bool trans_UBFM(DisasContext
*s
, arg_UBFM
*a
)
4402 TCGv_i64 tcg_rd
= cpu_reg(s
, a
->rd
);
4403 TCGv_i64 tcg_tmp
= read_cpu_reg(s
, a
->rn
, 1);
4404 unsigned int bitsize
= a
->sf
? 64 : 32;
4405 unsigned int ri
= a
->immr
;
4406 unsigned int si
= a
->imms
;
4407 unsigned int pos
, len
;
4409 tcg_rd
= cpu_reg(s
, a
->rd
);
4410 tcg_tmp
= read_cpu_reg(s
, a
->rn
, 1);
4413 /* Wd<s-r:0> = Wn<s:r> */
4414 len
= (si
- ri
) + 1;
4415 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4417 /* Wd<32+s-r,32-r> = Wn<s:0> */
4419 pos
= (bitsize
- ri
) & (bitsize
- 1);
4420 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4425 static bool trans_BFM(DisasContext
*s
, arg_BFM
*a
)
4427 TCGv_i64 tcg_rd
= cpu_reg(s
, a
->rd
);
4428 TCGv_i64 tcg_tmp
= read_cpu_reg(s
, a
->rn
, 1);
4429 unsigned int bitsize
= a
->sf
? 64 : 32;
4430 unsigned int ri
= a
->immr
;
4431 unsigned int si
= a
->imms
;
4432 unsigned int pos
, len
;
4434 tcg_rd
= cpu_reg(s
, a
->rd
);
4435 tcg_tmp
= read_cpu_reg(s
, a
->rn
, 1);
4438 /* Wd<s-r:0> = Wn<s:r> */
4439 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4440 len
= (si
- ri
) + 1;
4443 /* Wd<32+s-r,32-r> = Wn<s:0> */
4445 pos
= (bitsize
- ri
) & (bitsize
- 1);
4448 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4450 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4455 static bool trans_EXTR(DisasContext
*s
, arg_extract
*a
)
4457 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4459 tcg_rd
= cpu_reg(s
, a
->rd
);
4461 if (unlikely(a
->imm
== 0)) {
4463 * tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4464 * so an extract from bit 0 is a special case.
4467 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, a
->rm
));
4469 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, a
->rm
));
4472 tcg_rm
= cpu_reg(s
, a
->rm
);
4473 tcg_rn
= cpu_reg(s
, a
->rn
);
4476 /* Specialization to ROR happens in EXTRACT2. */
4477 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, a
->imm
);
4479 TCGv_i32 t0
= tcg_temp_new_i32();
4481 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4482 if (a
->rm
== a
->rn
) {
4483 tcg_gen_rotri_i32(t0
, t0
, a
->imm
);
4485 TCGv_i32 t1
= tcg_temp_new_i32();
4486 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4487 tcg_gen_extract2_i32(t0
, t0
, t1
, a
->imm
);
4489 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4495 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4496 * Note that it is the caller's responsibility to ensure that the
4497 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4498 * mandated semantics for out of range shifts.
4500 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4501 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4503 switch (shift_type
) {
4504 case A64_SHIFT_TYPE_LSL
:
4505 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4507 case A64_SHIFT_TYPE_LSR
:
4508 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4510 case A64_SHIFT_TYPE_ASR
:
4512 tcg_gen_ext32s_i64(dst
, src
);
4514 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4516 case A64_SHIFT_TYPE_ROR
:
4518 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4521 t0
= tcg_temp_new_i32();
4522 t1
= tcg_temp_new_i32();
4523 tcg_gen_extrl_i64_i32(t0
, src
);
4524 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4525 tcg_gen_rotr_i32(t0
, t0
, t1
);
4526 tcg_gen_extu_i32_i64(dst
, t0
);
4530 assert(FALSE
); /* all shift types should be handled */
4534 if (!sf
) { /* zero extend final result */
4535 tcg_gen_ext32u_i64(dst
, dst
);
4539 /* Shift a TCGv src by immediate, put result in dst.
4540 * The shift amount must be in range (this should always be true as the
4541 * relevant instructions will UNDEF on bad shift immediates).
4543 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4544 enum a64_shift_type shift_type
, unsigned int shift_i
)
4546 assert(shift_i
< (sf
? 64 : 32));
4549 tcg_gen_mov_i64(dst
, src
);
4551 shift_reg(dst
, src
, sf
, shift_type
, tcg_constant_i64(shift_i
));
4555 /* Logical (shifted register)
4556 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4557 * +----+-----+-----------+-------+---+------+--------+------+------+
4558 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4559 * +----+-----+-----------+-------+---+------+--------+------+------+
4561 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4563 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4564 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4566 sf
= extract32(insn
, 31, 1);
4567 opc
= extract32(insn
, 29, 2);
4568 shift_type
= extract32(insn
, 22, 2);
4569 invert
= extract32(insn
, 21, 1);
4570 rm
= extract32(insn
, 16, 5);
4571 shift_amount
= extract32(insn
, 10, 6);
4572 rn
= extract32(insn
, 5, 5);
4573 rd
= extract32(insn
, 0, 5);
4575 if (!sf
&& (shift_amount
& (1 << 5))) {
4576 unallocated_encoding(s
);
4580 tcg_rd
= cpu_reg(s
, rd
);
4582 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4583 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4584 * register-register MOV and MVN, so it is worth special casing.
4586 tcg_rm
= cpu_reg(s
, rm
);
4588 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4590 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4594 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4596 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4602 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4605 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4608 tcg_rn
= cpu_reg(s
, rn
);
4610 switch (opc
| (invert
<< 2)) {
4613 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4616 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4619 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4623 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4626 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4629 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4637 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4641 gen_logic_CC(sf
, tcg_rd
);
4646 * Add/subtract (extended register)
4648 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4649 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4650 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4651 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4653 * sf: 0 -> 32bit, 1 -> 64bit
4654 * op: 0 -> add , 1 -> sub
4657 * option: extension type (see DecodeRegExtend)
4658 * imm3: optional shift to Rm
4660 * Rd = Rn + LSL(extend(Rm), amount)
4662 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4664 int rd
= extract32(insn
, 0, 5);
4665 int rn
= extract32(insn
, 5, 5);
4666 int imm3
= extract32(insn
, 10, 3);
4667 int option
= extract32(insn
, 13, 3);
4668 int rm
= extract32(insn
, 16, 5);
4669 int opt
= extract32(insn
, 22, 2);
4670 bool setflags
= extract32(insn
, 29, 1);
4671 bool sub_op
= extract32(insn
, 30, 1);
4672 bool sf
= extract32(insn
, 31, 1);
4674 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4676 TCGv_i64 tcg_result
;
4678 if (imm3
> 4 || opt
!= 0) {
4679 unallocated_encoding(s
);
4683 /* non-flag setting ops may use SP */
4685 tcg_rd
= cpu_reg_sp(s
, rd
);
4687 tcg_rd
= cpu_reg(s
, rd
);
4689 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4691 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4692 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4694 tcg_result
= tcg_temp_new_i64();
4698 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4700 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4704 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4706 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4711 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4713 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4718 * Add/subtract (shifted register)
4720 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4721 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4722 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4723 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4725 * sf: 0 -> 32bit, 1 -> 64bit
4726 * op: 0 -> add , 1 -> sub
4728 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4729 * imm6: Shift amount to apply to Rm before the add/sub
4731 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4733 int rd
= extract32(insn
, 0, 5);
4734 int rn
= extract32(insn
, 5, 5);
4735 int imm6
= extract32(insn
, 10, 6);
4736 int rm
= extract32(insn
, 16, 5);
4737 int shift_type
= extract32(insn
, 22, 2);
4738 bool setflags
= extract32(insn
, 29, 1);
4739 bool sub_op
= extract32(insn
, 30, 1);
4740 bool sf
= extract32(insn
, 31, 1);
4742 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4743 TCGv_i64 tcg_rn
, tcg_rm
;
4744 TCGv_i64 tcg_result
;
4746 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4747 unallocated_encoding(s
);
4751 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4752 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4754 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4756 tcg_result
= tcg_temp_new_i64();
4760 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4762 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4766 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4768 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4773 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4775 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4779 /* Data-processing (3 source)
4781 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4782 * +--+------+-----------+------+------+----+------+------+------+
4783 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4784 * +--+------+-----------+------+------+----+------+------+------+
4786 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4788 int rd
= extract32(insn
, 0, 5);
4789 int rn
= extract32(insn
, 5, 5);
4790 int ra
= extract32(insn
, 10, 5);
4791 int rm
= extract32(insn
, 16, 5);
4792 int op_id
= (extract32(insn
, 29, 3) << 4) |
4793 (extract32(insn
, 21, 3) << 1) |
4794 extract32(insn
, 15, 1);
4795 bool sf
= extract32(insn
, 31, 1);
4796 bool is_sub
= extract32(op_id
, 0, 1);
4797 bool is_high
= extract32(op_id
, 2, 1);
4798 bool is_signed
= false;
4803 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4805 case 0x42: /* SMADDL */
4806 case 0x43: /* SMSUBL */
4807 case 0x44: /* SMULH */
4810 case 0x0: /* MADD (32bit) */
4811 case 0x1: /* MSUB (32bit) */
4812 case 0x40: /* MADD (64bit) */
4813 case 0x41: /* MSUB (64bit) */
4814 case 0x4a: /* UMADDL */
4815 case 0x4b: /* UMSUBL */
4816 case 0x4c: /* UMULH */
4819 unallocated_encoding(s
);
4824 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4825 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4826 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4827 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4830 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4832 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4837 tcg_op1
= tcg_temp_new_i64();
4838 tcg_op2
= tcg_temp_new_i64();
4839 tcg_tmp
= tcg_temp_new_i64();
4842 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4843 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4846 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4847 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4849 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4850 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4854 if (ra
== 31 && !is_sub
) {
4855 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4856 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4858 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4860 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4862 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4867 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4871 /* Add/subtract (with carry)
4872 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4873 * +--+--+--+------------------------+------+-------------+------+-----+
4874 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4875 * +--+--+--+------------------------+------+-------------+------+-----+
4878 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4880 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4881 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4883 sf
= extract32(insn
, 31, 1);
4884 op
= extract32(insn
, 30, 1);
4885 setflags
= extract32(insn
, 29, 1);
4886 rm
= extract32(insn
, 16, 5);
4887 rn
= extract32(insn
, 5, 5);
4888 rd
= extract32(insn
, 0, 5);
4890 tcg_rd
= cpu_reg(s
, rd
);
4891 tcg_rn
= cpu_reg(s
, rn
);
4894 tcg_y
= tcg_temp_new_i64();
4895 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4897 tcg_y
= cpu_reg(s
, rm
);
4901 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4903 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4908 * Rotate right into flags
4909 * 31 30 29 21 15 10 5 4 0
4910 * +--+--+--+-----------------+--------+-----------+------+--+------+
4911 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4912 * +--+--+--+-----------------+--------+-----------+------+--+------+
4914 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4916 int mask
= extract32(insn
, 0, 4);
4917 int o2
= extract32(insn
, 4, 1);
4918 int rn
= extract32(insn
, 5, 5);
4919 int imm6
= extract32(insn
, 15, 6);
4920 int sf_op_s
= extract32(insn
, 29, 3);
4924 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4925 unallocated_encoding(s
);
4929 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4930 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4932 nzcv
= tcg_temp_new_i32();
4933 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4935 if (mask
& 8) { /* N */
4936 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4938 if (mask
& 4) { /* Z */
4939 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4940 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4942 if (mask
& 2) { /* C */
4943 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4945 if (mask
& 1) { /* V */
4946 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4951 * Evaluate into flags
4952 * 31 30 29 21 15 14 10 5 4 0
4953 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4954 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4955 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4957 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4959 int o3_mask
= extract32(insn
, 0, 5);
4960 int rn
= extract32(insn
, 5, 5);
4961 int o2
= extract32(insn
, 15, 6);
4962 int sz
= extract32(insn
, 14, 1);
4963 int sf_op_s
= extract32(insn
, 29, 3);
4967 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4968 !dc_isar_feature(aa64_condm_4
, s
)) {
4969 unallocated_encoding(s
);
4972 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4974 tmp
= tcg_temp_new_i32();
4975 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4976 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4977 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4978 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4979 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4982 /* Conditional compare (immediate / register)
4983 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4984 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4985 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4986 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4989 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4991 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4992 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4993 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4996 if (!extract32(insn
, 29, 1)) {
4997 unallocated_encoding(s
);
5000 if (insn
& (1 << 10 | 1 << 4)) {
5001 unallocated_encoding(s
);
5004 sf
= extract32(insn
, 31, 1);
5005 op
= extract32(insn
, 30, 1);
5006 is_imm
= extract32(insn
, 11, 1);
5007 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5008 cond
= extract32(insn
, 12, 4);
5009 rn
= extract32(insn
, 5, 5);
5010 nzcv
= extract32(insn
, 0, 4);
5012 /* Set T0 = !COND. */
5013 tcg_t0
= tcg_temp_new_i32();
5014 arm_test_cc(&c
, cond
);
5015 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5017 /* Load the arguments for the new comparison. */
5019 tcg_y
= tcg_temp_new_i64();
5020 tcg_gen_movi_i64(tcg_y
, y
);
5022 tcg_y
= cpu_reg(s
, y
);
5024 tcg_rn
= cpu_reg(s
, rn
);
5026 /* Set the flags for the new comparison. */
5027 tcg_tmp
= tcg_temp_new_i64();
5029 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5031 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5034 /* If COND was false, force the flags to #nzcv. Compute two masks
5035 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5036 * For tcg hosts that support ANDC, we can make do with just T1.
5037 * In either case, allow the tcg optimizer to delete any unused mask.
5039 tcg_t1
= tcg_temp_new_i32();
5040 tcg_t2
= tcg_temp_new_i32();
5041 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5042 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5044 if (nzcv
& 8) { /* N */
5045 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5047 if (TCG_TARGET_HAS_andc_i32
) {
5048 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5050 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5053 if (nzcv
& 4) { /* Z */
5054 if (TCG_TARGET_HAS_andc_i32
) {
5055 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5057 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5060 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5062 if (nzcv
& 2) { /* C */
5063 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5065 if (TCG_TARGET_HAS_andc_i32
) {
5066 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5068 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5071 if (nzcv
& 1) { /* V */
5072 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5074 if (TCG_TARGET_HAS_andc_i32
) {
5075 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5077 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5082 /* Conditional select
5083 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5084 * +----+----+---+-----------------+------+------+-----+------+------+
5085 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5086 * +----+----+---+-----------------+------+------+-----+------+------+
5088 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5090 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5091 TCGv_i64 tcg_rd
, zero
;
5094 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5095 /* S == 1 or op2<1> == 1 */
5096 unallocated_encoding(s
);
5099 sf
= extract32(insn
, 31, 1);
5100 else_inv
= extract32(insn
, 30, 1);
5101 rm
= extract32(insn
, 16, 5);
5102 cond
= extract32(insn
, 12, 4);
5103 else_inc
= extract32(insn
, 10, 1);
5104 rn
= extract32(insn
, 5, 5);
5105 rd
= extract32(insn
, 0, 5);
5107 tcg_rd
= cpu_reg(s
, rd
);
5109 a64_test_cc(&c
, cond
);
5110 zero
= tcg_constant_i64(0);
5112 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5114 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5116 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5119 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5120 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5121 if (else_inv
&& else_inc
) {
5122 tcg_gen_neg_i64(t_false
, t_false
);
5123 } else if (else_inv
) {
5124 tcg_gen_not_i64(t_false
, t_false
);
5125 } else if (else_inc
) {
5126 tcg_gen_addi_i64(t_false
, t_false
, 1);
5128 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5132 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5136 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5137 unsigned int rn
, unsigned int rd
)
5139 TCGv_i64 tcg_rd
, tcg_rn
;
5140 tcg_rd
= cpu_reg(s
, rd
);
5141 tcg_rn
= cpu_reg(s
, rn
);
5144 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5146 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5147 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5148 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5149 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5153 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5154 unsigned int rn
, unsigned int rd
)
5156 TCGv_i64 tcg_rd
, tcg_rn
;
5157 tcg_rd
= cpu_reg(s
, rd
);
5158 tcg_rn
= cpu_reg(s
, rn
);
5161 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5163 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5164 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5165 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5166 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5170 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5171 unsigned int rn
, unsigned int rd
)
5173 TCGv_i64 tcg_rd
, tcg_rn
;
5174 tcg_rd
= cpu_reg(s
, rd
);
5175 tcg_rn
= cpu_reg(s
, rn
);
5178 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5180 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5181 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5182 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5183 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5187 /* REV with sf==1, opcode==3 ("REV64") */
5188 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5189 unsigned int rn
, unsigned int rd
)
5192 unallocated_encoding(s
);
5195 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5198 /* REV with sf==0, opcode==2
5199 * REV32 (sf==1, opcode==2)
5201 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5202 unsigned int rn
, unsigned int rd
)
5204 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5205 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5208 tcg_gen_bswap64_i64(tcg_rd
, tcg_rn
);
5209 tcg_gen_rotri_i64(tcg_rd
, tcg_rd
, 32);
5211 tcg_gen_bswap32_i64(tcg_rd
, tcg_rn
, TCG_BSWAP_OZ
);
5215 /* REV16 (opcode==1) */
5216 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5217 unsigned int rn
, unsigned int rd
)
5219 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5220 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5221 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5222 TCGv_i64 mask
= tcg_constant_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5224 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5225 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5226 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5227 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5228 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5231 /* Data-processing (1 source)
5232 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5233 * +----+---+---+-----------------+---------+--------+------+------+
5234 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5235 * +----+---+---+-----------------+---------+--------+------+------+
5237 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5239 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5242 if (extract32(insn
, 29, 1)) {
5243 unallocated_encoding(s
);
5247 sf
= extract32(insn
, 31, 1);
5248 opcode
= extract32(insn
, 10, 6);
5249 opcode2
= extract32(insn
, 16, 5);
5250 rn
= extract32(insn
, 5, 5);
5251 rd
= extract32(insn
, 0, 5);
5253 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5255 switch (MAP(sf
, opcode2
, opcode
)) {
5256 case MAP(0, 0x00, 0x00): /* RBIT */
5257 case MAP(1, 0x00, 0x00):
5258 handle_rbit(s
, sf
, rn
, rd
);
5260 case MAP(0, 0x00, 0x01): /* REV16 */
5261 case MAP(1, 0x00, 0x01):
5262 handle_rev16(s
, sf
, rn
, rd
);
5264 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5265 case MAP(1, 0x00, 0x02):
5266 handle_rev32(s
, sf
, rn
, rd
);
5268 case MAP(1, 0x00, 0x03): /* REV64 */
5269 handle_rev64(s
, sf
, rn
, rd
);
5271 case MAP(0, 0x00, 0x04): /* CLZ */
5272 case MAP(1, 0x00, 0x04):
5273 handle_clz(s
, sf
, rn
, rd
);
5275 case MAP(0, 0x00, 0x05): /* CLS */
5276 case MAP(1, 0x00, 0x05):
5277 handle_cls(s
, sf
, rn
, rd
);
5279 case MAP(1, 0x01, 0x00): /* PACIA */
5280 if (s
->pauth_active
) {
5281 tcg_rd
= cpu_reg(s
, rd
);
5282 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5283 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5284 goto do_unallocated
;
5287 case MAP(1, 0x01, 0x01): /* PACIB */
5288 if (s
->pauth_active
) {
5289 tcg_rd
= cpu_reg(s
, rd
);
5290 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5291 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5292 goto do_unallocated
;
5295 case MAP(1, 0x01, 0x02): /* PACDA */
5296 if (s
->pauth_active
) {
5297 tcg_rd
= cpu_reg(s
, rd
);
5298 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5299 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5300 goto do_unallocated
;
5303 case MAP(1, 0x01, 0x03): /* PACDB */
5304 if (s
->pauth_active
) {
5305 tcg_rd
= cpu_reg(s
, rd
);
5306 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5307 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5308 goto do_unallocated
;
5311 case MAP(1, 0x01, 0x04): /* AUTIA */
5312 if (s
->pauth_active
) {
5313 tcg_rd
= cpu_reg(s
, rd
);
5314 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5315 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5316 goto do_unallocated
;
5319 case MAP(1, 0x01, 0x05): /* AUTIB */
5320 if (s
->pauth_active
) {
5321 tcg_rd
= cpu_reg(s
, rd
);
5322 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5323 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5324 goto do_unallocated
;
5327 case MAP(1, 0x01, 0x06): /* AUTDA */
5328 if (s
->pauth_active
) {
5329 tcg_rd
= cpu_reg(s
, rd
);
5330 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5331 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5332 goto do_unallocated
;
5335 case MAP(1, 0x01, 0x07): /* AUTDB */
5336 if (s
->pauth_active
) {
5337 tcg_rd
= cpu_reg(s
, rd
);
5338 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5339 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5340 goto do_unallocated
;
5343 case MAP(1, 0x01, 0x08): /* PACIZA */
5344 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5345 goto do_unallocated
;
5346 } else if (s
->pauth_active
) {
5347 tcg_rd
= cpu_reg(s
, rd
);
5348 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5351 case MAP(1, 0x01, 0x09): /* PACIZB */
5352 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5353 goto do_unallocated
;
5354 } else if (s
->pauth_active
) {
5355 tcg_rd
= cpu_reg(s
, rd
);
5356 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5359 case MAP(1, 0x01, 0x0a): /* PACDZA */
5360 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5361 goto do_unallocated
;
5362 } else if (s
->pauth_active
) {
5363 tcg_rd
= cpu_reg(s
, rd
);
5364 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5367 case MAP(1, 0x01, 0x0b): /* PACDZB */
5368 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5369 goto do_unallocated
;
5370 } else if (s
->pauth_active
) {
5371 tcg_rd
= cpu_reg(s
, rd
);
5372 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5375 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5376 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5377 goto do_unallocated
;
5378 } else if (s
->pauth_active
) {
5379 tcg_rd
= cpu_reg(s
, rd
);
5380 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5383 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5384 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5385 goto do_unallocated
;
5386 } else if (s
->pauth_active
) {
5387 tcg_rd
= cpu_reg(s
, rd
);
5388 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5391 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5392 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5393 goto do_unallocated
;
5394 } else if (s
->pauth_active
) {
5395 tcg_rd
= cpu_reg(s
, rd
);
5396 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5399 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5400 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5401 goto do_unallocated
;
5402 } else if (s
->pauth_active
) {
5403 tcg_rd
= cpu_reg(s
, rd
);
5404 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, tcg_constant_i64(0));
5407 case MAP(1, 0x01, 0x10): /* XPACI */
5408 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5409 goto do_unallocated
;
5410 } else if (s
->pauth_active
) {
5411 tcg_rd
= cpu_reg(s
, rd
);
5412 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5415 case MAP(1, 0x01, 0x11): /* XPACD */
5416 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5417 goto do_unallocated
;
5418 } else if (s
->pauth_active
) {
5419 tcg_rd
= cpu_reg(s
, rd
);
5420 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5425 unallocated_encoding(s
);
5432 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5433 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5435 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5436 tcg_rd
= cpu_reg(s
, rd
);
5438 if (!sf
&& is_signed
) {
5439 tcg_n
= tcg_temp_new_i64();
5440 tcg_m
= tcg_temp_new_i64();
5441 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5442 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5444 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5445 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5449 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5451 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5454 if (!sf
) { /* zero extend final result */
5455 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5459 /* LSLV, LSRV, ASRV, RORV */
5460 static void handle_shift_reg(DisasContext
*s
,
5461 enum a64_shift_type shift_type
, unsigned int sf
,
5462 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5464 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5465 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5466 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5468 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5469 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5472 /* CRC32[BHWX], CRC32C[BHWX] */
5473 static void handle_crc32(DisasContext
*s
,
5474 unsigned int sf
, unsigned int sz
, bool crc32c
,
5475 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5477 TCGv_i64 tcg_acc
, tcg_val
;
5480 if (!dc_isar_feature(aa64_crc32
, s
)
5481 || (sf
== 1 && sz
!= 3)
5482 || (sf
== 0 && sz
== 3)) {
5483 unallocated_encoding(s
);
5488 tcg_val
= cpu_reg(s
, rm
);
5502 g_assert_not_reached();
5504 tcg_val
= tcg_temp_new_i64();
5505 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5508 tcg_acc
= cpu_reg(s
, rn
);
5509 tcg_bytes
= tcg_constant_i32(1 << sz
);
5512 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5514 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5518 /* Data-processing (2 source)
5519 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5520 * +----+---+---+-----------------+------+--------+------+------+
5521 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5522 * +----+---+---+-----------------+------+--------+------+------+
5524 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5526 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5527 sf
= extract32(insn
, 31, 1);
5528 setflag
= extract32(insn
, 29, 1);
5529 rm
= extract32(insn
, 16, 5);
5530 opcode
= extract32(insn
, 10, 6);
5531 rn
= extract32(insn
, 5, 5);
5532 rd
= extract32(insn
, 0, 5);
5534 if (setflag
&& opcode
!= 0) {
5535 unallocated_encoding(s
);
5540 case 0: /* SUBP(S) */
5541 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5542 goto do_unallocated
;
5544 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5546 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5547 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5548 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5549 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5550 tcg_d
= cpu_reg(s
, rd
);
5553 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5555 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5560 handle_div(s
, false, sf
, rm
, rn
, rd
);
5563 handle_div(s
, true, sf
, rm
, rn
, rd
);
5566 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5567 goto do_unallocated
;
5570 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5571 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5573 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5578 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5579 goto do_unallocated
;
5581 TCGv_i64 t
= tcg_temp_new_i64();
5583 tcg_gen_extract_i64(t
, cpu_reg_sp(s
, rn
), 56, 4);
5584 tcg_gen_shl_i64(t
, tcg_constant_i64(1), t
);
5585 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t
);
5589 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5592 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5595 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5598 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5600 case 12: /* PACGA */
5601 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5602 goto do_unallocated
;
5604 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5605 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5614 case 23: /* CRC32 */
5616 int sz
= extract32(opcode
, 0, 2);
5617 bool crc32c
= extract32(opcode
, 2, 1);
5618 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5623 unallocated_encoding(s
);
5629 * Data processing - register
5630 * 31 30 29 28 25 21 20 16 10 0
5631 * +--+---+--+---+-------+-----+-------+-------+---------+
5632 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5633 * +--+---+--+---+-------+-----+-------+-------+---------+
5635 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5637 int op0
= extract32(insn
, 30, 1);
5638 int op1
= extract32(insn
, 28, 1);
5639 int op2
= extract32(insn
, 21, 4);
5640 int op3
= extract32(insn
, 10, 6);
5645 /* Add/sub (extended register) */
5646 disas_add_sub_ext_reg(s
, insn
);
5648 /* Add/sub (shifted register) */
5649 disas_add_sub_reg(s
, insn
);
5652 /* Logical (shifted register) */
5653 disas_logic_reg(s
, insn
);
5661 case 0x00: /* Add/subtract (with carry) */
5662 disas_adc_sbc(s
, insn
);
5665 case 0x01: /* Rotate right into flags */
5667 disas_rotate_right_into_flags(s
, insn
);
5670 case 0x02: /* Evaluate into flags */
5674 disas_evaluate_into_flags(s
, insn
);
5678 goto do_unallocated
;
5682 case 0x2: /* Conditional compare */
5683 disas_cc(s
, insn
); /* both imm and reg forms */
5686 case 0x4: /* Conditional select */
5687 disas_cond_select(s
, insn
);
5690 case 0x6: /* Data-processing */
5691 if (op0
) { /* (1 source) */
5692 disas_data_proc_1src(s
, insn
);
5693 } else { /* (2 source) */
5694 disas_data_proc_2src(s
, insn
);
5697 case 0x8 ... 0xf: /* (3 source) */
5698 disas_data_proc_3src(s
, insn
);
5703 unallocated_encoding(s
);
5708 static void handle_fp_compare(DisasContext
*s
, int size
,
5709 unsigned int rn
, unsigned int rm
,
5710 bool cmp_with_zero
, bool signal_all_nans
)
5712 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5713 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5715 if (size
== MO_64
) {
5716 TCGv_i64 tcg_vn
, tcg_vm
;
5718 tcg_vn
= read_fp_dreg(s
, rn
);
5719 if (cmp_with_zero
) {
5720 tcg_vm
= tcg_constant_i64(0);
5722 tcg_vm
= read_fp_dreg(s
, rm
);
5724 if (signal_all_nans
) {
5725 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5727 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5730 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5731 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5733 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5734 if (cmp_with_zero
) {
5735 tcg_gen_movi_i32(tcg_vm
, 0);
5737 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5742 if (signal_all_nans
) {
5743 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5745 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5749 if (signal_all_nans
) {
5750 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5752 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5756 g_assert_not_reached();
5760 gen_set_nzcv(tcg_flags
);
5763 /* Floating point compare
5764 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5765 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5766 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5767 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5769 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5771 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5774 mos
= extract32(insn
, 29, 3);
5775 type
= extract32(insn
, 22, 2);
5776 rm
= extract32(insn
, 16, 5);
5777 op
= extract32(insn
, 14, 2);
5778 rn
= extract32(insn
, 5, 5);
5779 opc
= extract32(insn
, 3, 2);
5780 op2r
= extract32(insn
, 0, 3);
5782 if (mos
|| op
|| op2r
) {
5783 unallocated_encoding(s
);
5796 if (dc_isar_feature(aa64_fp16
, s
)) {
5801 unallocated_encoding(s
);
5805 if (!fp_access_check(s
)) {
5809 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5812 /* Floating point conditional compare
5813 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5814 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5815 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5816 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5818 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5820 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5821 TCGLabel
*label_continue
= NULL
;
5824 mos
= extract32(insn
, 29, 3);
5825 type
= extract32(insn
, 22, 2);
5826 rm
= extract32(insn
, 16, 5);
5827 cond
= extract32(insn
, 12, 4);
5828 rn
= extract32(insn
, 5, 5);
5829 op
= extract32(insn
, 4, 1);
5830 nzcv
= extract32(insn
, 0, 4);
5833 unallocated_encoding(s
);
5846 if (dc_isar_feature(aa64_fp16
, s
)) {
5851 unallocated_encoding(s
);
5855 if (!fp_access_check(s
)) {
5859 if (cond
< 0x0e) { /* not always */
5860 TCGLabel
*label_match
= gen_new_label();
5861 label_continue
= gen_new_label();
5862 arm_gen_test_cc(cond
, label_match
);
5864 gen_set_nzcv(tcg_constant_i64(nzcv
<< 28));
5865 tcg_gen_br(label_continue
);
5866 gen_set_label(label_match
);
5869 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5872 gen_set_label(label_continue
);
5876 /* Floating point conditional select
5877 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5878 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5879 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5880 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5882 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5884 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5885 TCGv_i64 t_true
, t_false
;
5889 mos
= extract32(insn
, 29, 3);
5890 type
= extract32(insn
, 22, 2);
5891 rm
= extract32(insn
, 16, 5);
5892 cond
= extract32(insn
, 12, 4);
5893 rn
= extract32(insn
, 5, 5);
5894 rd
= extract32(insn
, 0, 5);
5897 unallocated_encoding(s
);
5910 if (dc_isar_feature(aa64_fp16
, s
)) {
5915 unallocated_encoding(s
);
5919 if (!fp_access_check(s
)) {
5923 /* Zero extend sreg & hreg inputs to 64 bits now. */
5924 t_true
= tcg_temp_new_i64();
5925 t_false
= tcg_temp_new_i64();
5926 read_vec_element(s
, t_true
, rn
, 0, sz
);
5927 read_vec_element(s
, t_false
, rm
, 0, sz
);
5929 a64_test_cc(&c
, cond
);
5930 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, tcg_constant_i64(0),
5933 /* Note that sregs & hregs write back zeros to the high bits,
5934 and we've already done the zero-extension. */
5935 write_fp_dreg(s
, rd
, t_true
);
5938 /* Floating-point data-processing (1 source) - half precision */
5939 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5941 TCGv_ptr fpst
= NULL
;
5942 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5943 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5946 case 0x0: /* FMOV */
5947 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5949 case 0x1: /* FABS */
5950 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5952 case 0x2: /* FNEG */
5953 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5955 case 0x3: /* FSQRT */
5956 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
5957 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5959 case 0x8: /* FRINTN */
5960 case 0x9: /* FRINTP */
5961 case 0xa: /* FRINTM */
5962 case 0xb: /* FRINTZ */
5963 case 0xc: /* FRINTA */
5967 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
5968 tcg_rmode
= gen_set_rmode(opcode
& 7, fpst
);
5969 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5970 gen_restore_rmode(tcg_rmode
, fpst
);
5973 case 0xe: /* FRINTX */
5974 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
5975 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5977 case 0xf: /* FRINTI */
5978 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
5979 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5982 g_assert_not_reached();
5985 write_fp_sreg(s
, rd
, tcg_res
);
5988 /* Floating-point data-processing (1 source) - single precision */
5989 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5991 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5992 TCGv_i32 tcg_op
, tcg_res
;
5996 tcg_op
= read_fp_sreg(s
, rn
);
5997 tcg_res
= tcg_temp_new_i32();
6000 case 0x0: /* FMOV */
6001 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6003 case 0x1: /* FABS */
6004 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6006 case 0x2: /* FNEG */
6007 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6009 case 0x3: /* FSQRT */
6010 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6012 case 0x6: /* BFCVT */
6013 gen_fpst
= gen_helper_bfcvt
;
6015 case 0x8: /* FRINTN */
6016 case 0x9: /* FRINTP */
6017 case 0xa: /* FRINTM */
6018 case 0xb: /* FRINTZ */
6019 case 0xc: /* FRINTA */
6021 gen_fpst
= gen_helper_rints
;
6023 case 0xe: /* FRINTX */
6024 gen_fpst
= gen_helper_rints_exact
;
6026 case 0xf: /* FRINTI */
6027 gen_fpst
= gen_helper_rints
;
6029 case 0x10: /* FRINT32Z */
6030 rmode
= FPROUNDING_ZERO
;
6031 gen_fpst
= gen_helper_frint32_s
;
6033 case 0x11: /* FRINT32X */
6034 gen_fpst
= gen_helper_frint32_s
;
6036 case 0x12: /* FRINT64Z */
6037 rmode
= FPROUNDING_ZERO
;
6038 gen_fpst
= gen_helper_frint64_s
;
6040 case 0x13: /* FRINT64X */
6041 gen_fpst
= gen_helper_frint64_s
;
6044 g_assert_not_reached();
6047 fpst
= fpstatus_ptr(FPST_FPCR
);
6049 TCGv_i32 tcg_rmode
= gen_set_rmode(rmode
, fpst
);
6050 gen_fpst(tcg_res
, tcg_op
, fpst
);
6051 gen_restore_rmode(tcg_rmode
, fpst
);
6053 gen_fpst(tcg_res
, tcg_op
, fpst
);
6057 write_fp_sreg(s
, rd
, tcg_res
);
6060 /* Floating-point data-processing (1 source) - double precision */
6061 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6063 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6064 TCGv_i64 tcg_op
, tcg_res
;
6069 case 0x0: /* FMOV */
6070 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6074 tcg_op
= read_fp_dreg(s
, rn
);
6075 tcg_res
= tcg_temp_new_i64();
6078 case 0x1: /* FABS */
6079 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6081 case 0x2: /* FNEG */
6082 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6084 case 0x3: /* FSQRT */
6085 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6087 case 0x8: /* FRINTN */
6088 case 0x9: /* FRINTP */
6089 case 0xa: /* FRINTM */
6090 case 0xb: /* FRINTZ */
6091 case 0xc: /* FRINTA */
6093 gen_fpst
= gen_helper_rintd
;
6095 case 0xe: /* FRINTX */
6096 gen_fpst
= gen_helper_rintd_exact
;
6098 case 0xf: /* FRINTI */
6099 gen_fpst
= gen_helper_rintd
;
6101 case 0x10: /* FRINT32Z */
6102 rmode
= FPROUNDING_ZERO
;
6103 gen_fpst
= gen_helper_frint32_d
;
6105 case 0x11: /* FRINT32X */
6106 gen_fpst
= gen_helper_frint32_d
;
6108 case 0x12: /* FRINT64Z */
6109 rmode
= FPROUNDING_ZERO
;
6110 gen_fpst
= gen_helper_frint64_d
;
6112 case 0x13: /* FRINT64X */
6113 gen_fpst
= gen_helper_frint64_d
;
6116 g_assert_not_reached();
6119 fpst
= fpstatus_ptr(FPST_FPCR
);
6121 TCGv_i32 tcg_rmode
= gen_set_rmode(rmode
, fpst
);
6122 gen_fpst(tcg_res
, tcg_op
, fpst
);
6123 gen_restore_rmode(tcg_rmode
, fpst
);
6125 gen_fpst(tcg_res
, tcg_op
, fpst
);
6129 write_fp_dreg(s
, rd
, tcg_res
);
6132 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6133 int rd
, int rn
, int dtype
, int ntype
)
6138 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6140 /* Single to double */
6141 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6142 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6143 write_fp_dreg(s
, rd
, tcg_rd
);
6145 /* Single to half */
6146 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6147 TCGv_i32 ahp
= get_ahp_flag();
6148 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6150 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6151 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6152 write_fp_sreg(s
, rd
, tcg_rd
);
6158 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6159 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6161 /* Double to single */
6162 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6164 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6165 TCGv_i32 ahp
= get_ahp_flag();
6166 /* Double to half */
6167 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6168 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6170 write_fp_sreg(s
, rd
, tcg_rd
);
6175 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6176 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6177 TCGv_i32 tcg_ahp
= get_ahp_flag();
6178 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6180 /* Half to single */
6181 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6182 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6183 write_fp_sreg(s
, rd
, tcg_rd
);
6185 /* Half to double */
6186 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6187 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6188 write_fp_dreg(s
, rd
, tcg_rd
);
6193 g_assert_not_reached();
6197 /* Floating point data-processing (1 source)
6198 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6199 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6200 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6201 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6203 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6205 int mos
= extract32(insn
, 29, 3);
6206 int type
= extract32(insn
, 22, 2);
6207 int opcode
= extract32(insn
, 15, 6);
6208 int rn
= extract32(insn
, 5, 5);
6209 int rd
= extract32(insn
, 0, 5);
6212 goto do_unallocated
;
6216 case 0x4: case 0x5: case 0x7:
6218 /* FCVT between half, single and double precision */
6219 int dtype
= extract32(opcode
, 0, 2);
6220 if (type
== 2 || dtype
== type
) {
6221 goto do_unallocated
;
6223 if (!fp_access_check(s
)) {
6227 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6231 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6232 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6233 goto do_unallocated
;
6239 /* 32-to-32 and 64-to-64 ops */
6242 if (!fp_access_check(s
)) {
6245 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6248 if (!fp_access_check(s
)) {
6251 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6254 if (!dc_isar_feature(aa64_fp16
, s
)) {
6255 goto do_unallocated
;
6258 if (!fp_access_check(s
)) {
6261 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6264 goto do_unallocated
;
6271 if (!dc_isar_feature(aa64_bf16
, s
)) {
6272 goto do_unallocated
;
6274 if (!fp_access_check(s
)) {
6277 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6280 goto do_unallocated
;
6286 unallocated_encoding(s
);
6291 /* Floating-point data-processing (2 source) - single precision */
6292 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6293 int rd
, int rn
, int rm
)
6300 tcg_res
= tcg_temp_new_i32();
6301 fpst
= fpstatus_ptr(FPST_FPCR
);
6302 tcg_op1
= read_fp_sreg(s
, rn
);
6303 tcg_op2
= read_fp_sreg(s
, rm
);
6306 case 0x0: /* FMUL */
6307 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6309 case 0x1: /* FDIV */
6310 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6312 case 0x2: /* FADD */
6313 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6315 case 0x3: /* FSUB */
6316 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6318 case 0x4: /* FMAX */
6319 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6321 case 0x5: /* FMIN */
6322 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6324 case 0x6: /* FMAXNM */
6325 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6327 case 0x7: /* FMINNM */
6328 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6330 case 0x8: /* FNMUL */
6331 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6332 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6336 write_fp_sreg(s
, rd
, tcg_res
);
6339 /* Floating-point data-processing (2 source) - double precision */
6340 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6341 int rd
, int rn
, int rm
)
6348 tcg_res
= tcg_temp_new_i64();
6349 fpst
= fpstatus_ptr(FPST_FPCR
);
6350 tcg_op1
= read_fp_dreg(s
, rn
);
6351 tcg_op2
= read_fp_dreg(s
, rm
);
6354 case 0x0: /* FMUL */
6355 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6357 case 0x1: /* FDIV */
6358 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6360 case 0x2: /* FADD */
6361 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6363 case 0x3: /* FSUB */
6364 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6366 case 0x4: /* FMAX */
6367 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6369 case 0x5: /* FMIN */
6370 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6372 case 0x6: /* FMAXNM */
6373 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6375 case 0x7: /* FMINNM */
6376 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6378 case 0x8: /* FNMUL */
6379 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6380 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6384 write_fp_dreg(s
, rd
, tcg_res
);
6387 /* Floating-point data-processing (2 source) - half precision */
6388 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6389 int rd
, int rn
, int rm
)
6396 tcg_res
= tcg_temp_new_i32();
6397 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6398 tcg_op1
= read_fp_hreg(s
, rn
);
6399 tcg_op2
= read_fp_hreg(s
, rm
);
6402 case 0x0: /* FMUL */
6403 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6405 case 0x1: /* FDIV */
6406 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6408 case 0x2: /* FADD */
6409 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6411 case 0x3: /* FSUB */
6412 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6414 case 0x4: /* FMAX */
6415 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6417 case 0x5: /* FMIN */
6418 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6420 case 0x6: /* FMAXNM */
6421 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6423 case 0x7: /* FMINNM */
6424 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6426 case 0x8: /* FNMUL */
6427 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6428 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6431 g_assert_not_reached();
6434 write_fp_sreg(s
, rd
, tcg_res
);
6437 /* Floating point data-processing (2 source)
6438 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6439 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6440 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6441 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6443 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6445 int mos
= extract32(insn
, 29, 3);
6446 int type
= extract32(insn
, 22, 2);
6447 int rd
= extract32(insn
, 0, 5);
6448 int rn
= extract32(insn
, 5, 5);
6449 int rm
= extract32(insn
, 16, 5);
6450 int opcode
= extract32(insn
, 12, 4);
6452 if (opcode
> 8 || mos
) {
6453 unallocated_encoding(s
);
6459 if (!fp_access_check(s
)) {
6462 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6465 if (!fp_access_check(s
)) {
6468 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6471 if (!dc_isar_feature(aa64_fp16
, s
)) {
6472 unallocated_encoding(s
);
6475 if (!fp_access_check(s
)) {
6478 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6481 unallocated_encoding(s
);
6485 /* Floating-point data-processing (3 source) - single precision */
6486 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6487 int rd
, int rn
, int rm
, int ra
)
6489 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6490 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6491 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6493 tcg_op1
= read_fp_sreg(s
, rn
);
6494 tcg_op2
= read_fp_sreg(s
, rm
);
6495 tcg_op3
= read_fp_sreg(s
, ra
);
6497 /* These are fused multiply-add, and must be done as one
6498 * floating point operation with no rounding between the
6499 * multiplication and addition steps.
6500 * NB that doing the negations here as separate steps is
6501 * correct : an input NaN should come out with its sign bit
6502 * flipped if it is a negated-input.
6505 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6509 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6512 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6514 write_fp_sreg(s
, rd
, tcg_res
);
6517 /* Floating-point data-processing (3 source) - double precision */
6518 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6519 int rd
, int rn
, int rm
, int ra
)
6521 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6522 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6523 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6525 tcg_op1
= read_fp_dreg(s
, rn
);
6526 tcg_op2
= read_fp_dreg(s
, rm
);
6527 tcg_op3
= read_fp_dreg(s
, ra
);
6529 /* These are fused multiply-add, and must be done as one
6530 * floating point operation with no rounding between the
6531 * multiplication and addition steps.
6532 * NB that doing the negations here as separate steps is
6533 * correct : an input NaN should come out with its sign bit
6534 * flipped if it is a negated-input.
6537 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6541 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6544 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6546 write_fp_dreg(s
, rd
, tcg_res
);
6549 /* Floating-point data-processing (3 source) - half precision */
6550 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6551 int rd
, int rn
, int rm
, int ra
)
6553 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6554 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6555 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6557 tcg_op1
= read_fp_hreg(s
, rn
);
6558 tcg_op2
= read_fp_hreg(s
, rm
);
6559 tcg_op3
= read_fp_hreg(s
, ra
);
6561 /* These are fused multiply-add, and must be done as one
6562 * floating point operation with no rounding between the
6563 * multiplication and addition steps.
6564 * NB that doing the negations here as separate steps is
6565 * correct : an input NaN should come out with its sign bit
6566 * flipped if it is a negated-input.
6569 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6573 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6576 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6578 write_fp_sreg(s
, rd
, tcg_res
);
6581 /* Floating point data-processing (3 source)
6582 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6583 * +---+---+---+-----------+------+----+------+----+------+------+------+
6584 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6585 * +---+---+---+-----------+------+----+------+----+------+------+------+
6587 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6589 int mos
= extract32(insn
, 29, 3);
6590 int type
= extract32(insn
, 22, 2);
6591 int rd
= extract32(insn
, 0, 5);
6592 int rn
= extract32(insn
, 5, 5);
6593 int ra
= extract32(insn
, 10, 5);
6594 int rm
= extract32(insn
, 16, 5);
6595 bool o0
= extract32(insn
, 15, 1);
6596 bool o1
= extract32(insn
, 21, 1);
6599 unallocated_encoding(s
);
6605 if (!fp_access_check(s
)) {
6608 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6611 if (!fp_access_check(s
)) {
6614 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6617 if (!dc_isar_feature(aa64_fp16
, s
)) {
6618 unallocated_encoding(s
);
6621 if (!fp_access_check(s
)) {
6624 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6627 unallocated_encoding(s
);
6631 /* Floating point immediate
6632 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6633 * +---+---+---+-----------+------+---+------------+-------+------+------+
6634 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6635 * +---+---+---+-----------+------+---+------------+-------+------+------+
6637 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6639 int rd
= extract32(insn
, 0, 5);
6640 int imm5
= extract32(insn
, 5, 5);
6641 int imm8
= extract32(insn
, 13, 8);
6642 int type
= extract32(insn
, 22, 2);
6643 int mos
= extract32(insn
, 29, 3);
6648 unallocated_encoding(s
);
6661 if (dc_isar_feature(aa64_fp16
, s
)) {
6666 unallocated_encoding(s
);
6670 if (!fp_access_check(s
)) {
6674 imm
= vfp_expand_imm(sz
, imm8
);
6675 write_fp_dreg(s
, rd
, tcg_constant_i64(imm
));
6678 /* Handle floating point <=> fixed point conversions. Note that we can
6679 * also deal with fp <=> integer conversions as a special case (scale == 64)
6680 * OPTME: consider handling that special case specially or at least skipping
6681 * the call to scalbn in the helpers for zero shifts.
6683 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6684 bool itof
, int rmode
, int scale
, int sf
, int type
)
6686 bool is_signed
= !(opcode
& 1);
6687 TCGv_ptr tcg_fpstatus
;
6688 TCGv_i32 tcg_shift
, tcg_single
;
6689 TCGv_i64 tcg_double
;
6691 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
6693 tcg_shift
= tcg_constant_i32(64 - scale
);
6696 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6698 TCGv_i64 tcg_extend
= tcg_temp_new_i64();
6701 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6703 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6706 tcg_int
= tcg_extend
;
6710 case 1: /* float64 */
6711 tcg_double
= tcg_temp_new_i64();
6713 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6714 tcg_shift
, tcg_fpstatus
);
6716 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6717 tcg_shift
, tcg_fpstatus
);
6719 write_fp_dreg(s
, rd
, tcg_double
);
6722 case 0: /* float32 */
6723 tcg_single
= tcg_temp_new_i32();
6725 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6726 tcg_shift
, tcg_fpstatus
);
6728 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6729 tcg_shift
, tcg_fpstatus
);
6731 write_fp_sreg(s
, rd
, tcg_single
);
6734 case 3: /* float16 */
6735 tcg_single
= tcg_temp_new_i32();
6737 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6738 tcg_shift
, tcg_fpstatus
);
6740 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6741 tcg_shift
, tcg_fpstatus
);
6743 write_fp_sreg(s
, rd
, tcg_single
);
6747 g_assert_not_reached();
6750 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6753 if (extract32(opcode
, 2, 1)) {
6754 /* There are too many rounding modes to all fit into rmode,
6755 * so FCVTA[US] is a special case.
6757 rmode
= FPROUNDING_TIEAWAY
;
6760 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
6763 case 1: /* float64 */
6764 tcg_double
= read_fp_dreg(s
, rn
);
6767 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6768 tcg_shift
, tcg_fpstatus
);
6770 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6771 tcg_shift
, tcg_fpstatus
);
6775 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6776 tcg_shift
, tcg_fpstatus
);
6778 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6779 tcg_shift
, tcg_fpstatus
);
6783 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6787 case 0: /* float32 */
6788 tcg_single
= read_fp_sreg(s
, rn
);
6791 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6792 tcg_shift
, tcg_fpstatus
);
6794 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6795 tcg_shift
, tcg_fpstatus
);
6798 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6800 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6801 tcg_shift
, tcg_fpstatus
);
6803 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6804 tcg_shift
, tcg_fpstatus
);
6806 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6810 case 3: /* float16 */
6811 tcg_single
= read_fp_sreg(s
, rn
);
6814 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6815 tcg_shift
, tcg_fpstatus
);
6817 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6818 tcg_shift
, tcg_fpstatus
);
6821 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6823 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6824 tcg_shift
, tcg_fpstatus
);
6826 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6827 tcg_shift
, tcg_fpstatus
);
6829 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6834 g_assert_not_reached();
6837 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
6841 /* Floating point <-> fixed point conversions
6842 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6843 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6844 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6845 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6847 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6849 int rd
= extract32(insn
, 0, 5);
6850 int rn
= extract32(insn
, 5, 5);
6851 int scale
= extract32(insn
, 10, 6);
6852 int opcode
= extract32(insn
, 16, 3);
6853 int rmode
= extract32(insn
, 19, 2);
6854 int type
= extract32(insn
, 22, 2);
6855 bool sbit
= extract32(insn
, 29, 1);
6856 bool sf
= extract32(insn
, 31, 1);
6859 if (sbit
|| (!sf
&& scale
< 32)) {
6860 unallocated_encoding(s
);
6865 case 0: /* float32 */
6866 case 1: /* float64 */
6868 case 3: /* float16 */
6869 if (dc_isar_feature(aa64_fp16
, s
)) {
6874 unallocated_encoding(s
);
6878 switch ((rmode
<< 3) | opcode
) {
6879 case 0x2: /* SCVTF */
6880 case 0x3: /* UCVTF */
6883 case 0x18: /* FCVTZS */
6884 case 0x19: /* FCVTZU */
6888 unallocated_encoding(s
);
6892 if (!fp_access_check(s
)) {
6896 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6899 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6901 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6902 * without conversion.
6906 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6912 tmp
= tcg_temp_new_i64();
6913 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6914 write_fp_dreg(s
, rd
, tmp
);
6918 write_fp_dreg(s
, rd
, tcg_rn
);
6921 /* 64 bit to top half. */
6922 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6923 clear_vec_high(s
, true, rd
);
6927 tmp
= tcg_temp_new_i64();
6928 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6929 write_fp_dreg(s
, rd
, tmp
);
6932 g_assert_not_reached();
6935 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6940 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6944 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6947 /* 64 bits from top half */
6948 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6952 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6955 g_assert_not_reached();
6960 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6962 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6963 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
6965 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6967 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6968 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6969 tcg_gen_movi_i32(cpu_CF
, 0);
6970 tcg_gen_movi_i32(cpu_NF
, 0);
6971 tcg_gen_movi_i32(cpu_VF
, 0);
6974 /* Floating point <-> integer conversions
6975 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6976 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6977 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6978 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6980 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6982 int rd
= extract32(insn
, 0, 5);
6983 int rn
= extract32(insn
, 5, 5);
6984 int opcode
= extract32(insn
, 16, 3);
6985 int rmode
= extract32(insn
, 19, 2);
6986 int type
= extract32(insn
, 22, 2);
6987 bool sbit
= extract32(insn
, 29, 1);
6988 bool sf
= extract32(insn
, 31, 1);
6992 goto do_unallocated
;
7000 case 4: /* FCVTAS */
7001 case 5: /* FCVTAU */
7003 goto do_unallocated
;
7006 case 0: /* FCVT[NPMZ]S */
7007 case 1: /* FCVT[NPMZ]U */
7009 case 0: /* float32 */
7010 case 1: /* float64 */
7012 case 3: /* float16 */
7013 if (!dc_isar_feature(aa64_fp16
, s
)) {
7014 goto do_unallocated
;
7018 goto do_unallocated
;
7020 if (!fp_access_check(s
)) {
7023 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7027 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7028 case 0b01100110: /* FMOV half <-> 32-bit int */
7030 case 0b11100110: /* FMOV half <-> 64-bit int */
7032 if (!dc_isar_feature(aa64_fp16
, s
)) {
7033 goto do_unallocated
;
7036 case 0b00000110: /* FMOV 32-bit */
7038 case 0b10100110: /* FMOV 64-bit */
7040 case 0b11001110: /* FMOV top half of 128-bit */
7042 if (!fp_access_check(s
)) {
7046 handle_fmov(s
, rd
, rn
, type
, itof
);
7049 case 0b00111110: /* FJCVTZS */
7050 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7051 goto do_unallocated
;
7052 } else if (fp_access_check(s
)) {
7053 handle_fjcvtzs(s
, rd
, rn
);
7059 unallocated_encoding(s
);
7066 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7067 * 31 30 29 28 25 24 0
7068 * +---+---+---+---------+-----------------------------+
7069 * | | 0 | | 1 1 1 1 | |
7070 * +---+---+---+---------+-----------------------------+
7072 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7074 if (extract32(insn
, 24, 1)) {
7075 /* Floating point data-processing (3 source) */
7076 disas_fp_3src(s
, insn
);
7077 } else if (extract32(insn
, 21, 1) == 0) {
7078 /* Floating point to fixed point conversions */
7079 disas_fp_fixed_conv(s
, insn
);
7081 switch (extract32(insn
, 10, 2)) {
7083 /* Floating point conditional compare */
7084 disas_fp_ccomp(s
, insn
);
7087 /* Floating point data-processing (2 source) */
7088 disas_fp_2src(s
, insn
);
7091 /* Floating point conditional select */
7092 disas_fp_csel(s
, insn
);
7095 switch (ctz32(extract32(insn
, 12, 4))) {
7096 case 0: /* [15:12] == xxx1 */
7097 /* Floating point immediate */
7098 disas_fp_imm(s
, insn
);
7100 case 1: /* [15:12] == xx10 */
7101 /* Floating point compare */
7102 disas_fp_compare(s
, insn
);
7104 case 2: /* [15:12] == x100 */
7105 /* Floating point data-processing (1 source) */
7106 disas_fp_1src(s
, insn
);
7108 case 3: /* [15:12] == 1000 */
7109 unallocated_encoding(s
);
7111 default: /* [15:12] == 0000 */
7112 /* Floating point <-> integer conversions */
7113 disas_fp_int_conv(s
, insn
);
7121 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7124 /* Extract 64 bits from the middle of two concatenated 64 bit
7125 * vector register slices left:right. The extracted bits start
7126 * at 'pos' bits into the right (least significant) side.
7127 * We return the result in tcg_right, and guarantee not to
7130 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7131 assert(pos
> 0 && pos
< 64);
7133 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7134 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7135 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7139 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7140 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7141 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7142 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7144 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7146 int is_q
= extract32(insn
, 30, 1);
7147 int op2
= extract32(insn
, 22, 2);
7148 int imm4
= extract32(insn
, 11, 4);
7149 int rm
= extract32(insn
, 16, 5);
7150 int rn
= extract32(insn
, 5, 5);
7151 int rd
= extract32(insn
, 0, 5);
7152 int pos
= imm4
<< 3;
7153 TCGv_i64 tcg_resl
, tcg_resh
;
7155 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7156 unallocated_encoding(s
);
7160 if (!fp_access_check(s
)) {
7164 tcg_resh
= tcg_temp_new_i64();
7165 tcg_resl
= tcg_temp_new_i64();
7167 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7168 * either extracting 128 bits from a 128:128 concatenation, or
7169 * extracting 64 bits from a 64:64 concatenation.
7172 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7174 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7175 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7183 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7184 EltPosns
*elt
= eltposns
;
7191 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7193 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7196 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7197 tcg_hh
= tcg_temp_new_i64();
7198 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7199 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7203 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7205 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7207 clear_vec_high(s
, is_q
, rd
);
7211 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7212 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7213 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7214 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7216 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7218 int op2
= extract32(insn
, 22, 2);
7219 int is_q
= extract32(insn
, 30, 1);
7220 int rm
= extract32(insn
, 16, 5);
7221 int rn
= extract32(insn
, 5, 5);
7222 int rd
= extract32(insn
, 0, 5);
7223 int is_tbx
= extract32(insn
, 12, 1);
7224 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7227 unallocated_encoding(s
);
7231 if (!fp_access_check(s
)) {
7235 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7236 vec_full_reg_offset(s
, rm
), cpu_env
,
7237 is_q
? 16 : 8, vec_full_reg_size(s
),
7238 (len
<< 6) | (is_tbx
<< 5) | rn
,
7239 gen_helper_simd_tblx
);
7243 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7244 * +---+---+-------------+------+---+------+---+------------------+------+
7245 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7246 * +---+---+-------------+------+---+------+---+------------------+------+
7248 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7250 int rd
= extract32(insn
, 0, 5);
7251 int rn
= extract32(insn
, 5, 5);
7252 int rm
= extract32(insn
, 16, 5);
7253 int size
= extract32(insn
, 22, 2);
7254 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7255 * bit 2 indicates 1 vs 2 variant of the insn.
7257 int opcode
= extract32(insn
, 12, 2);
7258 bool part
= extract32(insn
, 14, 1);
7259 bool is_q
= extract32(insn
, 30, 1);
7260 int esize
= 8 << size
;
7262 int datasize
= is_q
? 128 : 64;
7263 int elements
= datasize
/ esize
;
7264 TCGv_i64 tcg_res
[2], tcg_ele
;
7266 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7267 unallocated_encoding(s
);
7271 if (!fp_access_check(s
)) {
7275 tcg_res
[0] = tcg_temp_new_i64();
7276 tcg_res
[1] = is_q
? tcg_temp_new_i64() : NULL
;
7277 tcg_ele
= tcg_temp_new_i64();
7279 for (i
= 0; i
< elements
; i
++) {
7283 case 1: /* UZP1/2 */
7285 int midpoint
= elements
/ 2;
7287 read_vec_element(s
, tcg_ele
, rn
, 2 * i
+ part
, size
);
7289 read_vec_element(s
, tcg_ele
, rm
,
7290 2 * (i
- midpoint
) + part
, size
);
7294 case 2: /* TRN1/2 */
7296 read_vec_element(s
, tcg_ele
, rm
, (i
& ~1) + part
, size
);
7298 read_vec_element(s
, tcg_ele
, rn
, (i
& ~1) + part
, size
);
7301 case 3: /* ZIP1/2 */
7303 int base
= part
* elements
/ 2;
7305 read_vec_element(s
, tcg_ele
, rm
, base
+ (i
>> 1), size
);
7307 read_vec_element(s
, tcg_ele
, rn
, base
+ (i
>> 1), size
);
7312 g_assert_not_reached();
7315 w
= (i
* esize
) / 64;
7316 o
= (i
* esize
) % 64;
7318 tcg_gen_mov_i64(tcg_res
[w
], tcg_ele
);
7320 tcg_gen_shli_i64(tcg_ele
, tcg_ele
, o
);
7321 tcg_gen_or_i64(tcg_res
[w
], tcg_res
[w
], tcg_ele
);
7325 for (i
= 0; i
<= is_q
; ++i
) {
7326 write_vec_element(s
, tcg_res
[i
], rd
, i
, MO_64
);
7328 clear_vec_high(s
, is_q
, rd
);
7332 * do_reduction_op helper
7334 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7335 * important for correct NaN propagation that we do these
7336 * operations in exactly the order specified by the pseudocode.
7338 * This is a recursive function, TCG temps should be freed by the
7339 * calling function once it is done with the values.
7341 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7342 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7344 if (esize
== size
) {
7346 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7349 /* We should have one register left here */
7350 assert(ctpop8(vmap
) == 1);
7351 element
= ctz32(vmap
);
7352 assert(element
< 8);
7354 tcg_elem
= tcg_temp_new_i32();
7355 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7358 int bits
= size
/ 2;
7359 int shift
= ctpop8(vmap
) / 2;
7360 int vmap_lo
= (vmap
>> shift
) & vmap
;
7361 int vmap_hi
= (vmap
& ~vmap_lo
);
7362 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7364 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7365 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7366 tcg_res
= tcg_temp_new_i32();
7369 case 0x0c: /* fmaxnmv half-precision */
7370 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7372 case 0x0f: /* fmaxv half-precision */
7373 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7375 case 0x1c: /* fminnmv half-precision */
7376 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7378 case 0x1f: /* fminv half-precision */
7379 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7381 case 0x2c: /* fmaxnmv */
7382 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7384 case 0x2f: /* fmaxv */
7385 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7387 case 0x3c: /* fminnmv */
7388 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7390 case 0x3f: /* fminv */
7391 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7394 g_assert_not_reached();
7400 /* AdvSIMD across lanes
7401 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7402 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7403 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7404 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7406 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7408 int rd
= extract32(insn
, 0, 5);
7409 int rn
= extract32(insn
, 5, 5);
7410 int size
= extract32(insn
, 22, 2);
7411 int opcode
= extract32(insn
, 12, 5);
7412 bool is_q
= extract32(insn
, 30, 1);
7413 bool is_u
= extract32(insn
, 29, 1);
7415 bool is_min
= false;
7419 TCGv_i64 tcg_res
, tcg_elt
;
7422 case 0x1b: /* ADDV */
7424 unallocated_encoding(s
);
7428 case 0x3: /* SADDLV, UADDLV */
7429 case 0xa: /* SMAXV, UMAXV */
7430 case 0x1a: /* SMINV, UMINV */
7431 if (size
== 3 || (size
== 2 && !is_q
)) {
7432 unallocated_encoding(s
);
7436 case 0xc: /* FMAXNMV, FMINNMV */
7437 case 0xf: /* FMAXV, FMINV */
7438 /* Bit 1 of size field encodes min vs max and the actual size
7439 * depends on the encoding of the U bit. If not set (and FP16
7440 * enabled) then we do half-precision float instead of single
7443 is_min
= extract32(size
, 1, 1);
7445 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7447 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7448 unallocated_encoding(s
);
7455 unallocated_encoding(s
);
7459 if (!fp_access_check(s
)) {
7464 elements
= (is_q
? 128 : 64) / esize
;
7466 tcg_res
= tcg_temp_new_i64();
7467 tcg_elt
= tcg_temp_new_i64();
7469 /* These instructions operate across all lanes of a vector
7470 * to produce a single result. We can guarantee that a 64
7471 * bit intermediate is sufficient:
7472 * + for [US]ADDLV the maximum element size is 32 bits, and
7473 * the result type is 64 bits
7474 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7475 * same as the element size, which is 32 bits at most
7476 * For the integer operations we can choose to work at 64
7477 * or 32 bits and truncate at the end; for simplicity
7478 * we use 64 bits always. The floating point
7479 * ops do require 32 bit intermediates, though.
7482 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7484 for (i
= 1; i
< elements
; i
++) {
7485 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7488 case 0x03: /* SADDLV / UADDLV */
7489 case 0x1b: /* ADDV */
7490 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7492 case 0x0a: /* SMAXV / UMAXV */
7494 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7496 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7499 case 0x1a: /* SMINV / UMINV */
7501 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7503 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7507 g_assert_not_reached();
7512 /* Floating point vector reduction ops which work across 32
7513 * bit (single) or 16 bit (half-precision) intermediates.
7514 * Note that correct NaN propagation requires that we do these
7515 * operations in exactly the order specified by the pseudocode.
7517 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7518 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7519 int vmap
= (1 << elements
) - 1;
7520 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7521 (is_q
? 128 : 64), vmap
, fpst
);
7522 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7525 /* Now truncate the result to the width required for the final output */
7526 if (opcode
== 0x03) {
7527 /* SADDLV, UADDLV: result is 2*esize */
7533 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7536 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7539 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7544 g_assert_not_reached();
7547 write_fp_dreg(s
, rd
, tcg_res
);
7550 /* DUP (Element, Vector)
7552 * 31 30 29 21 20 16 15 10 9 5 4 0
7553 * +---+---+-------------------+--------+-------------+------+------+
7554 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7555 * +---+---+-------------------+--------+-------------+------+------+
7557 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7559 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7562 int size
= ctz32(imm5
);
7565 if (size
> 3 || (size
== 3 && !is_q
)) {
7566 unallocated_encoding(s
);
7570 if (!fp_access_check(s
)) {
7574 index
= imm5
>> (size
+ 1);
7575 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7576 vec_reg_offset(s
, rn
, index
, size
),
7577 is_q
? 16 : 8, vec_full_reg_size(s
));
7580 /* DUP (element, scalar)
7581 * 31 21 20 16 15 10 9 5 4 0
7582 * +-----------------------+--------+-------------+------+------+
7583 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7584 * +-----------------------+--------+-------------+------+------+
7586 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7589 int size
= ctz32(imm5
);
7594 unallocated_encoding(s
);
7598 if (!fp_access_check(s
)) {
7602 index
= imm5
>> (size
+ 1);
7604 /* This instruction just extracts the specified element and
7605 * zero-extends it into the bottom of the destination register.
7607 tmp
= tcg_temp_new_i64();
7608 read_vec_element(s
, tmp
, rn
, index
, size
);
7609 write_fp_dreg(s
, rd
, tmp
);
7614 * 31 30 29 21 20 16 15 10 9 5 4 0
7615 * +---+---+-------------------+--------+-------------+------+------+
7616 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7617 * +---+---+-------------------+--------+-------------+------+------+
7619 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7621 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7624 int size
= ctz32(imm5
);
7625 uint32_t dofs
, oprsz
, maxsz
;
7627 if (size
> 3 || ((size
== 3) && !is_q
)) {
7628 unallocated_encoding(s
);
7632 if (!fp_access_check(s
)) {
7636 dofs
= vec_full_reg_offset(s
, rd
);
7637 oprsz
= is_q
? 16 : 8;
7638 maxsz
= vec_full_reg_size(s
);
7640 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7645 * 31 21 20 16 15 14 11 10 9 5 4 0
7646 * +-----------------------+--------+------------+---+------+------+
7647 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7648 * +-----------------------+--------+------------+---+------+------+
7650 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7651 * index: encoded in imm5<4:size+1>
7653 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7656 int size
= ctz32(imm5
);
7657 int src_index
, dst_index
;
7661 unallocated_encoding(s
);
7665 if (!fp_access_check(s
)) {
7669 dst_index
= extract32(imm5
, 1+size
, 5);
7670 src_index
= extract32(imm4
, size
, 4);
7672 tmp
= tcg_temp_new_i64();
7674 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7675 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7677 /* INS is considered a 128-bit write for SVE. */
7678 clear_vec_high(s
, true, rd
);
7684 * 31 21 20 16 15 10 9 5 4 0
7685 * +-----------------------+--------+-------------+------+------+
7686 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7687 * +-----------------------+--------+-------------+------+------+
7689 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7690 * index: encoded in imm5<4:size+1>
7692 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7694 int size
= ctz32(imm5
);
7698 unallocated_encoding(s
);
7702 if (!fp_access_check(s
)) {
7706 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7707 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7709 /* INS is considered a 128-bit write for SVE. */
7710 clear_vec_high(s
, true, rd
);
7717 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7718 * +---+---+-------------------+--------+-------------+------+------+
7719 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7720 * +---+---+-------------------+--------+-------------+------+------+
7722 * U: unsigned when set
7723 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7725 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7726 int rn
, int rd
, int imm5
)
7728 int size
= ctz32(imm5
);
7732 /* Check for UnallocatedEncodings */
7734 if (size
> 2 || (size
== 2 && !is_q
)) {
7735 unallocated_encoding(s
);
7740 || (size
< 3 && is_q
)
7741 || (size
== 3 && !is_q
)) {
7742 unallocated_encoding(s
);
7747 if (!fp_access_check(s
)) {
7751 element
= extract32(imm5
, 1+size
, 4);
7753 tcg_rd
= cpu_reg(s
, rd
);
7754 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7755 if (is_signed
&& !is_q
) {
7756 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7761 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7762 * +---+---+----+-----------------+------+---+------+---+------+------+
7763 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7764 * +---+---+----+-----------------+------+---+------+---+------+------+
7766 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7768 int rd
= extract32(insn
, 0, 5);
7769 int rn
= extract32(insn
, 5, 5);
7770 int imm4
= extract32(insn
, 11, 4);
7771 int op
= extract32(insn
, 29, 1);
7772 int is_q
= extract32(insn
, 30, 1);
7773 int imm5
= extract32(insn
, 16, 5);
7778 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7780 unallocated_encoding(s
);
7785 /* DUP (element - vector) */
7786 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7790 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7795 handle_simd_insg(s
, rd
, rn
, imm5
);
7797 unallocated_encoding(s
);
7802 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7803 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7806 unallocated_encoding(s
);
7812 /* AdvSIMD modified immediate
7813 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7814 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7815 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7816 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7818 * There are a number of operations that can be carried out here:
7819 * MOVI - move (shifted) imm into register
7820 * MVNI - move inverted (shifted) imm into register
7821 * ORR - bitwise OR of (shifted) imm with register
7822 * BIC - bitwise clear of (shifted) imm with register
7823 * With ARMv8.2 we also have:
7824 * FMOV half-precision
7826 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7828 int rd
= extract32(insn
, 0, 5);
7829 int cmode
= extract32(insn
, 12, 4);
7830 int o2
= extract32(insn
, 11, 1);
7831 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7832 bool is_neg
= extract32(insn
, 29, 1);
7833 bool is_q
= extract32(insn
, 30, 1);
7836 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7837 /* Check for FMOV (vector, immediate) - half-precision */
7838 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7839 unallocated_encoding(s
);
7844 if (!fp_access_check(s
)) {
7848 if (cmode
== 15 && o2
&& !is_neg
) {
7849 /* FMOV (vector, immediate) - half-precision */
7850 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7851 /* now duplicate across the lanes */
7852 imm
= dup_const(MO_16
, imm
);
7854 imm
= asimd_imm_const(abcdefgh
, cmode
, is_neg
);
7857 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7858 /* MOVI or MVNI, with MVNI negation handled above. */
7859 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7860 vec_full_reg_size(s
), imm
);
7862 /* ORR or BIC, with BIC negation to AND handled above. */
7864 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7866 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7871 /* AdvSIMD scalar copy
7872 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7873 * +-----+----+-----------------+------+---+------+---+------+------+
7874 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7875 * +-----+----+-----------------+------+---+------+---+------+------+
7877 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7879 int rd
= extract32(insn
, 0, 5);
7880 int rn
= extract32(insn
, 5, 5);
7881 int imm4
= extract32(insn
, 11, 4);
7882 int imm5
= extract32(insn
, 16, 5);
7883 int op
= extract32(insn
, 29, 1);
7885 if (op
!= 0 || imm4
!= 0) {
7886 unallocated_encoding(s
);
7890 /* DUP (element, scalar) */
7891 handle_simd_dupes(s
, rd
, rn
, imm5
);
7894 /* AdvSIMD scalar pairwise
7895 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7896 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7897 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7898 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7900 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7902 int u
= extract32(insn
, 29, 1);
7903 int size
= extract32(insn
, 22, 2);
7904 int opcode
= extract32(insn
, 12, 5);
7905 int rn
= extract32(insn
, 5, 5);
7906 int rd
= extract32(insn
, 0, 5);
7909 /* For some ops (the FP ones), size[1] is part of the encoding.
7910 * For ADDP strictly it is not but size[1] is always 1 for valid
7913 opcode
|= (extract32(size
, 1, 1) << 5);
7916 case 0x3b: /* ADDP */
7917 if (u
|| size
!= 3) {
7918 unallocated_encoding(s
);
7921 if (!fp_access_check(s
)) {
7927 case 0xc: /* FMAXNMP */
7928 case 0xd: /* FADDP */
7929 case 0xf: /* FMAXP */
7930 case 0x2c: /* FMINNMP */
7931 case 0x2f: /* FMINP */
7932 /* FP op, size[0] is 32 or 64 bit*/
7934 if (!dc_isar_feature(aa64_fp16
, s
)) {
7935 unallocated_encoding(s
);
7941 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7944 if (!fp_access_check(s
)) {
7948 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7951 unallocated_encoding(s
);
7955 if (size
== MO_64
) {
7956 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7957 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7958 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7960 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7961 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7964 case 0x3b: /* ADDP */
7965 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7967 case 0xc: /* FMAXNMP */
7968 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7970 case 0xd: /* FADDP */
7971 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7973 case 0xf: /* FMAXP */
7974 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7976 case 0x2c: /* FMINNMP */
7977 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7979 case 0x2f: /* FMINP */
7980 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7983 g_assert_not_reached();
7986 write_fp_dreg(s
, rd
, tcg_res
);
7988 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7989 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7990 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7992 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7993 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7995 if (size
== MO_16
) {
7997 case 0xc: /* FMAXNMP */
7998 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8000 case 0xd: /* FADDP */
8001 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8003 case 0xf: /* FMAXP */
8004 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8006 case 0x2c: /* FMINNMP */
8007 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8009 case 0x2f: /* FMINP */
8010 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8013 g_assert_not_reached();
8017 case 0xc: /* FMAXNMP */
8018 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8020 case 0xd: /* FADDP */
8021 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8023 case 0xf: /* FMAXP */
8024 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8026 case 0x2c: /* FMINNMP */
8027 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8029 case 0x2f: /* FMINP */
8030 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8033 g_assert_not_reached();
8037 write_fp_sreg(s
, rd
, tcg_res
);
8042 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8044 * This code is handles the common shifting code and is used by both
8045 * the vector and scalar code.
8047 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8048 TCGv_i64 tcg_rnd
, bool accumulate
,
8049 bool is_u
, int size
, int shift
)
8051 bool extended_result
= false;
8052 bool round
= tcg_rnd
!= NULL
;
8054 TCGv_i64 tcg_src_hi
;
8056 if (round
&& size
== 3) {
8057 extended_result
= true;
8058 ext_lshift
= 64 - shift
;
8059 tcg_src_hi
= tcg_temp_new_i64();
8060 } else if (shift
== 64) {
8061 if (!accumulate
&& is_u
) {
8062 /* result is zero */
8063 tcg_gen_movi_i64(tcg_res
, 0);
8068 /* Deal with the rounding step */
8070 if (extended_result
) {
8071 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
8073 /* take care of sign extending tcg_res */
8074 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8075 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8076 tcg_src
, tcg_src_hi
,
8079 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8084 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8088 /* Now do the shift right */
8089 if (round
&& extended_result
) {
8090 /* extended case, >64 bit precision required */
8091 if (ext_lshift
== 0) {
8092 /* special case, only high bits matter */
8093 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8095 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8096 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8097 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8102 /* essentially shifting in 64 zeros */
8103 tcg_gen_movi_i64(tcg_src
, 0);
8105 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8109 /* effectively extending the sign-bit */
8110 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8112 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8118 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8120 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8124 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8125 static void handle_scalar_simd_shri(DisasContext
*s
,
8126 bool is_u
, int immh
, int immb
,
8127 int opcode
, int rn
, int rd
)
8130 int immhb
= immh
<< 3 | immb
;
8131 int shift
= 2 * (8 << size
) - immhb
;
8132 bool accumulate
= false;
8134 bool insert
= false;
8139 if (!extract32(immh
, 3, 1)) {
8140 unallocated_encoding(s
);
8144 if (!fp_access_check(s
)) {
8149 case 0x02: /* SSRA / USRA (accumulate) */
8152 case 0x04: /* SRSHR / URSHR (rounding) */
8155 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8156 accumulate
= round
= true;
8158 case 0x08: /* SRI */
8164 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
8169 tcg_rn
= read_fp_dreg(s
, rn
);
8170 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8173 /* shift count same as element size is valid but does nothing;
8174 * special case to avoid potential shift by 64.
8176 int esize
= 8 << size
;
8177 if (shift
!= esize
) {
8178 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8179 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8182 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8183 accumulate
, is_u
, size
, shift
);
8186 write_fp_dreg(s
, rd
, tcg_rd
);
8189 /* SHL/SLI - Scalar shift left */
8190 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8191 int immh
, int immb
, int opcode
,
8194 int size
= 32 - clz32(immh
) - 1;
8195 int immhb
= immh
<< 3 | immb
;
8196 int shift
= immhb
- (8 << size
);
8200 if (!extract32(immh
, 3, 1)) {
8201 unallocated_encoding(s
);
8205 if (!fp_access_check(s
)) {
8209 tcg_rn
= read_fp_dreg(s
, rn
);
8210 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8213 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8215 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8218 write_fp_dreg(s
, rd
, tcg_rd
);
8221 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8222 * (signed/unsigned) narrowing */
8223 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8224 bool is_u_shift
, bool is_u_narrow
,
8225 int immh
, int immb
, int opcode
,
8228 int immhb
= immh
<< 3 | immb
;
8229 int size
= 32 - clz32(immh
) - 1;
8230 int esize
= 8 << size
;
8231 int shift
= (2 * esize
) - immhb
;
8232 int elements
= is_scalar
? 1 : (64 / esize
);
8233 bool round
= extract32(opcode
, 0, 1);
8234 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8235 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8236 TCGv_i32 tcg_rd_narrowed
;
8239 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8240 { gen_helper_neon_narrow_sat_s8
,
8241 gen_helper_neon_unarrow_sat8
},
8242 { gen_helper_neon_narrow_sat_s16
,
8243 gen_helper_neon_unarrow_sat16
},
8244 { gen_helper_neon_narrow_sat_s32
,
8245 gen_helper_neon_unarrow_sat32
},
8248 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8249 gen_helper_neon_narrow_sat_u8
,
8250 gen_helper_neon_narrow_sat_u16
,
8251 gen_helper_neon_narrow_sat_u32
,
8254 NeonGenNarrowEnvFn
*narrowfn
;
8260 if (extract32(immh
, 3, 1)) {
8261 unallocated_encoding(s
);
8265 if (!fp_access_check(s
)) {
8270 narrowfn
= unsigned_narrow_fns
[size
];
8272 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8275 tcg_rn
= tcg_temp_new_i64();
8276 tcg_rd
= tcg_temp_new_i64();
8277 tcg_rd_narrowed
= tcg_temp_new_i32();
8278 tcg_final
= tcg_temp_new_i64();
8281 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
8286 for (i
= 0; i
< elements
; i
++) {
8287 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8288 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8289 false, is_u_shift
, size
+1, shift
);
8290 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8291 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8293 tcg_gen_mov_i64(tcg_final
, tcg_rd
);
8295 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8300 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8302 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8304 clear_vec_high(s
, is_q
, rd
);
8307 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8308 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8309 bool src_unsigned
, bool dst_unsigned
,
8310 int immh
, int immb
, int rn
, int rd
)
8312 int immhb
= immh
<< 3 | immb
;
8313 int size
= 32 - clz32(immh
) - 1;
8314 int shift
= immhb
- (8 << size
);
8318 assert(!(scalar
&& is_q
));
8321 if (!is_q
&& extract32(immh
, 3, 1)) {
8322 unallocated_encoding(s
);
8326 /* Since we use the variable-shift helpers we must
8327 * replicate the shift count into each element of
8328 * the tcg_shift value.
8332 shift
|= shift
<< 8;
8335 shift
|= shift
<< 16;
8341 g_assert_not_reached();
8345 if (!fp_access_check(s
)) {
8350 TCGv_i64 tcg_shift
= tcg_constant_i64(shift
);
8351 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8352 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8353 { NULL
, gen_helper_neon_qshl_u64
},
8355 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8356 int maxpass
= is_q
? 2 : 1;
8358 for (pass
= 0; pass
< maxpass
; pass
++) {
8359 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8361 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8362 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8363 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8365 clear_vec_high(s
, is_q
, rd
);
8367 TCGv_i32 tcg_shift
= tcg_constant_i32(shift
);
8368 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8370 { gen_helper_neon_qshl_s8
,
8371 gen_helper_neon_qshl_s16
,
8372 gen_helper_neon_qshl_s32
},
8373 { gen_helper_neon_qshlu_s8
,
8374 gen_helper_neon_qshlu_s16
,
8375 gen_helper_neon_qshlu_s32
}
8377 { NULL
, NULL
, NULL
},
8378 { gen_helper_neon_qshl_u8
,
8379 gen_helper_neon_qshl_u16
,
8380 gen_helper_neon_qshl_u32
}
8383 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8384 MemOp memop
= scalar
? size
: MO_32
;
8385 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8387 for (pass
= 0; pass
< maxpass
; pass
++) {
8388 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8390 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8391 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8395 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8398 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8403 g_assert_not_reached();
8405 write_fp_sreg(s
, rd
, tcg_op
);
8407 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8412 clear_vec_high(s
, is_q
, rd
);
8417 /* Common vector code for handling integer to FP conversion */
8418 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8419 int elements
, int is_signed
,
8420 int fracbits
, int size
)
8422 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8423 TCGv_i32 tcg_shift
= NULL
;
8425 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8428 if (fracbits
|| size
== MO_64
) {
8429 tcg_shift
= tcg_constant_i32(fracbits
);
8432 if (size
== MO_64
) {
8433 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8434 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8436 for (pass
= 0; pass
< elements
; pass
++) {
8437 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8440 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8441 tcg_shift
, tcg_fpst
);
8443 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8444 tcg_shift
, tcg_fpst
);
8446 if (elements
== 1) {
8447 write_fp_dreg(s
, rd
, tcg_double
);
8449 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8453 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8454 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8456 for (pass
= 0; pass
< elements
; pass
++) {
8457 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8463 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8464 tcg_shift
, tcg_fpst
);
8466 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8467 tcg_shift
, tcg_fpst
);
8471 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8473 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8480 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8481 tcg_shift
, tcg_fpst
);
8483 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8484 tcg_shift
, tcg_fpst
);
8488 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8490 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8495 g_assert_not_reached();
8498 if (elements
== 1) {
8499 write_fp_sreg(s
, rd
, tcg_float
);
8501 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8506 clear_vec_high(s
, elements
<< size
== 16, rd
);
8509 /* UCVTF/SCVTF - Integer to FP conversion */
8510 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8511 bool is_q
, bool is_u
,
8512 int immh
, int immb
, int opcode
,
8515 int size
, elements
, fracbits
;
8516 int immhb
= immh
<< 3 | immb
;
8520 if (!is_scalar
&& !is_q
) {
8521 unallocated_encoding(s
);
8524 } else if (immh
& 4) {
8526 } else if (immh
& 2) {
8528 if (!dc_isar_feature(aa64_fp16
, s
)) {
8529 unallocated_encoding(s
);
8533 /* immh == 0 would be a failure of the decode logic */
8534 g_assert(immh
== 1);
8535 unallocated_encoding(s
);
8542 elements
= (8 << is_q
) >> size
;
8544 fracbits
= (16 << size
) - immhb
;
8546 if (!fp_access_check(s
)) {
8550 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8553 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8554 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8555 bool is_q
, bool is_u
,
8556 int immh
, int immb
, int rn
, int rd
)
8558 int immhb
= immh
<< 3 | immb
;
8559 int pass
, size
, fracbits
;
8560 TCGv_ptr tcg_fpstatus
;
8561 TCGv_i32 tcg_rmode
, tcg_shift
;
8565 if (!is_scalar
&& !is_q
) {
8566 unallocated_encoding(s
);
8569 } else if (immh
& 0x4) {
8571 } else if (immh
& 0x2) {
8573 if (!dc_isar_feature(aa64_fp16
, s
)) {
8574 unallocated_encoding(s
);
8578 /* Should have split out AdvSIMD modified immediate earlier. */
8580 unallocated_encoding(s
);
8584 if (!fp_access_check(s
)) {
8588 assert(!(is_scalar
&& is_q
));
8590 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8591 tcg_rmode
= gen_set_rmode(FPROUNDING_ZERO
, tcg_fpstatus
);
8592 fracbits
= (16 << size
) - immhb
;
8593 tcg_shift
= tcg_constant_i32(fracbits
);
8595 if (size
== MO_64
) {
8596 int maxpass
= is_scalar
? 1 : 2;
8598 for (pass
= 0; pass
< maxpass
; pass
++) {
8599 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8601 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8603 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8605 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8607 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8609 clear_vec_high(s
, is_q
, rd
);
8611 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8612 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8617 fn
= gen_helper_vfp_touhh
;
8619 fn
= gen_helper_vfp_toshh
;
8624 fn
= gen_helper_vfp_touls
;
8626 fn
= gen_helper_vfp_tosls
;
8630 g_assert_not_reached();
8633 for (pass
= 0; pass
< maxpass
; pass
++) {
8634 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8636 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8637 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8639 write_fp_sreg(s
, rd
, tcg_op
);
8641 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8645 clear_vec_high(s
, is_q
, rd
);
8649 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
8652 /* AdvSIMD scalar shift by immediate
8653 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8654 * +-----+---+-------------+------+------+--------+---+------+------+
8655 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8656 * +-----+---+-------------+------+------+--------+---+------+------+
8658 * This is the scalar version so it works on a fixed sized registers
8660 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8662 int rd
= extract32(insn
, 0, 5);
8663 int rn
= extract32(insn
, 5, 5);
8664 int opcode
= extract32(insn
, 11, 5);
8665 int immb
= extract32(insn
, 16, 3);
8666 int immh
= extract32(insn
, 19, 4);
8667 bool is_u
= extract32(insn
, 29, 1);
8670 unallocated_encoding(s
);
8675 case 0x08: /* SRI */
8677 unallocated_encoding(s
);
8681 case 0x00: /* SSHR / USHR */
8682 case 0x02: /* SSRA / USRA */
8683 case 0x04: /* SRSHR / URSHR */
8684 case 0x06: /* SRSRA / URSRA */
8685 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8687 case 0x0a: /* SHL / SLI */
8688 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8690 case 0x1c: /* SCVTF, UCVTF */
8691 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8694 case 0x10: /* SQSHRUN, SQSHRUN2 */
8695 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8697 unallocated_encoding(s
);
8700 handle_vec_simd_sqshrn(s
, true, false, false, true,
8701 immh
, immb
, opcode
, rn
, rd
);
8703 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8704 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8705 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8706 immh
, immb
, opcode
, rn
, rd
);
8708 case 0xc: /* SQSHLU */
8710 unallocated_encoding(s
);
8713 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8715 case 0xe: /* SQSHL, UQSHL */
8716 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8718 case 0x1f: /* FCVTZS, FCVTZU */
8719 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8722 unallocated_encoding(s
);
8727 /* AdvSIMD scalar three different
8728 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8729 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8730 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8731 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8733 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8735 bool is_u
= extract32(insn
, 29, 1);
8736 int size
= extract32(insn
, 22, 2);
8737 int opcode
= extract32(insn
, 12, 4);
8738 int rm
= extract32(insn
, 16, 5);
8739 int rn
= extract32(insn
, 5, 5);
8740 int rd
= extract32(insn
, 0, 5);
8743 unallocated_encoding(s
);
8748 case 0x9: /* SQDMLAL, SQDMLAL2 */
8749 case 0xb: /* SQDMLSL, SQDMLSL2 */
8750 case 0xd: /* SQDMULL, SQDMULL2 */
8751 if (size
== 0 || size
== 3) {
8752 unallocated_encoding(s
);
8757 unallocated_encoding(s
);
8761 if (!fp_access_check(s
)) {
8766 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8767 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8768 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8770 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8771 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8773 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8774 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8777 case 0xd: /* SQDMULL, SQDMULL2 */
8779 case 0xb: /* SQDMLSL, SQDMLSL2 */
8780 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8782 case 0x9: /* SQDMLAL, SQDMLAL2 */
8783 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8784 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8788 g_assert_not_reached();
8791 write_fp_dreg(s
, rd
, tcg_res
);
8793 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8794 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8795 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8797 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8798 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8801 case 0xd: /* SQDMULL, SQDMULL2 */
8803 case 0xb: /* SQDMLSL, SQDMLSL2 */
8804 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8806 case 0x9: /* SQDMLAL, SQDMLAL2 */
8808 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8809 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8810 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8815 g_assert_not_reached();
8818 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8819 write_fp_dreg(s
, rd
, tcg_res
);
8823 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8824 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8826 /* Handle 64x64->64 opcodes which are shared between the scalar
8827 * and vector 3-same groups. We cover every opcode where size == 3
8828 * is valid in either the three-reg-same (integer, not pairwise)
8829 * or scalar-three-reg-same groups.
8834 case 0x1: /* SQADD */
8836 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8838 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8841 case 0x5: /* SQSUB */
8843 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8845 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8848 case 0x6: /* CMGT, CMHI */
8849 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8850 * We implement this using setcond (test) and then negating.
8852 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8854 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8855 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8857 case 0x7: /* CMGE, CMHS */
8858 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8860 case 0x11: /* CMTST, CMEQ */
8865 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8867 case 0x8: /* SSHL, USHL */
8869 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8871 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8874 case 0x9: /* SQSHL, UQSHL */
8876 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8878 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8881 case 0xa: /* SRSHL, URSHL */
8883 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8885 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8888 case 0xb: /* SQRSHL, UQRSHL */
8890 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8892 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8895 case 0x10: /* ADD, SUB */
8897 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8899 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8903 g_assert_not_reached();
8907 /* Handle the 3-same-operands float operations; shared by the scalar
8908 * and vector encodings. The caller must filter out any encodings
8909 * not allocated for the encoding it is dealing with.
8911 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8912 int fpopcode
, int rd
, int rn
, int rm
)
8915 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
8917 for (pass
= 0; pass
< elements
; pass
++) {
8920 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8921 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8922 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8924 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8925 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8928 case 0x39: /* FMLS */
8929 /* As usual for ARM, separate negation for fused multiply-add */
8930 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8932 case 0x19: /* FMLA */
8933 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8934 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8937 case 0x18: /* FMAXNM */
8938 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8940 case 0x1a: /* FADD */
8941 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8943 case 0x1b: /* FMULX */
8944 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8946 case 0x1c: /* FCMEQ */
8947 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8949 case 0x1e: /* FMAX */
8950 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8952 case 0x1f: /* FRECPS */
8953 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8955 case 0x38: /* FMINNM */
8956 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8958 case 0x3a: /* FSUB */
8959 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8961 case 0x3e: /* FMIN */
8962 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8964 case 0x3f: /* FRSQRTS */
8965 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8967 case 0x5b: /* FMUL */
8968 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8970 case 0x5c: /* FCMGE */
8971 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8973 case 0x5d: /* FACGE */
8974 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8976 case 0x5f: /* FDIV */
8977 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8979 case 0x7a: /* FABD */
8980 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8981 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8983 case 0x7c: /* FCMGT */
8984 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8986 case 0x7d: /* FACGT */
8987 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8990 g_assert_not_reached();
8993 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8996 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8997 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8998 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9000 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9001 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9004 case 0x39: /* FMLS */
9005 /* As usual for ARM, separate negation for fused multiply-add */
9006 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9008 case 0x19: /* FMLA */
9009 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9010 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9013 case 0x1a: /* FADD */
9014 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9016 case 0x1b: /* FMULX */
9017 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9019 case 0x1c: /* FCMEQ */
9020 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9022 case 0x1e: /* FMAX */
9023 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9025 case 0x1f: /* FRECPS */
9026 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9028 case 0x18: /* FMAXNM */
9029 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9031 case 0x38: /* FMINNM */
9032 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9034 case 0x3a: /* FSUB */
9035 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9037 case 0x3e: /* FMIN */
9038 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9040 case 0x3f: /* FRSQRTS */
9041 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9043 case 0x5b: /* FMUL */
9044 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9046 case 0x5c: /* FCMGE */
9047 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9049 case 0x5d: /* FACGE */
9050 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9052 case 0x5f: /* FDIV */
9053 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9055 case 0x7a: /* FABD */
9056 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9057 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9059 case 0x7c: /* FCMGT */
9060 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9062 case 0x7d: /* FACGT */
9063 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9066 g_assert_not_reached();
9069 if (elements
== 1) {
9070 /* scalar single so clear high part */
9071 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9073 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9074 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9076 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9081 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9084 /* AdvSIMD scalar three same
9085 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9086 * +-----+---+-----------+------+---+------+--------+---+------+------+
9087 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9088 * +-----+---+-----------+------+---+------+--------+---+------+------+
9090 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9092 int rd
= extract32(insn
, 0, 5);
9093 int rn
= extract32(insn
, 5, 5);
9094 int opcode
= extract32(insn
, 11, 5);
9095 int rm
= extract32(insn
, 16, 5);
9096 int size
= extract32(insn
, 22, 2);
9097 bool u
= extract32(insn
, 29, 1);
9100 if (opcode
>= 0x18) {
9101 /* Floating point: U, size[1] and opcode indicate operation */
9102 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9104 case 0x1b: /* FMULX */
9105 case 0x1f: /* FRECPS */
9106 case 0x3f: /* FRSQRTS */
9107 case 0x5d: /* FACGE */
9108 case 0x7d: /* FACGT */
9109 case 0x1c: /* FCMEQ */
9110 case 0x5c: /* FCMGE */
9111 case 0x7c: /* FCMGT */
9112 case 0x7a: /* FABD */
9115 unallocated_encoding(s
);
9119 if (!fp_access_check(s
)) {
9123 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9128 case 0x1: /* SQADD, UQADD */
9129 case 0x5: /* SQSUB, UQSUB */
9130 case 0x9: /* SQSHL, UQSHL */
9131 case 0xb: /* SQRSHL, UQRSHL */
9133 case 0x8: /* SSHL, USHL */
9134 case 0xa: /* SRSHL, URSHL */
9135 case 0x6: /* CMGT, CMHI */
9136 case 0x7: /* CMGE, CMHS */
9137 case 0x11: /* CMTST, CMEQ */
9138 case 0x10: /* ADD, SUB (vector) */
9140 unallocated_encoding(s
);
9144 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9145 if (size
!= 1 && size
!= 2) {
9146 unallocated_encoding(s
);
9151 unallocated_encoding(s
);
9155 if (!fp_access_check(s
)) {
9159 tcg_rd
= tcg_temp_new_i64();
9162 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9163 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9165 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9167 /* Do a single operation on the lowest element in the vector.
9168 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9169 * no side effects for all these operations.
9170 * OPTME: special-purpose helpers would avoid doing some
9171 * unnecessary work in the helper for the 8 and 16 bit cases.
9173 NeonGenTwoOpEnvFn
*genenvfn
;
9174 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9175 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9176 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9178 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9179 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9182 case 0x1: /* SQADD, UQADD */
9184 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9185 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9186 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9187 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9189 genenvfn
= fns
[size
][u
];
9192 case 0x5: /* SQSUB, UQSUB */
9194 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9195 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9196 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9197 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9199 genenvfn
= fns
[size
][u
];
9202 case 0x9: /* SQSHL, UQSHL */
9204 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9205 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9206 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9207 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9209 genenvfn
= fns
[size
][u
];
9212 case 0xb: /* SQRSHL, UQRSHL */
9214 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9215 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9216 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9217 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9219 genenvfn
= fns
[size
][u
];
9222 case 0x16: /* SQDMULH, SQRDMULH */
9224 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9225 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9226 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9228 assert(size
== 1 || size
== 2);
9229 genenvfn
= fns
[size
- 1][u
];
9233 g_assert_not_reached();
9236 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9237 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9240 write_fp_dreg(s
, rd
, tcg_rd
);
9243 /* AdvSIMD scalar three same FP16
9244 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9245 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9246 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9247 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9248 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9249 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9251 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9254 int rd
= extract32(insn
, 0, 5);
9255 int rn
= extract32(insn
, 5, 5);
9256 int opcode
= extract32(insn
, 11, 3);
9257 int rm
= extract32(insn
, 16, 5);
9258 bool u
= extract32(insn
, 29, 1);
9259 bool a
= extract32(insn
, 23, 1);
9260 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9267 case 0x03: /* FMULX */
9268 case 0x04: /* FCMEQ (reg) */
9269 case 0x07: /* FRECPS */
9270 case 0x0f: /* FRSQRTS */
9271 case 0x14: /* FCMGE (reg) */
9272 case 0x15: /* FACGE */
9273 case 0x1a: /* FABD */
9274 case 0x1c: /* FCMGT (reg) */
9275 case 0x1d: /* FACGT */
9278 unallocated_encoding(s
);
9282 if (!dc_isar_feature(aa64_fp16
, s
)) {
9283 unallocated_encoding(s
);
9286 if (!fp_access_check(s
)) {
9290 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9292 tcg_op1
= read_fp_hreg(s
, rn
);
9293 tcg_op2
= read_fp_hreg(s
, rm
);
9294 tcg_res
= tcg_temp_new_i32();
9297 case 0x03: /* FMULX */
9298 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9300 case 0x04: /* FCMEQ (reg) */
9301 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9303 case 0x07: /* FRECPS */
9304 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9306 case 0x0f: /* FRSQRTS */
9307 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9309 case 0x14: /* FCMGE (reg) */
9310 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9312 case 0x15: /* FACGE */
9313 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9315 case 0x1a: /* FABD */
9316 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9317 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9319 case 0x1c: /* FCMGT (reg) */
9320 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9322 case 0x1d: /* FACGT */
9323 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9326 g_assert_not_reached();
9329 write_fp_sreg(s
, rd
, tcg_res
);
9332 /* AdvSIMD scalar three same extra
9333 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9334 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9335 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9336 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9338 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9341 int rd
= extract32(insn
, 0, 5);
9342 int rn
= extract32(insn
, 5, 5);
9343 int opcode
= extract32(insn
, 11, 4);
9344 int rm
= extract32(insn
, 16, 5);
9345 int size
= extract32(insn
, 22, 2);
9346 bool u
= extract32(insn
, 29, 1);
9347 TCGv_i32 ele1
, ele2
, ele3
;
9351 switch (u
* 16 + opcode
) {
9352 case 0x10: /* SQRDMLAH (vector) */
9353 case 0x11: /* SQRDMLSH (vector) */
9354 if (size
!= 1 && size
!= 2) {
9355 unallocated_encoding(s
);
9358 feature
= dc_isar_feature(aa64_rdm
, s
);
9361 unallocated_encoding(s
);
9365 unallocated_encoding(s
);
9368 if (!fp_access_check(s
)) {
9372 /* Do a single operation on the lowest element in the vector.
9373 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9374 * with no side effects for all these operations.
9375 * OPTME: special-purpose helpers would avoid doing some
9376 * unnecessary work in the helper for the 16 bit cases.
9378 ele1
= tcg_temp_new_i32();
9379 ele2
= tcg_temp_new_i32();
9380 ele3
= tcg_temp_new_i32();
9382 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9383 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9384 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9387 case 0x0: /* SQRDMLAH */
9389 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9391 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9394 case 0x1: /* SQRDMLSH */
9396 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9398 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9402 g_assert_not_reached();
9405 res
= tcg_temp_new_i64();
9406 tcg_gen_extu_i32_i64(res
, ele3
);
9407 write_fp_dreg(s
, rd
, res
);
9410 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9411 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9412 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9414 /* Handle 64->64 opcodes which are shared between the scalar and
9415 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9416 * is valid in either group and also the double-precision fp ops.
9417 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9423 case 0x4: /* CLS, CLZ */
9425 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9427 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9431 /* This opcode is shared with CNT and RBIT but we have earlier
9432 * enforced that size == 3 if and only if this is the NOT insn.
9434 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9436 case 0x7: /* SQABS, SQNEG */
9438 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9440 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9443 case 0xa: /* CMLT */
9444 /* 64 bit integer comparison against zero, result is
9445 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9450 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9451 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9453 case 0x8: /* CMGT, CMGE */
9454 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9456 case 0x9: /* CMEQ, CMLE */
9457 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9459 case 0xb: /* ABS, NEG */
9461 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9463 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9466 case 0x2f: /* FABS */
9467 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9469 case 0x6f: /* FNEG */
9470 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9472 case 0x7f: /* FSQRT */
9473 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9475 case 0x1a: /* FCVTNS */
9476 case 0x1b: /* FCVTMS */
9477 case 0x1c: /* FCVTAS */
9478 case 0x3a: /* FCVTPS */
9479 case 0x3b: /* FCVTZS */
9480 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_constant_i32(0), tcg_fpstatus
);
9482 case 0x5a: /* FCVTNU */
9483 case 0x5b: /* FCVTMU */
9484 case 0x5c: /* FCVTAU */
9485 case 0x7a: /* FCVTPU */
9486 case 0x7b: /* FCVTZU */
9487 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_constant_i32(0), tcg_fpstatus
);
9489 case 0x18: /* FRINTN */
9490 case 0x19: /* FRINTM */
9491 case 0x38: /* FRINTP */
9492 case 0x39: /* FRINTZ */
9493 case 0x58: /* FRINTA */
9494 case 0x79: /* FRINTI */
9495 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9497 case 0x59: /* FRINTX */
9498 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9500 case 0x1e: /* FRINT32Z */
9501 case 0x5e: /* FRINT32X */
9502 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9504 case 0x1f: /* FRINT64Z */
9505 case 0x5f: /* FRINT64X */
9506 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9509 g_assert_not_reached();
9513 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9514 bool is_scalar
, bool is_u
, bool is_q
,
9515 int size
, int rn
, int rd
)
9517 bool is_double
= (size
== MO_64
);
9520 if (!fp_access_check(s
)) {
9524 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9527 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9528 TCGv_i64 tcg_zero
= tcg_constant_i64(0);
9529 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9530 NeonGenTwoDoubleOpFn
*genfn
;
9535 case 0x2e: /* FCMLT (zero) */
9538 case 0x2c: /* FCMGT (zero) */
9539 genfn
= gen_helper_neon_cgt_f64
;
9541 case 0x2d: /* FCMEQ (zero) */
9542 genfn
= gen_helper_neon_ceq_f64
;
9544 case 0x6d: /* FCMLE (zero) */
9547 case 0x6c: /* FCMGE (zero) */
9548 genfn
= gen_helper_neon_cge_f64
;
9551 g_assert_not_reached();
9554 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9555 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9557 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9559 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9561 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9564 clear_vec_high(s
, !is_scalar
, rd
);
9566 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9567 TCGv_i32 tcg_zero
= tcg_constant_i32(0);
9568 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9569 NeonGenTwoSingleOpFn
*genfn
;
9571 int pass
, maxpasses
;
9573 if (size
== MO_16
) {
9575 case 0x2e: /* FCMLT (zero) */
9578 case 0x2c: /* FCMGT (zero) */
9579 genfn
= gen_helper_advsimd_cgt_f16
;
9581 case 0x2d: /* FCMEQ (zero) */
9582 genfn
= gen_helper_advsimd_ceq_f16
;
9584 case 0x6d: /* FCMLE (zero) */
9587 case 0x6c: /* FCMGE (zero) */
9588 genfn
= gen_helper_advsimd_cge_f16
;
9591 g_assert_not_reached();
9595 case 0x2e: /* FCMLT (zero) */
9598 case 0x2c: /* FCMGT (zero) */
9599 genfn
= gen_helper_neon_cgt_f32
;
9601 case 0x2d: /* FCMEQ (zero) */
9602 genfn
= gen_helper_neon_ceq_f32
;
9604 case 0x6d: /* FCMLE (zero) */
9607 case 0x6c: /* FCMGE (zero) */
9608 genfn
= gen_helper_neon_cge_f32
;
9611 g_assert_not_reached();
9618 int vector_size
= 8 << is_q
;
9619 maxpasses
= vector_size
>> size
;
9622 for (pass
= 0; pass
< maxpasses
; pass
++) {
9623 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9625 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9627 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9630 write_fp_sreg(s
, rd
, tcg_res
);
9632 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9637 clear_vec_high(s
, is_q
, rd
);
9642 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9643 bool is_scalar
, bool is_u
, bool is_q
,
9644 int size
, int rn
, int rd
)
9646 bool is_double
= (size
== 3);
9647 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9650 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9651 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9654 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9655 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9657 case 0x3d: /* FRECPE */
9658 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9660 case 0x3f: /* FRECPX */
9661 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9663 case 0x7d: /* FRSQRTE */
9664 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9667 g_assert_not_reached();
9669 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9671 clear_vec_high(s
, !is_scalar
, rd
);
9673 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9674 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9675 int pass
, maxpasses
;
9680 maxpasses
= is_q
? 4 : 2;
9683 for (pass
= 0; pass
< maxpasses
; pass
++) {
9684 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9687 case 0x3c: /* URECPE */
9688 gen_helper_recpe_u32(tcg_res
, tcg_op
);
9690 case 0x3d: /* FRECPE */
9691 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9693 case 0x3f: /* FRECPX */
9694 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9696 case 0x7d: /* FRSQRTE */
9697 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9700 g_assert_not_reached();
9704 write_fp_sreg(s
, rd
, tcg_res
);
9706 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9710 clear_vec_high(s
, is_q
, rd
);
9715 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9716 int opcode
, bool u
, bool is_q
,
9717 int size
, int rn
, int rd
)
9719 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9720 * in the source becomes a size element in the destination).
9723 TCGv_i32 tcg_res
[2];
9724 int destelt
= is_q
? 2 : 0;
9725 int passes
= scalar
? 1 : 2;
9728 tcg_res
[1] = tcg_constant_i32(0);
9731 for (pass
= 0; pass
< passes
; pass
++) {
9732 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9733 NeonGenNarrowFn
*genfn
= NULL
;
9734 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9737 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9739 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9741 tcg_res
[pass
] = tcg_temp_new_i32();
9744 case 0x12: /* XTN, SQXTUN */
9746 static NeonGenNarrowFn
* const xtnfns
[3] = {
9747 gen_helper_neon_narrow_u8
,
9748 gen_helper_neon_narrow_u16
,
9749 tcg_gen_extrl_i64_i32
,
9751 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9752 gen_helper_neon_unarrow_sat8
,
9753 gen_helper_neon_unarrow_sat16
,
9754 gen_helper_neon_unarrow_sat32
,
9757 genenvfn
= sqxtunfns
[size
];
9759 genfn
= xtnfns
[size
];
9763 case 0x14: /* SQXTN, UQXTN */
9765 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9766 { gen_helper_neon_narrow_sat_s8
,
9767 gen_helper_neon_narrow_sat_u8
},
9768 { gen_helper_neon_narrow_sat_s16
,
9769 gen_helper_neon_narrow_sat_u16
},
9770 { gen_helper_neon_narrow_sat_s32
,
9771 gen_helper_neon_narrow_sat_u32
},
9773 genenvfn
= fns
[size
][u
];
9776 case 0x16: /* FCVTN, FCVTN2 */
9777 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9779 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9781 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9782 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9783 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9784 TCGv_i32 ahp
= get_ahp_flag();
9786 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9787 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9788 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9789 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9792 case 0x36: /* BFCVTN, BFCVTN2 */
9794 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9795 gen_helper_bfcvt_pair(tcg_res
[pass
], tcg_op
, fpst
);
9798 case 0x56: /* FCVTXN, FCVTXN2 */
9799 /* 64 bit to 32 bit float conversion
9800 * with von Neumann rounding (round to odd)
9803 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9806 g_assert_not_reached();
9810 genfn(tcg_res
[pass
], tcg_op
);
9811 } else if (genenvfn
) {
9812 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9816 for (pass
= 0; pass
< 2; pass
++) {
9817 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9819 clear_vec_high(s
, is_q
, rd
);
9822 /* Remaining saturating accumulating ops */
9823 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9824 bool is_q
, int size
, int rn
, int rd
)
9826 bool is_double
= (size
== 3);
9829 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9830 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9833 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9834 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9835 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9837 if (is_u
) { /* USQADD */
9838 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9839 } else { /* SUQADD */
9840 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9842 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9844 clear_vec_high(s
, !is_scalar
, rd
);
9846 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9847 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9848 int pass
, maxpasses
;
9853 maxpasses
= is_q
? 4 : 2;
9856 for (pass
= 0; pass
< maxpasses
; pass
++) {
9858 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9859 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9861 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9862 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9865 if (is_u
) { /* USQADD */
9868 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9871 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9874 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9877 g_assert_not_reached();
9879 } else { /* SUQADD */
9882 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9885 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9888 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9891 g_assert_not_reached();
9896 write_vec_element(s
, tcg_constant_i64(0), rd
, 0, MO_64
);
9898 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9900 clear_vec_high(s
, is_q
, rd
);
9904 /* AdvSIMD scalar two reg misc
9905 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9906 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9907 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9908 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9910 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9912 int rd
= extract32(insn
, 0, 5);
9913 int rn
= extract32(insn
, 5, 5);
9914 int opcode
= extract32(insn
, 12, 5);
9915 int size
= extract32(insn
, 22, 2);
9916 bool u
= extract32(insn
, 29, 1);
9917 bool is_fcvt
= false;
9920 TCGv_ptr tcg_fpstatus
;
9923 case 0x3: /* USQADD / SUQADD*/
9924 if (!fp_access_check(s
)) {
9927 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9929 case 0x7: /* SQABS / SQNEG */
9931 case 0xa: /* CMLT */
9933 unallocated_encoding(s
);
9937 case 0x8: /* CMGT, CMGE */
9938 case 0x9: /* CMEQ, CMLE */
9939 case 0xb: /* ABS, NEG */
9941 unallocated_encoding(s
);
9945 case 0x12: /* SQXTUN */
9947 unallocated_encoding(s
);
9951 case 0x14: /* SQXTN, UQXTN */
9953 unallocated_encoding(s
);
9956 if (!fp_access_check(s
)) {
9959 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9964 /* Floating point: U, size[1] and opcode indicate operation;
9965 * size[0] indicates single or double precision.
9967 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9968 size
= extract32(size
, 0, 1) ? 3 : 2;
9970 case 0x2c: /* FCMGT (zero) */
9971 case 0x2d: /* FCMEQ (zero) */
9972 case 0x2e: /* FCMLT (zero) */
9973 case 0x6c: /* FCMGE (zero) */
9974 case 0x6d: /* FCMLE (zero) */
9975 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9977 case 0x1d: /* SCVTF */
9978 case 0x5d: /* UCVTF */
9980 bool is_signed
= (opcode
== 0x1d);
9981 if (!fp_access_check(s
)) {
9984 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9987 case 0x3d: /* FRECPE */
9988 case 0x3f: /* FRECPX */
9989 case 0x7d: /* FRSQRTE */
9990 if (!fp_access_check(s
)) {
9993 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9995 case 0x1a: /* FCVTNS */
9996 case 0x1b: /* FCVTMS */
9997 case 0x3a: /* FCVTPS */
9998 case 0x3b: /* FCVTZS */
9999 case 0x5a: /* FCVTNU */
10000 case 0x5b: /* FCVTMU */
10001 case 0x7a: /* FCVTPU */
10002 case 0x7b: /* FCVTZU */
10004 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10006 case 0x1c: /* FCVTAS */
10007 case 0x5c: /* FCVTAU */
10008 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10010 rmode
= FPROUNDING_TIEAWAY
;
10012 case 0x56: /* FCVTXN, FCVTXN2 */
10014 unallocated_encoding(s
);
10017 if (!fp_access_check(s
)) {
10020 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10023 unallocated_encoding(s
);
10028 unallocated_encoding(s
);
10032 if (!fp_access_check(s
)) {
10037 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10038 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
10040 tcg_fpstatus
= NULL
;
10045 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10046 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10048 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10049 write_fp_dreg(s
, rd
, tcg_rd
);
10051 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10052 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10054 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10057 case 0x7: /* SQABS, SQNEG */
10059 NeonGenOneOpEnvFn
*genfn
;
10060 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10061 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10062 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10063 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10065 genfn
= fns
[size
][u
];
10066 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10069 case 0x1a: /* FCVTNS */
10070 case 0x1b: /* FCVTMS */
10071 case 0x1c: /* FCVTAS */
10072 case 0x3a: /* FCVTPS */
10073 case 0x3b: /* FCVTZS */
10074 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_constant_i32(0),
10077 case 0x5a: /* FCVTNU */
10078 case 0x5b: /* FCVTMU */
10079 case 0x5c: /* FCVTAU */
10080 case 0x7a: /* FCVTPU */
10081 case 0x7b: /* FCVTZU */
10082 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_constant_i32(0),
10086 g_assert_not_reached();
10089 write_fp_sreg(s
, rd
, tcg_rd
);
10093 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
10097 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10098 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10099 int immh
, int immb
, int opcode
, int rn
, int rd
)
10101 int size
= 32 - clz32(immh
) - 1;
10102 int immhb
= immh
<< 3 | immb
;
10103 int shift
= 2 * (8 << size
) - immhb
;
10104 GVecGen2iFn
*gvec_fn
;
10106 if (extract32(immh
, 3, 1) && !is_q
) {
10107 unallocated_encoding(s
);
10110 tcg_debug_assert(size
<= 3);
10112 if (!fp_access_check(s
)) {
10117 case 0x02: /* SSRA / USRA (accumulate) */
10118 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10121 case 0x08: /* SRI */
10122 gvec_fn
= gen_gvec_sri
;
10125 case 0x00: /* SSHR / USHR */
10127 if (shift
== 8 << size
) {
10128 /* Shift count the same size as element size produces zero. */
10129 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10130 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10133 gvec_fn
= tcg_gen_gvec_shri
;
10135 /* Shift count the same size as element size produces all sign. */
10136 if (shift
== 8 << size
) {
10139 gvec_fn
= tcg_gen_gvec_sari
;
10143 case 0x04: /* SRSHR / URSHR (rounding) */
10144 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10147 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10148 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10152 g_assert_not_reached();
10155 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10158 /* SHL/SLI - Vector shift left */
10159 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10160 int immh
, int immb
, int opcode
, int rn
, int rd
)
10162 int size
= 32 - clz32(immh
) - 1;
10163 int immhb
= immh
<< 3 | immb
;
10164 int shift
= immhb
- (8 << size
);
10166 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10167 assert(size
>= 0 && size
<= 3);
10169 if (extract32(immh
, 3, 1) && !is_q
) {
10170 unallocated_encoding(s
);
10174 if (!fp_access_check(s
)) {
10179 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10181 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10185 /* USHLL/SHLL - Vector shift left with widening */
10186 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10187 int immh
, int immb
, int opcode
, int rn
, int rd
)
10189 int size
= 32 - clz32(immh
) - 1;
10190 int immhb
= immh
<< 3 | immb
;
10191 int shift
= immhb
- (8 << size
);
10193 int esize
= 8 << size
;
10194 int elements
= dsize
/esize
;
10195 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10196 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10200 unallocated_encoding(s
);
10204 if (!fp_access_check(s
)) {
10208 /* For the LL variants the store is larger than the load,
10209 * so if rd == rn we would overwrite parts of our input.
10210 * So load everything right now and use shifts in the main loop.
10212 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10214 for (i
= 0; i
< elements
; i
++) {
10215 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10216 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10217 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10218 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10222 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10223 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10224 int immh
, int immb
, int opcode
, int rn
, int rd
)
10226 int immhb
= immh
<< 3 | immb
;
10227 int size
= 32 - clz32(immh
) - 1;
10229 int esize
= 8 << size
;
10230 int elements
= dsize
/esize
;
10231 int shift
= (2 * esize
) - immhb
;
10232 bool round
= extract32(opcode
, 0, 1);
10233 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10234 TCGv_i64 tcg_round
;
10237 if (extract32(immh
, 3, 1)) {
10238 unallocated_encoding(s
);
10242 if (!fp_access_check(s
)) {
10246 tcg_rn
= tcg_temp_new_i64();
10247 tcg_rd
= tcg_temp_new_i64();
10248 tcg_final
= tcg_temp_new_i64();
10249 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10252 tcg_round
= tcg_constant_i64(1ULL << (shift
- 1));
10257 for (i
= 0; i
< elements
; i
++) {
10258 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10259 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10260 false, true, size
+1, shift
);
10262 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10266 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10268 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10271 clear_vec_high(s
, is_q
, rd
);
10275 /* AdvSIMD shift by immediate
10276 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10277 * +---+---+---+-------------+------+------+--------+---+------+------+
10278 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10279 * +---+---+---+-------------+------+------+--------+---+------+------+
10281 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10283 int rd
= extract32(insn
, 0, 5);
10284 int rn
= extract32(insn
, 5, 5);
10285 int opcode
= extract32(insn
, 11, 5);
10286 int immb
= extract32(insn
, 16, 3);
10287 int immh
= extract32(insn
, 19, 4);
10288 bool is_u
= extract32(insn
, 29, 1);
10289 bool is_q
= extract32(insn
, 30, 1);
10291 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10295 case 0x08: /* SRI */
10297 unallocated_encoding(s
);
10301 case 0x00: /* SSHR / USHR */
10302 case 0x02: /* SSRA / USRA (accumulate) */
10303 case 0x04: /* SRSHR / URSHR (rounding) */
10304 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10305 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10307 case 0x0a: /* SHL / SLI */
10308 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10310 case 0x10: /* SHRN */
10311 case 0x11: /* RSHRN / SQRSHRUN */
10313 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10316 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10319 case 0x12: /* SQSHRN / UQSHRN */
10320 case 0x13: /* SQRSHRN / UQRSHRN */
10321 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10324 case 0x14: /* SSHLL / USHLL */
10325 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10327 case 0x1c: /* SCVTF / UCVTF */
10328 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10331 case 0xc: /* SQSHLU */
10333 unallocated_encoding(s
);
10336 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10338 case 0xe: /* SQSHL, UQSHL */
10339 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10341 case 0x1f: /* FCVTZS/ FCVTZU */
10342 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10345 unallocated_encoding(s
);
10350 /* Generate code to do a "long" addition or subtraction, ie one done in
10351 * TCGv_i64 on vector lanes twice the width specified by size.
10353 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10354 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10356 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10357 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10358 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10359 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10361 NeonGenTwo64OpFn
*genfn
;
10364 genfn
= fns
[size
][is_sub
];
10365 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10368 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10369 int opcode
, int rd
, int rn
, int rm
)
10371 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10372 TCGv_i64 tcg_res
[2];
10375 tcg_res
[0] = tcg_temp_new_i64();
10376 tcg_res
[1] = tcg_temp_new_i64();
10378 /* Does this op do an adding accumulate, a subtracting accumulate,
10379 * or no accumulate at all?
10397 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10398 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10401 /* size == 2 means two 32x32->64 operations; this is worth special
10402 * casing because we can generally handle it inline.
10405 for (pass
= 0; pass
< 2; pass
++) {
10406 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10407 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10408 TCGv_i64 tcg_passres
;
10409 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10411 int elt
= pass
+ is_q
* 2;
10413 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10414 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10417 tcg_passres
= tcg_res
[pass
];
10419 tcg_passres
= tcg_temp_new_i64();
10423 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10424 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10426 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10427 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10429 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10430 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10432 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10433 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10435 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10436 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10437 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10439 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10442 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10443 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10444 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10445 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10447 case 9: /* SQDMLAL, SQDMLAL2 */
10448 case 11: /* SQDMLSL, SQDMLSL2 */
10449 case 13: /* SQDMULL, SQDMULL2 */
10450 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10451 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10452 tcg_passres
, tcg_passres
);
10455 g_assert_not_reached();
10458 if (opcode
== 9 || opcode
== 11) {
10459 /* saturating accumulate ops */
10461 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10463 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10464 tcg_res
[pass
], tcg_passres
);
10465 } else if (accop
> 0) {
10466 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10467 } else if (accop
< 0) {
10468 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10472 /* size 0 or 1, generally helper functions */
10473 for (pass
= 0; pass
< 2; pass
++) {
10474 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10475 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10476 TCGv_i64 tcg_passres
;
10477 int elt
= pass
+ is_q
* 2;
10479 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10480 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10483 tcg_passres
= tcg_res
[pass
];
10485 tcg_passres
= tcg_temp_new_i64();
10489 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10490 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10492 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10493 static NeonGenWidenFn
* const widenfns
[2][2] = {
10494 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10495 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10497 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10499 widenfn(tcg_op2_64
, tcg_op2
);
10500 widenfn(tcg_passres
, tcg_op1
);
10501 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10502 tcg_passres
, tcg_op2_64
);
10505 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10506 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10509 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10511 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10515 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10517 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10521 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10522 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10523 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10526 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10528 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10532 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10534 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10538 case 9: /* SQDMLAL, SQDMLAL2 */
10539 case 11: /* SQDMLSL, SQDMLSL2 */
10540 case 13: /* SQDMULL, SQDMULL2 */
10542 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10543 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10544 tcg_passres
, tcg_passres
);
10547 g_assert_not_reached();
10551 if (opcode
== 9 || opcode
== 11) {
10552 /* saturating accumulate ops */
10554 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10556 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10560 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10561 tcg_res
[pass
], tcg_passres
);
10567 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10568 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10571 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10572 int opcode
, int rd
, int rn
, int rm
)
10574 TCGv_i64 tcg_res
[2];
10575 int part
= is_q
? 2 : 0;
10578 for (pass
= 0; pass
< 2; pass
++) {
10579 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10580 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10581 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10582 static NeonGenWidenFn
* const widenfns
[3][2] = {
10583 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10584 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10585 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10587 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10589 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10590 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10591 widenfn(tcg_op2_wide
, tcg_op2
);
10592 tcg_res
[pass
] = tcg_temp_new_i64();
10593 gen_neon_addl(size
, (opcode
== 3),
10594 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10597 for (pass
= 0; pass
< 2; pass
++) {
10598 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10602 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10604 tcg_gen_addi_i64(in
, in
, 1U << 31);
10605 tcg_gen_extrh_i64_i32(res
, in
);
10608 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10609 int opcode
, int rd
, int rn
, int rm
)
10611 TCGv_i32 tcg_res
[2];
10612 int part
= is_q
? 2 : 0;
10615 for (pass
= 0; pass
< 2; pass
++) {
10616 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10617 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10618 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10619 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10620 { gen_helper_neon_narrow_high_u8
,
10621 gen_helper_neon_narrow_round_high_u8
},
10622 { gen_helper_neon_narrow_high_u16
,
10623 gen_helper_neon_narrow_round_high_u16
},
10624 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10626 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10628 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10629 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10631 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10633 tcg_res
[pass
] = tcg_temp_new_i32();
10634 gennarrow(tcg_res
[pass
], tcg_wideres
);
10637 for (pass
= 0; pass
< 2; pass
++) {
10638 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10640 clear_vec_high(s
, is_q
, rd
);
10643 /* AdvSIMD three different
10644 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10645 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10646 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10647 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10649 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10651 /* Instructions in this group fall into three basic classes
10652 * (in each case with the operation working on each element in
10653 * the input vectors):
10654 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10656 * (2) wide 64 x 128 -> 128
10657 * (3) narrowing 128 x 128 -> 64
10658 * Here we do initial decode, catch unallocated cases and
10659 * dispatch to separate functions for each class.
10661 int is_q
= extract32(insn
, 30, 1);
10662 int is_u
= extract32(insn
, 29, 1);
10663 int size
= extract32(insn
, 22, 2);
10664 int opcode
= extract32(insn
, 12, 4);
10665 int rm
= extract32(insn
, 16, 5);
10666 int rn
= extract32(insn
, 5, 5);
10667 int rd
= extract32(insn
, 0, 5);
10670 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10671 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10672 /* 64 x 128 -> 128 */
10674 unallocated_encoding(s
);
10677 if (!fp_access_check(s
)) {
10680 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10682 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10683 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10684 /* 128 x 128 -> 64 */
10686 unallocated_encoding(s
);
10689 if (!fp_access_check(s
)) {
10692 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10694 case 14: /* PMULL, PMULL2 */
10696 unallocated_encoding(s
);
10700 case 0: /* PMULL.P8 */
10701 if (!fp_access_check(s
)) {
10704 /* The Q field specifies lo/hi half input for this insn. */
10705 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10706 gen_helper_neon_pmull_h
);
10709 case 3: /* PMULL.P64 */
10710 if (!dc_isar_feature(aa64_pmull
, s
)) {
10711 unallocated_encoding(s
);
10714 if (!fp_access_check(s
)) {
10717 /* The Q field specifies lo/hi half input for this insn. */
10718 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10719 gen_helper_gvec_pmull_q
);
10723 unallocated_encoding(s
);
10727 case 9: /* SQDMLAL, SQDMLAL2 */
10728 case 11: /* SQDMLSL, SQDMLSL2 */
10729 case 13: /* SQDMULL, SQDMULL2 */
10730 if (is_u
|| size
== 0) {
10731 unallocated_encoding(s
);
10735 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10736 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10737 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10738 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10739 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10740 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10741 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10742 /* 64 x 64 -> 128 */
10744 unallocated_encoding(s
);
10747 if (!fp_access_check(s
)) {
10751 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10754 /* opcode 15 not allocated */
10755 unallocated_encoding(s
);
10760 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10761 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10763 int rd
= extract32(insn
, 0, 5);
10764 int rn
= extract32(insn
, 5, 5);
10765 int rm
= extract32(insn
, 16, 5);
10766 int size
= extract32(insn
, 22, 2);
10767 bool is_u
= extract32(insn
, 29, 1);
10768 bool is_q
= extract32(insn
, 30, 1);
10770 if (!fp_access_check(s
)) {
10774 switch (size
+ 4 * is_u
) {
10776 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10779 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10782 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10785 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10788 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10791 case 5: /* BSL bitwise select */
10792 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10794 case 6: /* BIT, bitwise insert if true */
10795 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10797 case 7: /* BIF, bitwise insert if false */
10798 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10802 g_assert_not_reached();
10806 /* Pairwise op subgroup of C3.6.16.
10808 * This is called directly or via the handle_3same_float for float pairwise
10809 * operations where the opcode and size are calculated differently.
10811 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10812 int size
, int rn
, int rm
, int rd
)
10817 /* Floating point operations need fpst */
10818 if (opcode
>= 0x58) {
10819 fpst
= fpstatus_ptr(FPST_FPCR
);
10824 if (!fp_access_check(s
)) {
10828 /* These operations work on the concatenated rm:rn, with each pair of
10829 * adjacent elements being operated on to produce an element in the result.
10832 TCGv_i64 tcg_res
[2];
10834 for (pass
= 0; pass
< 2; pass
++) {
10835 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10836 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10837 int passreg
= (pass
== 0) ? rn
: rm
;
10839 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10840 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10841 tcg_res
[pass
] = tcg_temp_new_i64();
10844 case 0x17: /* ADDP */
10845 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10847 case 0x58: /* FMAXNMP */
10848 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10850 case 0x5a: /* FADDP */
10851 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10853 case 0x5e: /* FMAXP */
10854 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10856 case 0x78: /* FMINNMP */
10857 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10859 case 0x7e: /* FMINP */
10860 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10863 g_assert_not_reached();
10867 for (pass
= 0; pass
< 2; pass
++) {
10868 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10871 int maxpass
= is_q
? 4 : 2;
10872 TCGv_i32 tcg_res
[4];
10874 for (pass
= 0; pass
< maxpass
; pass
++) {
10875 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10876 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10877 NeonGenTwoOpFn
*genfn
= NULL
;
10878 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10879 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10881 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10882 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10883 tcg_res
[pass
] = tcg_temp_new_i32();
10886 case 0x17: /* ADDP */
10888 static NeonGenTwoOpFn
* const fns
[3] = {
10889 gen_helper_neon_padd_u8
,
10890 gen_helper_neon_padd_u16
,
10896 case 0x14: /* SMAXP, UMAXP */
10898 static NeonGenTwoOpFn
* const fns
[3][2] = {
10899 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10900 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10901 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10903 genfn
= fns
[size
][u
];
10906 case 0x15: /* SMINP, UMINP */
10908 static NeonGenTwoOpFn
* const fns
[3][2] = {
10909 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10910 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10911 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10913 genfn
= fns
[size
][u
];
10916 /* The FP operations are all on single floats (32 bit) */
10917 case 0x58: /* FMAXNMP */
10918 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10920 case 0x5a: /* FADDP */
10921 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10923 case 0x5e: /* FMAXP */
10924 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10926 case 0x78: /* FMINNMP */
10927 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10929 case 0x7e: /* FMINP */
10930 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10933 g_assert_not_reached();
10936 /* FP ops called directly, otherwise call now */
10938 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10942 for (pass
= 0; pass
< maxpass
; pass
++) {
10943 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10945 clear_vec_high(s
, is_q
, rd
);
10949 /* Floating point op subgroup of C3.6.16. */
10950 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10952 /* For floating point ops, the U, size[1] and opcode bits
10953 * together indicate the operation. size[0] indicates single
10956 int fpopcode
= extract32(insn
, 11, 5)
10957 | (extract32(insn
, 23, 1) << 5)
10958 | (extract32(insn
, 29, 1) << 6);
10959 int is_q
= extract32(insn
, 30, 1);
10960 int size
= extract32(insn
, 22, 1);
10961 int rm
= extract32(insn
, 16, 5);
10962 int rn
= extract32(insn
, 5, 5);
10963 int rd
= extract32(insn
, 0, 5);
10965 int datasize
= is_q
? 128 : 64;
10966 int esize
= 32 << size
;
10967 int elements
= datasize
/ esize
;
10969 if (size
== 1 && !is_q
) {
10970 unallocated_encoding(s
);
10974 switch (fpopcode
) {
10975 case 0x58: /* FMAXNMP */
10976 case 0x5a: /* FADDP */
10977 case 0x5e: /* FMAXP */
10978 case 0x78: /* FMINNMP */
10979 case 0x7e: /* FMINP */
10980 if (size
&& !is_q
) {
10981 unallocated_encoding(s
);
10984 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10987 case 0x1b: /* FMULX */
10988 case 0x1f: /* FRECPS */
10989 case 0x3f: /* FRSQRTS */
10990 case 0x5d: /* FACGE */
10991 case 0x7d: /* FACGT */
10992 case 0x19: /* FMLA */
10993 case 0x39: /* FMLS */
10994 case 0x18: /* FMAXNM */
10995 case 0x1a: /* FADD */
10996 case 0x1c: /* FCMEQ */
10997 case 0x1e: /* FMAX */
10998 case 0x38: /* FMINNM */
10999 case 0x3a: /* FSUB */
11000 case 0x3e: /* FMIN */
11001 case 0x5b: /* FMUL */
11002 case 0x5c: /* FCMGE */
11003 case 0x5f: /* FDIV */
11004 case 0x7a: /* FABD */
11005 case 0x7c: /* FCMGT */
11006 if (!fp_access_check(s
)) {
11009 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11012 case 0x1d: /* FMLAL */
11013 case 0x3d: /* FMLSL */
11014 case 0x59: /* FMLAL2 */
11015 case 0x79: /* FMLSL2 */
11016 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11017 unallocated_encoding(s
);
11020 if (fp_access_check(s
)) {
11021 int is_s
= extract32(insn
, 23, 1);
11022 int is_2
= extract32(insn
, 29, 1);
11023 int data
= (is_2
<< 1) | is_s
;
11024 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11025 vec_full_reg_offset(s
, rn
),
11026 vec_full_reg_offset(s
, rm
), cpu_env
,
11027 is_q
? 16 : 8, vec_full_reg_size(s
),
11028 data
, gen_helper_gvec_fmlal_a64
);
11033 unallocated_encoding(s
);
11038 /* Integer op subgroup of C3.6.16. */
11039 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11041 int is_q
= extract32(insn
, 30, 1);
11042 int u
= extract32(insn
, 29, 1);
11043 int size
= extract32(insn
, 22, 2);
11044 int opcode
= extract32(insn
, 11, 5);
11045 int rm
= extract32(insn
, 16, 5);
11046 int rn
= extract32(insn
, 5, 5);
11047 int rd
= extract32(insn
, 0, 5);
11052 case 0x13: /* MUL, PMUL */
11053 if (u
&& size
!= 0) {
11054 unallocated_encoding(s
);
11058 case 0x0: /* SHADD, UHADD */
11059 case 0x2: /* SRHADD, URHADD */
11060 case 0x4: /* SHSUB, UHSUB */
11061 case 0xc: /* SMAX, UMAX */
11062 case 0xd: /* SMIN, UMIN */
11063 case 0xe: /* SABD, UABD */
11064 case 0xf: /* SABA, UABA */
11065 case 0x12: /* MLA, MLS */
11067 unallocated_encoding(s
);
11071 case 0x16: /* SQDMULH, SQRDMULH */
11072 if (size
== 0 || size
== 3) {
11073 unallocated_encoding(s
);
11078 if (size
== 3 && !is_q
) {
11079 unallocated_encoding(s
);
11085 if (!fp_access_check(s
)) {
11090 case 0x01: /* SQADD, UQADD */
11092 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11094 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11097 case 0x05: /* SQSUB, UQSUB */
11099 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11101 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11104 case 0x08: /* SSHL, USHL */
11106 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11108 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11111 case 0x0c: /* SMAX, UMAX */
11113 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11115 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11118 case 0x0d: /* SMIN, UMIN */
11120 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11122 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11125 case 0xe: /* SABD, UABD */
11127 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11129 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11132 case 0xf: /* SABA, UABA */
11134 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11136 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11139 case 0x10: /* ADD, SUB */
11141 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11143 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11146 case 0x13: /* MUL, PMUL */
11147 if (!u
) { /* MUL */
11148 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11149 } else { /* PMUL */
11150 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11153 case 0x12: /* MLA, MLS */
11155 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11157 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11160 case 0x16: /* SQDMULH, SQRDMULH */
11162 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11163 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11164 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11166 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11170 if (!u
) { /* CMTST */
11171 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11175 cond
= TCG_COND_EQ
;
11177 case 0x06: /* CMGT, CMHI */
11178 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11180 case 0x07: /* CMGE, CMHS */
11181 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11183 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11184 vec_full_reg_offset(s
, rn
),
11185 vec_full_reg_offset(s
, rm
),
11186 is_q
? 16 : 8, vec_full_reg_size(s
));
11192 for (pass
= 0; pass
< 2; pass
++) {
11193 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11194 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11195 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11197 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11198 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11200 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11202 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11205 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11206 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11207 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11208 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11209 NeonGenTwoOpFn
*genfn
= NULL
;
11210 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11212 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11213 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11216 case 0x0: /* SHADD, UHADD */
11218 static NeonGenTwoOpFn
* const fns
[3][2] = {
11219 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11220 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11221 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11223 genfn
= fns
[size
][u
];
11226 case 0x2: /* SRHADD, URHADD */
11228 static NeonGenTwoOpFn
* const fns
[3][2] = {
11229 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11230 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11231 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11233 genfn
= fns
[size
][u
];
11236 case 0x4: /* SHSUB, UHSUB */
11238 static NeonGenTwoOpFn
* const fns
[3][2] = {
11239 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11240 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11241 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11243 genfn
= fns
[size
][u
];
11246 case 0x9: /* SQSHL, UQSHL */
11248 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11249 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11250 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11251 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11253 genenvfn
= fns
[size
][u
];
11256 case 0xa: /* SRSHL, URSHL */
11258 static NeonGenTwoOpFn
* const fns
[3][2] = {
11259 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11260 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11261 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11263 genfn
= fns
[size
][u
];
11266 case 0xb: /* SQRSHL, UQRSHL */
11268 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11269 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11270 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11271 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11273 genenvfn
= fns
[size
][u
];
11277 g_assert_not_reached();
11281 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11283 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11286 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11289 clear_vec_high(s
, is_q
, rd
);
11292 /* AdvSIMD three same
11293 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11294 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11295 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11296 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11298 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11300 int opcode
= extract32(insn
, 11, 5);
11303 case 0x3: /* logic ops */
11304 disas_simd_3same_logic(s
, insn
);
11306 case 0x17: /* ADDP */
11307 case 0x14: /* SMAXP, UMAXP */
11308 case 0x15: /* SMINP, UMINP */
11310 /* Pairwise operations */
11311 int is_q
= extract32(insn
, 30, 1);
11312 int u
= extract32(insn
, 29, 1);
11313 int size
= extract32(insn
, 22, 2);
11314 int rm
= extract32(insn
, 16, 5);
11315 int rn
= extract32(insn
, 5, 5);
11316 int rd
= extract32(insn
, 0, 5);
11317 if (opcode
== 0x17) {
11318 if (u
|| (size
== 3 && !is_q
)) {
11319 unallocated_encoding(s
);
11324 unallocated_encoding(s
);
11328 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11331 case 0x18 ... 0x31:
11332 /* floating point ops, sz[1] and U are part of opcode */
11333 disas_simd_3same_float(s
, insn
);
11336 disas_simd_3same_int(s
, insn
);
11342 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11344 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11345 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11346 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11347 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11349 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11350 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11353 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11355 int opcode
= extract32(insn
, 11, 3);
11356 int u
= extract32(insn
, 29, 1);
11357 int a
= extract32(insn
, 23, 1);
11358 int is_q
= extract32(insn
, 30, 1);
11359 int rm
= extract32(insn
, 16, 5);
11360 int rn
= extract32(insn
, 5, 5);
11361 int rd
= extract32(insn
, 0, 5);
11363 * For these floating point ops, the U, a and opcode bits
11364 * together indicate the operation.
11366 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11367 int datasize
= is_q
? 128 : 64;
11368 int elements
= datasize
/ 16;
11373 switch (fpopcode
) {
11374 case 0x0: /* FMAXNM */
11375 case 0x1: /* FMLA */
11376 case 0x2: /* FADD */
11377 case 0x3: /* FMULX */
11378 case 0x4: /* FCMEQ */
11379 case 0x6: /* FMAX */
11380 case 0x7: /* FRECPS */
11381 case 0x8: /* FMINNM */
11382 case 0x9: /* FMLS */
11383 case 0xa: /* FSUB */
11384 case 0xe: /* FMIN */
11385 case 0xf: /* FRSQRTS */
11386 case 0x13: /* FMUL */
11387 case 0x14: /* FCMGE */
11388 case 0x15: /* FACGE */
11389 case 0x17: /* FDIV */
11390 case 0x1a: /* FABD */
11391 case 0x1c: /* FCMGT */
11392 case 0x1d: /* FACGT */
11395 case 0x10: /* FMAXNMP */
11396 case 0x12: /* FADDP */
11397 case 0x16: /* FMAXP */
11398 case 0x18: /* FMINNMP */
11399 case 0x1e: /* FMINP */
11403 unallocated_encoding(s
);
11407 if (!dc_isar_feature(aa64_fp16
, s
)) {
11408 unallocated_encoding(s
);
11412 if (!fp_access_check(s
)) {
11416 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
11419 int maxpass
= is_q
? 8 : 4;
11420 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11421 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11422 TCGv_i32 tcg_res
[8];
11424 for (pass
= 0; pass
< maxpass
; pass
++) {
11425 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11426 int passelt
= (pass
<< 1) & (maxpass
- 1);
11428 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11429 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11430 tcg_res
[pass
] = tcg_temp_new_i32();
11432 switch (fpopcode
) {
11433 case 0x10: /* FMAXNMP */
11434 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11437 case 0x12: /* FADDP */
11438 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11440 case 0x16: /* FMAXP */
11441 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11443 case 0x18: /* FMINNMP */
11444 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11447 case 0x1e: /* FMINP */
11448 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11451 g_assert_not_reached();
11455 for (pass
= 0; pass
< maxpass
; pass
++) {
11456 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11459 for (pass
= 0; pass
< elements
; pass
++) {
11460 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11461 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11462 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11464 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11465 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11467 switch (fpopcode
) {
11468 case 0x0: /* FMAXNM */
11469 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11471 case 0x1: /* FMLA */
11472 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11473 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11476 case 0x2: /* FADD */
11477 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11479 case 0x3: /* FMULX */
11480 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11482 case 0x4: /* FCMEQ */
11483 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11485 case 0x6: /* FMAX */
11486 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11488 case 0x7: /* FRECPS */
11489 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11491 case 0x8: /* FMINNM */
11492 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11494 case 0x9: /* FMLS */
11495 /* As usual for ARM, separate negation for fused multiply-add */
11496 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11497 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11498 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11501 case 0xa: /* FSUB */
11502 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11504 case 0xe: /* FMIN */
11505 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11507 case 0xf: /* FRSQRTS */
11508 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11510 case 0x13: /* FMUL */
11511 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11513 case 0x14: /* FCMGE */
11514 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11516 case 0x15: /* FACGE */
11517 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11519 case 0x17: /* FDIV */
11520 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11522 case 0x1a: /* FABD */
11523 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11524 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11526 case 0x1c: /* FCMGT */
11527 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11529 case 0x1d: /* FACGT */
11530 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11533 g_assert_not_reached();
11536 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11540 clear_vec_high(s
, is_q
, rd
);
11543 /* AdvSIMD three same extra
11544 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11545 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11546 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11547 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11549 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11551 int rd
= extract32(insn
, 0, 5);
11552 int rn
= extract32(insn
, 5, 5);
11553 int opcode
= extract32(insn
, 11, 4);
11554 int rm
= extract32(insn
, 16, 5);
11555 int size
= extract32(insn
, 22, 2);
11556 bool u
= extract32(insn
, 29, 1);
11557 bool is_q
= extract32(insn
, 30, 1);
11561 switch (u
* 16 + opcode
) {
11562 case 0x10: /* SQRDMLAH (vector) */
11563 case 0x11: /* SQRDMLSH (vector) */
11564 if (size
!= 1 && size
!= 2) {
11565 unallocated_encoding(s
);
11568 feature
= dc_isar_feature(aa64_rdm
, s
);
11570 case 0x02: /* SDOT (vector) */
11571 case 0x12: /* UDOT (vector) */
11572 if (size
!= MO_32
) {
11573 unallocated_encoding(s
);
11576 feature
= dc_isar_feature(aa64_dp
, s
);
11578 case 0x03: /* USDOT */
11579 if (size
!= MO_32
) {
11580 unallocated_encoding(s
);
11583 feature
= dc_isar_feature(aa64_i8mm
, s
);
11585 case 0x04: /* SMMLA */
11586 case 0x14: /* UMMLA */
11587 case 0x05: /* USMMLA */
11588 if (!is_q
|| size
!= MO_32
) {
11589 unallocated_encoding(s
);
11592 feature
= dc_isar_feature(aa64_i8mm
, s
);
11594 case 0x18: /* FCMLA, #0 */
11595 case 0x19: /* FCMLA, #90 */
11596 case 0x1a: /* FCMLA, #180 */
11597 case 0x1b: /* FCMLA, #270 */
11598 case 0x1c: /* FCADD, #90 */
11599 case 0x1e: /* FCADD, #270 */
11601 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11602 || (size
== 3 && !is_q
)) {
11603 unallocated_encoding(s
);
11606 feature
= dc_isar_feature(aa64_fcma
, s
);
11608 case 0x1d: /* BFMMLA */
11609 if (size
!= MO_16
|| !is_q
) {
11610 unallocated_encoding(s
);
11613 feature
= dc_isar_feature(aa64_bf16
, s
);
11617 case 1: /* BFDOT */
11618 case 3: /* BFMLAL{B,T} */
11619 feature
= dc_isar_feature(aa64_bf16
, s
);
11622 unallocated_encoding(s
);
11627 unallocated_encoding(s
);
11631 unallocated_encoding(s
);
11634 if (!fp_access_check(s
)) {
11639 case 0x0: /* SQRDMLAH (vector) */
11640 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
11643 case 0x1: /* SQRDMLSH (vector) */
11644 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
11647 case 0x2: /* SDOT / UDOT */
11648 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0,
11649 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11652 case 0x3: /* USDOT */
11653 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usdot_b
);
11656 case 0x04: /* SMMLA, UMMLA */
11657 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0,
11658 u
? gen_helper_gvec_ummla_b
11659 : gen_helper_gvec_smmla_b
);
11661 case 0x05: /* USMMLA */
11662 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usmmla_b
);
11665 case 0x8: /* FCMLA, #0 */
11666 case 0x9: /* FCMLA, #90 */
11667 case 0xa: /* FCMLA, #180 */
11668 case 0xb: /* FCMLA, #270 */
11669 rot
= extract32(opcode
, 0, 2);
11672 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, true, rot
,
11673 gen_helper_gvec_fcmlah
);
11676 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
11677 gen_helper_gvec_fcmlas
);
11680 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
11681 gen_helper_gvec_fcmlad
);
11684 g_assert_not_reached();
11688 case 0xc: /* FCADD, #90 */
11689 case 0xe: /* FCADD, #270 */
11690 rot
= extract32(opcode
, 1, 1);
11693 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11694 gen_helper_gvec_fcaddh
);
11697 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11698 gen_helper_gvec_fcadds
);
11701 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11702 gen_helper_gvec_fcaddd
);
11705 g_assert_not_reached();
11709 case 0xd: /* BFMMLA */
11710 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfmmla
);
11714 case 1: /* BFDOT */
11715 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfdot
);
11717 case 3: /* BFMLAL{B,T} */
11718 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, false, is_q
,
11719 gen_helper_gvec_bfmlal
);
11722 g_assert_not_reached();
11727 g_assert_not_reached();
11731 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11732 int size
, int rn
, int rd
)
11734 /* Handle 2-reg-misc ops which are widening (so each size element
11735 * in the source becomes a 2*size element in the destination.
11736 * The only instruction like this is FCVTL.
11741 /* 32 -> 64 bit fp conversion */
11742 TCGv_i64 tcg_res
[2];
11743 int srcelt
= is_q
? 2 : 0;
11745 for (pass
= 0; pass
< 2; pass
++) {
11746 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11747 tcg_res
[pass
] = tcg_temp_new_i64();
11749 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11750 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11752 for (pass
= 0; pass
< 2; pass
++) {
11753 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11756 /* 16 -> 32 bit fp conversion */
11757 int srcelt
= is_q
? 4 : 0;
11758 TCGv_i32 tcg_res
[4];
11759 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
11760 TCGv_i32 ahp
= get_ahp_flag();
11762 for (pass
= 0; pass
< 4; pass
++) {
11763 tcg_res
[pass
] = tcg_temp_new_i32();
11765 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11766 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11769 for (pass
= 0; pass
< 4; pass
++) {
11770 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11775 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11776 bool is_q
, int size
, int rn
, int rd
)
11778 int op
= (opcode
<< 1) | u
;
11779 int opsz
= op
+ size
;
11780 int grp_size
= 3 - opsz
;
11781 int dsize
= is_q
? 128 : 64;
11785 unallocated_encoding(s
);
11789 if (!fp_access_check(s
)) {
11794 /* Special case bytes, use bswap op on each group of elements */
11795 int groups
= dsize
/ (8 << grp_size
);
11797 for (i
= 0; i
< groups
; i
++) {
11798 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11800 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11801 switch (grp_size
) {
11803 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
11806 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
11809 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11812 g_assert_not_reached();
11814 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11816 clear_vec_high(s
, is_q
, rd
);
11818 int revmask
= (1 << grp_size
) - 1;
11819 int esize
= 8 << size
;
11820 int elements
= dsize
/ esize
;
11821 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11822 TCGv_i64 tcg_rd
[2];
11824 for (i
= 0; i
< 2; i
++) {
11825 tcg_rd
[i
] = tcg_temp_new_i64();
11826 tcg_gen_movi_i64(tcg_rd
[i
], 0);
11829 for (i
= 0; i
< elements
; i
++) {
11830 int e_rev
= (i
& 0xf) ^ revmask
;
11831 int w
= (e_rev
* esize
) / 64;
11832 int o
= (e_rev
* esize
) % 64;
11834 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11835 tcg_gen_deposit_i64(tcg_rd
[w
], tcg_rd
[w
], tcg_rn
, o
, esize
);
11838 for (i
= 0; i
< 2; i
++) {
11839 write_vec_element(s
, tcg_rd
[i
], rd
, i
, MO_64
);
11841 clear_vec_high(s
, true, rd
);
11845 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11846 bool is_q
, int size
, int rn
, int rd
)
11848 /* Implement the pairwise operations from 2-misc:
11849 * SADDLP, UADDLP, SADALP, UADALP.
11850 * These all add pairs of elements in the input to produce a
11851 * double-width result element in the output (possibly accumulating).
11853 bool accum
= (opcode
== 0x6);
11854 int maxpass
= is_q
? 2 : 1;
11856 TCGv_i64 tcg_res
[2];
11859 /* 32 + 32 -> 64 op */
11860 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11862 for (pass
= 0; pass
< maxpass
; pass
++) {
11863 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11864 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11866 tcg_res
[pass
] = tcg_temp_new_i64();
11868 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11869 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11870 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11872 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11873 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11877 for (pass
= 0; pass
< maxpass
; pass
++) {
11878 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11879 NeonGenOne64OpFn
*genfn
;
11880 static NeonGenOne64OpFn
* const fns
[2][2] = {
11881 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11882 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11885 genfn
= fns
[size
][u
];
11887 tcg_res
[pass
] = tcg_temp_new_i64();
11889 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11890 genfn(tcg_res
[pass
], tcg_op
);
11893 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11895 gen_helper_neon_addl_u16(tcg_res
[pass
],
11896 tcg_res
[pass
], tcg_op
);
11898 gen_helper_neon_addl_u32(tcg_res
[pass
],
11899 tcg_res
[pass
], tcg_op
);
11905 tcg_res
[1] = tcg_constant_i64(0);
11907 for (pass
= 0; pass
< 2; pass
++) {
11908 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11912 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11914 /* Implement SHLL and SHLL2 */
11916 int part
= is_q
? 2 : 0;
11917 TCGv_i64 tcg_res
[2];
11919 for (pass
= 0; pass
< 2; pass
++) {
11920 static NeonGenWidenFn
* const widenfns
[3] = {
11921 gen_helper_neon_widen_u8
,
11922 gen_helper_neon_widen_u16
,
11923 tcg_gen_extu_i32_i64
,
11925 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11926 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11928 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11929 tcg_res
[pass
] = tcg_temp_new_i64();
11930 widenfn(tcg_res
[pass
], tcg_op
);
11931 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11934 for (pass
= 0; pass
< 2; pass
++) {
11935 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11939 /* AdvSIMD two reg misc
11940 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11941 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11942 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11943 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11945 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11947 int size
= extract32(insn
, 22, 2);
11948 int opcode
= extract32(insn
, 12, 5);
11949 bool u
= extract32(insn
, 29, 1);
11950 bool is_q
= extract32(insn
, 30, 1);
11951 int rn
= extract32(insn
, 5, 5);
11952 int rd
= extract32(insn
, 0, 5);
11953 bool need_fpstatus
= false;
11955 TCGv_i32 tcg_rmode
;
11956 TCGv_ptr tcg_fpstatus
;
11959 case 0x0: /* REV64, REV32 */
11960 case 0x1: /* REV16 */
11961 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11963 case 0x5: /* CNT, NOT, RBIT */
11964 if (u
&& size
== 0) {
11967 } else if (u
&& size
== 1) {
11970 } else if (!u
&& size
== 0) {
11974 unallocated_encoding(s
);
11976 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11977 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11979 unallocated_encoding(s
);
11982 if (!fp_access_check(s
)) {
11986 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11988 case 0x4: /* CLS, CLZ */
11990 unallocated_encoding(s
);
11994 case 0x2: /* SADDLP, UADDLP */
11995 case 0x6: /* SADALP, UADALP */
11997 unallocated_encoding(s
);
12000 if (!fp_access_check(s
)) {
12003 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12005 case 0x13: /* SHLL, SHLL2 */
12006 if (u
== 0 || size
== 3) {
12007 unallocated_encoding(s
);
12010 if (!fp_access_check(s
)) {
12013 handle_shll(s
, is_q
, size
, rn
, rd
);
12015 case 0xa: /* CMLT */
12017 unallocated_encoding(s
);
12021 case 0x8: /* CMGT, CMGE */
12022 case 0x9: /* CMEQ, CMLE */
12023 case 0xb: /* ABS, NEG */
12024 if (size
== 3 && !is_q
) {
12025 unallocated_encoding(s
);
12029 case 0x3: /* SUQADD, USQADD */
12030 if (size
== 3 && !is_q
) {
12031 unallocated_encoding(s
);
12034 if (!fp_access_check(s
)) {
12037 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12039 case 0x7: /* SQABS, SQNEG */
12040 if (size
== 3 && !is_q
) {
12041 unallocated_encoding(s
);
12046 case 0x16 ... 0x1f:
12048 /* Floating point: U, size[1] and opcode indicate operation;
12049 * size[0] indicates single or double precision.
12051 int is_double
= extract32(size
, 0, 1);
12052 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12053 size
= is_double
? 3 : 2;
12055 case 0x2f: /* FABS */
12056 case 0x6f: /* FNEG */
12057 if (size
== 3 && !is_q
) {
12058 unallocated_encoding(s
);
12062 case 0x1d: /* SCVTF */
12063 case 0x5d: /* UCVTF */
12065 bool is_signed
= (opcode
== 0x1d) ? true : false;
12066 int elements
= is_double
? 2 : is_q
? 4 : 2;
12067 if (is_double
&& !is_q
) {
12068 unallocated_encoding(s
);
12071 if (!fp_access_check(s
)) {
12074 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12077 case 0x2c: /* FCMGT (zero) */
12078 case 0x2d: /* FCMEQ (zero) */
12079 case 0x2e: /* FCMLT (zero) */
12080 case 0x6c: /* FCMGE (zero) */
12081 case 0x6d: /* FCMLE (zero) */
12082 if (size
== 3 && !is_q
) {
12083 unallocated_encoding(s
);
12086 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12088 case 0x7f: /* FSQRT */
12089 if (size
== 3 && !is_q
) {
12090 unallocated_encoding(s
);
12094 case 0x1a: /* FCVTNS */
12095 case 0x1b: /* FCVTMS */
12096 case 0x3a: /* FCVTPS */
12097 case 0x3b: /* FCVTZS */
12098 case 0x5a: /* FCVTNU */
12099 case 0x5b: /* FCVTMU */
12100 case 0x7a: /* FCVTPU */
12101 case 0x7b: /* FCVTZU */
12102 need_fpstatus
= true;
12103 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12104 if (size
== 3 && !is_q
) {
12105 unallocated_encoding(s
);
12109 case 0x5c: /* FCVTAU */
12110 case 0x1c: /* FCVTAS */
12111 need_fpstatus
= true;
12112 rmode
= FPROUNDING_TIEAWAY
;
12113 if (size
== 3 && !is_q
) {
12114 unallocated_encoding(s
);
12118 case 0x3c: /* URECPE */
12120 unallocated_encoding(s
);
12124 case 0x3d: /* FRECPE */
12125 case 0x7d: /* FRSQRTE */
12126 if (size
== 3 && !is_q
) {
12127 unallocated_encoding(s
);
12130 if (!fp_access_check(s
)) {
12133 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12135 case 0x56: /* FCVTXN, FCVTXN2 */
12137 unallocated_encoding(s
);
12141 case 0x16: /* FCVTN, FCVTN2 */
12142 /* handle_2misc_narrow does a 2*size -> size operation, but these
12143 * instructions encode the source size rather than dest size.
12145 if (!fp_access_check(s
)) {
12148 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12150 case 0x36: /* BFCVTN, BFCVTN2 */
12151 if (!dc_isar_feature(aa64_bf16
, s
) || size
!= 2) {
12152 unallocated_encoding(s
);
12155 if (!fp_access_check(s
)) {
12158 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12160 case 0x17: /* FCVTL, FCVTL2 */
12161 if (!fp_access_check(s
)) {
12164 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12166 case 0x18: /* FRINTN */
12167 case 0x19: /* FRINTM */
12168 case 0x38: /* FRINTP */
12169 case 0x39: /* FRINTZ */
12170 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12172 case 0x59: /* FRINTX */
12173 case 0x79: /* FRINTI */
12174 need_fpstatus
= true;
12175 if (size
== 3 && !is_q
) {
12176 unallocated_encoding(s
);
12180 case 0x58: /* FRINTA */
12181 rmode
= FPROUNDING_TIEAWAY
;
12182 need_fpstatus
= true;
12183 if (size
== 3 && !is_q
) {
12184 unallocated_encoding(s
);
12188 case 0x7c: /* URSQRTE */
12190 unallocated_encoding(s
);
12194 case 0x1e: /* FRINT32Z */
12195 case 0x1f: /* FRINT64Z */
12196 rmode
= FPROUNDING_ZERO
;
12198 case 0x5e: /* FRINT32X */
12199 case 0x5f: /* FRINT64X */
12200 need_fpstatus
= true;
12201 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12202 unallocated_encoding(s
);
12207 unallocated_encoding(s
);
12213 unallocated_encoding(s
);
12217 if (!fp_access_check(s
)) {
12221 if (need_fpstatus
|| rmode
>= 0) {
12222 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12224 tcg_fpstatus
= NULL
;
12227 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
12234 if (u
&& size
== 0) { /* NOT */
12235 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12239 case 0x8: /* CMGT, CMGE */
12241 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12243 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12246 case 0x9: /* CMEQ, CMLE */
12248 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12250 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12253 case 0xa: /* CMLT */
12254 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12257 if (u
) { /* ABS, NEG */
12258 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12260 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12266 /* All 64-bit element operations can be shared with scalar 2misc */
12269 /* Coverity claims (size == 3 && !is_q) has been eliminated
12270 * from all paths leading to here.
12272 tcg_debug_assert(is_q
);
12273 for (pass
= 0; pass
< 2; pass
++) {
12274 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12275 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12277 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12279 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12280 tcg_rmode
, tcg_fpstatus
);
12282 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12287 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12288 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12289 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12291 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12294 /* Special cases for 32 bit elements */
12296 case 0x4: /* CLS */
12298 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12300 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12303 case 0x7: /* SQABS, SQNEG */
12305 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12307 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12310 case 0x2f: /* FABS */
12311 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12313 case 0x6f: /* FNEG */
12314 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12316 case 0x7f: /* FSQRT */
12317 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12319 case 0x1a: /* FCVTNS */
12320 case 0x1b: /* FCVTMS */
12321 case 0x1c: /* FCVTAS */
12322 case 0x3a: /* FCVTPS */
12323 case 0x3b: /* FCVTZS */
12324 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12325 tcg_constant_i32(0), tcg_fpstatus
);
12327 case 0x5a: /* FCVTNU */
12328 case 0x5b: /* FCVTMU */
12329 case 0x5c: /* FCVTAU */
12330 case 0x7a: /* FCVTPU */
12331 case 0x7b: /* FCVTZU */
12332 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12333 tcg_constant_i32(0), tcg_fpstatus
);
12335 case 0x18: /* FRINTN */
12336 case 0x19: /* FRINTM */
12337 case 0x38: /* FRINTP */
12338 case 0x39: /* FRINTZ */
12339 case 0x58: /* FRINTA */
12340 case 0x79: /* FRINTI */
12341 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12343 case 0x59: /* FRINTX */
12344 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12346 case 0x7c: /* URSQRTE */
12347 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12349 case 0x1e: /* FRINT32Z */
12350 case 0x5e: /* FRINT32X */
12351 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12353 case 0x1f: /* FRINT64Z */
12354 case 0x5f: /* FRINT64X */
12355 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12358 g_assert_not_reached();
12361 /* Use helpers for 8 and 16 bit elements */
12363 case 0x5: /* CNT, RBIT */
12364 /* For these two insns size is part of the opcode specifier
12365 * (handled earlier); they always operate on byte elements.
12368 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12370 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12373 case 0x7: /* SQABS, SQNEG */
12375 NeonGenOneOpEnvFn
*genfn
;
12376 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12377 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12378 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12380 genfn
= fns
[size
][u
];
12381 genfn(tcg_res
, cpu_env
, tcg_op
);
12384 case 0x4: /* CLS, CLZ */
12387 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12389 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12393 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12395 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12400 g_assert_not_reached();
12404 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12407 clear_vec_high(s
, is_q
, rd
);
12410 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
12414 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12416 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12417 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12418 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12419 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12420 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12421 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12423 * This actually covers two groups where scalar access is governed by
12424 * bit 28. A bunch of the instructions (float to integral) only exist
12425 * in the vector form and are un-allocated for the scalar decode. Also
12426 * in the scalar decode Q is always 1.
12428 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12430 int fpop
, opcode
, a
, u
;
12434 bool only_in_vector
= false;
12437 TCGv_i32 tcg_rmode
= NULL
;
12438 TCGv_ptr tcg_fpstatus
= NULL
;
12439 bool need_fpst
= true;
12442 if (!dc_isar_feature(aa64_fp16
, s
)) {
12443 unallocated_encoding(s
);
12447 rd
= extract32(insn
, 0, 5);
12448 rn
= extract32(insn
, 5, 5);
12450 a
= extract32(insn
, 23, 1);
12451 u
= extract32(insn
, 29, 1);
12452 is_scalar
= extract32(insn
, 28, 1);
12453 is_q
= extract32(insn
, 30, 1);
12455 opcode
= extract32(insn
, 12, 5);
12456 fpop
= deposit32(opcode
, 5, 1, a
);
12457 fpop
= deposit32(fpop
, 6, 1, u
);
12460 case 0x1d: /* SCVTF */
12461 case 0x5d: /* UCVTF */
12468 elements
= (is_q
? 8 : 4);
12471 if (!fp_access_check(s
)) {
12474 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12478 case 0x2c: /* FCMGT (zero) */
12479 case 0x2d: /* FCMEQ (zero) */
12480 case 0x2e: /* FCMLT (zero) */
12481 case 0x6c: /* FCMGE (zero) */
12482 case 0x6d: /* FCMLE (zero) */
12483 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12485 case 0x3d: /* FRECPE */
12486 case 0x3f: /* FRECPX */
12488 case 0x18: /* FRINTN */
12489 only_in_vector
= true;
12490 rmode
= FPROUNDING_TIEEVEN
;
12492 case 0x19: /* FRINTM */
12493 only_in_vector
= true;
12494 rmode
= FPROUNDING_NEGINF
;
12496 case 0x38: /* FRINTP */
12497 only_in_vector
= true;
12498 rmode
= FPROUNDING_POSINF
;
12500 case 0x39: /* FRINTZ */
12501 only_in_vector
= true;
12502 rmode
= FPROUNDING_ZERO
;
12504 case 0x58: /* FRINTA */
12505 only_in_vector
= true;
12506 rmode
= FPROUNDING_TIEAWAY
;
12508 case 0x59: /* FRINTX */
12509 case 0x79: /* FRINTI */
12510 only_in_vector
= true;
12511 /* current rounding mode */
12513 case 0x1a: /* FCVTNS */
12514 rmode
= FPROUNDING_TIEEVEN
;
12516 case 0x1b: /* FCVTMS */
12517 rmode
= FPROUNDING_NEGINF
;
12519 case 0x1c: /* FCVTAS */
12520 rmode
= FPROUNDING_TIEAWAY
;
12522 case 0x3a: /* FCVTPS */
12523 rmode
= FPROUNDING_POSINF
;
12525 case 0x3b: /* FCVTZS */
12526 rmode
= FPROUNDING_ZERO
;
12528 case 0x5a: /* FCVTNU */
12529 rmode
= FPROUNDING_TIEEVEN
;
12531 case 0x5b: /* FCVTMU */
12532 rmode
= FPROUNDING_NEGINF
;
12534 case 0x5c: /* FCVTAU */
12535 rmode
= FPROUNDING_TIEAWAY
;
12537 case 0x7a: /* FCVTPU */
12538 rmode
= FPROUNDING_POSINF
;
12540 case 0x7b: /* FCVTZU */
12541 rmode
= FPROUNDING_ZERO
;
12543 case 0x2f: /* FABS */
12544 case 0x6f: /* FNEG */
12547 case 0x7d: /* FRSQRTE */
12548 case 0x7f: /* FSQRT (vector) */
12551 unallocated_encoding(s
);
12556 /* Check additional constraints for the scalar encoding */
12559 unallocated_encoding(s
);
12562 /* FRINTxx is only in the vector form */
12563 if (only_in_vector
) {
12564 unallocated_encoding(s
);
12569 if (!fp_access_check(s
)) {
12573 if (rmode
>= 0 || need_fpst
) {
12574 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
12578 tcg_rmode
= gen_set_rmode(rmode
, tcg_fpstatus
);
12582 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12583 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12586 case 0x1a: /* FCVTNS */
12587 case 0x1b: /* FCVTMS */
12588 case 0x1c: /* FCVTAS */
12589 case 0x3a: /* FCVTPS */
12590 case 0x3b: /* FCVTZS */
12591 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12593 case 0x3d: /* FRECPE */
12594 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12596 case 0x3f: /* FRECPX */
12597 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12599 case 0x5a: /* FCVTNU */
12600 case 0x5b: /* FCVTMU */
12601 case 0x5c: /* FCVTAU */
12602 case 0x7a: /* FCVTPU */
12603 case 0x7b: /* FCVTZU */
12604 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12606 case 0x6f: /* FNEG */
12607 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12609 case 0x7d: /* FRSQRTE */
12610 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12613 g_assert_not_reached();
12616 /* limit any sign extension going on */
12617 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12618 write_fp_sreg(s
, rd
, tcg_res
);
12620 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12621 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12622 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12624 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12627 case 0x1a: /* FCVTNS */
12628 case 0x1b: /* FCVTMS */
12629 case 0x1c: /* FCVTAS */
12630 case 0x3a: /* FCVTPS */
12631 case 0x3b: /* FCVTZS */
12632 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12634 case 0x3d: /* FRECPE */
12635 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12637 case 0x5a: /* FCVTNU */
12638 case 0x5b: /* FCVTMU */
12639 case 0x5c: /* FCVTAU */
12640 case 0x7a: /* FCVTPU */
12641 case 0x7b: /* FCVTZU */
12642 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12644 case 0x18: /* FRINTN */
12645 case 0x19: /* FRINTM */
12646 case 0x38: /* FRINTP */
12647 case 0x39: /* FRINTZ */
12648 case 0x58: /* FRINTA */
12649 case 0x79: /* FRINTI */
12650 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12652 case 0x59: /* FRINTX */
12653 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12655 case 0x2f: /* FABS */
12656 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12658 case 0x6f: /* FNEG */
12659 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12661 case 0x7d: /* FRSQRTE */
12662 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12664 case 0x7f: /* FSQRT */
12665 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12668 g_assert_not_reached();
12671 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12674 clear_vec_high(s
, is_q
, rd
);
12678 gen_restore_rmode(tcg_rmode
, tcg_fpstatus
);
12682 /* AdvSIMD scalar x indexed element
12683 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12684 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12685 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12686 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12687 * AdvSIMD vector x indexed element
12688 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12689 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12690 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12691 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12693 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12695 /* This encoding has two kinds of instruction:
12696 * normal, where we perform elt x idxelt => elt for each
12697 * element in the vector
12698 * long, where we perform elt x idxelt and generate a result of
12699 * double the width of the input element
12700 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12702 bool is_scalar
= extract32(insn
, 28, 1);
12703 bool is_q
= extract32(insn
, 30, 1);
12704 bool u
= extract32(insn
, 29, 1);
12705 int size
= extract32(insn
, 22, 2);
12706 int l
= extract32(insn
, 21, 1);
12707 int m
= extract32(insn
, 20, 1);
12708 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12709 int rm
= extract32(insn
, 16, 4);
12710 int opcode
= extract32(insn
, 12, 4);
12711 int h
= extract32(insn
, 11, 1);
12712 int rn
= extract32(insn
, 5, 5);
12713 int rd
= extract32(insn
, 0, 5);
12714 bool is_long
= false;
12716 bool is_fp16
= false;
12720 switch (16 * u
+ opcode
) {
12721 case 0x08: /* MUL */
12722 case 0x10: /* MLA */
12723 case 0x14: /* MLS */
12725 unallocated_encoding(s
);
12729 case 0x02: /* SMLAL, SMLAL2 */
12730 case 0x12: /* UMLAL, UMLAL2 */
12731 case 0x06: /* SMLSL, SMLSL2 */
12732 case 0x16: /* UMLSL, UMLSL2 */
12733 case 0x0a: /* SMULL, SMULL2 */
12734 case 0x1a: /* UMULL, UMULL2 */
12736 unallocated_encoding(s
);
12741 case 0x03: /* SQDMLAL, SQDMLAL2 */
12742 case 0x07: /* SQDMLSL, SQDMLSL2 */
12743 case 0x0b: /* SQDMULL, SQDMULL2 */
12746 case 0x0c: /* SQDMULH */
12747 case 0x0d: /* SQRDMULH */
12749 case 0x01: /* FMLA */
12750 case 0x05: /* FMLS */
12751 case 0x09: /* FMUL */
12752 case 0x19: /* FMULX */
12755 case 0x1d: /* SQRDMLAH */
12756 case 0x1f: /* SQRDMLSH */
12757 if (!dc_isar_feature(aa64_rdm
, s
)) {
12758 unallocated_encoding(s
);
12762 case 0x0e: /* SDOT */
12763 case 0x1e: /* UDOT */
12764 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12765 unallocated_encoding(s
);
12771 case 0: /* SUDOT */
12772 case 2: /* USDOT */
12773 if (is_scalar
|| !dc_isar_feature(aa64_i8mm
, s
)) {
12774 unallocated_encoding(s
);
12779 case 1: /* BFDOT */
12780 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
12781 unallocated_encoding(s
);
12786 case 3: /* BFMLAL{B,T} */
12787 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
12788 unallocated_encoding(s
);
12791 /* can't set is_fp without other incorrect size checks */
12795 unallocated_encoding(s
);
12799 case 0x11: /* FCMLA #0 */
12800 case 0x13: /* FCMLA #90 */
12801 case 0x15: /* FCMLA #180 */
12802 case 0x17: /* FCMLA #270 */
12803 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12804 unallocated_encoding(s
);
12809 case 0x00: /* FMLAL */
12810 case 0x04: /* FMLSL */
12811 case 0x18: /* FMLAL2 */
12812 case 0x1c: /* FMLSL2 */
12813 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12814 unallocated_encoding(s
);
12818 /* is_fp, but we pass cpu_env not fp_status. */
12821 unallocated_encoding(s
);
12826 case 1: /* normal fp */
12827 /* convert insn encoded size to MemOp size */
12829 case 0: /* half-precision */
12833 case MO_32
: /* single precision */
12834 case MO_64
: /* double precision */
12837 unallocated_encoding(s
);
12842 case 2: /* complex fp */
12843 /* Each indexable element is a complex pair. */
12848 unallocated_encoding(s
);
12856 unallocated_encoding(s
);
12861 default: /* integer */
12865 unallocated_encoding(s
);
12870 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12871 unallocated_encoding(s
);
12875 /* Given MemOp size, adjust register and indexing. */
12878 index
= h
<< 2 | l
<< 1 | m
;
12881 index
= h
<< 1 | l
;
12886 unallocated_encoding(s
);
12893 g_assert_not_reached();
12896 if (!fp_access_check(s
)) {
12901 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
12906 switch (16 * u
+ opcode
) {
12907 case 0x0e: /* SDOT */
12908 case 0x1e: /* UDOT */
12909 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
12910 u
? gen_helper_gvec_udot_idx_b
12911 : gen_helper_gvec_sdot_idx_b
);
12914 switch (extract32(insn
, 22, 2)) {
12915 case 0: /* SUDOT */
12916 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
12917 gen_helper_gvec_sudot_idx_b
);
12919 case 1: /* BFDOT */
12920 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
12921 gen_helper_gvec_bfdot_idx
);
12923 case 2: /* USDOT */
12924 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
12925 gen_helper_gvec_usdot_idx_b
);
12927 case 3: /* BFMLAL{B,T} */
12928 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, 0, (index
<< 1) | is_q
,
12929 gen_helper_gvec_bfmlal_idx
);
12932 g_assert_not_reached();
12933 case 0x11: /* FCMLA #0 */
12934 case 0x13: /* FCMLA #90 */
12935 case 0x15: /* FCMLA #180 */
12936 case 0x17: /* FCMLA #270 */
12938 int rot
= extract32(insn
, 13, 2);
12939 int data
= (index
<< 2) | rot
;
12940 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
12941 vec_full_reg_offset(s
, rn
),
12942 vec_full_reg_offset(s
, rm
),
12943 vec_full_reg_offset(s
, rd
), fpst
,
12944 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12946 ? gen_helper_gvec_fcmlas_idx
12947 : gen_helper_gvec_fcmlah_idx
);
12951 case 0x00: /* FMLAL */
12952 case 0x04: /* FMLSL */
12953 case 0x18: /* FMLAL2 */
12954 case 0x1c: /* FMLSL2 */
12956 int is_s
= extract32(opcode
, 2, 1);
12958 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
12959 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12960 vec_full_reg_offset(s
, rn
),
12961 vec_full_reg_offset(s
, rm
), cpu_env
,
12962 is_q
? 16 : 8, vec_full_reg_size(s
),
12963 data
, gen_helper_gvec_fmlal_idx_a64
);
12967 case 0x08: /* MUL */
12968 if (!is_long
&& !is_scalar
) {
12969 static gen_helper_gvec_3
* const fns
[3] = {
12970 gen_helper_gvec_mul_idx_h
,
12971 gen_helper_gvec_mul_idx_s
,
12972 gen_helper_gvec_mul_idx_d
,
12974 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
12975 vec_full_reg_offset(s
, rn
),
12976 vec_full_reg_offset(s
, rm
),
12977 is_q
? 16 : 8, vec_full_reg_size(s
),
12978 index
, fns
[size
- 1]);
12983 case 0x10: /* MLA */
12984 if (!is_long
&& !is_scalar
) {
12985 static gen_helper_gvec_4
* const fns
[3] = {
12986 gen_helper_gvec_mla_idx_h
,
12987 gen_helper_gvec_mla_idx_s
,
12988 gen_helper_gvec_mla_idx_d
,
12990 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
12991 vec_full_reg_offset(s
, rn
),
12992 vec_full_reg_offset(s
, rm
),
12993 vec_full_reg_offset(s
, rd
),
12994 is_q
? 16 : 8, vec_full_reg_size(s
),
12995 index
, fns
[size
- 1]);
13000 case 0x14: /* MLS */
13001 if (!is_long
&& !is_scalar
) {
13002 static gen_helper_gvec_4
* const fns
[3] = {
13003 gen_helper_gvec_mls_idx_h
,
13004 gen_helper_gvec_mls_idx_s
,
13005 gen_helper_gvec_mls_idx_d
,
13007 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13008 vec_full_reg_offset(s
, rn
),
13009 vec_full_reg_offset(s
, rm
),
13010 vec_full_reg_offset(s
, rd
),
13011 is_q
? 16 : 8, vec_full_reg_size(s
),
13012 index
, fns
[size
- 1]);
13019 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13022 assert(is_fp
&& is_q
&& !is_long
);
13024 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13026 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13027 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13028 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13030 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13032 switch (16 * u
+ opcode
) {
13033 case 0x05: /* FMLS */
13034 /* As usual for ARM, separate negation for fused multiply-add */
13035 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13037 case 0x01: /* FMLA */
13038 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13039 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13041 case 0x09: /* FMUL */
13042 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13044 case 0x19: /* FMULX */
13045 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13048 g_assert_not_reached();
13051 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13054 clear_vec_high(s
, !is_scalar
, rd
);
13055 } else if (!is_long
) {
13056 /* 32 bit floating point, or 16 or 32 bit integer.
13057 * For the 16 bit scalar case we use the usual Neon helpers and
13058 * rely on the fact that 0 op 0 == 0 with no side effects.
13060 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13061 int pass
, maxpasses
;
13066 maxpasses
= is_q
? 4 : 2;
13069 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13071 if (size
== 1 && !is_scalar
) {
13072 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13073 * the index into both halves of the 32 bit tcg_idx and then use
13074 * the usual Neon helpers.
13076 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13079 for (pass
= 0; pass
< maxpasses
; pass
++) {
13080 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13081 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13083 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13085 switch (16 * u
+ opcode
) {
13086 case 0x08: /* MUL */
13087 case 0x10: /* MLA */
13088 case 0x14: /* MLS */
13090 static NeonGenTwoOpFn
* const fns
[2][2] = {
13091 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13092 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13094 NeonGenTwoOpFn
*genfn
;
13095 bool is_sub
= opcode
== 0x4;
13098 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13100 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13102 if (opcode
== 0x8) {
13105 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13106 genfn
= fns
[size
- 1][is_sub
];
13107 genfn(tcg_res
, tcg_op
, tcg_res
);
13110 case 0x05: /* FMLS */
13111 case 0x01: /* FMLA */
13112 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13113 is_scalar
? size
: MO_32
);
13116 if (opcode
== 0x5) {
13117 /* As usual for ARM, separate negation for fused
13119 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13122 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13125 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13130 if (opcode
== 0x5) {
13131 /* As usual for ARM, separate negation for
13132 * fused multiply-add */
13133 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13135 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13139 g_assert_not_reached();
13142 case 0x09: /* FMUL */
13146 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13149 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13154 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13157 g_assert_not_reached();
13160 case 0x19: /* FMULX */
13164 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13167 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13172 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13175 g_assert_not_reached();
13178 case 0x0c: /* SQDMULH */
13180 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13183 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13187 case 0x0d: /* SQRDMULH */
13189 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13192 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13196 case 0x1d: /* SQRDMLAH */
13197 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13198 is_scalar
? size
: MO_32
);
13200 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13201 tcg_op
, tcg_idx
, tcg_res
);
13203 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13204 tcg_op
, tcg_idx
, tcg_res
);
13207 case 0x1f: /* SQRDMLSH */
13208 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13209 is_scalar
? size
: MO_32
);
13211 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13212 tcg_op
, tcg_idx
, tcg_res
);
13214 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13215 tcg_op
, tcg_idx
, tcg_res
);
13219 g_assert_not_reached();
13223 write_fp_sreg(s
, rd
, tcg_res
);
13225 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13229 clear_vec_high(s
, is_q
, rd
);
13231 /* long ops: 16x16->32 or 32x32->64 */
13232 TCGv_i64 tcg_res
[2];
13234 bool satop
= extract32(opcode
, 0, 1);
13235 MemOp memop
= MO_32
;
13242 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13244 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13246 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13247 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13248 TCGv_i64 tcg_passres
;
13254 passelt
= pass
+ (is_q
* 2);
13257 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13259 tcg_res
[pass
] = tcg_temp_new_i64();
13261 if (opcode
== 0xa || opcode
== 0xb) {
13262 /* Non-accumulating ops */
13263 tcg_passres
= tcg_res
[pass
];
13265 tcg_passres
= tcg_temp_new_i64();
13268 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13271 /* saturating, doubling */
13272 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13273 tcg_passres
, tcg_passres
);
13276 if (opcode
== 0xa || opcode
== 0xb) {
13280 /* Accumulating op: handle accumulate step */
13281 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13284 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13285 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13287 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13288 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13290 case 0x7: /* SQDMLSL, SQDMLSL2 */
13291 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13293 case 0x3: /* SQDMLAL, SQDMLAL2 */
13294 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13299 g_assert_not_reached();
13303 clear_vec_high(s
, !is_scalar
, rd
);
13305 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13308 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13311 /* The simplest way to handle the 16x16 indexed ops is to
13312 * duplicate the index into both halves of the 32 bit tcg_idx
13313 * and then use the usual Neon helpers.
13315 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13318 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13319 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13320 TCGv_i64 tcg_passres
;
13323 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13325 read_vec_element_i32(s
, tcg_op
, rn
,
13326 pass
+ (is_q
* 2), MO_32
);
13329 tcg_res
[pass
] = tcg_temp_new_i64();
13331 if (opcode
== 0xa || opcode
== 0xb) {
13332 /* Non-accumulating ops */
13333 tcg_passres
= tcg_res
[pass
];
13335 tcg_passres
= tcg_temp_new_i64();
13338 if (memop
& MO_SIGN
) {
13339 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13341 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13344 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13345 tcg_passres
, tcg_passres
);
13348 if (opcode
== 0xa || opcode
== 0xb) {
13352 /* Accumulating op: handle accumulate step */
13353 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13356 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13357 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13360 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13361 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13364 case 0x7: /* SQDMLSL, SQDMLSL2 */
13365 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13367 case 0x3: /* SQDMLAL, SQDMLAL2 */
13368 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13373 g_assert_not_reached();
13378 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13383 tcg_res
[1] = tcg_constant_i64(0);
13386 for (pass
= 0; pass
< 2; pass
++) {
13387 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13393 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13394 * +-----------------+------+-----------+--------+-----+------+------+
13395 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13396 * +-----------------+------+-----------+--------+-----+------+------+
13398 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13400 int size
= extract32(insn
, 22, 2);
13401 int opcode
= extract32(insn
, 12, 5);
13402 int rn
= extract32(insn
, 5, 5);
13403 int rd
= extract32(insn
, 0, 5);
13405 gen_helper_gvec_2
*genfn2
= NULL
;
13406 gen_helper_gvec_3
*genfn3
= NULL
;
13408 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13409 unallocated_encoding(s
);
13414 case 0x4: /* AESE */
13416 genfn3
= gen_helper_crypto_aese
;
13418 case 0x6: /* AESMC */
13420 genfn2
= gen_helper_crypto_aesmc
;
13422 case 0x5: /* AESD */
13424 genfn3
= gen_helper_crypto_aese
;
13426 case 0x7: /* AESIMC */
13428 genfn2
= gen_helper_crypto_aesmc
;
13431 unallocated_encoding(s
);
13435 if (!fp_access_check(s
)) {
13439 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13441 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13445 /* Crypto three-reg SHA
13446 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13447 * +-----------------+------+---+------+---+--------+-----+------+------+
13448 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13449 * +-----------------+------+---+------+---+--------+-----+------+------+
13451 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13453 int size
= extract32(insn
, 22, 2);
13454 int opcode
= extract32(insn
, 12, 3);
13455 int rm
= extract32(insn
, 16, 5);
13456 int rn
= extract32(insn
, 5, 5);
13457 int rd
= extract32(insn
, 0, 5);
13458 gen_helper_gvec_3
*genfn
;
13462 unallocated_encoding(s
);
13467 case 0: /* SHA1C */
13468 genfn
= gen_helper_crypto_sha1c
;
13469 feature
= dc_isar_feature(aa64_sha1
, s
);
13471 case 1: /* SHA1P */
13472 genfn
= gen_helper_crypto_sha1p
;
13473 feature
= dc_isar_feature(aa64_sha1
, s
);
13475 case 2: /* SHA1M */
13476 genfn
= gen_helper_crypto_sha1m
;
13477 feature
= dc_isar_feature(aa64_sha1
, s
);
13479 case 3: /* SHA1SU0 */
13480 genfn
= gen_helper_crypto_sha1su0
;
13481 feature
= dc_isar_feature(aa64_sha1
, s
);
13483 case 4: /* SHA256H */
13484 genfn
= gen_helper_crypto_sha256h
;
13485 feature
= dc_isar_feature(aa64_sha256
, s
);
13487 case 5: /* SHA256H2 */
13488 genfn
= gen_helper_crypto_sha256h2
;
13489 feature
= dc_isar_feature(aa64_sha256
, s
);
13491 case 6: /* SHA256SU1 */
13492 genfn
= gen_helper_crypto_sha256su1
;
13493 feature
= dc_isar_feature(aa64_sha256
, s
);
13496 unallocated_encoding(s
);
13501 unallocated_encoding(s
);
13505 if (!fp_access_check(s
)) {
13508 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
13511 /* Crypto two-reg SHA
13512 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13513 * +-----------------+------+-----------+--------+-----+------+------+
13514 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13515 * +-----------------+------+-----------+--------+-----+------+------+
13517 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13519 int size
= extract32(insn
, 22, 2);
13520 int opcode
= extract32(insn
, 12, 5);
13521 int rn
= extract32(insn
, 5, 5);
13522 int rd
= extract32(insn
, 0, 5);
13523 gen_helper_gvec_2
*genfn
;
13527 unallocated_encoding(s
);
13532 case 0: /* SHA1H */
13533 feature
= dc_isar_feature(aa64_sha1
, s
);
13534 genfn
= gen_helper_crypto_sha1h
;
13536 case 1: /* SHA1SU1 */
13537 feature
= dc_isar_feature(aa64_sha1
, s
);
13538 genfn
= gen_helper_crypto_sha1su1
;
13540 case 2: /* SHA256SU0 */
13541 feature
= dc_isar_feature(aa64_sha256
, s
);
13542 genfn
= gen_helper_crypto_sha256su0
;
13545 unallocated_encoding(s
);
13550 unallocated_encoding(s
);
13554 if (!fp_access_check(s
)) {
13557 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
13560 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
13562 tcg_gen_rotli_i64(d
, m
, 1);
13563 tcg_gen_xor_i64(d
, d
, n
);
13566 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
13568 tcg_gen_rotli_vec(vece
, d
, m
, 1);
13569 tcg_gen_xor_vec(vece
, d
, d
, n
);
13572 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
13573 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
13575 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
13576 static const GVecGen3 op
= {
13577 .fni8
= gen_rax1_i64
,
13578 .fniv
= gen_rax1_vec
,
13579 .opt_opc
= vecop_list
,
13580 .fno
= gen_helper_crypto_rax1
,
13583 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
13586 /* Crypto three-reg SHA512
13587 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13588 * +-----------------------+------+---+---+-----+--------+------+------+
13589 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13590 * +-----------------------+------+---+---+-----+--------+------+------+
13592 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13594 int opcode
= extract32(insn
, 10, 2);
13595 int o
= extract32(insn
, 14, 1);
13596 int rm
= extract32(insn
, 16, 5);
13597 int rn
= extract32(insn
, 5, 5);
13598 int rd
= extract32(insn
, 0, 5);
13600 gen_helper_gvec_3
*oolfn
= NULL
;
13601 GVecGen3Fn
*gvecfn
= NULL
;
13605 case 0: /* SHA512H */
13606 feature
= dc_isar_feature(aa64_sha512
, s
);
13607 oolfn
= gen_helper_crypto_sha512h
;
13609 case 1: /* SHA512H2 */
13610 feature
= dc_isar_feature(aa64_sha512
, s
);
13611 oolfn
= gen_helper_crypto_sha512h2
;
13613 case 2: /* SHA512SU1 */
13614 feature
= dc_isar_feature(aa64_sha512
, s
);
13615 oolfn
= gen_helper_crypto_sha512su1
;
13618 feature
= dc_isar_feature(aa64_sha3
, s
);
13619 gvecfn
= gen_gvec_rax1
;
13622 g_assert_not_reached();
13626 case 0: /* SM3PARTW1 */
13627 feature
= dc_isar_feature(aa64_sm3
, s
);
13628 oolfn
= gen_helper_crypto_sm3partw1
;
13630 case 1: /* SM3PARTW2 */
13631 feature
= dc_isar_feature(aa64_sm3
, s
);
13632 oolfn
= gen_helper_crypto_sm3partw2
;
13634 case 2: /* SM4EKEY */
13635 feature
= dc_isar_feature(aa64_sm4
, s
);
13636 oolfn
= gen_helper_crypto_sm4ekey
;
13639 unallocated_encoding(s
);
13645 unallocated_encoding(s
);
13649 if (!fp_access_check(s
)) {
13654 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
13656 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
13660 /* Crypto two-reg SHA512
13661 * 31 12 11 10 9 5 4 0
13662 * +-----------------------------------------+--------+------+------+
13663 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13664 * +-----------------------------------------+--------+------+------+
13666 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13668 int opcode
= extract32(insn
, 10, 2);
13669 int rn
= extract32(insn
, 5, 5);
13670 int rd
= extract32(insn
, 0, 5);
13674 case 0: /* SHA512SU0 */
13675 feature
= dc_isar_feature(aa64_sha512
, s
);
13678 feature
= dc_isar_feature(aa64_sm4
, s
);
13681 unallocated_encoding(s
);
13686 unallocated_encoding(s
);
13690 if (!fp_access_check(s
)) {
13695 case 0: /* SHA512SU0 */
13696 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
13699 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
13702 g_assert_not_reached();
13706 /* Crypto four-register
13707 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13708 * +-------------------+-----+------+---+------+------+------+
13709 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13710 * +-------------------+-----+------+---+------+------+------+
13712 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13714 int op0
= extract32(insn
, 21, 2);
13715 int rm
= extract32(insn
, 16, 5);
13716 int ra
= extract32(insn
, 10, 5);
13717 int rn
= extract32(insn
, 5, 5);
13718 int rd
= extract32(insn
, 0, 5);
13724 feature
= dc_isar_feature(aa64_sha3
, s
);
13726 case 2: /* SM3SS1 */
13727 feature
= dc_isar_feature(aa64_sm3
, s
);
13730 unallocated_encoding(s
);
13735 unallocated_encoding(s
);
13739 if (!fp_access_check(s
)) {
13744 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13747 tcg_op1
= tcg_temp_new_i64();
13748 tcg_op2
= tcg_temp_new_i64();
13749 tcg_op3
= tcg_temp_new_i64();
13750 tcg_res
[0] = tcg_temp_new_i64();
13751 tcg_res
[1] = tcg_temp_new_i64();
13753 for (pass
= 0; pass
< 2; pass
++) {
13754 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13755 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13756 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13760 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13763 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13765 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13767 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13768 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13770 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13772 tcg_op1
= tcg_temp_new_i32();
13773 tcg_op2
= tcg_temp_new_i32();
13774 tcg_op3
= tcg_temp_new_i32();
13775 tcg_res
= tcg_temp_new_i32();
13776 tcg_zero
= tcg_constant_i32(0);
13778 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13779 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13780 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13782 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13783 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13784 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13785 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13787 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13788 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13789 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13790 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13795 * 31 21 20 16 15 10 9 5 4 0
13796 * +-----------------------+------+--------+------+------+
13797 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13798 * +-----------------------+------+--------+------+------+
13800 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13802 int rm
= extract32(insn
, 16, 5);
13803 int imm6
= extract32(insn
, 10, 6);
13804 int rn
= extract32(insn
, 5, 5);
13805 int rd
= extract32(insn
, 0, 5);
13807 if (!dc_isar_feature(aa64_sha3
, s
)) {
13808 unallocated_encoding(s
);
13812 if (!fp_access_check(s
)) {
13816 gen_gvec_xar(MO_64
, vec_full_reg_offset(s
, rd
),
13817 vec_full_reg_offset(s
, rn
),
13818 vec_full_reg_offset(s
, rm
), imm6
, 16,
13819 vec_full_reg_size(s
));
13822 /* Crypto three-reg imm2
13823 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13824 * +-----------------------+------+-----+------+--------+------+------+
13825 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13826 * +-----------------------+------+-----+------+--------+------+------+
13828 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13830 static gen_helper_gvec_3
* const fns
[4] = {
13831 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
13832 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
13834 int opcode
= extract32(insn
, 10, 2);
13835 int imm2
= extract32(insn
, 12, 2);
13836 int rm
= extract32(insn
, 16, 5);
13837 int rn
= extract32(insn
, 5, 5);
13838 int rd
= extract32(insn
, 0, 5);
13840 if (!dc_isar_feature(aa64_sm3
, s
)) {
13841 unallocated_encoding(s
);
13845 if (!fp_access_check(s
)) {
13849 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
13852 /* C3.6 Data processing - SIMD, inc Crypto
13854 * As the decode gets a little complex we are using a table based
13855 * approach for this part of the decode.
13857 static const AArch64DecodeTable data_proc_simd
[] = {
13858 /* pattern , mask , fn */
13859 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13860 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13861 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13862 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13863 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13864 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13865 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13866 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13867 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13868 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13869 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13870 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13871 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13872 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13873 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13874 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13875 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13876 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13877 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13878 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13879 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13880 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13881 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13882 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13883 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13884 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13885 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13886 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13887 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13888 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13889 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13890 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13891 { 0x00000000, 0x00000000, NULL
}
13894 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13896 /* Note that this is called with all non-FP cases from
13897 * table C3-6 so it must UNDEF for entries not specifically
13898 * allocated to instructions in that table.
13900 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13904 unallocated_encoding(s
);
13908 /* C3.6 Data processing - SIMD and floating point */
13909 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13911 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13912 disas_data_proc_fp(s
, insn
);
13914 /* SIMD, including crypto */
13915 disas_data_proc_simd(s
, insn
);
13919 static bool trans_OK(DisasContext
*s
, arg_OK
*a
)
13924 static bool trans_FAIL(DisasContext
*s
, arg_OK
*a
)
13926 s
->is_nonstreaming
= true;
13932 * @env: The cpu environment
13933 * @s: The DisasContext
13935 * Return true if the page is guarded.
13937 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13939 uint64_t addr
= s
->base
.pc_first
;
13940 #ifdef CONFIG_USER_ONLY
13941 return page_get_flags(addr
) & PAGE_BTI
;
13943 CPUTLBEntryFull
*full
;
13945 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13949 * We test this immediately after reading an insn, which means
13950 * that the TLB entry must be present and valid, and thus this
13951 * access will never raise an exception.
13953 flags
= probe_access_full(env
, addr
, 0, MMU_INST_FETCH
, mmu_idx
,
13954 false, &host
, &full
, 0);
13955 assert(!(flags
& TLB_INVALID_MASK
));
13957 return full
->guarded
;
13962 * btype_destination_ok:
13963 * @insn: The instruction at the branch destination
13964 * @bt: SCTLR_ELx.BT
13965 * @btype: PSTATE.BTYPE, and is non-zero
13967 * On a guarded page, there are a limited number of insns
13968 * that may be present at the branch target:
13969 * - branch target identifiers,
13970 * - paciasp, pacibsp,
13973 * Anything else causes a Branch Target Exception.
13975 * Return true if the branch is compatible, false to raise BTITRAP.
13977 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
13979 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
13981 switch (extract32(insn
, 5, 7)) {
13982 case 0b011001: /* PACIASP */
13983 case 0b011011: /* PACIBSP */
13985 * If SCTLR_ELx.BT, then PACI*SP are not compatible
13986 * with btype == 3. Otherwise all btype are ok.
13988 return !bt
|| btype
!= 3;
13989 case 0b100000: /* BTI */
13990 /* Not compatible with any btype. */
13992 case 0b100010: /* BTI c */
13993 /* Not compatible with btype == 3 */
13995 case 0b100100: /* BTI j */
13996 /* Not compatible with btype == 2 */
13998 case 0b100110: /* BTI jc */
13999 /* Compatible with any btype. */
14003 switch (insn
& 0xffe0001fu
) {
14004 case 0xd4200000u
: /* BRK */
14005 case 0xd4400000u
: /* HLT */
14006 /* Give priority to the breakpoint exception. */
14013 /* C3.1 A64 instruction index by encoding */
14014 static void disas_a64_legacy(DisasContext
*s
, uint32_t insn
)
14016 switch (extract32(insn
, 25, 4)) {
14017 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14018 disas_b_exc_sys(s
, insn
);
14023 case 0xe: /* Loads and stores */
14024 disas_ldst(s
, insn
);
14027 case 0xd: /* Data processing - register */
14028 disas_data_proc_reg(s
, insn
);
14031 case 0xf: /* Data processing - SIMD and floating point */
14032 disas_data_proc_simd_fp(s
, insn
);
14035 unallocated_encoding(s
);
14040 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14043 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14044 CPUARMState
*env
= cpu
->env_ptr
;
14045 ARMCPU
*arm_cpu
= env_archcpu(env
);
14046 CPUARMTBFlags tb_flags
= arm_tbflags_from_tb(dc
->base
.tb
);
14047 int bound
, core_mmu_idx
;
14049 dc
->isar
= &arm_cpu
->isar
;
14051 dc
->pc_save
= dc
->base
.pc_first
;
14052 dc
->aarch64
= true;
14055 dc
->be_data
= EX_TBFLAG_ANY(tb_flags
, BE_DATA
) ? MO_BE
: MO_LE
;
14056 dc
->condexec_mask
= 0;
14057 dc
->condexec_cond
= 0;
14058 core_mmu_idx
= EX_TBFLAG_ANY(tb_flags
, MMUIDX
);
14059 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14060 dc
->tbii
= EX_TBFLAG_A64(tb_flags
, TBII
);
14061 dc
->tbid
= EX_TBFLAG_A64(tb_flags
, TBID
);
14062 dc
->tcma
= EX_TBFLAG_A64(tb_flags
, TCMA
);
14063 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14064 #if !defined(CONFIG_USER_ONLY)
14065 dc
->user
= (dc
->current_el
== 0);
14067 dc
->fp_excp_el
= EX_TBFLAG_ANY(tb_flags
, FPEXC_EL
);
14068 dc
->align_mem
= EX_TBFLAG_ANY(tb_flags
, ALIGN_MEM
);
14069 dc
->pstate_il
= EX_TBFLAG_ANY(tb_flags
, PSTATE__IL
);
14070 dc
->fgt_active
= EX_TBFLAG_ANY(tb_flags
, FGT_ACTIVE
);
14071 dc
->fgt_svc
= EX_TBFLAG_ANY(tb_flags
, FGT_SVC
);
14072 dc
->fgt_eret
= EX_TBFLAG_A64(tb_flags
, FGT_ERET
);
14073 dc
->sve_excp_el
= EX_TBFLAG_A64(tb_flags
, SVEEXC_EL
);
14074 dc
->sme_excp_el
= EX_TBFLAG_A64(tb_flags
, SMEEXC_EL
);
14075 dc
->vl
= (EX_TBFLAG_A64(tb_flags
, VL
) + 1) * 16;
14076 dc
->svl
= (EX_TBFLAG_A64(tb_flags
, SVL
) + 1) * 16;
14077 dc
->pauth_active
= EX_TBFLAG_A64(tb_flags
, PAUTH_ACTIVE
);
14078 dc
->bt
= EX_TBFLAG_A64(tb_flags
, BT
);
14079 dc
->btype
= EX_TBFLAG_A64(tb_flags
, BTYPE
);
14080 dc
->unpriv
= EX_TBFLAG_A64(tb_flags
, UNPRIV
);
14081 dc
->ata
= EX_TBFLAG_A64(tb_flags
, ATA
);
14082 dc
->mte_active
[0] = EX_TBFLAG_A64(tb_flags
, MTE_ACTIVE
);
14083 dc
->mte_active
[1] = EX_TBFLAG_A64(tb_flags
, MTE0_ACTIVE
);
14084 dc
->pstate_sm
= EX_TBFLAG_A64(tb_flags
, PSTATE_SM
);
14085 dc
->pstate_za
= EX_TBFLAG_A64(tb_flags
, PSTATE_ZA
);
14086 dc
->sme_trap_nonstreaming
= EX_TBFLAG_A64(tb_flags
, SME_TRAP_NONSTREAMING
);
14088 dc
->vec_stride
= 0;
14089 dc
->cp_regs
= arm_cpu
->cp_regs
;
14090 dc
->features
= env
->features
;
14091 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14093 #ifdef CONFIG_USER_ONLY
14094 /* In sve_probe_page, we assume TBI is enabled. */
14095 tcg_debug_assert(dc
->tbid
& 1);
14098 dc
->lse2
= dc_isar_feature(aa64_lse2
, dc
);
14100 /* Single step state. The code-generation logic here is:
14102 * generate code with no special handling for single-stepping (except
14103 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14104 * this happens anyway because those changes are all system register or
14106 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14107 * emit code for one insn
14108 * emit code to clear PSTATE.SS
14109 * emit code to generate software step exception for completed step
14110 * end TB (as usual for having generated an exception)
14111 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14112 * emit code to generate a software step exception
14115 dc
->ss_active
= EX_TBFLAG_ANY(tb_flags
, SS_ACTIVE
);
14116 dc
->pstate_ss
= EX_TBFLAG_ANY(tb_flags
, PSTATE__SS
);
14117 dc
->is_ldex
= false;
14119 /* Bound the number of insns to execute to those left on the page. */
14120 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14122 /* If architectural single step active, limit to 1. */
14123 if (dc
->ss_active
) {
14126 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14129 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14133 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14135 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14136 target_ulong pc_arg
= dc
->base
.pc_next
;
14138 if (tb_cflags(dcbase
->tb
) & CF_PCREL
) {
14139 pc_arg
&= ~TARGET_PAGE_MASK
;
14141 tcg_gen_insn_start(pc_arg
, 0, 0);
14142 dc
->insn_start
= tcg_last_op();
14145 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14147 DisasContext
*s
= container_of(dcbase
, DisasContext
, base
);
14148 CPUARMState
*env
= cpu
->env_ptr
;
14149 uint64_t pc
= s
->base
.pc_next
;
14152 /* Singlestep exceptions have the highest priority. */
14153 if (s
->ss_active
&& !s
->pstate_ss
) {
14154 /* Singlestep state is Active-pending.
14155 * If we're in this state at the start of a TB then either
14156 * a) we just took an exception to an EL which is being debugged
14157 * and this is the first insn in the exception handler
14158 * b) debug exceptions were masked and we just unmasked them
14159 * without changing EL (eg by clearing PSTATE.D)
14160 * In either case we're going to take a swstep exception in the
14161 * "did not step an insn" case, and so the syndrome ISV and EX
14162 * bits should be zero.
14164 assert(s
->base
.num_insns
== 1);
14165 gen_swstep_exception(s
, 0, 0);
14166 s
->base
.is_jmp
= DISAS_NORETURN
;
14167 s
->base
.pc_next
= pc
+ 4;
14173 * PC alignment fault. This has priority over the instruction abort
14174 * that we would receive from a translation fault via arm_ldl_code.
14175 * This should only be possible after an indirect branch, at the
14178 assert(s
->base
.num_insns
== 1);
14179 gen_helper_exception_pc_alignment(cpu_env
, tcg_constant_tl(pc
));
14180 s
->base
.is_jmp
= DISAS_NORETURN
;
14181 s
->base
.pc_next
= QEMU_ALIGN_UP(pc
, 4);
14186 insn
= arm_ldl_code(env
, &s
->base
, pc
, s
->sctlr_b
);
14188 s
->base
.pc_next
= pc
+ 4;
14190 s
->fp_access_checked
= false;
14191 s
->sve_access_checked
= false;
14193 if (s
->pstate_il
) {
14195 * Illegal execution state. This has priority over BTI
14196 * exceptions, but comes after instruction abort exceptions.
14198 gen_exception_insn(s
, 0, EXCP_UDEF
, syn_illegalstate());
14202 if (dc_isar_feature(aa64_bti
, s
)) {
14203 if (s
->base
.num_insns
== 1) {
14205 * At the first insn of the TB, compute s->guarded_page.
14206 * We delayed computing this until successfully reading
14207 * the first insn of the TB, above. This (mostly) ensures
14208 * that the softmmu tlb entry has been populated, and the
14209 * page table GP bit is available.
14211 * Note that we need to compute this even if btype == 0,
14212 * because this value is used for BR instructions later
14213 * where ENV is not available.
14215 s
->guarded_page
= is_guarded_page(env
, s
);
14217 /* First insn can have btype set to non-zero. */
14218 tcg_debug_assert(s
->btype
>= 0);
14221 * Note that the Branch Target Exception has fairly high
14222 * priority -- below debugging exceptions but above most
14223 * everything else. This allows us to handle this now
14224 * instead of waiting until the insn is otherwise decoded.
14228 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14229 gen_exception_insn(s
, 0, EXCP_UDEF
, syn_btitrap(s
->btype
));
14233 /* Not the first insn: btype must be 0. */
14234 tcg_debug_assert(s
->btype
== 0);
14238 s
->is_nonstreaming
= false;
14239 if (s
->sme_trap_nonstreaming
) {
14240 disas_sme_fa64(s
, insn
);
14243 if (!disas_a64(s
, insn
) &&
14244 !disas_sme(s
, insn
) &&
14245 !disas_sve(s
, insn
)) {
14246 disas_a64_legacy(s
, insn
);
14250 * After execution of most insns, btype is reset to 0.
14251 * Note that we set btype == -1 when the insn sets btype.
14253 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14258 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14260 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14262 if (unlikely(dc
->ss_active
)) {
14263 /* Note that this means single stepping WFI doesn't halt the CPU.
14264 * For conditional branch insns this is harmless unreachable code as
14265 * gen_goto_tb() has already handled emitting the debug exception
14266 * (and thus a tb-jump is not possible when singlestepping).
14268 switch (dc
->base
.is_jmp
) {
14270 gen_a64_update_pc(dc
, 4);
14274 gen_step_complete_exception(dc
);
14276 case DISAS_NORETURN
:
14280 switch (dc
->base
.is_jmp
) {
14282 case DISAS_TOO_MANY
:
14283 gen_goto_tb(dc
, 1, 4);
14286 case DISAS_UPDATE_EXIT
:
14287 gen_a64_update_pc(dc
, 4);
14290 tcg_gen_exit_tb(NULL
, 0);
14292 case DISAS_UPDATE_NOCHAIN
:
14293 gen_a64_update_pc(dc
, 4);
14296 tcg_gen_lookup_and_goto_ptr();
14298 case DISAS_NORETURN
:
14302 gen_a64_update_pc(dc
, 4);
14303 gen_helper_wfe(cpu_env
);
14306 gen_a64_update_pc(dc
, 4);
14307 gen_helper_yield(cpu_env
);
14311 * This is a special case because we don't want to just halt
14312 * the CPU if trying to debug across a WFI.
14314 gen_a64_update_pc(dc
, 4);
14315 gen_helper_wfi(cpu_env
, tcg_constant_i32(4));
14317 * The helper doesn't necessarily throw an exception, but we
14318 * must go back to the main loop to check for interrupts anyway.
14320 tcg_gen_exit_tb(NULL
, 0);
14326 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14327 CPUState
*cpu
, FILE *logfile
)
14329 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14331 fprintf(logfile
, "IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14332 target_disas(logfile
, cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14335 const TranslatorOps aarch64_translator_ops
= {
14336 .init_disas_context
= aarch64_tr_init_disas_context
,
14337 .tb_start
= aarch64_tr_tb_start
,
14338 .insn_start
= aarch64_tr_insn_start
,
14339 .translate_insn
= aarch64_tr_translate_insn
,
14340 .tb_stop
= aarch64_tr_tb_stop
,
14341 .disas_log
= aarch64_tr_disas_log
,