4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "internals.h"
25 #include "disas/disas.h"
26 #include "exec/exec-all.h"
27 #include "tcg/tcg-op.h"
28 #include "tcg/tcg-op-gvec.h"
30 #include "qemu/bitops.h"
32 #include "hw/semihosting/semihost.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
41 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T)
42 #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
43 /* currently all emulated v5 cores are also v5TE, so don't bother */
44 #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
45 #define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s)
46 #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
47 #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
48 #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
49 #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7)
50 #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8)
52 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
54 #include "translate.h"
56 #if defined(CONFIG_USER_ONLY)
59 #define IS_USER(s) (s->user)
62 /* We reuse the same 64-bit temporaries for efficiency. */
63 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
64 static TCGv_i32 cpu_R
[16];
65 TCGv_i32 cpu_CF
, cpu_NF
, cpu_VF
, cpu_ZF
;
66 TCGv_i64 cpu_exclusive_addr
;
67 TCGv_i64 cpu_exclusive_val
;
69 #include "exec/gen-icount.h"
71 static const char * const regnames
[] =
72 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
73 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
75 /* Function prototypes for gen_ functions calling Neon helpers. */
76 typedef void NeonGenThreeOpEnvFn(TCGv_i32
, TCGv_env
, TCGv_i32
,
78 /* Function prototypes for gen_ functions for fix point conversions */
79 typedef void VFPGenFixPointFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 /* initialize TCG globals. */
82 void arm_translate_init(void)
86 for (i
= 0; i
< 16; i
++) {
87 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
88 offsetof(CPUARMState
, regs
[i
]),
91 cpu_CF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, CF
), "CF");
92 cpu_NF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, NF
), "NF");
93 cpu_VF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, VF
), "VF");
94 cpu_ZF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, ZF
), "ZF");
96 cpu_exclusive_addr
= tcg_global_mem_new_i64(cpu_env
,
97 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
98 cpu_exclusive_val
= tcg_global_mem_new_i64(cpu_env
,
99 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
101 a64_translate_init();
104 /* Flags for the disas_set_da_iss info argument:
105 * lower bits hold the Rt register number, higher bits are flags.
107 typedef enum ISSInfo
{
110 ISSInvalid
= (1 << 5),
111 ISSIsAcqRel
= (1 << 6),
112 ISSIsWrite
= (1 << 7),
113 ISSIs16Bit
= (1 << 8),
116 /* Save the syndrome information for a Data Abort */
117 static void disas_set_da_iss(DisasContext
*s
, MemOp memop
, ISSInfo issinfo
)
120 int sas
= memop
& MO_SIZE
;
121 bool sse
= memop
& MO_SIGN
;
122 bool is_acqrel
= issinfo
& ISSIsAcqRel
;
123 bool is_write
= issinfo
& ISSIsWrite
;
124 bool is_16bit
= issinfo
& ISSIs16Bit
;
125 int srt
= issinfo
& ISSRegMask
;
127 if (issinfo
& ISSInvalid
) {
128 /* Some callsites want to conditionally provide ISS info,
129 * eg "only if this was not a writeback"
135 /* For AArch32, insns where the src/dest is R15 never generate
136 * ISS information. Catching that here saves checking at all
142 syn
= syn_data_abort_with_iss(0, sas
, sse
, srt
, 0, is_acqrel
,
143 0, 0, 0, is_write
, 0, is_16bit
);
144 disas_set_insn_syndrome(s
, syn
);
147 static inline int get_a32_user_mem_index(DisasContext
*s
)
149 /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store"
151 * if PL2, UNPREDICTABLE (we choose to implement as if PL0)
152 * otherwise, access as if at PL0.
154 switch (s
->mmu_idx
) {
155 case ARMMMUIdx_E2
: /* this one is UNPREDICTABLE */
156 case ARMMMUIdx_E10_0
:
157 case ARMMMUIdx_E10_1
:
158 case ARMMMUIdx_E10_1_PAN
:
159 return arm_to_core_mmu_idx(ARMMMUIdx_E10_0
);
161 case ARMMMUIdx_SE10_0
:
162 case ARMMMUIdx_SE10_1
:
163 case ARMMMUIdx_SE10_1_PAN
:
164 return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0
);
165 case ARMMMUIdx_MUser
:
166 case ARMMMUIdx_MPriv
:
167 return arm_to_core_mmu_idx(ARMMMUIdx_MUser
);
168 case ARMMMUIdx_MUserNegPri
:
169 case ARMMMUIdx_MPrivNegPri
:
170 return arm_to_core_mmu_idx(ARMMMUIdx_MUserNegPri
);
171 case ARMMMUIdx_MSUser
:
172 case ARMMMUIdx_MSPriv
:
173 return arm_to_core_mmu_idx(ARMMMUIdx_MSUser
);
174 case ARMMMUIdx_MSUserNegPri
:
175 case ARMMMUIdx_MSPrivNegPri
:
176 return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri
);
178 g_assert_not_reached();
182 static inline TCGv_i32
load_cpu_offset(int offset
)
184 TCGv_i32 tmp
= tcg_temp_new_i32();
185 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
189 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
191 static inline void store_cpu_offset(TCGv_i32 var
, int offset
)
193 tcg_gen_st_i32(var
, cpu_env
, offset
);
194 tcg_temp_free_i32(var
);
197 #define store_cpu_field(var, name) \
198 store_cpu_offset(var, offsetof(CPUARMState, name))
200 /* The architectural value of PC. */
201 static uint32_t read_pc(DisasContext
*s
)
203 return s
->pc_curr
+ (s
->thumb
? 4 : 8);
206 /* Set a variable to the value of a CPU register. */
207 static void load_reg_var(DisasContext
*s
, TCGv_i32 var
, int reg
)
210 tcg_gen_movi_i32(var
, read_pc(s
));
212 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
216 /* Create a new temporary and set it to the value of a CPU register. */
217 static inline TCGv_i32
load_reg(DisasContext
*s
, int reg
)
219 TCGv_i32 tmp
= tcg_temp_new_i32();
220 load_reg_var(s
, tmp
, reg
);
225 * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
226 * This is used for load/store for which use of PC implies (literal),
227 * or ADD that implies ADR.
229 static TCGv_i32
add_reg_for_lit(DisasContext
*s
, int reg
, int ofs
)
231 TCGv_i32 tmp
= tcg_temp_new_i32();
234 tcg_gen_movi_i32(tmp
, (read_pc(s
) & ~3) + ofs
);
236 tcg_gen_addi_i32(tmp
, cpu_R
[reg
], ofs
);
241 /* Set a CPU register. The source must be a temporary and will be
243 static void store_reg(DisasContext
*s
, int reg
, TCGv_i32 var
)
246 /* In Thumb mode, we must ignore bit 0.
247 * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]
248 * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0].
249 * We choose to ignore [1:0] in ARM mode for all architecture versions.
251 tcg_gen_andi_i32(var
, var
, s
->thumb
? ~1 : ~3);
252 s
->base
.is_jmp
= DISAS_JUMP
;
254 tcg_gen_mov_i32(cpu_R
[reg
], var
);
255 tcg_temp_free_i32(var
);
259 * Variant of store_reg which applies v8M stack-limit checks before updating
260 * SP. If the check fails this will result in an exception being taken.
261 * We disable the stack checks for CONFIG_USER_ONLY because we have
262 * no idea what the stack limits should be in that case.
263 * If stack checking is not being done this just acts like store_reg().
265 static void store_sp_checked(DisasContext
*s
, TCGv_i32 var
)
267 #ifndef CONFIG_USER_ONLY
268 if (s
->v8m_stackcheck
) {
269 gen_helper_v8m_stackcheck(cpu_env
, var
);
272 store_reg(s
, 13, var
);
275 /* Value extensions. */
276 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
277 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
278 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
279 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
281 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
282 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
285 static inline void gen_set_cpsr(TCGv_i32 var
, uint32_t mask
)
287 TCGv_i32 tmp_mask
= tcg_const_i32(mask
);
288 gen_helper_cpsr_write(cpu_env
, var
, tmp_mask
);
289 tcg_temp_free_i32(tmp_mask
);
291 /* Set NZCV flags from the high 4 bits of var. */
292 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
294 static void gen_exception_internal(int excp
)
296 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
298 assert(excp_is_internal(excp
));
299 gen_helper_exception_internal(cpu_env
, tcg_excp
);
300 tcg_temp_free_i32(tcg_excp
);
303 static void gen_step_complete_exception(DisasContext
*s
)
305 /* We just completed step of an insn. Move from Active-not-pending
306 * to Active-pending, and then also take the swstep exception.
307 * This corresponds to making the (IMPDEF) choice to prioritize
308 * swstep exceptions over asynchronous exceptions taken to an exception
309 * level where debug is disabled. This choice has the advantage that
310 * we do not need to maintain internal state corresponding to the
311 * ISV/EX syndrome bits between completion of the step and generation
312 * of the exception, and our syndrome information is always correct.
315 gen_swstep_exception(s
, 1, s
->is_ldex
);
316 s
->base
.is_jmp
= DISAS_NORETURN
;
319 static void gen_singlestep_exception(DisasContext
*s
)
321 /* Generate the right kind of exception for singlestep, which is
322 * either the architectural singlestep or EXCP_DEBUG for QEMU's
323 * gdb singlestepping.
326 gen_step_complete_exception(s
);
328 gen_exception_internal(EXCP_DEBUG
);
332 static inline bool is_singlestepping(DisasContext
*s
)
334 /* Return true if we are singlestepping either because of
335 * architectural singlestep or QEMU gdbstub singlestep. This does
336 * not include the command line '-singlestep' mode which is rather
337 * misnamed as it only means "one instruction per TB" and doesn't
338 * affect the code we generate.
340 return s
->base
.singlestep_enabled
|| s
->ss_active
;
343 static void gen_smul_dual(TCGv_i32 a
, TCGv_i32 b
)
345 TCGv_i32 tmp1
= tcg_temp_new_i32();
346 TCGv_i32 tmp2
= tcg_temp_new_i32();
347 tcg_gen_ext16s_i32(tmp1
, a
);
348 tcg_gen_ext16s_i32(tmp2
, b
);
349 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
350 tcg_temp_free_i32(tmp2
);
351 tcg_gen_sari_i32(a
, a
, 16);
352 tcg_gen_sari_i32(b
, b
, 16);
353 tcg_gen_mul_i32(b
, b
, a
);
354 tcg_gen_mov_i32(a
, tmp1
);
355 tcg_temp_free_i32(tmp1
);
358 /* Byteswap each halfword. */
359 static void gen_rev16(TCGv_i32 dest
, TCGv_i32 var
)
361 TCGv_i32 tmp
= tcg_temp_new_i32();
362 TCGv_i32 mask
= tcg_const_i32(0x00ff00ff);
363 tcg_gen_shri_i32(tmp
, var
, 8);
364 tcg_gen_and_i32(tmp
, tmp
, mask
);
365 tcg_gen_and_i32(var
, var
, mask
);
366 tcg_gen_shli_i32(var
, var
, 8);
367 tcg_gen_or_i32(dest
, var
, tmp
);
368 tcg_temp_free_i32(mask
);
369 tcg_temp_free_i32(tmp
);
372 /* Byteswap low halfword and sign extend. */
373 static void gen_revsh(TCGv_i32 dest
, TCGv_i32 var
)
375 tcg_gen_ext16u_i32(var
, var
);
376 tcg_gen_bswap16_i32(var
, var
);
377 tcg_gen_ext16s_i32(dest
, var
);
380 /* 32x32->64 multiply. Marks inputs as dead. */
381 static TCGv_i64
gen_mulu_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
383 TCGv_i32 lo
= tcg_temp_new_i32();
384 TCGv_i32 hi
= tcg_temp_new_i32();
387 tcg_gen_mulu2_i32(lo
, hi
, a
, b
);
388 tcg_temp_free_i32(a
);
389 tcg_temp_free_i32(b
);
391 ret
= tcg_temp_new_i64();
392 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
393 tcg_temp_free_i32(lo
);
394 tcg_temp_free_i32(hi
);
399 static TCGv_i64
gen_muls_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
401 TCGv_i32 lo
= tcg_temp_new_i32();
402 TCGv_i32 hi
= tcg_temp_new_i32();
405 tcg_gen_muls2_i32(lo
, hi
, a
, b
);
406 tcg_temp_free_i32(a
);
407 tcg_temp_free_i32(b
);
409 ret
= tcg_temp_new_i64();
410 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
411 tcg_temp_free_i32(lo
);
412 tcg_temp_free_i32(hi
);
417 /* Swap low and high halfwords. */
418 static void gen_swap_half(TCGv_i32 var
)
420 tcg_gen_rotri_i32(var
, var
, 16);
423 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
424 tmp = (t0 ^ t1) & 0x8000;
427 t0 = (t0 + t1) ^ tmp;
430 static void gen_add16(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
432 TCGv_i32 tmp
= tcg_temp_new_i32();
433 tcg_gen_xor_i32(tmp
, t0
, t1
);
434 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
435 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
436 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
437 tcg_gen_add_i32(t0
, t0
, t1
);
438 tcg_gen_xor_i32(dest
, t0
, tmp
);
439 tcg_temp_free_i32(tmp
);
442 /* Set N and Z flags from var. */
443 static inline void gen_logic_CC(TCGv_i32 var
)
445 tcg_gen_mov_i32(cpu_NF
, var
);
446 tcg_gen_mov_i32(cpu_ZF
, var
);
449 /* dest = T0 + T1 + CF. */
450 static void gen_add_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
452 tcg_gen_add_i32(dest
, t0
, t1
);
453 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
456 /* dest = T0 - T1 + CF - 1. */
457 static void gen_sub_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
459 tcg_gen_sub_i32(dest
, t0
, t1
);
460 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
461 tcg_gen_subi_i32(dest
, dest
, 1);
464 /* dest = T0 + T1. Compute C, N, V and Z flags */
465 static void gen_add_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
467 TCGv_i32 tmp
= tcg_temp_new_i32();
468 tcg_gen_movi_i32(tmp
, 0);
469 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, t1
, tmp
);
470 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
471 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
472 tcg_gen_xor_i32(tmp
, t0
, t1
);
473 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
474 tcg_temp_free_i32(tmp
);
475 tcg_gen_mov_i32(dest
, cpu_NF
);
478 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
479 static void gen_adc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
481 TCGv_i32 tmp
= tcg_temp_new_i32();
482 if (TCG_TARGET_HAS_add2_i32
) {
483 tcg_gen_movi_i32(tmp
, 0);
484 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, cpu_CF
, tmp
);
485 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1
, tmp
);
487 TCGv_i64 q0
= tcg_temp_new_i64();
488 TCGv_i64 q1
= tcg_temp_new_i64();
489 tcg_gen_extu_i32_i64(q0
, t0
);
490 tcg_gen_extu_i32_i64(q1
, t1
);
491 tcg_gen_add_i64(q0
, q0
, q1
);
492 tcg_gen_extu_i32_i64(q1
, cpu_CF
);
493 tcg_gen_add_i64(q0
, q0
, q1
);
494 tcg_gen_extr_i64_i32(cpu_NF
, cpu_CF
, q0
);
495 tcg_temp_free_i64(q0
);
496 tcg_temp_free_i64(q1
);
498 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
499 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
500 tcg_gen_xor_i32(tmp
, t0
, t1
);
501 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
502 tcg_temp_free_i32(tmp
);
503 tcg_gen_mov_i32(dest
, cpu_NF
);
506 /* dest = T0 - T1. Compute C, N, V and Z flags */
507 static void gen_sub_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
510 tcg_gen_sub_i32(cpu_NF
, t0
, t1
);
511 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
512 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0
, t1
);
513 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
514 tmp
= tcg_temp_new_i32();
515 tcg_gen_xor_i32(tmp
, t0
, t1
);
516 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
517 tcg_temp_free_i32(tmp
);
518 tcg_gen_mov_i32(dest
, cpu_NF
);
521 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
522 static void gen_sbc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
524 TCGv_i32 tmp
= tcg_temp_new_i32();
525 tcg_gen_not_i32(tmp
, t1
);
526 gen_adc_CC(dest
, t0
, tmp
);
527 tcg_temp_free_i32(tmp
);
530 #define GEN_SHIFT(name) \
531 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
533 TCGv_i32 tmp1, tmp2, tmp3; \
534 tmp1 = tcg_temp_new_i32(); \
535 tcg_gen_andi_i32(tmp1, t1, 0xff); \
536 tmp2 = tcg_const_i32(0); \
537 tmp3 = tcg_const_i32(0x1f); \
538 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
539 tcg_temp_free_i32(tmp3); \
540 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
541 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
542 tcg_temp_free_i32(tmp2); \
543 tcg_temp_free_i32(tmp1); \
549 static void gen_sar(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
552 tmp1
= tcg_temp_new_i32();
553 tcg_gen_andi_i32(tmp1
, t1
, 0xff);
554 tmp2
= tcg_const_i32(0x1f);
555 tcg_gen_movcond_i32(TCG_COND_GTU
, tmp1
, tmp1
, tmp2
, tmp2
, tmp1
);
556 tcg_temp_free_i32(tmp2
);
557 tcg_gen_sar_i32(dest
, t0
, tmp1
);
558 tcg_temp_free_i32(tmp1
);
561 static void shifter_out_im(TCGv_i32 var
, int shift
)
563 tcg_gen_extract_i32(cpu_CF
, var
, shift
, 1);
566 /* Shift by immediate. Includes special handling for shift == 0. */
567 static inline void gen_arm_shift_im(TCGv_i32 var
, int shiftop
,
568 int shift
, int flags
)
574 shifter_out_im(var
, 32 - shift
);
575 tcg_gen_shli_i32(var
, var
, shift
);
581 tcg_gen_shri_i32(cpu_CF
, var
, 31);
583 tcg_gen_movi_i32(var
, 0);
586 shifter_out_im(var
, shift
- 1);
587 tcg_gen_shri_i32(var
, var
, shift
);
594 shifter_out_im(var
, shift
- 1);
597 tcg_gen_sari_i32(var
, var
, shift
);
599 case 3: /* ROR/RRX */
602 shifter_out_im(var
, shift
- 1);
603 tcg_gen_rotri_i32(var
, var
, shift
); break;
605 TCGv_i32 tmp
= tcg_temp_new_i32();
606 tcg_gen_shli_i32(tmp
, cpu_CF
, 31);
608 shifter_out_im(var
, 0);
609 tcg_gen_shri_i32(var
, var
, 1);
610 tcg_gen_or_i32(var
, var
, tmp
);
611 tcg_temp_free_i32(tmp
);
616 static inline void gen_arm_shift_reg(TCGv_i32 var
, int shiftop
,
617 TCGv_i32 shift
, int flags
)
621 case 0: gen_helper_shl_cc(var
, cpu_env
, var
, shift
); break;
622 case 1: gen_helper_shr_cc(var
, cpu_env
, var
, shift
); break;
623 case 2: gen_helper_sar_cc(var
, cpu_env
, var
, shift
); break;
624 case 3: gen_helper_ror_cc(var
, cpu_env
, var
, shift
); break;
629 gen_shl(var
, var
, shift
);
632 gen_shr(var
, var
, shift
);
635 gen_sar(var
, var
, shift
);
637 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
638 tcg_gen_rotr_i32(var
, var
, shift
); break;
641 tcg_temp_free_i32(shift
);
645 * Generate a conditional based on ARM condition code cc.
646 * This is common between ARM and Aarch64 targets.
648 void arm_test_cc(DisasCompare
*cmp
, int cc
)
679 case 8: /* hi: C && !Z */
680 case 9: /* ls: !C || Z -> !(C && !Z) */
682 value
= tcg_temp_new_i32();
684 /* CF is 1 for C, so -CF is an all-bits-set mask for C;
685 ZF is non-zero for !Z; so AND the two subexpressions. */
686 tcg_gen_neg_i32(value
, cpu_CF
);
687 tcg_gen_and_i32(value
, value
, cpu_ZF
);
690 case 10: /* ge: N == V -> N ^ V == 0 */
691 case 11: /* lt: N != V -> N ^ V != 0 */
692 /* Since we're only interested in the sign bit, == 0 is >= 0. */
694 value
= tcg_temp_new_i32();
696 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
699 case 12: /* gt: !Z && N == V */
700 case 13: /* le: Z || N != V */
702 value
= tcg_temp_new_i32();
704 /* (N == V) is equal to the sign bit of ~(NF ^ VF). Propagate
705 * the sign bit then AND with ZF to yield the result. */
706 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
707 tcg_gen_sari_i32(value
, value
, 31);
708 tcg_gen_andc_i32(value
, cpu_ZF
, value
);
711 case 14: /* always */
712 case 15: /* always */
713 /* Use the ALWAYS condition, which will fold early.
714 * It doesn't matter what we use for the value. */
715 cond
= TCG_COND_ALWAYS
;
720 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
725 cond
= tcg_invert_cond(cond
);
731 cmp
->value_global
= global
;
734 void arm_free_cc(DisasCompare
*cmp
)
736 if (!cmp
->value_global
) {
737 tcg_temp_free_i32(cmp
->value
);
741 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
)
743 tcg_gen_brcondi_i32(cmp
->cond
, cmp
->value
, 0, label
);
746 void arm_gen_test_cc(int cc
, TCGLabel
*label
)
749 arm_test_cc(&cmp
, cc
);
750 arm_jump_cc(&cmp
, label
);
754 static inline void gen_set_condexec(DisasContext
*s
)
756 if (s
->condexec_mask
) {
757 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
758 TCGv_i32 tmp
= tcg_temp_new_i32();
759 tcg_gen_movi_i32(tmp
, val
);
760 store_cpu_field(tmp
, condexec_bits
);
764 static inline void gen_set_pc_im(DisasContext
*s
, target_ulong val
)
766 tcg_gen_movi_i32(cpu_R
[15], val
);
769 /* Set PC and Thumb state from var. var is marked as dead. */
770 static inline void gen_bx(DisasContext
*s
, TCGv_i32 var
)
772 s
->base
.is_jmp
= DISAS_JUMP
;
773 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
774 tcg_gen_andi_i32(var
, var
, 1);
775 store_cpu_field(var
, thumb
);
779 * Set PC and Thumb state from var. var is marked as dead.
780 * For M-profile CPUs, include logic to detect exception-return
781 * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
782 * and BX reg, and no others, and happens only for code in Handler mode.
783 * The Security Extension also requires us to check for the FNC_RETURN
784 * which signals a function return from non-secure state; this can happen
785 * in both Handler and Thread mode.
786 * To avoid having to do multiple comparisons in inline generated code,
787 * we make the check we do here loose, so it will match for EXC_RETURN
788 * in Thread mode. For system emulation do_v7m_exception_exit() checks
789 * for these spurious cases and returns without doing anything (giving
790 * the same behaviour as for a branch to a non-magic address).
792 * In linux-user mode it is unclear what the right behaviour for an
793 * attempted FNC_RETURN should be, because in real hardware this will go
794 * directly to Secure code (ie not the Linux kernel) which will then treat
795 * the error in any way it chooses. For QEMU we opt to make the FNC_RETURN
796 * attempt behave the way it would on a CPU without the security extension,
797 * which is to say "like a normal branch". That means we can simply treat
798 * all branches as normal with no magic address behaviour.
800 static inline void gen_bx_excret(DisasContext
*s
, TCGv_i32 var
)
802 /* Generate the same code here as for a simple bx, but flag via
803 * s->base.is_jmp that we need to do the rest of the work later.
806 #ifndef CONFIG_USER_ONLY
807 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
) ||
808 (s
->v7m_handler_mode
&& arm_dc_feature(s
, ARM_FEATURE_M
))) {
809 s
->base
.is_jmp
= DISAS_BX_EXCRET
;
814 static inline void gen_bx_excret_final_code(DisasContext
*s
)
816 /* Generate the code to finish possible exception return and end the TB */
817 TCGLabel
*excret_label
= gen_new_label();
820 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
)) {
821 /* Covers FNC_RETURN and EXC_RETURN magic */
822 min_magic
= FNC_RETURN_MIN_MAGIC
;
824 /* EXC_RETURN magic only */
825 min_magic
= EXC_RETURN_MIN_MAGIC
;
828 /* Is the new PC value in the magic range indicating exception return? */
829 tcg_gen_brcondi_i32(TCG_COND_GEU
, cpu_R
[15], min_magic
, excret_label
);
830 /* No: end the TB as we would for a DISAS_JMP */
831 if (is_singlestepping(s
)) {
832 gen_singlestep_exception(s
);
834 tcg_gen_exit_tb(NULL
, 0);
836 gen_set_label(excret_label
);
837 /* Yes: this is an exception return.
838 * At this point in runtime env->regs[15] and env->thumb will hold
839 * the exception-return magic number, which do_v7m_exception_exit()
840 * will read. Nothing else will be able to see those values because
841 * the cpu-exec main loop guarantees that we will always go straight
842 * from raising the exception to the exception-handling code.
844 * gen_ss_advance(s) does nothing on M profile currently but
845 * calling it is conceptually the right thing as we have executed
846 * this instruction (compare SWI, HVC, SMC handling).
849 gen_exception_internal(EXCP_EXCEPTION_EXIT
);
852 static inline void gen_bxns(DisasContext
*s
, int rm
)
854 TCGv_i32 var
= load_reg(s
, rm
);
856 /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
857 * we need to sync state before calling it, but:
858 * - we don't need to do gen_set_pc_im() because the bxns helper will
859 * always set the PC itself
860 * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
861 * unless it's outside an IT block or the last insn in an IT block,
862 * so we know that condexec == 0 (already set at the top of the TB)
863 * is correct in the non-UNPREDICTABLE cases, and we can choose
864 * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
866 gen_helper_v7m_bxns(cpu_env
, var
);
867 tcg_temp_free_i32(var
);
868 s
->base
.is_jmp
= DISAS_EXIT
;
871 static inline void gen_blxns(DisasContext
*s
, int rm
)
873 TCGv_i32 var
= load_reg(s
, rm
);
875 /* We don't need to sync condexec state, for the same reason as bxns.
876 * We do however need to set the PC, because the blxns helper reads it.
877 * The blxns helper may throw an exception.
879 gen_set_pc_im(s
, s
->base
.pc_next
);
880 gen_helper_v7m_blxns(cpu_env
, var
);
881 tcg_temp_free_i32(var
);
882 s
->base
.is_jmp
= DISAS_EXIT
;
885 /* Variant of store_reg which uses branch&exchange logic when storing
886 to r15 in ARM architecture v7 and above. The source must be a temporary
887 and will be marked as dead. */
888 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv_i32 var
)
890 if (reg
== 15 && ENABLE_ARCH_7
) {
893 store_reg(s
, reg
, var
);
897 /* Variant of store_reg which uses branch&exchange logic when storing
898 * to r15 in ARM architecture v5T and above. This is used for storing
899 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
900 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
901 static inline void store_reg_from_load(DisasContext
*s
, int reg
, TCGv_i32 var
)
903 if (reg
== 15 && ENABLE_ARCH_5
) {
904 gen_bx_excret(s
, var
);
906 store_reg(s
, reg
, var
);
910 #ifdef CONFIG_USER_ONLY
911 #define IS_USER_ONLY 1
913 #define IS_USER_ONLY 0
916 /* Abstractions of "generate code to do a guest load/store for
917 * AArch32", where a vaddr is always 32 bits (and is zero
918 * extended if we're a 64 bit core) and data is also
919 * 32 bits unless specifically doing a 64 bit access.
920 * These functions work like tcg_gen_qemu_{ld,st}* except
921 * that the address argument is TCGv_i32 rather than TCGv.
924 static inline TCGv
gen_aa32_addr(DisasContext
*s
, TCGv_i32 a32
, MemOp op
)
926 TCGv addr
= tcg_temp_new();
927 tcg_gen_extu_i32_tl(addr
, a32
);
929 /* Not needed for user-mode BE32, where we use MO_BE instead. */
930 if (!IS_USER_ONLY
&& s
->sctlr_b
&& (op
& MO_SIZE
) < MO_32
) {
931 tcg_gen_xori_tl(addr
, addr
, 4 - (1 << (op
& MO_SIZE
)));
936 static void gen_aa32_ld_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
937 int index
, MemOp opc
)
941 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
942 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
946 addr
= gen_aa32_addr(s
, a32
, opc
);
947 tcg_gen_qemu_ld_i32(val
, addr
, index
, opc
);
951 static void gen_aa32_st_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
952 int index
, MemOp opc
)
956 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
957 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
961 addr
= gen_aa32_addr(s
, a32
, opc
);
962 tcg_gen_qemu_st_i32(val
, addr
, index
, opc
);
966 #define DO_GEN_LD(SUFF, OPC) \
967 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
968 TCGv_i32 a32, int index) \
970 gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
973 #define DO_GEN_ST(SUFF, OPC) \
974 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
975 TCGv_i32 a32, int index) \
977 gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
980 static inline void gen_aa32_frob64(DisasContext
*s
, TCGv_i64 val
)
982 /* Not needed for user-mode BE32, where we use MO_BE instead. */
983 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
984 tcg_gen_rotri_i64(val
, val
, 32);
988 static void gen_aa32_ld_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
989 int index
, MemOp opc
)
991 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
992 tcg_gen_qemu_ld_i64(val
, addr
, index
, opc
);
993 gen_aa32_frob64(s
, val
);
997 static inline void gen_aa32_ld64(DisasContext
*s
, TCGv_i64 val
,
998 TCGv_i32 a32
, int index
)
1000 gen_aa32_ld_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1003 static void gen_aa32_st_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1004 int index
, MemOp opc
)
1006 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1008 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1009 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1010 TCGv_i64 tmp
= tcg_temp_new_i64();
1011 tcg_gen_rotri_i64(tmp
, val
, 32);
1012 tcg_gen_qemu_st_i64(tmp
, addr
, index
, opc
);
1013 tcg_temp_free_i64(tmp
);
1015 tcg_gen_qemu_st_i64(val
, addr
, index
, opc
);
1017 tcg_temp_free(addr
);
1020 static inline void gen_aa32_st64(DisasContext
*s
, TCGv_i64 val
,
1021 TCGv_i32 a32
, int index
)
1023 gen_aa32_st_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1026 DO_GEN_LD(8u, MO_UB
)
1027 DO_GEN_LD(16u, MO_UW
)
1028 DO_GEN_LD(32u, MO_UL
)
1030 DO_GEN_ST(16, MO_UW
)
1031 DO_GEN_ST(32, MO_UL
)
1033 static inline void gen_hvc(DisasContext
*s
, int imm16
)
1035 /* The pre HVC helper handles cases when HVC gets trapped
1036 * as an undefined insn by runtime configuration (ie before
1037 * the insn really executes).
1039 gen_set_pc_im(s
, s
->pc_curr
);
1040 gen_helper_pre_hvc(cpu_env
);
1041 /* Otherwise we will treat this as a real exception which
1042 * happens after execution of the insn. (The distinction matters
1043 * for the PC value reported to the exception handler and also
1044 * for single stepping.)
1047 gen_set_pc_im(s
, s
->base
.pc_next
);
1048 s
->base
.is_jmp
= DISAS_HVC
;
1051 static inline void gen_smc(DisasContext
*s
)
1053 /* As with HVC, we may take an exception either before or after
1054 * the insn executes.
1058 gen_set_pc_im(s
, s
->pc_curr
);
1059 tmp
= tcg_const_i32(syn_aa32_smc());
1060 gen_helper_pre_smc(cpu_env
, tmp
);
1061 tcg_temp_free_i32(tmp
);
1062 gen_set_pc_im(s
, s
->base
.pc_next
);
1063 s
->base
.is_jmp
= DISAS_SMC
;
1066 static void gen_exception_internal_insn(DisasContext
*s
, uint32_t pc
, int excp
)
1068 gen_set_condexec(s
);
1069 gen_set_pc_im(s
, pc
);
1070 gen_exception_internal(excp
);
1071 s
->base
.is_jmp
= DISAS_NORETURN
;
1074 static void gen_exception_insn(DisasContext
*s
, uint32_t pc
, int excp
,
1075 int syn
, uint32_t target_el
)
1077 gen_set_condexec(s
);
1078 gen_set_pc_im(s
, pc
);
1079 gen_exception(excp
, syn
, target_el
);
1080 s
->base
.is_jmp
= DISAS_NORETURN
;
1083 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syn
)
1087 gen_set_condexec(s
);
1088 gen_set_pc_im(s
, s
->pc_curr
);
1089 tcg_syn
= tcg_const_i32(syn
);
1090 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
1091 tcg_temp_free_i32(tcg_syn
);
1092 s
->base
.is_jmp
= DISAS_NORETURN
;
1095 static void unallocated_encoding(DisasContext
*s
)
1097 /* Unallocated and reserved encodings are uncategorized */
1098 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
1099 default_exception_el(s
));
1102 /* Force a TB lookup after an instruction that changes the CPU state. */
1103 static inline void gen_lookup_tb(DisasContext
*s
)
1105 tcg_gen_movi_i32(cpu_R
[15], s
->base
.pc_next
);
1106 s
->base
.is_jmp
= DISAS_EXIT
;
1109 static inline void gen_hlt(DisasContext
*s
, int imm
)
1111 /* HLT. This has two purposes.
1112 * Architecturally, it is an external halting debug instruction.
1113 * Since QEMU doesn't implement external debug, we treat this as
1114 * it is required for halting debug disabled: it will UNDEF.
1115 * Secondly, "HLT 0x3C" is a T32 semihosting trap instruction,
1116 * and "HLT 0xF000" is an A32 semihosting syscall. These traps
1117 * must trigger semihosting even for ARMv7 and earlier, where
1118 * HLT was an undefined encoding.
1119 * In system mode, we don't allow userspace access to
1120 * semihosting, to provide some semblance of security
1121 * (and for consistency with our 32-bit semihosting).
1123 if (semihosting_enabled() &&
1124 #ifndef CONFIG_USER_ONLY
1125 s
->current_el
!= 0 &&
1127 (imm
== (s
->thumb
? 0x3c : 0xf000))) {
1128 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1132 unallocated_encoding(s
);
1135 static TCGv_ptr
get_fpstatus_ptr(int neon
)
1137 TCGv_ptr statusptr
= tcg_temp_new_ptr();
1140 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
1142 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
1144 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
1148 static inline long vfp_reg_offset(bool dp
, unsigned reg
)
1151 return offsetof(CPUARMState
, vfp
.zregs
[reg
>> 1].d
[reg
& 1]);
1153 long ofs
= offsetof(CPUARMState
, vfp
.zregs
[reg
>> 2].d
[(reg
>> 1) & 1]);
1155 ofs
+= offsetof(CPU_DoubleU
, l
.upper
);
1157 ofs
+= offsetof(CPU_DoubleU
, l
.lower
);
1163 /* Return the offset of a 32-bit piece of a NEON register.
1164 zero is the least significant end of the register. */
1166 neon_reg_offset (int reg
, int n
)
1170 return vfp_reg_offset(0, sreg
);
1173 /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
1174 * where 0 is the least significant end of the register.
1177 neon_element_offset(int reg
, int element
, MemOp size
)
1179 int element_size
= 1 << size
;
1180 int ofs
= element
* element_size
;
1181 #ifdef HOST_WORDS_BIGENDIAN
1182 /* Calculate the offset assuming fully little-endian,
1183 * then XOR to account for the order of the 8-byte units.
1185 if (element_size
< 8) {
1186 ofs
^= 8 - element_size
;
1189 return neon_reg_offset(reg
, 0) + ofs
;
1192 static TCGv_i32
neon_load_reg(int reg
, int pass
)
1194 TCGv_i32 tmp
= tcg_temp_new_i32();
1195 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1199 static void neon_load_element(TCGv_i32 var
, int reg
, int ele
, MemOp mop
)
1201 long offset
= neon_element_offset(reg
, ele
, mop
& MO_SIZE
);
1205 tcg_gen_ld8u_i32(var
, cpu_env
, offset
);
1208 tcg_gen_ld16u_i32(var
, cpu_env
, offset
);
1211 tcg_gen_ld_i32(var
, cpu_env
, offset
);
1214 g_assert_not_reached();
1218 static void neon_load_element64(TCGv_i64 var
, int reg
, int ele
, MemOp mop
)
1220 long offset
= neon_element_offset(reg
, ele
, mop
& MO_SIZE
);
1224 tcg_gen_ld8u_i64(var
, cpu_env
, offset
);
1227 tcg_gen_ld16u_i64(var
, cpu_env
, offset
);
1230 tcg_gen_ld32u_i64(var
, cpu_env
, offset
);
1233 tcg_gen_ld_i64(var
, cpu_env
, offset
);
1236 g_assert_not_reached();
1240 static void neon_store_reg(int reg
, int pass
, TCGv_i32 var
)
1242 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1243 tcg_temp_free_i32(var
);
1246 static void neon_store_element(int reg
, int ele
, MemOp size
, TCGv_i32 var
)
1248 long offset
= neon_element_offset(reg
, ele
, size
);
1252 tcg_gen_st8_i32(var
, cpu_env
, offset
);
1255 tcg_gen_st16_i32(var
, cpu_env
, offset
);
1258 tcg_gen_st_i32(var
, cpu_env
, offset
);
1261 g_assert_not_reached();
1265 static void neon_store_element64(int reg
, int ele
, MemOp size
, TCGv_i64 var
)
1267 long offset
= neon_element_offset(reg
, ele
, size
);
1271 tcg_gen_st8_i64(var
, cpu_env
, offset
);
1274 tcg_gen_st16_i64(var
, cpu_env
, offset
);
1277 tcg_gen_st32_i64(var
, cpu_env
, offset
);
1280 tcg_gen_st_i64(var
, cpu_env
, offset
);
1283 g_assert_not_reached();
1287 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1289 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1292 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1294 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1297 static inline void neon_load_reg32(TCGv_i32 var
, int reg
)
1299 tcg_gen_ld_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
1302 static inline void neon_store_reg32(TCGv_i32 var
, int reg
)
1304 tcg_gen_st_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
1307 static TCGv_ptr
vfp_reg_ptr(bool dp
, int reg
)
1309 TCGv_ptr ret
= tcg_temp_new_ptr();
1310 tcg_gen_addi_ptr(ret
, cpu_env
, vfp_reg_offset(dp
, reg
));
1314 #define ARM_CP_RW_BIT (1 << 20)
1316 /* Include the VFP and Neon decoders */
1317 #include "translate-vfp.inc.c"
1318 #include "translate-neon.inc.c"
1320 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1322 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1325 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1327 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1330 static inline TCGv_i32
iwmmxt_load_creg(int reg
)
1332 TCGv_i32 var
= tcg_temp_new_i32();
1333 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1337 static inline void iwmmxt_store_creg(int reg
, TCGv_i32 var
)
1339 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1340 tcg_temp_free_i32(var
);
1343 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1345 iwmmxt_store_reg(cpu_M0
, rn
);
1348 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1350 iwmmxt_load_reg(cpu_M0
, rn
);
1353 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1355 iwmmxt_load_reg(cpu_V1
, rn
);
1356 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1359 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1361 iwmmxt_load_reg(cpu_V1
, rn
);
1362 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1365 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1367 iwmmxt_load_reg(cpu_V1
, rn
);
1368 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1371 #define IWMMXT_OP(name) \
1372 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1374 iwmmxt_load_reg(cpu_V1, rn); \
1375 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1378 #define IWMMXT_OP_ENV(name) \
1379 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1381 iwmmxt_load_reg(cpu_V1, rn); \
1382 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1385 #define IWMMXT_OP_ENV_SIZE(name) \
1386 IWMMXT_OP_ENV(name##b) \
1387 IWMMXT_OP_ENV(name##w) \
1388 IWMMXT_OP_ENV(name##l)
1390 #define IWMMXT_OP_ENV1(name) \
1391 static inline void gen_op_iwmmxt_##name##_M0(void) \
1393 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1407 IWMMXT_OP_ENV_SIZE(unpackl
)
1408 IWMMXT_OP_ENV_SIZE(unpackh
)
1410 IWMMXT_OP_ENV1(unpacklub
)
1411 IWMMXT_OP_ENV1(unpackluw
)
1412 IWMMXT_OP_ENV1(unpacklul
)
1413 IWMMXT_OP_ENV1(unpackhub
)
1414 IWMMXT_OP_ENV1(unpackhuw
)
1415 IWMMXT_OP_ENV1(unpackhul
)
1416 IWMMXT_OP_ENV1(unpacklsb
)
1417 IWMMXT_OP_ENV1(unpacklsw
)
1418 IWMMXT_OP_ENV1(unpacklsl
)
1419 IWMMXT_OP_ENV1(unpackhsb
)
1420 IWMMXT_OP_ENV1(unpackhsw
)
1421 IWMMXT_OP_ENV1(unpackhsl
)
1423 IWMMXT_OP_ENV_SIZE(cmpeq
)
1424 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1425 IWMMXT_OP_ENV_SIZE(cmpgts
)
1427 IWMMXT_OP_ENV_SIZE(mins
)
1428 IWMMXT_OP_ENV_SIZE(minu
)
1429 IWMMXT_OP_ENV_SIZE(maxs
)
1430 IWMMXT_OP_ENV_SIZE(maxu
)
1432 IWMMXT_OP_ENV_SIZE(subn
)
1433 IWMMXT_OP_ENV_SIZE(addn
)
1434 IWMMXT_OP_ENV_SIZE(subu
)
1435 IWMMXT_OP_ENV_SIZE(addu
)
1436 IWMMXT_OP_ENV_SIZE(subs
)
1437 IWMMXT_OP_ENV_SIZE(adds
)
1439 IWMMXT_OP_ENV(avgb0
)
1440 IWMMXT_OP_ENV(avgb1
)
1441 IWMMXT_OP_ENV(avgw0
)
1442 IWMMXT_OP_ENV(avgw1
)
1444 IWMMXT_OP_ENV(packuw
)
1445 IWMMXT_OP_ENV(packul
)
1446 IWMMXT_OP_ENV(packuq
)
1447 IWMMXT_OP_ENV(packsw
)
1448 IWMMXT_OP_ENV(packsl
)
1449 IWMMXT_OP_ENV(packsq
)
1451 static void gen_op_iwmmxt_set_mup(void)
1454 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1455 tcg_gen_ori_i32(tmp
, tmp
, 2);
1456 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1459 static void gen_op_iwmmxt_set_cup(void)
1462 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1463 tcg_gen_ori_i32(tmp
, tmp
, 1);
1464 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1467 static void gen_op_iwmmxt_setpsr_nz(void)
1469 TCGv_i32 tmp
= tcg_temp_new_i32();
1470 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1471 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1474 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1476 iwmmxt_load_reg(cpu_V1
, rn
);
1477 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1478 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1481 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
,
1488 rd
= (insn
>> 16) & 0xf;
1489 tmp
= load_reg(s
, rd
);
1491 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1492 if (insn
& (1 << 24)) {
1494 if (insn
& (1 << 23))
1495 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1497 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1498 tcg_gen_mov_i32(dest
, tmp
);
1499 if (insn
& (1 << 21))
1500 store_reg(s
, rd
, tmp
);
1502 tcg_temp_free_i32(tmp
);
1503 } else if (insn
& (1 << 21)) {
1505 tcg_gen_mov_i32(dest
, tmp
);
1506 if (insn
& (1 << 23))
1507 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1509 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1510 store_reg(s
, rd
, tmp
);
1511 } else if (!(insn
& (1 << 23)))
1516 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv_i32 dest
)
1518 int rd
= (insn
>> 0) & 0xf;
1521 if (insn
& (1 << 8)) {
1522 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1525 tmp
= iwmmxt_load_creg(rd
);
1528 tmp
= tcg_temp_new_i32();
1529 iwmmxt_load_reg(cpu_V0
, rd
);
1530 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
1532 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1533 tcg_gen_mov_i32(dest
, tmp
);
1534 tcg_temp_free_i32(tmp
);
1538 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1539 (ie. an undefined instruction). */
1540 static int disas_iwmmxt_insn(DisasContext
*s
, uint32_t insn
)
1543 int rdhi
, rdlo
, rd0
, rd1
, i
;
1545 TCGv_i32 tmp
, tmp2
, tmp3
;
1547 if ((insn
& 0x0e000e00) == 0x0c000000) {
1548 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1550 rdlo
= (insn
>> 12) & 0xf;
1551 rdhi
= (insn
>> 16) & 0xf;
1552 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1553 iwmmxt_load_reg(cpu_V0
, wrd
);
1554 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1555 tcg_gen_extrh_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1556 } else { /* TMCRR */
1557 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1558 iwmmxt_store_reg(cpu_V0
, wrd
);
1559 gen_op_iwmmxt_set_mup();
1564 wrd
= (insn
>> 12) & 0xf;
1565 addr
= tcg_temp_new_i32();
1566 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1567 tcg_temp_free_i32(addr
);
1570 if (insn
& ARM_CP_RW_BIT
) {
1571 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1572 tmp
= tcg_temp_new_i32();
1573 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1574 iwmmxt_store_creg(wrd
, tmp
);
1577 if (insn
& (1 << 8)) {
1578 if (insn
& (1 << 22)) { /* WLDRD */
1579 gen_aa32_ld64(s
, cpu_M0
, addr
, get_mem_index(s
));
1581 } else { /* WLDRW wRd */
1582 tmp
= tcg_temp_new_i32();
1583 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1586 tmp
= tcg_temp_new_i32();
1587 if (insn
& (1 << 22)) { /* WLDRH */
1588 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
1589 } else { /* WLDRB */
1590 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
1594 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1595 tcg_temp_free_i32(tmp
);
1597 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1600 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1601 tmp
= iwmmxt_load_creg(wrd
);
1602 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1604 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1605 tmp
= tcg_temp_new_i32();
1606 if (insn
& (1 << 8)) {
1607 if (insn
& (1 << 22)) { /* WSTRD */
1608 gen_aa32_st64(s
, cpu_M0
, addr
, get_mem_index(s
));
1609 } else { /* WSTRW wRd */
1610 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1611 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1614 if (insn
& (1 << 22)) { /* WSTRH */
1615 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1616 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
1617 } else { /* WSTRB */
1618 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1619 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
1623 tcg_temp_free_i32(tmp
);
1625 tcg_temp_free_i32(addr
);
1629 if ((insn
& 0x0f000000) != 0x0e000000)
1632 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1633 case 0x000: /* WOR */
1634 wrd
= (insn
>> 12) & 0xf;
1635 rd0
= (insn
>> 0) & 0xf;
1636 rd1
= (insn
>> 16) & 0xf;
1637 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1638 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1639 gen_op_iwmmxt_setpsr_nz();
1640 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1641 gen_op_iwmmxt_set_mup();
1642 gen_op_iwmmxt_set_cup();
1644 case 0x011: /* TMCR */
1647 rd
= (insn
>> 12) & 0xf;
1648 wrd
= (insn
>> 16) & 0xf;
1650 case ARM_IWMMXT_wCID
:
1651 case ARM_IWMMXT_wCASF
:
1653 case ARM_IWMMXT_wCon
:
1654 gen_op_iwmmxt_set_cup();
1656 case ARM_IWMMXT_wCSSF
:
1657 tmp
= iwmmxt_load_creg(wrd
);
1658 tmp2
= load_reg(s
, rd
);
1659 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1660 tcg_temp_free_i32(tmp2
);
1661 iwmmxt_store_creg(wrd
, tmp
);
1663 case ARM_IWMMXT_wCGR0
:
1664 case ARM_IWMMXT_wCGR1
:
1665 case ARM_IWMMXT_wCGR2
:
1666 case ARM_IWMMXT_wCGR3
:
1667 gen_op_iwmmxt_set_cup();
1668 tmp
= load_reg(s
, rd
);
1669 iwmmxt_store_creg(wrd
, tmp
);
1675 case 0x100: /* WXOR */
1676 wrd
= (insn
>> 12) & 0xf;
1677 rd0
= (insn
>> 0) & 0xf;
1678 rd1
= (insn
>> 16) & 0xf;
1679 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1680 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1681 gen_op_iwmmxt_setpsr_nz();
1682 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1683 gen_op_iwmmxt_set_mup();
1684 gen_op_iwmmxt_set_cup();
1686 case 0x111: /* TMRC */
1689 rd
= (insn
>> 12) & 0xf;
1690 wrd
= (insn
>> 16) & 0xf;
1691 tmp
= iwmmxt_load_creg(wrd
);
1692 store_reg(s
, rd
, tmp
);
1694 case 0x300: /* WANDN */
1695 wrd
= (insn
>> 12) & 0xf;
1696 rd0
= (insn
>> 0) & 0xf;
1697 rd1
= (insn
>> 16) & 0xf;
1698 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1699 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1700 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1701 gen_op_iwmmxt_setpsr_nz();
1702 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1703 gen_op_iwmmxt_set_mup();
1704 gen_op_iwmmxt_set_cup();
1706 case 0x200: /* WAND */
1707 wrd
= (insn
>> 12) & 0xf;
1708 rd0
= (insn
>> 0) & 0xf;
1709 rd1
= (insn
>> 16) & 0xf;
1710 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1711 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1712 gen_op_iwmmxt_setpsr_nz();
1713 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1714 gen_op_iwmmxt_set_mup();
1715 gen_op_iwmmxt_set_cup();
1717 case 0x810: case 0xa10: /* WMADD */
1718 wrd
= (insn
>> 12) & 0xf;
1719 rd0
= (insn
>> 0) & 0xf;
1720 rd1
= (insn
>> 16) & 0xf;
1721 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1722 if (insn
& (1 << 21))
1723 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1725 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1726 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1727 gen_op_iwmmxt_set_mup();
1729 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1730 wrd
= (insn
>> 12) & 0xf;
1731 rd0
= (insn
>> 16) & 0xf;
1732 rd1
= (insn
>> 0) & 0xf;
1733 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1734 switch ((insn
>> 22) & 3) {
1736 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1739 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1742 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1747 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1748 gen_op_iwmmxt_set_mup();
1749 gen_op_iwmmxt_set_cup();
1751 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1752 wrd
= (insn
>> 12) & 0xf;
1753 rd0
= (insn
>> 16) & 0xf;
1754 rd1
= (insn
>> 0) & 0xf;
1755 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1756 switch ((insn
>> 22) & 3) {
1758 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1761 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1764 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1769 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1770 gen_op_iwmmxt_set_mup();
1771 gen_op_iwmmxt_set_cup();
1773 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1774 wrd
= (insn
>> 12) & 0xf;
1775 rd0
= (insn
>> 16) & 0xf;
1776 rd1
= (insn
>> 0) & 0xf;
1777 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1778 if (insn
& (1 << 22))
1779 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1781 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1782 if (!(insn
& (1 << 20)))
1783 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1784 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1785 gen_op_iwmmxt_set_mup();
1787 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1788 wrd
= (insn
>> 12) & 0xf;
1789 rd0
= (insn
>> 16) & 0xf;
1790 rd1
= (insn
>> 0) & 0xf;
1791 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1792 if (insn
& (1 << 21)) {
1793 if (insn
& (1 << 20))
1794 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1796 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1798 if (insn
& (1 << 20))
1799 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1801 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1803 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1804 gen_op_iwmmxt_set_mup();
1806 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1807 wrd
= (insn
>> 12) & 0xf;
1808 rd0
= (insn
>> 16) & 0xf;
1809 rd1
= (insn
>> 0) & 0xf;
1810 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1811 if (insn
& (1 << 21))
1812 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1814 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1815 if (!(insn
& (1 << 20))) {
1816 iwmmxt_load_reg(cpu_V1
, wrd
);
1817 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1819 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1820 gen_op_iwmmxt_set_mup();
1822 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1823 wrd
= (insn
>> 12) & 0xf;
1824 rd0
= (insn
>> 16) & 0xf;
1825 rd1
= (insn
>> 0) & 0xf;
1826 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1827 switch ((insn
>> 22) & 3) {
1829 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1832 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1835 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1840 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1841 gen_op_iwmmxt_set_mup();
1842 gen_op_iwmmxt_set_cup();
1844 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1845 wrd
= (insn
>> 12) & 0xf;
1846 rd0
= (insn
>> 16) & 0xf;
1847 rd1
= (insn
>> 0) & 0xf;
1848 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1849 if (insn
& (1 << 22)) {
1850 if (insn
& (1 << 20))
1851 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
1853 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
1855 if (insn
& (1 << 20))
1856 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
1858 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
1860 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1861 gen_op_iwmmxt_set_mup();
1862 gen_op_iwmmxt_set_cup();
1864 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1865 wrd
= (insn
>> 12) & 0xf;
1866 rd0
= (insn
>> 16) & 0xf;
1867 rd1
= (insn
>> 0) & 0xf;
1868 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1869 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
1870 tcg_gen_andi_i32(tmp
, tmp
, 7);
1871 iwmmxt_load_reg(cpu_V1
, rd1
);
1872 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
1873 tcg_temp_free_i32(tmp
);
1874 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1875 gen_op_iwmmxt_set_mup();
1877 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1878 if (((insn
>> 6) & 3) == 3)
1880 rd
= (insn
>> 12) & 0xf;
1881 wrd
= (insn
>> 16) & 0xf;
1882 tmp
= load_reg(s
, rd
);
1883 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1884 switch ((insn
>> 6) & 3) {
1886 tmp2
= tcg_const_i32(0xff);
1887 tmp3
= tcg_const_i32((insn
& 7) << 3);
1890 tmp2
= tcg_const_i32(0xffff);
1891 tmp3
= tcg_const_i32((insn
& 3) << 4);
1894 tmp2
= tcg_const_i32(0xffffffff);
1895 tmp3
= tcg_const_i32((insn
& 1) << 5);
1901 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
1902 tcg_temp_free_i32(tmp3
);
1903 tcg_temp_free_i32(tmp2
);
1904 tcg_temp_free_i32(tmp
);
1905 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1906 gen_op_iwmmxt_set_mup();
1908 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1909 rd
= (insn
>> 12) & 0xf;
1910 wrd
= (insn
>> 16) & 0xf;
1911 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
1913 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1914 tmp
= tcg_temp_new_i32();
1915 switch ((insn
>> 22) & 3) {
1917 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
1918 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1920 tcg_gen_ext8s_i32(tmp
, tmp
);
1922 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
1926 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
1927 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1929 tcg_gen_ext16s_i32(tmp
, tmp
);
1931 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
1935 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
1936 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1939 store_reg(s
, rd
, tmp
);
1941 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1942 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1944 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1945 switch ((insn
>> 22) & 3) {
1947 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
1950 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
1953 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
1956 tcg_gen_shli_i32(tmp
, tmp
, 28);
1958 tcg_temp_free_i32(tmp
);
1960 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1961 if (((insn
>> 6) & 3) == 3)
1963 rd
= (insn
>> 12) & 0xf;
1964 wrd
= (insn
>> 16) & 0xf;
1965 tmp
= load_reg(s
, rd
);
1966 switch ((insn
>> 6) & 3) {
1968 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
1971 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
1974 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
1977 tcg_temp_free_i32(tmp
);
1978 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1979 gen_op_iwmmxt_set_mup();
1981 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1982 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1984 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1985 tmp2
= tcg_temp_new_i32();
1986 tcg_gen_mov_i32(tmp2
, tmp
);
1987 switch ((insn
>> 22) & 3) {
1989 for (i
= 0; i
< 7; i
++) {
1990 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1991 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1995 for (i
= 0; i
< 3; i
++) {
1996 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1997 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2001 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2002 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2006 tcg_temp_free_i32(tmp2
);
2007 tcg_temp_free_i32(tmp
);
2009 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
2010 wrd
= (insn
>> 12) & 0xf;
2011 rd0
= (insn
>> 16) & 0xf;
2012 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2013 switch ((insn
>> 22) & 3) {
2015 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
2018 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
2021 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
2026 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2027 gen_op_iwmmxt_set_mup();
2029 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
2030 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2032 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2033 tmp2
= tcg_temp_new_i32();
2034 tcg_gen_mov_i32(tmp2
, tmp
);
2035 switch ((insn
>> 22) & 3) {
2037 for (i
= 0; i
< 7; i
++) {
2038 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2039 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2043 for (i
= 0; i
< 3; i
++) {
2044 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2045 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2049 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2050 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2054 tcg_temp_free_i32(tmp2
);
2055 tcg_temp_free_i32(tmp
);
2057 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2058 rd
= (insn
>> 12) & 0xf;
2059 rd0
= (insn
>> 16) & 0xf;
2060 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
2062 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2063 tmp
= tcg_temp_new_i32();
2064 switch ((insn
>> 22) & 3) {
2066 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
2069 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
2072 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
2075 store_reg(s
, rd
, tmp
);
2077 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2078 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2079 wrd
= (insn
>> 12) & 0xf;
2080 rd0
= (insn
>> 16) & 0xf;
2081 rd1
= (insn
>> 0) & 0xf;
2082 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2083 switch ((insn
>> 22) & 3) {
2085 if (insn
& (1 << 21))
2086 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
2088 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
2091 if (insn
& (1 << 21))
2092 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
2094 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
2097 if (insn
& (1 << 21))
2098 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
2100 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
2105 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2106 gen_op_iwmmxt_set_mup();
2107 gen_op_iwmmxt_set_cup();
2109 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2110 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2111 wrd
= (insn
>> 12) & 0xf;
2112 rd0
= (insn
>> 16) & 0xf;
2113 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2114 switch ((insn
>> 22) & 3) {
2116 if (insn
& (1 << 21))
2117 gen_op_iwmmxt_unpacklsb_M0();
2119 gen_op_iwmmxt_unpacklub_M0();
2122 if (insn
& (1 << 21))
2123 gen_op_iwmmxt_unpacklsw_M0();
2125 gen_op_iwmmxt_unpackluw_M0();
2128 if (insn
& (1 << 21))
2129 gen_op_iwmmxt_unpacklsl_M0();
2131 gen_op_iwmmxt_unpacklul_M0();
2136 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2137 gen_op_iwmmxt_set_mup();
2138 gen_op_iwmmxt_set_cup();
2140 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2141 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2142 wrd
= (insn
>> 12) & 0xf;
2143 rd0
= (insn
>> 16) & 0xf;
2144 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2145 switch ((insn
>> 22) & 3) {
2147 if (insn
& (1 << 21))
2148 gen_op_iwmmxt_unpackhsb_M0();
2150 gen_op_iwmmxt_unpackhub_M0();
2153 if (insn
& (1 << 21))
2154 gen_op_iwmmxt_unpackhsw_M0();
2156 gen_op_iwmmxt_unpackhuw_M0();
2159 if (insn
& (1 << 21))
2160 gen_op_iwmmxt_unpackhsl_M0();
2162 gen_op_iwmmxt_unpackhul_M0();
2167 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2168 gen_op_iwmmxt_set_mup();
2169 gen_op_iwmmxt_set_cup();
2171 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2172 case 0x214: case 0x614: case 0xa14: case 0xe14:
2173 if (((insn
>> 22) & 3) == 0)
2175 wrd
= (insn
>> 12) & 0xf;
2176 rd0
= (insn
>> 16) & 0xf;
2177 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2178 tmp
= tcg_temp_new_i32();
2179 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2180 tcg_temp_free_i32(tmp
);
2183 switch ((insn
>> 22) & 3) {
2185 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2188 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2191 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2194 tcg_temp_free_i32(tmp
);
2195 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2196 gen_op_iwmmxt_set_mup();
2197 gen_op_iwmmxt_set_cup();
2199 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2200 case 0x014: case 0x414: case 0x814: case 0xc14:
2201 if (((insn
>> 22) & 3) == 0)
2203 wrd
= (insn
>> 12) & 0xf;
2204 rd0
= (insn
>> 16) & 0xf;
2205 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2206 tmp
= tcg_temp_new_i32();
2207 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2208 tcg_temp_free_i32(tmp
);
2211 switch ((insn
>> 22) & 3) {
2213 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2216 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2219 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2222 tcg_temp_free_i32(tmp
);
2223 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2224 gen_op_iwmmxt_set_mup();
2225 gen_op_iwmmxt_set_cup();
2227 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2228 case 0x114: case 0x514: case 0x914: case 0xd14:
2229 if (((insn
>> 22) & 3) == 0)
2231 wrd
= (insn
>> 12) & 0xf;
2232 rd0
= (insn
>> 16) & 0xf;
2233 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2234 tmp
= tcg_temp_new_i32();
2235 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2236 tcg_temp_free_i32(tmp
);
2239 switch ((insn
>> 22) & 3) {
2241 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2244 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2247 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2250 tcg_temp_free_i32(tmp
);
2251 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2252 gen_op_iwmmxt_set_mup();
2253 gen_op_iwmmxt_set_cup();
2255 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2256 case 0x314: case 0x714: case 0xb14: case 0xf14:
2257 if (((insn
>> 22) & 3) == 0)
2259 wrd
= (insn
>> 12) & 0xf;
2260 rd0
= (insn
>> 16) & 0xf;
2261 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2262 tmp
= tcg_temp_new_i32();
2263 switch ((insn
>> 22) & 3) {
2265 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2266 tcg_temp_free_i32(tmp
);
2269 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2272 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2273 tcg_temp_free_i32(tmp
);
2276 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2279 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2280 tcg_temp_free_i32(tmp
);
2283 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2286 tcg_temp_free_i32(tmp
);
2287 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2288 gen_op_iwmmxt_set_mup();
2289 gen_op_iwmmxt_set_cup();
2291 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2292 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2293 wrd
= (insn
>> 12) & 0xf;
2294 rd0
= (insn
>> 16) & 0xf;
2295 rd1
= (insn
>> 0) & 0xf;
2296 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2297 switch ((insn
>> 22) & 3) {
2299 if (insn
& (1 << 21))
2300 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2302 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2305 if (insn
& (1 << 21))
2306 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2308 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2311 if (insn
& (1 << 21))
2312 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2314 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2319 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2320 gen_op_iwmmxt_set_mup();
2322 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2323 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2324 wrd
= (insn
>> 12) & 0xf;
2325 rd0
= (insn
>> 16) & 0xf;
2326 rd1
= (insn
>> 0) & 0xf;
2327 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2328 switch ((insn
>> 22) & 3) {
2330 if (insn
& (1 << 21))
2331 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2333 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2336 if (insn
& (1 << 21))
2337 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2339 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2342 if (insn
& (1 << 21))
2343 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2345 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2350 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2351 gen_op_iwmmxt_set_mup();
2353 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2354 case 0x402: case 0x502: case 0x602: case 0x702:
2355 wrd
= (insn
>> 12) & 0xf;
2356 rd0
= (insn
>> 16) & 0xf;
2357 rd1
= (insn
>> 0) & 0xf;
2358 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2359 tmp
= tcg_const_i32((insn
>> 20) & 3);
2360 iwmmxt_load_reg(cpu_V1
, rd1
);
2361 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2362 tcg_temp_free_i32(tmp
);
2363 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2364 gen_op_iwmmxt_set_mup();
2366 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2367 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2368 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2369 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2370 wrd
= (insn
>> 12) & 0xf;
2371 rd0
= (insn
>> 16) & 0xf;
2372 rd1
= (insn
>> 0) & 0xf;
2373 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2374 switch ((insn
>> 20) & 0xf) {
2376 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2379 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2382 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2385 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2388 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2391 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2394 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2397 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2400 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2405 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2406 gen_op_iwmmxt_set_mup();
2407 gen_op_iwmmxt_set_cup();
2409 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2410 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2411 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2412 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2413 wrd
= (insn
>> 12) & 0xf;
2414 rd0
= (insn
>> 16) & 0xf;
2415 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2416 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2417 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2418 tcg_temp_free_i32(tmp
);
2419 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2420 gen_op_iwmmxt_set_mup();
2421 gen_op_iwmmxt_set_cup();
2423 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2424 case 0x418: case 0x518: case 0x618: case 0x718:
2425 case 0x818: case 0x918: case 0xa18: case 0xb18:
2426 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2427 wrd
= (insn
>> 12) & 0xf;
2428 rd0
= (insn
>> 16) & 0xf;
2429 rd1
= (insn
>> 0) & 0xf;
2430 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2431 switch ((insn
>> 20) & 0xf) {
2433 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2436 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2439 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2442 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2445 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2448 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2451 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2454 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2457 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2462 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2463 gen_op_iwmmxt_set_mup();
2464 gen_op_iwmmxt_set_cup();
2466 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2467 case 0x408: case 0x508: case 0x608: case 0x708:
2468 case 0x808: case 0x908: case 0xa08: case 0xb08:
2469 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2470 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2472 wrd
= (insn
>> 12) & 0xf;
2473 rd0
= (insn
>> 16) & 0xf;
2474 rd1
= (insn
>> 0) & 0xf;
2475 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2476 switch ((insn
>> 22) & 3) {
2478 if (insn
& (1 << 21))
2479 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2481 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2484 if (insn
& (1 << 21))
2485 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2487 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2490 if (insn
& (1 << 21))
2491 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2493 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2496 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2497 gen_op_iwmmxt_set_mup();
2498 gen_op_iwmmxt_set_cup();
2500 case 0x201: case 0x203: case 0x205: case 0x207:
2501 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2502 case 0x211: case 0x213: case 0x215: case 0x217:
2503 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2504 wrd
= (insn
>> 5) & 0xf;
2505 rd0
= (insn
>> 12) & 0xf;
2506 rd1
= (insn
>> 0) & 0xf;
2507 if (rd0
== 0xf || rd1
== 0xf)
2509 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2510 tmp
= load_reg(s
, rd0
);
2511 tmp2
= load_reg(s
, rd1
);
2512 switch ((insn
>> 16) & 0xf) {
2513 case 0x0: /* TMIA */
2514 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2516 case 0x8: /* TMIAPH */
2517 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2519 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2520 if (insn
& (1 << 16))
2521 tcg_gen_shri_i32(tmp
, tmp
, 16);
2522 if (insn
& (1 << 17))
2523 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2524 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2527 tcg_temp_free_i32(tmp2
);
2528 tcg_temp_free_i32(tmp
);
2531 tcg_temp_free_i32(tmp2
);
2532 tcg_temp_free_i32(tmp
);
2533 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2534 gen_op_iwmmxt_set_mup();
2543 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2544 (ie. an undefined instruction). */
2545 static int disas_dsp_insn(DisasContext
*s
, uint32_t insn
)
2547 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2550 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2551 /* Multiply with Internal Accumulate Format */
2552 rd0
= (insn
>> 12) & 0xf;
2554 acc
= (insn
>> 5) & 7;
2559 tmp
= load_reg(s
, rd0
);
2560 tmp2
= load_reg(s
, rd1
);
2561 switch ((insn
>> 16) & 0xf) {
2563 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2565 case 0x8: /* MIAPH */
2566 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2568 case 0xc: /* MIABB */
2569 case 0xd: /* MIABT */
2570 case 0xe: /* MIATB */
2571 case 0xf: /* MIATT */
2572 if (insn
& (1 << 16))
2573 tcg_gen_shri_i32(tmp
, tmp
, 16);
2574 if (insn
& (1 << 17))
2575 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2576 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2581 tcg_temp_free_i32(tmp2
);
2582 tcg_temp_free_i32(tmp
);
2584 gen_op_iwmmxt_movq_wRn_M0(acc
);
2588 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2589 /* Internal Accumulator Access Format */
2590 rdhi
= (insn
>> 16) & 0xf;
2591 rdlo
= (insn
>> 12) & 0xf;
2597 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2598 iwmmxt_load_reg(cpu_V0
, acc
);
2599 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2600 tcg_gen_extrh_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2601 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2603 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2604 iwmmxt_store_reg(cpu_V0
, acc
);
2612 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2613 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2614 if (dc_isar_feature(aa32_simd_r32, s)) { \
2615 reg = (((insn) >> (bigbit)) & 0x0f) \
2616 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2618 if (insn & (1 << (smallbit))) \
2620 reg = ((insn) >> (bigbit)) & 0x0f; \
2623 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2624 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2625 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2627 static void gen_neon_dup_low16(TCGv_i32 var
)
2629 TCGv_i32 tmp
= tcg_temp_new_i32();
2630 tcg_gen_ext16u_i32(var
, var
);
2631 tcg_gen_shli_i32(tmp
, var
, 16);
2632 tcg_gen_or_i32(var
, var
, tmp
);
2633 tcg_temp_free_i32(tmp
);
2636 static void gen_neon_dup_high16(TCGv_i32 var
)
2638 TCGv_i32 tmp
= tcg_temp_new_i32();
2639 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2640 tcg_gen_shri_i32(tmp
, var
, 16);
2641 tcg_gen_or_i32(var
, var
, tmp
);
2642 tcg_temp_free_i32(tmp
);
2645 static inline bool use_goto_tb(DisasContext
*s
, target_ulong dest
)
2647 #ifndef CONFIG_USER_ONLY
2648 return (s
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
2649 ((s
->base
.pc_next
- 1) & TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
2655 static void gen_goto_ptr(void)
2657 tcg_gen_lookup_and_goto_ptr();
2660 /* This will end the TB but doesn't guarantee we'll return to
2661 * cpu_loop_exec. Any live exit_requests will be processed as we
2662 * enter the next TB.
2664 static void gen_goto_tb(DisasContext
*s
, int n
, target_ulong dest
)
2666 if (use_goto_tb(s
, dest
)) {
2668 gen_set_pc_im(s
, dest
);
2669 tcg_gen_exit_tb(s
->base
.tb
, n
);
2671 gen_set_pc_im(s
, dest
);
2674 s
->base
.is_jmp
= DISAS_NORETURN
;
2677 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
2679 if (unlikely(is_singlestepping(s
))) {
2680 /* An indirect jump so that we still trigger the debug exception. */
2681 gen_set_pc_im(s
, dest
);
2682 s
->base
.is_jmp
= DISAS_JUMP
;
2684 gen_goto_tb(s
, 0, dest
);
2688 static inline void gen_mulxy(TCGv_i32 t0
, TCGv_i32 t1
, int x
, int y
)
2691 tcg_gen_sari_i32(t0
, t0
, 16);
2695 tcg_gen_sari_i32(t1
, t1
, 16);
2698 tcg_gen_mul_i32(t0
, t0
, t1
);
2701 /* Return the mask of PSR bits set by a MSR instruction. */
2702 static uint32_t msr_mask(DisasContext
*s
, int flags
, int spsr
)
2706 if (flags
& (1 << 0)) {
2709 if (flags
& (1 << 1)) {
2712 if (flags
& (1 << 2)) {
2715 if (flags
& (1 << 3)) {
2719 /* Mask out undefined and reserved bits. */
2720 mask
&= aarch32_cpsr_valid_mask(s
->features
, s
->isar
);
2722 /* Mask out execution state. */
2727 /* Mask out privileged bits. */
2734 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
2735 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv_i32 t0
)
2739 /* ??? This is also undefined in system mode. */
2743 tmp
= load_cpu_field(spsr
);
2744 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
2745 tcg_gen_andi_i32(t0
, t0
, mask
);
2746 tcg_gen_or_i32(tmp
, tmp
, t0
);
2747 store_cpu_field(tmp
, spsr
);
2749 gen_set_cpsr(t0
, mask
);
2751 tcg_temp_free_i32(t0
);
2756 /* Returns nonzero if access to the PSR is not permitted. */
2757 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
2760 tmp
= tcg_temp_new_i32();
2761 tcg_gen_movi_i32(tmp
, val
);
2762 return gen_set_psr(s
, mask
, spsr
, tmp
);
2765 static bool msr_banked_access_decode(DisasContext
*s
, int r
, int sysm
, int rn
,
2766 int *tgtmode
, int *regno
)
2768 /* Decode the r and sysm fields of MSR/MRS banked accesses into
2769 * the target mode and register number, and identify the various
2770 * unpredictable cases.
2771 * MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if:
2772 * + executed in user mode
2773 * + using R15 as the src/dest register
2774 * + accessing an unimplemented register
2775 * + accessing a register that's inaccessible at current PL/security state*
2776 * + accessing a register that you could access with a different insn
2777 * We choose to UNDEF in all these cases.
2778 * Since we don't know which of the various AArch32 modes we are in
2779 * we have to defer some checks to runtime.
2780 * Accesses to Monitor mode registers from Secure EL1 (which implies
2781 * that EL3 is AArch64) must trap to EL3.
2783 * If the access checks fail this function will emit code to take
2784 * an exception and return false. Otherwise it will return true,
2785 * and set *tgtmode and *regno appropriately.
2787 int exc_target
= default_exception_el(s
);
2789 /* These instructions are present only in ARMv8, or in ARMv7 with the
2790 * Virtualization Extensions.
2792 if (!arm_dc_feature(s
, ARM_FEATURE_V8
) &&
2793 !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
2797 if (IS_USER(s
) || rn
== 15) {
2801 /* The table in the v8 ARM ARM section F5.2.3 describes the encoding
2802 * of registers into (r, sysm).
2805 /* SPSRs for other modes */
2807 case 0xe: /* SPSR_fiq */
2808 *tgtmode
= ARM_CPU_MODE_FIQ
;
2810 case 0x10: /* SPSR_irq */
2811 *tgtmode
= ARM_CPU_MODE_IRQ
;
2813 case 0x12: /* SPSR_svc */
2814 *tgtmode
= ARM_CPU_MODE_SVC
;
2816 case 0x14: /* SPSR_abt */
2817 *tgtmode
= ARM_CPU_MODE_ABT
;
2819 case 0x16: /* SPSR_und */
2820 *tgtmode
= ARM_CPU_MODE_UND
;
2822 case 0x1c: /* SPSR_mon */
2823 *tgtmode
= ARM_CPU_MODE_MON
;
2825 case 0x1e: /* SPSR_hyp */
2826 *tgtmode
= ARM_CPU_MODE_HYP
;
2828 default: /* unallocated */
2831 /* We arbitrarily assign SPSR a register number of 16. */
2834 /* general purpose registers for other modes */
2836 case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */
2837 *tgtmode
= ARM_CPU_MODE_USR
;
2840 case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */
2841 *tgtmode
= ARM_CPU_MODE_FIQ
;
2844 case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */
2845 *tgtmode
= ARM_CPU_MODE_IRQ
;
2846 *regno
= sysm
& 1 ? 13 : 14;
2848 case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */
2849 *tgtmode
= ARM_CPU_MODE_SVC
;
2850 *regno
= sysm
& 1 ? 13 : 14;
2852 case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */
2853 *tgtmode
= ARM_CPU_MODE_ABT
;
2854 *regno
= sysm
& 1 ? 13 : 14;
2856 case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */
2857 *tgtmode
= ARM_CPU_MODE_UND
;
2858 *regno
= sysm
& 1 ? 13 : 14;
2860 case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */
2861 *tgtmode
= ARM_CPU_MODE_MON
;
2862 *regno
= sysm
& 1 ? 13 : 14;
2864 case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */
2865 *tgtmode
= ARM_CPU_MODE_HYP
;
2866 /* Arbitrarily pick 17 for ELR_Hyp (which is not a banked LR!) */
2867 *regno
= sysm
& 1 ? 13 : 17;
2869 default: /* unallocated */
2874 /* Catch the 'accessing inaccessible register' cases we can detect
2875 * at translate time.
2878 case ARM_CPU_MODE_MON
:
2879 if (!arm_dc_feature(s
, ARM_FEATURE_EL3
) || s
->ns
) {
2882 if (s
->current_el
== 1) {
2883 /* If we're in Secure EL1 (which implies that EL3 is AArch64)
2884 * then accesses to Mon registers trap to EL3
2890 case ARM_CPU_MODE_HYP
:
2892 * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
2893 * (and so we can forbid accesses from EL2 or below). elr_hyp
2894 * can be accessed also from Hyp mode, so forbid accesses from
2897 if (!arm_dc_feature(s
, ARM_FEATURE_EL2
) || s
->current_el
< 2 ||
2898 (s
->current_el
< 3 && *regno
!= 17)) {
2909 /* If we get here then some access check did not pass */
2910 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
2911 syn_uncategorized(), exc_target
);
2915 static void gen_msr_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
2917 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
2918 int tgtmode
= 0, regno
= 0;
2920 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
2924 /* Sync state because msr_banked() can raise exceptions */
2925 gen_set_condexec(s
);
2926 gen_set_pc_im(s
, s
->pc_curr
);
2927 tcg_reg
= load_reg(s
, rn
);
2928 tcg_tgtmode
= tcg_const_i32(tgtmode
);
2929 tcg_regno
= tcg_const_i32(regno
);
2930 gen_helper_msr_banked(cpu_env
, tcg_reg
, tcg_tgtmode
, tcg_regno
);
2931 tcg_temp_free_i32(tcg_tgtmode
);
2932 tcg_temp_free_i32(tcg_regno
);
2933 tcg_temp_free_i32(tcg_reg
);
2934 s
->base
.is_jmp
= DISAS_UPDATE
;
2937 static void gen_mrs_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
2939 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
2940 int tgtmode
= 0, regno
= 0;
2942 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
2946 /* Sync state because mrs_banked() can raise exceptions */
2947 gen_set_condexec(s
);
2948 gen_set_pc_im(s
, s
->pc_curr
);
2949 tcg_reg
= tcg_temp_new_i32();
2950 tcg_tgtmode
= tcg_const_i32(tgtmode
);
2951 tcg_regno
= tcg_const_i32(regno
);
2952 gen_helper_mrs_banked(tcg_reg
, cpu_env
, tcg_tgtmode
, tcg_regno
);
2953 tcg_temp_free_i32(tcg_tgtmode
);
2954 tcg_temp_free_i32(tcg_regno
);
2955 store_reg(s
, rn
, tcg_reg
);
2956 s
->base
.is_jmp
= DISAS_UPDATE
;
2959 /* Store value to PC as for an exception return (ie don't
2960 * mask bits). The subsequent call to gen_helper_cpsr_write_eret()
2961 * will do the masking based on the new value of the Thumb bit.
2963 static void store_pc_exc_ret(DisasContext
*s
, TCGv_i32 pc
)
2965 tcg_gen_mov_i32(cpu_R
[15], pc
);
2966 tcg_temp_free_i32(pc
);
2969 /* Generate a v6 exception return. Marks both values as dead. */
2970 static void gen_rfe(DisasContext
*s
, TCGv_i32 pc
, TCGv_i32 cpsr
)
2972 store_pc_exc_ret(s
, pc
);
2973 /* The cpsr_write_eret helper will mask the low bits of PC
2974 * appropriately depending on the new Thumb bit, so it must
2975 * be called after storing the new PC.
2977 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2980 gen_helper_cpsr_write_eret(cpu_env
, cpsr
);
2981 tcg_temp_free_i32(cpsr
);
2982 /* Must exit loop to check un-masked IRQs */
2983 s
->base
.is_jmp
= DISAS_EXIT
;
2986 /* Generate an old-style exception return. Marks pc as dead. */
2987 static void gen_exception_return(DisasContext
*s
, TCGv_i32 pc
)
2989 gen_rfe(s
, pc
, load_cpu_field(spsr
));
2992 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
2994 static inline void gen_neon_add(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
2997 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
2998 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
2999 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3004 static inline void gen_neon_rsb(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
3007 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3008 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3009 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3014 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3015 #define gen_helper_neon_pmax_s32 tcg_gen_smax_i32
3016 #define gen_helper_neon_pmax_u32 tcg_gen_umax_i32
3017 #define gen_helper_neon_pmin_s32 tcg_gen_smin_i32
3018 #define gen_helper_neon_pmin_u32 tcg_gen_umin_i32
3020 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3021 switch ((size << 1) | u) { \
3023 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3026 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3029 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3032 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3035 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3038 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3040 default: return 1; \
3043 #define GEN_NEON_INTEGER_OP(name) do { \
3044 switch ((size << 1) | u) { \
3046 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3049 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3052 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3055 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3058 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3061 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3063 default: return 1; \
3066 static TCGv_i32
neon_load_scratch(int scratch
)
3068 TCGv_i32 tmp
= tcg_temp_new_i32();
3069 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3073 static void neon_store_scratch(int scratch
, TCGv_i32 var
)
3075 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3076 tcg_temp_free_i32(var
);
3079 static inline TCGv_i32
neon_get_scalar(int size
, int reg
)
3083 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
3085 gen_neon_dup_high16(tmp
);
3087 gen_neon_dup_low16(tmp
);
3090 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
3095 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
3099 if (!q
&& size
== 2) {
3102 pd
= vfp_reg_ptr(true, rd
);
3103 pm
= vfp_reg_ptr(true, rm
);
3107 gen_helper_neon_qunzip8(pd
, pm
);
3110 gen_helper_neon_qunzip16(pd
, pm
);
3113 gen_helper_neon_qunzip32(pd
, pm
);
3121 gen_helper_neon_unzip8(pd
, pm
);
3124 gen_helper_neon_unzip16(pd
, pm
);
3130 tcg_temp_free_ptr(pd
);
3131 tcg_temp_free_ptr(pm
);
3135 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
3139 if (!q
&& size
== 2) {
3142 pd
= vfp_reg_ptr(true, rd
);
3143 pm
= vfp_reg_ptr(true, rm
);
3147 gen_helper_neon_qzip8(pd
, pm
);
3150 gen_helper_neon_qzip16(pd
, pm
);
3153 gen_helper_neon_qzip32(pd
, pm
);
3161 gen_helper_neon_zip8(pd
, pm
);
3164 gen_helper_neon_zip16(pd
, pm
);
3170 tcg_temp_free_ptr(pd
);
3171 tcg_temp_free_ptr(pm
);
3175 static void gen_neon_trn_u8(TCGv_i32 t0
, TCGv_i32 t1
)
3179 rd
= tcg_temp_new_i32();
3180 tmp
= tcg_temp_new_i32();
3182 tcg_gen_shli_i32(rd
, t0
, 8);
3183 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
3184 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
3185 tcg_gen_or_i32(rd
, rd
, tmp
);
3187 tcg_gen_shri_i32(t1
, t1
, 8);
3188 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
3189 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
3190 tcg_gen_or_i32(t1
, t1
, tmp
);
3191 tcg_gen_mov_i32(t0
, rd
);
3193 tcg_temp_free_i32(tmp
);
3194 tcg_temp_free_i32(rd
);
3197 static void gen_neon_trn_u16(TCGv_i32 t0
, TCGv_i32 t1
)
3201 rd
= tcg_temp_new_i32();
3202 tmp
= tcg_temp_new_i32();
3204 tcg_gen_shli_i32(rd
, t0
, 16);
3205 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
3206 tcg_gen_or_i32(rd
, rd
, tmp
);
3207 tcg_gen_shri_i32(t1
, t1
, 16);
3208 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
3209 tcg_gen_or_i32(t1
, t1
, tmp
);
3210 tcg_gen_mov_i32(t0
, rd
);
3212 tcg_temp_free_i32(tmp
);
3213 tcg_temp_free_i32(rd
);
3216 static inline void gen_neon_narrow(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3219 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
3220 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
3221 case 2: tcg_gen_extrl_i64_i32(dest
, src
); break;
3226 static inline void gen_neon_narrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3229 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
3230 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
3231 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
3236 static inline void gen_neon_narrow_satu(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3239 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
3240 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
3241 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
3246 static inline void gen_neon_unarrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
3249 case 0: gen_helper_neon_unarrow_sat8(dest
, cpu_env
, src
); break;
3250 case 1: gen_helper_neon_unarrow_sat16(dest
, cpu_env
, src
); break;
3251 case 2: gen_helper_neon_unarrow_sat32(dest
, cpu_env
, src
); break;
3256 static inline void gen_neon_shift_narrow(int size
, TCGv_i32 var
, TCGv_i32 shift
,
3262 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
3263 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
3268 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
3269 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
3276 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
3277 case 2: gen_ushl_i32(var
, var
, shift
); break;
3282 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
3283 case 2: gen_sshl_i32(var
, var
, shift
); break;
3290 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv_i32 src
, int size
, int u
)
3294 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
3295 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
3296 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
3301 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
3302 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
3303 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
3307 tcg_temp_free_i32(src
);
3310 static inline void gen_neon_addl(int size
)
3313 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
3314 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
3315 case 2: tcg_gen_add_i64(CPU_V001
); break;
3320 static inline void gen_neon_subl(int size
)
3323 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
3324 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
3325 case 2: tcg_gen_sub_i64(CPU_V001
); break;
3330 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
3333 case 0: gen_helper_neon_negl_u16(var
, var
); break;
3334 case 1: gen_helper_neon_negl_u32(var
, var
); break;
3336 tcg_gen_neg_i64(var
, var
);
3342 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
3345 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
3346 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
3351 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv_i32 a
, TCGv_i32 b
,
3356 switch ((size
<< 1) | u
) {
3357 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
3358 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
3359 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
3360 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
3362 tmp
= gen_muls_i64_i32(a
, b
);
3363 tcg_gen_mov_i64(dest
, tmp
);
3364 tcg_temp_free_i64(tmp
);
3367 tmp
= gen_mulu_i64_i32(a
, b
);
3368 tcg_gen_mov_i64(dest
, tmp
);
3369 tcg_temp_free_i64(tmp
);
3374 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
3375 Don't forget to clean them now. */
3377 tcg_temp_free_i32(a
);
3378 tcg_temp_free_i32(b
);
3382 static void gen_neon_narrow_op(int op
, int u
, int size
,
3383 TCGv_i32 dest
, TCGv_i64 src
)
3387 gen_neon_unarrow_sats(size
, dest
, src
);
3389 gen_neon_narrow(size
, dest
, src
);
3393 gen_neon_narrow_satu(size
, dest
, src
);
3395 gen_neon_narrow_sats(size
, dest
, src
);
3400 /* Symbolic constants for op fields for Neon 3-register same-length.
3401 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
3404 #define NEON_3R_VHADD 0
3405 #define NEON_3R_VQADD 1
3406 #define NEON_3R_VRHADD 2
3407 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
3408 #define NEON_3R_VHSUB 4
3409 #define NEON_3R_VQSUB 5
3410 #define NEON_3R_VCGT 6
3411 #define NEON_3R_VCGE 7
3412 #define NEON_3R_VSHL 8
3413 #define NEON_3R_VQSHL 9
3414 #define NEON_3R_VRSHL 10
3415 #define NEON_3R_VQRSHL 11
3416 #define NEON_3R_VMAX 12
3417 #define NEON_3R_VMIN 13
3418 #define NEON_3R_VABD 14
3419 #define NEON_3R_VABA 15
3420 #define NEON_3R_VADD_VSUB 16
3421 #define NEON_3R_VTST_VCEQ 17
3422 #define NEON_3R_VML 18 /* VMLA, VMLS */
3423 #define NEON_3R_VMUL 19
3424 #define NEON_3R_VPMAX 20
3425 #define NEON_3R_VPMIN 21
3426 #define NEON_3R_VQDMULH_VQRDMULH 22
3427 #define NEON_3R_VPADD_VQRDMLAH 23
3428 #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
3429 #define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */
3430 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
3431 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
3432 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
3433 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
3434 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
3435 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
3437 static const uint8_t neon_3r_sizes
[] = {
3438 [NEON_3R_VHADD
] = 0x7,
3439 [NEON_3R_VQADD
] = 0xf,
3440 [NEON_3R_VRHADD
] = 0x7,
3441 [NEON_3R_LOGIC
] = 0xf, /* size field encodes op type */
3442 [NEON_3R_VHSUB
] = 0x7,
3443 [NEON_3R_VQSUB
] = 0xf,
3444 [NEON_3R_VCGT
] = 0x7,
3445 [NEON_3R_VCGE
] = 0x7,
3446 [NEON_3R_VSHL
] = 0xf,
3447 [NEON_3R_VQSHL
] = 0xf,
3448 [NEON_3R_VRSHL
] = 0xf,
3449 [NEON_3R_VQRSHL
] = 0xf,
3450 [NEON_3R_VMAX
] = 0x7,
3451 [NEON_3R_VMIN
] = 0x7,
3452 [NEON_3R_VABD
] = 0x7,
3453 [NEON_3R_VABA
] = 0x7,
3454 [NEON_3R_VADD_VSUB
] = 0xf,
3455 [NEON_3R_VTST_VCEQ
] = 0x7,
3456 [NEON_3R_VML
] = 0x7,
3457 [NEON_3R_VMUL
] = 0x7,
3458 [NEON_3R_VPMAX
] = 0x7,
3459 [NEON_3R_VPMIN
] = 0x7,
3460 [NEON_3R_VQDMULH_VQRDMULH
] = 0x6,
3461 [NEON_3R_VPADD_VQRDMLAH
] = 0x7,
3462 [NEON_3R_SHA
] = 0xf, /* size field encodes op type */
3463 [NEON_3R_VFM_VQRDMLSH
] = 0x7, /* For VFM, size bit 1 encodes op */
3464 [NEON_3R_FLOAT_ARITH
] = 0x5, /* size bit 1 encodes op */
3465 [NEON_3R_FLOAT_MULTIPLY
] = 0x5, /* size bit 1 encodes op */
3466 [NEON_3R_FLOAT_CMP
] = 0x5, /* size bit 1 encodes op */
3467 [NEON_3R_FLOAT_ACMP
] = 0x5, /* size bit 1 encodes op */
3468 [NEON_3R_FLOAT_MINMAX
] = 0x5, /* size bit 1 encodes op */
3469 [NEON_3R_FLOAT_MISC
] = 0x5, /* size bit 1 encodes op */
3472 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
3473 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
3476 #define NEON_2RM_VREV64 0
3477 #define NEON_2RM_VREV32 1
3478 #define NEON_2RM_VREV16 2
3479 #define NEON_2RM_VPADDL 4
3480 #define NEON_2RM_VPADDL_U 5
3481 #define NEON_2RM_AESE 6 /* Includes AESD */
3482 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
3483 #define NEON_2RM_VCLS 8
3484 #define NEON_2RM_VCLZ 9
3485 #define NEON_2RM_VCNT 10
3486 #define NEON_2RM_VMVN 11
3487 #define NEON_2RM_VPADAL 12
3488 #define NEON_2RM_VPADAL_U 13
3489 #define NEON_2RM_VQABS 14
3490 #define NEON_2RM_VQNEG 15
3491 #define NEON_2RM_VCGT0 16
3492 #define NEON_2RM_VCGE0 17
3493 #define NEON_2RM_VCEQ0 18
3494 #define NEON_2RM_VCLE0 19
3495 #define NEON_2RM_VCLT0 20
3496 #define NEON_2RM_SHA1H 21
3497 #define NEON_2RM_VABS 22
3498 #define NEON_2RM_VNEG 23
3499 #define NEON_2RM_VCGT0_F 24
3500 #define NEON_2RM_VCGE0_F 25
3501 #define NEON_2RM_VCEQ0_F 26
3502 #define NEON_2RM_VCLE0_F 27
3503 #define NEON_2RM_VCLT0_F 28
3504 #define NEON_2RM_VABS_F 30
3505 #define NEON_2RM_VNEG_F 31
3506 #define NEON_2RM_VSWP 32
3507 #define NEON_2RM_VTRN 33
3508 #define NEON_2RM_VUZP 34
3509 #define NEON_2RM_VZIP 35
3510 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
3511 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
3512 #define NEON_2RM_VSHLL 38
3513 #define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
3514 #define NEON_2RM_VRINTN 40
3515 #define NEON_2RM_VRINTX 41
3516 #define NEON_2RM_VRINTA 42
3517 #define NEON_2RM_VRINTZ 43
3518 #define NEON_2RM_VCVT_F16_F32 44
3519 #define NEON_2RM_VRINTM 45
3520 #define NEON_2RM_VCVT_F32_F16 46
3521 #define NEON_2RM_VRINTP 47
3522 #define NEON_2RM_VCVTAU 48
3523 #define NEON_2RM_VCVTAS 49
3524 #define NEON_2RM_VCVTNU 50
3525 #define NEON_2RM_VCVTNS 51
3526 #define NEON_2RM_VCVTPU 52
3527 #define NEON_2RM_VCVTPS 53
3528 #define NEON_2RM_VCVTMU 54
3529 #define NEON_2RM_VCVTMS 55
3530 #define NEON_2RM_VRECPE 56
3531 #define NEON_2RM_VRSQRTE 57
3532 #define NEON_2RM_VRECPE_F 58
3533 #define NEON_2RM_VRSQRTE_F 59
3534 #define NEON_2RM_VCVT_FS 60
3535 #define NEON_2RM_VCVT_FU 61
3536 #define NEON_2RM_VCVT_SF 62
3537 #define NEON_2RM_VCVT_UF 63
3539 static bool neon_2rm_is_v8_op(int op
)
3541 /* Return true if this neon 2reg-misc op is ARMv8 and up */
3543 case NEON_2RM_VRINTN
:
3544 case NEON_2RM_VRINTA
:
3545 case NEON_2RM_VRINTM
:
3546 case NEON_2RM_VRINTP
:
3547 case NEON_2RM_VRINTZ
:
3548 case NEON_2RM_VRINTX
:
3549 case NEON_2RM_VCVTAU
:
3550 case NEON_2RM_VCVTAS
:
3551 case NEON_2RM_VCVTNU
:
3552 case NEON_2RM_VCVTNS
:
3553 case NEON_2RM_VCVTPU
:
3554 case NEON_2RM_VCVTPS
:
3555 case NEON_2RM_VCVTMU
:
3556 case NEON_2RM_VCVTMS
:
3563 /* Each entry in this array has bit n set if the insn allows
3564 * size value n (otherwise it will UNDEF). Since unallocated
3565 * op values will have no bits set they always UNDEF.
3567 static const uint8_t neon_2rm_sizes
[] = {
3568 [NEON_2RM_VREV64
] = 0x7,
3569 [NEON_2RM_VREV32
] = 0x3,
3570 [NEON_2RM_VREV16
] = 0x1,
3571 [NEON_2RM_VPADDL
] = 0x7,
3572 [NEON_2RM_VPADDL_U
] = 0x7,
3573 [NEON_2RM_AESE
] = 0x1,
3574 [NEON_2RM_AESMC
] = 0x1,
3575 [NEON_2RM_VCLS
] = 0x7,
3576 [NEON_2RM_VCLZ
] = 0x7,
3577 [NEON_2RM_VCNT
] = 0x1,
3578 [NEON_2RM_VMVN
] = 0x1,
3579 [NEON_2RM_VPADAL
] = 0x7,
3580 [NEON_2RM_VPADAL_U
] = 0x7,
3581 [NEON_2RM_VQABS
] = 0x7,
3582 [NEON_2RM_VQNEG
] = 0x7,
3583 [NEON_2RM_VCGT0
] = 0x7,
3584 [NEON_2RM_VCGE0
] = 0x7,
3585 [NEON_2RM_VCEQ0
] = 0x7,
3586 [NEON_2RM_VCLE0
] = 0x7,
3587 [NEON_2RM_VCLT0
] = 0x7,
3588 [NEON_2RM_SHA1H
] = 0x4,
3589 [NEON_2RM_VABS
] = 0x7,
3590 [NEON_2RM_VNEG
] = 0x7,
3591 [NEON_2RM_VCGT0_F
] = 0x4,
3592 [NEON_2RM_VCGE0_F
] = 0x4,
3593 [NEON_2RM_VCEQ0_F
] = 0x4,
3594 [NEON_2RM_VCLE0_F
] = 0x4,
3595 [NEON_2RM_VCLT0_F
] = 0x4,
3596 [NEON_2RM_VABS_F
] = 0x4,
3597 [NEON_2RM_VNEG_F
] = 0x4,
3598 [NEON_2RM_VSWP
] = 0x1,
3599 [NEON_2RM_VTRN
] = 0x7,
3600 [NEON_2RM_VUZP
] = 0x7,
3601 [NEON_2RM_VZIP
] = 0x7,
3602 [NEON_2RM_VMOVN
] = 0x7,
3603 [NEON_2RM_VQMOVN
] = 0x7,
3604 [NEON_2RM_VSHLL
] = 0x7,
3605 [NEON_2RM_SHA1SU1
] = 0x4,
3606 [NEON_2RM_VRINTN
] = 0x4,
3607 [NEON_2RM_VRINTX
] = 0x4,
3608 [NEON_2RM_VRINTA
] = 0x4,
3609 [NEON_2RM_VRINTZ
] = 0x4,
3610 [NEON_2RM_VCVT_F16_F32
] = 0x2,
3611 [NEON_2RM_VRINTM
] = 0x4,
3612 [NEON_2RM_VCVT_F32_F16
] = 0x2,
3613 [NEON_2RM_VRINTP
] = 0x4,
3614 [NEON_2RM_VCVTAU
] = 0x4,
3615 [NEON_2RM_VCVTAS
] = 0x4,
3616 [NEON_2RM_VCVTNU
] = 0x4,
3617 [NEON_2RM_VCVTNS
] = 0x4,
3618 [NEON_2RM_VCVTPU
] = 0x4,
3619 [NEON_2RM_VCVTPS
] = 0x4,
3620 [NEON_2RM_VCVTMU
] = 0x4,
3621 [NEON_2RM_VCVTMS
] = 0x4,
3622 [NEON_2RM_VRECPE
] = 0x4,
3623 [NEON_2RM_VRSQRTE
] = 0x4,
3624 [NEON_2RM_VRECPE_F
] = 0x4,
3625 [NEON_2RM_VRSQRTE_F
] = 0x4,
3626 [NEON_2RM_VCVT_FS
] = 0x4,
3627 [NEON_2RM_VCVT_FU
] = 0x4,
3628 [NEON_2RM_VCVT_SF
] = 0x4,
3629 [NEON_2RM_VCVT_UF
] = 0x4,
3633 /* Expand v8.1 simd helper. */
3634 static int do_v81_helper(DisasContext
*s
, gen_helper_gvec_3_ptr
*fn
,
3635 int q
, int rd
, int rn
, int rm
)
3637 if (dc_isar_feature(aa32_rdm
, s
)) {
3638 int opr_sz
= (1 + q
) * 8;
3639 tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd
),
3640 vfp_reg_offset(1, rn
),
3641 vfp_reg_offset(1, rm
), cpu_env
,
3642 opr_sz
, opr_sz
, 0, fn
);
3648 static void gen_ceq0_i32(TCGv_i32 d
, TCGv_i32 a
)
3650 tcg_gen_setcondi_i32(TCG_COND_EQ
, d
, a
, 0);
3651 tcg_gen_neg_i32(d
, d
);
3654 static void gen_ceq0_i64(TCGv_i64 d
, TCGv_i64 a
)
3656 tcg_gen_setcondi_i64(TCG_COND_EQ
, d
, a
, 0);
3657 tcg_gen_neg_i64(d
, d
);
3660 static void gen_ceq0_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
)
3662 TCGv_vec zero
= tcg_const_zeros_vec_matching(d
);
3663 tcg_gen_cmp_vec(TCG_COND_EQ
, vece
, d
, a
, zero
);
3664 tcg_temp_free_vec(zero
);
3667 static const TCGOpcode vecop_list_cmp
[] = {
3671 const GVecGen2 ceq0_op
[4] = {
3672 { .fno
= gen_helper_gvec_ceq0_b
,
3673 .fniv
= gen_ceq0_vec
,
3674 .opt_opc
= vecop_list_cmp
,
3676 { .fno
= gen_helper_gvec_ceq0_h
,
3677 .fniv
= gen_ceq0_vec
,
3678 .opt_opc
= vecop_list_cmp
,
3680 { .fni4
= gen_ceq0_i32
,
3681 .fniv
= gen_ceq0_vec
,
3682 .opt_opc
= vecop_list_cmp
,
3684 { .fni8
= gen_ceq0_i64
,
3685 .fniv
= gen_ceq0_vec
,
3686 .opt_opc
= vecop_list_cmp
,
3687 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3691 static void gen_cle0_i32(TCGv_i32 d
, TCGv_i32 a
)
3693 tcg_gen_setcondi_i32(TCG_COND_LE
, d
, a
, 0);
3694 tcg_gen_neg_i32(d
, d
);
3697 static void gen_cle0_i64(TCGv_i64 d
, TCGv_i64 a
)
3699 tcg_gen_setcondi_i64(TCG_COND_LE
, d
, a
, 0);
3700 tcg_gen_neg_i64(d
, d
);
3703 static void gen_cle0_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
)
3705 TCGv_vec zero
= tcg_const_zeros_vec_matching(d
);
3706 tcg_gen_cmp_vec(TCG_COND_LE
, vece
, d
, a
, zero
);
3707 tcg_temp_free_vec(zero
);
3710 const GVecGen2 cle0_op
[4] = {
3711 { .fno
= gen_helper_gvec_cle0_b
,
3712 .fniv
= gen_cle0_vec
,
3713 .opt_opc
= vecop_list_cmp
,
3715 { .fno
= gen_helper_gvec_cle0_h
,
3716 .fniv
= gen_cle0_vec
,
3717 .opt_opc
= vecop_list_cmp
,
3719 { .fni4
= gen_cle0_i32
,
3720 .fniv
= gen_cle0_vec
,
3721 .opt_opc
= vecop_list_cmp
,
3723 { .fni8
= gen_cle0_i64
,
3724 .fniv
= gen_cle0_vec
,
3725 .opt_opc
= vecop_list_cmp
,
3726 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3730 static void gen_cge0_i32(TCGv_i32 d
, TCGv_i32 a
)
3732 tcg_gen_setcondi_i32(TCG_COND_GE
, d
, a
, 0);
3733 tcg_gen_neg_i32(d
, d
);
3736 static void gen_cge0_i64(TCGv_i64 d
, TCGv_i64 a
)
3738 tcg_gen_setcondi_i64(TCG_COND_GE
, d
, a
, 0);
3739 tcg_gen_neg_i64(d
, d
);
3742 static void gen_cge0_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
)
3744 TCGv_vec zero
= tcg_const_zeros_vec_matching(d
);
3745 tcg_gen_cmp_vec(TCG_COND_GE
, vece
, d
, a
, zero
);
3746 tcg_temp_free_vec(zero
);
3749 const GVecGen2 cge0_op
[4] = {
3750 { .fno
= gen_helper_gvec_cge0_b
,
3751 .fniv
= gen_cge0_vec
,
3752 .opt_opc
= vecop_list_cmp
,
3754 { .fno
= gen_helper_gvec_cge0_h
,
3755 .fniv
= gen_cge0_vec
,
3756 .opt_opc
= vecop_list_cmp
,
3758 { .fni4
= gen_cge0_i32
,
3759 .fniv
= gen_cge0_vec
,
3760 .opt_opc
= vecop_list_cmp
,
3762 { .fni8
= gen_cge0_i64
,
3763 .fniv
= gen_cge0_vec
,
3764 .opt_opc
= vecop_list_cmp
,
3765 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3769 static void gen_clt0_i32(TCGv_i32 d
, TCGv_i32 a
)
3771 tcg_gen_setcondi_i32(TCG_COND_LT
, d
, a
, 0);
3772 tcg_gen_neg_i32(d
, d
);
3775 static void gen_clt0_i64(TCGv_i64 d
, TCGv_i64 a
)
3777 tcg_gen_setcondi_i64(TCG_COND_LT
, d
, a
, 0);
3778 tcg_gen_neg_i64(d
, d
);
3781 static void gen_clt0_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
)
3783 TCGv_vec zero
= tcg_const_zeros_vec_matching(d
);
3784 tcg_gen_cmp_vec(TCG_COND_LT
, vece
, d
, a
, zero
);
3785 tcg_temp_free_vec(zero
);
3788 const GVecGen2 clt0_op
[4] = {
3789 { .fno
= gen_helper_gvec_clt0_b
,
3790 .fniv
= gen_clt0_vec
,
3791 .opt_opc
= vecop_list_cmp
,
3793 { .fno
= gen_helper_gvec_clt0_h
,
3794 .fniv
= gen_clt0_vec
,
3795 .opt_opc
= vecop_list_cmp
,
3797 { .fni4
= gen_clt0_i32
,
3798 .fniv
= gen_clt0_vec
,
3799 .opt_opc
= vecop_list_cmp
,
3801 { .fni8
= gen_clt0_i64
,
3802 .fniv
= gen_clt0_vec
,
3803 .opt_opc
= vecop_list_cmp
,
3804 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3808 static void gen_cgt0_i32(TCGv_i32 d
, TCGv_i32 a
)
3810 tcg_gen_setcondi_i32(TCG_COND_GT
, d
, a
, 0);
3811 tcg_gen_neg_i32(d
, d
);
3814 static void gen_cgt0_i64(TCGv_i64 d
, TCGv_i64 a
)
3816 tcg_gen_setcondi_i64(TCG_COND_GT
, d
, a
, 0);
3817 tcg_gen_neg_i64(d
, d
);
3820 static void gen_cgt0_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
)
3822 TCGv_vec zero
= tcg_const_zeros_vec_matching(d
);
3823 tcg_gen_cmp_vec(TCG_COND_GT
, vece
, d
, a
, zero
);
3824 tcg_temp_free_vec(zero
);
3827 const GVecGen2 cgt0_op
[4] = {
3828 { .fno
= gen_helper_gvec_cgt0_b
,
3829 .fniv
= gen_cgt0_vec
,
3830 .opt_opc
= vecop_list_cmp
,
3832 { .fno
= gen_helper_gvec_cgt0_h
,
3833 .fniv
= gen_cgt0_vec
,
3834 .opt_opc
= vecop_list_cmp
,
3836 { .fni4
= gen_cgt0_i32
,
3837 .fniv
= gen_cgt0_vec
,
3838 .opt_opc
= vecop_list_cmp
,
3840 { .fni8
= gen_cgt0_i64
,
3841 .fniv
= gen_cgt0_vec
,
3842 .opt_opc
= vecop_list_cmp
,
3843 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3847 static void gen_ssra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3849 tcg_gen_vec_sar8i_i64(a
, a
, shift
);
3850 tcg_gen_vec_add8_i64(d
, d
, a
);
3853 static void gen_ssra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3855 tcg_gen_vec_sar16i_i64(a
, a
, shift
);
3856 tcg_gen_vec_add16_i64(d
, d
, a
);
3859 static void gen_ssra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
3861 tcg_gen_sari_i32(a
, a
, shift
);
3862 tcg_gen_add_i32(d
, d
, a
);
3865 static void gen_ssra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3867 tcg_gen_sari_i64(a
, a
, shift
);
3868 tcg_gen_add_i64(d
, d
, a
);
3871 static void gen_ssra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
3873 tcg_gen_sari_vec(vece
, a
, a
, sh
);
3874 tcg_gen_add_vec(vece
, d
, d
, a
);
3877 void gen_gvec_ssra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
3878 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
3880 static const TCGOpcode vecop_list
[] = {
3881 INDEX_op_sari_vec
, INDEX_op_add_vec
, 0
3883 static const GVecGen2i ops
[4] = {
3884 { .fni8
= gen_ssra8_i64
,
3885 .fniv
= gen_ssra_vec
,
3886 .fno
= gen_helper_gvec_ssra_b
,
3888 .opt_opc
= vecop_list
,
3890 { .fni8
= gen_ssra16_i64
,
3891 .fniv
= gen_ssra_vec
,
3892 .fno
= gen_helper_gvec_ssra_h
,
3894 .opt_opc
= vecop_list
,
3896 { .fni4
= gen_ssra32_i32
,
3897 .fniv
= gen_ssra_vec
,
3898 .fno
= gen_helper_gvec_ssra_s
,
3900 .opt_opc
= vecop_list
,
3902 { .fni8
= gen_ssra64_i64
,
3903 .fniv
= gen_ssra_vec
,
3904 .fno
= gen_helper_gvec_ssra_b
,
3905 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3906 .opt_opc
= vecop_list
,
3911 /* tszimm encoding produces immediates in the range [1..esize]. */
3912 tcg_debug_assert(shift
> 0);
3913 tcg_debug_assert(shift
<= (8 << vece
));
3916 * Shifts larger than the element size are architecturally valid.
3917 * Signed results in all sign bits.
3919 shift
= MIN(shift
, (8 << vece
) - 1);
3920 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
3923 static void gen_usra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3925 tcg_gen_vec_shr8i_i64(a
, a
, shift
);
3926 tcg_gen_vec_add8_i64(d
, d
, a
);
3929 static void gen_usra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3931 tcg_gen_vec_shr16i_i64(a
, a
, shift
);
3932 tcg_gen_vec_add16_i64(d
, d
, a
);
3935 static void gen_usra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
3937 tcg_gen_shri_i32(a
, a
, shift
);
3938 tcg_gen_add_i32(d
, d
, a
);
3941 static void gen_usra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
3943 tcg_gen_shri_i64(a
, a
, shift
);
3944 tcg_gen_add_i64(d
, d
, a
);
3947 static void gen_usra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
3949 tcg_gen_shri_vec(vece
, a
, a
, sh
);
3950 tcg_gen_add_vec(vece
, d
, d
, a
);
3953 void gen_gvec_usra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
3954 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
3956 static const TCGOpcode vecop_list
[] = {
3957 INDEX_op_shri_vec
, INDEX_op_add_vec
, 0
3959 static const GVecGen2i ops
[4] = {
3960 { .fni8
= gen_usra8_i64
,
3961 .fniv
= gen_usra_vec
,
3962 .fno
= gen_helper_gvec_usra_b
,
3964 .opt_opc
= vecop_list
,
3966 { .fni8
= gen_usra16_i64
,
3967 .fniv
= gen_usra_vec
,
3968 .fno
= gen_helper_gvec_usra_h
,
3970 .opt_opc
= vecop_list
,
3972 { .fni4
= gen_usra32_i32
,
3973 .fniv
= gen_usra_vec
,
3974 .fno
= gen_helper_gvec_usra_s
,
3976 .opt_opc
= vecop_list
,
3978 { .fni8
= gen_usra64_i64
,
3979 .fniv
= gen_usra_vec
,
3980 .fno
= gen_helper_gvec_usra_d
,
3981 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
3983 .opt_opc
= vecop_list
,
3987 /* tszimm encoding produces immediates in the range [1..esize]. */
3988 tcg_debug_assert(shift
> 0);
3989 tcg_debug_assert(shift
<= (8 << vece
));
3992 * Shifts larger than the element size are architecturally valid.
3993 * Unsigned results in all zeros as input to accumulate: nop.
3995 if (shift
< (8 << vece
)) {
3996 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
3998 /* Nop, but we do need to clear the tail. */
3999 tcg_gen_gvec_mov(vece
, rd_ofs
, rd_ofs
, opr_sz
, max_sz
);
4004 * Shift one less than the requested amount, and the low bit is
4005 * the rounding bit. For the 8 and 16-bit operations, because we
4006 * mask the low bit, we can perform a normal integer shift instead
4007 * of a vector shift.
4009 static void gen_srshr8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4011 TCGv_i64 t
= tcg_temp_new_i64();
4013 tcg_gen_shri_i64(t
, a
, sh
- 1);
4014 tcg_gen_andi_i64(t
, t
, dup_const(MO_8
, 1));
4015 tcg_gen_vec_sar8i_i64(d
, a
, sh
);
4016 tcg_gen_vec_add8_i64(d
, d
, t
);
4017 tcg_temp_free_i64(t
);
4020 static void gen_srshr16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4022 TCGv_i64 t
= tcg_temp_new_i64();
4024 tcg_gen_shri_i64(t
, a
, sh
- 1);
4025 tcg_gen_andi_i64(t
, t
, dup_const(MO_16
, 1));
4026 tcg_gen_vec_sar16i_i64(d
, a
, sh
);
4027 tcg_gen_vec_add16_i64(d
, d
, t
);
4028 tcg_temp_free_i64(t
);
4031 static void gen_srshr32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
4033 TCGv_i32 t
= tcg_temp_new_i32();
4035 tcg_gen_extract_i32(t
, a
, sh
- 1, 1);
4036 tcg_gen_sari_i32(d
, a
, sh
);
4037 tcg_gen_add_i32(d
, d
, t
);
4038 tcg_temp_free_i32(t
);
4041 static void gen_srshr64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4043 TCGv_i64 t
= tcg_temp_new_i64();
4045 tcg_gen_extract_i64(t
, a
, sh
- 1, 1);
4046 tcg_gen_sari_i64(d
, a
, sh
);
4047 tcg_gen_add_i64(d
, d
, t
);
4048 tcg_temp_free_i64(t
);
4051 static void gen_srshr_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4053 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4054 TCGv_vec ones
= tcg_temp_new_vec_matching(d
);
4056 tcg_gen_shri_vec(vece
, t
, a
, sh
- 1);
4057 tcg_gen_dupi_vec(vece
, ones
, 1);
4058 tcg_gen_and_vec(vece
, t
, t
, ones
);
4059 tcg_gen_sari_vec(vece
, d
, a
, sh
);
4060 tcg_gen_add_vec(vece
, d
, d
, t
);
4062 tcg_temp_free_vec(t
);
4063 tcg_temp_free_vec(ones
);
4066 void gen_gvec_srshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4067 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4069 static const TCGOpcode vecop_list
[] = {
4070 INDEX_op_shri_vec
, INDEX_op_sari_vec
, INDEX_op_add_vec
, 0
4072 static const GVecGen2i ops
[4] = {
4073 { .fni8
= gen_srshr8_i64
,
4074 .fniv
= gen_srshr_vec
,
4075 .fno
= gen_helper_gvec_srshr_b
,
4076 .opt_opc
= vecop_list
,
4078 { .fni8
= gen_srshr16_i64
,
4079 .fniv
= gen_srshr_vec
,
4080 .fno
= gen_helper_gvec_srshr_h
,
4081 .opt_opc
= vecop_list
,
4083 { .fni4
= gen_srshr32_i32
,
4084 .fniv
= gen_srshr_vec
,
4085 .fno
= gen_helper_gvec_srshr_s
,
4086 .opt_opc
= vecop_list
,
4088 { .fni8
= gen_srshr64_i64
,
4089 .fniv
= gen_srshr_vec
,
4090 .fno
= gen_helper_gvec_srshr_d
,
4091 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4092 .opt_opc
= vecop_list
,
4096 /* tszimm encoding produces immediates in the range [1..esize] */
4097 tcg_debug_assert(shift
> 0);
4098 tcg_debug_assert(shift
<= (8 << vece
));
4100 if (shift
== (8 << vece
)) {
4102 * Shifts larger than the element size are architecturally valid.
4103 * Signed results in all sign bits. With rounding, this produces
4104 * (-1 + 1) >> 1 == 0, or (0 + 1) >> 1 == 0.
4107 tcg_gen_gvec_dup_imm(vece
, rd_ofs
, opr_sz
, max_sz
, 0);
4109 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4113 static void gen_srsra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4115 TCGv_i64 t
= tcg_temp_new_i64();
4117 gen_srshr8_i64(t
, a
, sh
);
4118 tcg_gen_vec_add8_i64(d
, d
, t
);
4119 tcg_temp_free_i64(t
);
4122 static void gen_srsra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4124 TCGv_i64 t
= tcg_temp_new_i64();
4126 gen_srshr16_i64(t
, a
, sh
);
4127 tcg_gen_vec_add16_i64(d
, d
, t
);
4128 tcg_temp_free_i64(t
);
4131 static void gen_srsra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
4133 TCGv_i32 t
= tcg_temp_new_i32();
4135 gen_srshr32_i32(t
, a
, sh
);
4136 tcg_gen_add_i32(d
, d
, t
);
4137 tcg_temp_free_i32(t
);
4140 static void gen_srsra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4142 TCGv_i64 t
= tcg_temp_new_i64();
4144 gen_srshr64_i64(t
, a
, sh
);
4145 tcg_gen_add_i64(d
, d
, t
);
4146 tcg_temp_free_i64(t
);
4149 static void gen_srsra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4151 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4153 gen_srshr_vec(vece
, t
, a
, sh
);
4154 tcg_gen_add_vec(vece
, d
, d
, t
);
4155 tcg_temp_free_vec(t
);
4158 void gen_gvec_srsra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4159 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4161 static const TCGOpcode vecop_list
[] = {
4162 INDEX_op_shri_vec
, INDEX_op_sari_vec
, INDEX_op_add_vec
, 0
4164 static const GVecGen2i ops
[4] = {
4165 { .fni8
= gen_srsra8_i64
,
4166 .fniv
= gen_srsra_vec
,
4167 .fno
= gen_helper_gvec_srsra_b
,
4168 .opt_opc
= vecop_list
,
4171 { .fni8
= gen_srsra16_i64
,
4172 .fniv
= gen_srsra_vec
,
4173 .fno
= gen_helper_gvec_srsra_h
,
4174 .opt_opc
= vecop_list
,
4177 { .fni4
= gen_srsra32_i32
,
4178 .fniv
= gen_srsra_vec
,
4179 .fno
= gen_helper_gvec_srsra_s
,
4180 .opt_opc
= vecop_list
,
4183 { .fni8
= gen_srsra64_i64
,
4184 .fniv
= gen_srsra_vec
,
4185 .fno
= gen_helper_gvec_srsra_d
,
4186 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4187 .opt_opc
= vecop_list
,
4192 /* tszimm encoding produces immediates in the range [1..esize] */
4193 tcg_debug_assert(shift
> 0);
4194 tcg_debug_assert(shift
<= (8 << vece
));
4197 * Shifts larger than the element size are architecturally valid.
4198 * Signed results in all sign bits. With rounding, this produces
4199 * (-1 + 1) >> 1 == 0, or (0 + 1) >> 1 == 0.
4200 * I.e. always zero. With accumulation, this leaves D unchanged.
4202 if (shift
== (8 << vece
)) {
4203 /* Nop, but we do need to clear the tail. */
4204 tcg_gen_gvec_mov(vece
, rd_ofs
, rd_ofs
, opr_sz
, max_sz
);
4206 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4210 static void gen_urshr8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4212 TCGv_i64 t
= tcg_temp_new_i64();
4214 tcg_gen_shri_i64(t
, a
, sh
- 1);
4215 tcg_gen_andi_i64(t
, t
, dup_const(MO_8
, 1));
4216 tcg_gen_vec_shr8i_i64(d
, a
, sh
);
4217 tcg_gen_vec_add8_i64(d
, d
, t
);
4218 tcg_temp_free_i64(t
);
4221 static void gen_urshr16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4223 TCGv_i64 t
= tcg_temp_new_i64();
4225 tcg_gen_shri_i64(t
, a
, sh
- 1);
4226 tcg_gen_andi_i64(t
, t
, dup_const(MO_16
, 1));
4227 tcg_gen_vec_shr16i_i64(d
, a
, sh
);
4228 tcg_gen_vec_add16_i64(d
, d
, t
);
4229 tcg_temp_free_i64(t
);
4232 static void gen_urshr32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
4234 TCGv_i32 t
= tcg_temp_new_i32();
4236 tcg_gen_extract_i32(t
, a
, sh
- 1, 1);
4237 tcg_gen_shri_i32(d
, a
, sh
);
4238 tcg_gen_add_i32(d
, d
, t
);
4239 tcg_temp_free_i32(t
);
4242 static void gen_urshr64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4244 TCGv_i64 t
= tcg_temp_new_i64();
4246 tcg_gen_extract_i64(t
, a
, sh
- 1, 1);
4247 tcg_gen_shri_i64(d
, a
, sh
);
4248 tcg_gen_add_i64(d
, d
, t
);
4249 tcg_temp_free_i64(t
);
4252 static void gen_urshr_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t shift
)
4254 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4255 TCGv_vec ones
= tcg_temp_new_vec_matching(d
);
4257 tcg_gen_shri_vec(vece
, t
, a
, shift
- 1);
4258 tcg_gen_dupi_vec(vece
, ones
, 1);
4259 tcg_gen_and_vec(vece
, t
, t
, ones
);
4260 tcg_gen_shri_vec(vece
, d
, a
, shift
);
4261 tcg_gen_add_vec(vece
, d
, d
, t
);
4263 tcg_temp_free_vec(t
);
4264 tcg_temp_free_vec(ones
);
4267 void gen_gvec_urshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4268 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4270 static const TCGOpcode vecop_list
[] = {
4271 INDEX_op_shri_vec
, INDEX_op_add_vec
, 0
4273 static const GVecGen2i ops
[4] = {
4274 { .fni8
= gen_urshr8_i64
,
4275 .fniv
= gen_urshr_vec
,
4276 .fno
= gen_helper_gvec_urshr_b
,
4277 .opt_opc
= vecop_list
,
4279 { .fni8
= gen_urshr16_i64
,
4280 .fniv
= gen_urshr_vec
,
4281 .fno
= gen_helper_gvec_urshr_h
,
4282 .opt_opc
= vecop_list
,
4284 { .fni4
= gen_urshr32_i32
,
4285 .fniv
= gen_urshr_vec
,
4286 .fno
= gen_helper_gvec_urshr_s
,
4287 .opt_opc
= vecop_list
,
4289 { .fni8
= gen_urshr64_i64
,
4290 .fniv
= gen_urshr_vec
,
4291 .fno
= gen_helper_gvec_urshr_d
,
4292 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4293 .opt_opc
= vecop_list
,
4297 /* tszimm encoding produces immediates in the range [1..esize] */
4298 tcg_debug_assert(shift
> 0);
4299 tcg_debug_assert(shift
<= (8 << vece
));
4301 if (shift
== (8 << vece
)) {
4303 * Shifts larger than the element size are architecturally valid.
4304 * Unsigned results in zero. With rounding, this produces a
4305 * copy of the most significant bit.
4307 tcg_gen_gvec_shri(vece
, rd_ofs
, rm_ofs
, shift
- 1, opr_sz
, max_sz
);
4309 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4313 static void gen_ursra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4315 TCGv_i64 t
= tcg_temp_new_i64();
4318 tcg_gen_vec_shr8i_i64(t
, a
, 7);
4320 gen_urshr8_i64(t
, a
, sh
);
4322 tcg_gen_vec_add8_i64(d
, d
, t
);
4323 tcg_temp_free_i64(t
);
4326 static void gen_ursra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4328 TCGv_i64 t
= tcg_temp_new_i64();
4331 tcg_gen_vec_shr16i_i64(t
, a
, 15);
4333 gen_urshr16_i64(t
, a
, sh
);
4335 tcg_gen_vec_add16_i64(d
, d
, t
);
4336 tcg_temp_free_i64(t
);
4339 static void gen_ursra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
)
4341 TCGv_i32 t
= tcg_temp_new_i32();
4344 tcg_gen_shri_i32(t
, a
, 31);
4346 gen_urshr32_i32(t
, a
, sh
);
4348 tcg_gen_add_i32(d
, d
, t
);
4349 tcg_temp_free_i32(t
);
4352 static void gen_ursra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
)
4354 TCGv_i64 t
= tcg_temp_new_i64();
4357 tcg_gen_shri_i64(t
, a
, 63);
4359 gen_urshr64_i64(t
, a
, sh
);
4361 tcg_gen_add_i64(d
, d
, t
);
4362 tcg_temp_free_i64(t
);
4365 static void gen_ursra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4367 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4369 if (sh
== (8 << vece
)) {
4370 tcg_gen_shri_vec(vece
, t
, a
, sh
- 1);
4372 gen_urshr_vec(vece
, t
, a
, sh
);
4374 tcg_gen_add_vec(vece
, d
, d
, t
);
4375 tcg_temp_free_vec(t
);
4378 void gen_gvec_ursra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4379 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4381 static const TCGOpcode vecop_list
[] = {
4382 INDEX_op_shri_vec
, INDEX_op_add_vec
, 0
4384 static const GVecGen2i ops
[4] = {
4385 { .fni8
= gen_ursra8_i64
,
4386 .fniv
= gen_ursra_vec
,
4387 .fno
= gen_helper_gvec_ursra_b
,
4388 .opt_opc
= vecop_list
,
4391 { .fni8
= gen_ursra16_i64
,
4392 .fniv
= gen_ursra_vec
,
4393 .fno
= gen_helper_gvec_ursra_h
,
4394 .opt_opc
= vecop_list
,
4397 { .fni4
= gen_ursra32_i32
,
4398 .fniv
= gen_ursra_vec
,
4399 .fno
= gen_helper_gvec_ursra_s
,
4400 .opt_opc
= vecop_list
,
4403 { .fni8
= gen_ursra64_i64
,
4404 .fniv
= gen_ursra_vec
,
4405 .fno
= gen_helper_gvec_ursra_d
,
4406 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4407 .opt_opc
= vecop_list
,
4412 /* tszimm encoding produces immediates in the range [1..esize] */
4413 tcg_debug_assert(shift
> 0);
4414 tcg_debug_assert(shift
<= (8 << vece
));
4416 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4419 static void gen_shr8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4421 uint64_t mask
= dup_const(MO_8
, 0xff >> shift
);
4422 TCGv_i64 t
= tcg_temp_new_i64();
4424 tcg_gen_shri_i64(t
, a
, shift
);
4425 tcg_gen_andi_i64(t
, t
, mask
);
4426 tcg_gen_andi_i64(d
, d
, ~mask
);
4427 tcg_gen_or_i64(d
, d
, t
);
4428 tcg_temp_free_i64(t
);
4431 static void gen_shr16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4433 uint64_t mask
= dup_const(MO_16
, 0xffff >> shift
);
4434 TCGv_i64 t
= tcg_temp_new_i64();
4436 tcg_gen_shri_i64(t
, a
, shift
);
4437 tcg_gen_andi_i64(t
, t
, mask
);
4438 tcg_gen_andi_i64(d
, d
, ~mask
);
4439 tcg_gen_or_i64(d
, d
, t
);
4440 tcg_temp_free_i64(t
);
4443 static void gen_shr32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4445 tcg_gen_shri_i32(a
, a
, shift
);
4446 tcg_gen_deposit_i32(d
, d
, a
, 0, 32 - shift
);
4449 static void gen_shr64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4451 tcg_gen_shri_i64(a
, a
, shift
);
4452 tcg_gen_deposit_i64(d
, d
, a
, 0, 64 - shift
);
4455 static void gen_shr_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4457 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4458 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
4460 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK((8 << vece
) - sh
, sh
));
4461 tcg_gen_shri_vec(vece
, t
, a
, sh
);
4462 tcg_gen_and_vec(vece
, d
, d
, m
);
4463 tcg_gen_or_vec(vece
, d
, d
, t
);
4465 tcg_temp_free_vec(t
);
4466 tcg_temp_free_vec(m
);
4469 void gen_gvec_sri(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4470 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4472 static const TCGOpcode vecop_list
[] = { INDEX_op_shri_vec
, 0 };
4473 const GVecGen2i ops
[4] = {
4474 { .fni8
= gen_shr8_ins_i64
,
4475 .fniv
= gen_shr_ins_vec
,
4476 .fno
= gen_helper_gvec_sri_b
,
4478 .opt_opc
= vecop_list
,
4480 { .fni8
= gen_shr16_ins_i64
,
4481 .fniv
= gen_shr_ins_vec
,
4482 .fno
= gen_helper_gvec_sri_h
,
4484 .opt_opc
= vecop_list
,
4486 { .fni4
= gen_shr32_ins_i32
,
4487 .fniv
= gen_shr_ins_vec
,
4488 .fno
= gen_helper_gvec_sri_s
,
4490 .opt_opc
= vecop_list
,
4492 { .fni8
= gen_shr64_ins_i64
,
4493 .fniv
= gen_shr_ins_vec
,
4494 .fno
= gen_helper_gvec_sri_d
,
4495 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4497 .opt_opc
= vecop_list
,
4501 /* tszimm encoding produces immediates in the range [1..esize]. */
4502 tcg_debug_assert(shift
> 0);
4503 tcg_debug_assert(shift
<= (8 << vece
));
4505 /* Shift of esize leaves destination unchanged. */
4506 if (shift
< (8 << vece
)) {
4507 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4509 /* Nop, but we do need to clear the tail. */
4510 tcg_gen_gvec_mov(vece
, rd_ofs
, rd_ofs
, opr_sz
, max_sz
);
4514 static void gen_shl8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4516 uint64_t mask
= dup_const(MO_8
, 0xff << shift
);
4517 TCGv_i64 t
= tcg_temp_new_i64();
4519 tcg_gen_shli_i64(t
, a
, shift
);
4520 tcg_gen_andi_i64(t
, t
, mask
);
4521 tcg_gen_andi_i64(d
, d
, ~mask
);
4522 tcg_gen_or_i64(d
, d
, t
);
4523 tcg_temp_free_i64(t
);
4526 static void gen_shl16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4528 uint64_t mask
= dup_const(MO_16
, 0xffff << shift
);
4529 TCGv_i64 t
= tcg_temp_new_i64();
4531 tcg_gen_shli_i64(t
, a
, shift
);
4532 tcg_gen_andi_i64(t
, t
, mask
);
4533 tcg_gen_andi_i64(d
, d
, ~mask
);
4534 tcg_gen_or_i64(d
, d
, t
);
4535 tcg_temp_free_i64(t
);
4538 static void gen_shl32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
4540 tcg_gen_deposit_i32(d
, d
, a
, shift
, 32 - shift
);
4543 static void gen_shl64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
4545 tcg_gen_deposit_i64(d
, d
, a
, shift
, 64 - shift
);
4548 static void gen_shl_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
4550 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
4551 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
4553 tcg_gen_shli_vec(vece
, t
, a
, sh
);
4554 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK(0, sh
));
4555 tcg_gen_and_vec(vece
, d
, d
, m
);
4556 tcg_gen_or_vec(vece
, d
, d
, t
);
4558 tcg_temp_free_vec(t
);
4559 tcg_temp_free_vec(m
);
4562 void gen_gvec_sli(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
4563 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
)
4565 static const TCGOpcode vecop_list
[] = { INDEX_op_shli_vec
, 0 };
4566 const GVecGen2i ops
[4] = {
4567 { .fni8
= gen_shl8_ins_i64
,
4568 .fniv
= gen_shl_ins_vec
,
4569 .fno
= gen_helper_gvec_sli_b
,
4571 .opt_opc
= vecop_list
,
4573 { .fni8
= gen_shl16_ins_i64
,
4574 .fniv
= gen_shl_ins_vec
,
4575 .fno
= gen_helper_gvec_sli_h
,
4577 .opt_opc
= vecop_list
,
4579 { .fni4
= gen_shl32_ins_i32
,
4580 .fniv
= gen_shl_ins_vec
,
4581 .fno
= gen_helper_gvec_sli_s
,
4583 .opt_opc
= vecop_list
,
4585 { .fni8
= gen_shl64_ins_i64
,
4586 .fniv
= gen_shl_ins_vec
,
4587 .fno
= gen_helper_gvec_sli_d
,
4588 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4590 .opt_opc
= vecop_list
,
4594 /* tszimm encoding produces immediates in the range [0..esize-1]. */
4595 tcg_debug_assert(shift
>= 0);
4596 tcg_debug_assert(shift
< (8 << vece
));
4599 tcg_gen_gvec_mov(vece
, rd_ofs
, rm_ofs
, opr_sz
, max_sz
);
4601 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, opr_sz
, max_sz
, shift
, &ops
[vece
]);
4605 static void gen_mla8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4607 gen_helper_neon_mul_u8(a
, a
, b
);
4608 gen_helper_neon_add_u8(d
, d
, a
);
4611 static void gen_mls8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4613 gen_helper_neon_mul_u8(a
, a
, b
);
4614 gen_helper_neon_sub_u8(d
, d
, a
);
4617 static void gen_mla16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4619 gen_helper_neon_mul_u16(a
, a
, b
);
4620 gen_helper_neon_add_u16(d
, d
, a
);
4623 static void gen_mls16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4625 gen_helper_neon_mul_u16(a
, a
, b
);
4626 gen_helper_neon_sub_u16(d
, d
, a
);
4629 static void gen_mla32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4631 tcg_gen_mul_i32(a
, a
, b
);
4632 tcg_gen_add_i32(d
, d
, a
);
4635 static void gen_mls32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4637 tcg_gen_mul_i32(a
, a
, b
);
4638 tcg_gen_sub_i32(d
, d
, a
);
4641 static void gen_mla64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4643 tcg_gen_mul_i64(a
, a
, b
);
4644 tcg_gen_add_i64(d
, d
, a
);
4647 static void gen_mls64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4649 tcg_gen_mul_i64(a
, a
, b
);
4650 tcg_gen_sub_i64(d
, d
, a
);
4653 static void gen_mla_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4655 tcg_gen_mul_vec(vece
, a
, a
, b
);
4656 tcg_gen_add_vec(vece
, d
, d
, a
);
4659 static void gen_mls_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4661 tcg_gen_mul_vec(vece
, a
, a
, b
);
4662 tcg_gen_sub_vec(vece
, d
, d
, a
);
4665 /* Note that while NEON does not support VMLA and VMLS as 64-bit ops,
4666 * these tables are shared with AArch64 which does support them.
4669 static const TCGOpcode vecop_list_mla
[] = {
4670 INDEX_op_mul_vec
, INDEX_op_add_vec
, 0
4673 static const TCGOpcode vecop_list_mls
[] = {
4674 INDEX_op_mul_vec
, INDEX_op_sub_vec
, 0
4677 const GVecGen3 mla_op
[4] = {
4678 { .fni4
= gen_mla8_i32
,
4679 .fniv
= gen_mla_vec
,
4681 .opt_opc
= vecop_list_mla
,
4683 { .fni4
= gen_mla16_i32
,
4684 .fniv
= gen_mla_vec
,
4686 .opt_opc
= vecop_list_mla
,
4688 { .fni4
= gen_mla32_i32
,
4689 .fniv
= gen_mla_vec
,
4691 .opt_opc
= vecop_list_mla
,
4693 { .fni8
= gen_mla64_i64
,
4694 .fniv
= gen_mla_vec
,
4695 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4697 .opt_opc
= vecop_list_mla
,
4701 const GVecGen3 mls_op
[4] = {
4702 { .fni4
= gen_mls8_i32
,
4703 .fniv
= gen_mls_vec
,
4705 .opt_opc
= vecop_list_mls
,
4707 { .fni4
= gen_mls16_i32
,
4708 .fniv
= gen_mls_vec
,
4710 .opt_opc
= vecop_list_mls
,
4712 { .fni4
= gen_mls32_i32
,
4713 .fniv
= gen_mls_vec
,
4715 .opt_opc
= vecop_list_mls
,
4717 { .fni8
= gen_mls64_i64
,
4718 .fniv
= gen_mls_vec
,
4719 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4721 .opt_opc
= vecop_list_mls
,
4725 /* CMTST : test is "if (X & Y != 0)". */
4726 static void gen_cmtst_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
4728 tcg_gen_and_i32(d
, a
, b
);
4729 tcg_gen_setcondi_i32(TCG_COND_NE
, d
, d
, 0);
4730 tcg_gen_neg_i32(d
, d
);
4733 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
4735 tcg_gen_and_i64(d
, a
, b
);
4736 tcg_gen_setcondi_i64(TCG_COND_NE
, d
, d
, 0);
4737 tcg_gen_neg_i64(d
, d
);
4740 static void gen_cmtst_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
4742 tcg_gen_and_vec(vece
, d
, a
, b
);
4743 tcg_gen_dupi_vec(vece
, a
, 0);
4744 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, d
, d
, a
);
4747 static const TCGOpcode vecop_list_cmtst
[] = { INDEX_op_cmp_vec
, 0 };
4749 const GVecGen3 cmtst_op
[4] = {
4750 { .fni4
= gen_helper_neon_tst_u8
,
4751 .fniv
= gen_cmtst_vec
,
4752 .opt_opc
= vecop_list_cmtst
,
4754 { .fni4
= gen_helper_neon_tst_u16
,
4755 .fniv
= gen_cmtst_vec
,
4756 .opt_opc
= vecop_list_cmtst
,
4758 { .fni4
= gen_cmtst_i32
,
4759 .fniv
= gen_cmtst_vec
,
4760 .opt_opc
= vecop_list_cmtst
,
4762 { .fni8
= gen_cmtst_i64
,
4763 .fniv
= gen_cmtst_vec
,
4764 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
4765 .opt_opc
= vecop_list_cmtst
,
4769 void gen_ushl_i32(TCGv_i32 dst
, TCGv_i32 src
, TCGv_i32 shift
)
4771 TCGv_i32 lval
= tcg_temp_new_i32();
4772 TCGv_i32 rval
= tcg_temp_new_i32();
4773 TCGv_i32 lsh
= tcg_temp_new_i32();
4774 TCGv_i32 rsh
= tcg_temp_new_i32();
4775 TCGv_i32 zero
= tcg_const_i32(0);
4776 TCGv_i32 max
= tcg_const_i32(32);
4779 * Rely on the TCG guarantee that out of range shifts produce
4780 * unspecified results, not undefined behaviour (i.e. no trap).
4781 * Discard out-of-range results after the fact.
4783 tcg_gen_ext8s_i32(lsh
, shift
);
4784 tcg_gen_neg_i32(rsh
, lsh
);
4785 tcg_gen_shl_i32(lval
, src
, lsh
);
4786 tcg_gen_shr_i32(rval
, src
, rsh
);
4787 tcg_gen_movcond_i32(TCG_COND_LTU
, dst
, lsh
, max
, lval
, zero
);
4788 tcg_gen_movcond_i32(TCG_COND_LTU
, dst
, rsh
, max
, rval
, dst
);
4790 tcg_temp_free_i32(lval
);
4791 tcg_temp_free_i32(rval
);
4792 tcg_temp_free_i32(lsh
);
4793 tcg_temp_free_i32(rsh
);
4794 tcg_temp_free_i32(zero
);
4795 tcg_temp_free_i32(max
);
4798 void gen_ushl_i64(TCGv_i64 dst
, TCGv_i64 src
, TCGv_i64 shift
)
4800 TCGv_i64 lval
= tcg_temp_new_i64();
4801 TCGv_i64 rval
= tcg_temp_new_i64();
4802 TCGv_i64 lsh
= tcg_temp_new_i64();
4803 TCGv_i64 rsh
= tcg_temp_new_i64();
4804 TCGv_i64 zero
= tcg_const_i64(0);
4805 TCGv_i64 max
= tcg_const_i64(64);
4808 * Rely on the TCG guarantee that out of range shifts produce
4809 * unspecified results, not undefined behaviour (i.e. no trap).
4810 * Discard out-of-range results after the fact.
4812 tcg_gen_ext8s_i64(lsh
, shift
);
4813 tcg_gen_neg_i64(rsh
, lsh
);
4814 tcg_gen_shl_i64(lval
, src
, lsh
);
4815 tcg_gen_shr_i64(rval
, src
, rsh
);
4816 tcg_gen_movcond_i64(TCG_COND_LTU
, dst
, lsh
, max
, lval
, zero
);
4817 tcg_gen_movcond_i64(TCG_COND_LTU
, dst
, rsh
, max
, rval
, dst
);
4819 tcg_temp_free_i64(lval
);
4820 tcg_temp_free_i64(rval
);
4821 tcg_temp_free_i64(lsh
);
4822 tcg_temp_free_i64(rsh
);
4823 tcg_temp_free_i64(zero
);
4824 tcg_temp_free_i64(max
);
4827 static void gen_ushl_vec(unsigned vece
, TCGv_vec dst
,
4828 TCGv_vec src
, TCGv_vec shift
)
4830 TCGv_vec lval
= tcg_temp_new_vec_matching(dst
);
4831 TCGv_vec rval
= tcg_temp_new_vec_matching(dst
);
4832 TCGv_vec lsh
= tcg_temp_new_vec_matching(dst
);
4833 TCGv_vec rsh
= tcg_temp_new_vec_matching(dst
);
4836 tcg_gen_neg_vec(vece
, rsh
, shift
);
4838 tcg_gen_mov_vec(lsh
, shift
);
4840 msk
= tcg_temp_new_vec_matching(dst
);
4841 tcg_gen_dupi_vec(vece
, msk
, 0xff);
4842 tcg_gen_and_vec(vece
, lsh
, shift
, msk
);
4843 tcg_gen_and_vec(vece
, rsh
, rsh
, msk
);
4844 tcg_temp_free_vec(msk
);
4848 * Rely on the TCG guarantee that out of range shifts produce
4849 * unspecified results, not undefined behaviour (i.e. no trap).
4850 * Discard out-of-range results after the fact.
4852 tcg_gen_shlv_vec(vece
, lval
, src
, lsh
);
4853 tcg_gen_shrv_vec(vece
, rval
, src
, rsh
);
4855 max
= tcg_temp_new_vec_matching(dst
);
4856 tcg_gen_dupi_vec(vece
, max
, 8 << vece
);
4859 * The choice of LT (signed) and GEU (unsigned) are biased toward
4860 * the instructions of the x86_64 host. For MO_8, the whole byte
4861 * is significant so we must use an unsigned compare; otherwise we
4862 * have already masked to a byte and so a signed compare works.
4863 * Other tcg hosts have a full set of comparisons and do not care.
4866 tcg_gen_cmp_vec(TCG_COND_GEU
, vece
, lsh
, lsh
, max
);
4867 tcg_gen_cmp_vec(TCG_COND_GEU
, vece
, rsh
, rsh
, max
);
4868 tcg_gen_andc_vec(vece
, lval
, lval
, lsh
);
4869 tcg_gen_andc_vec(vece
, rval
, rval
, rsh
);
4871 tcg_gen_cmp_vec(TCG_COND_LT
, vece
, lsh
, lsh
, max
);
4872 tcg_gen_cmp_vec(TCG_COND_LT
, vece
, rsh
, rsh
, max
);
4873 tcg_gen_and_vec(vece
, lval
, lval
, lsh
);
4874 tcg_gen_and_vec(vece
, rval
, rval
, rsh
);
4876 tcg_gen_or_vec(vece
, dst
, lval
, rval
);
4878 tcg_temp_free_vec(max
);
4879 tcg_temp_free_vec(lval
);
4880 tcg_temp_free_vec(rval
);
4881 tcg_temp_free_vec(lsh
);
4882 tcg_temp_free_vec(rsh
);
4885 static const TCGOpcode ushl_list
[] = {
4886 INDEX_op_neg_vec
, INDEX_op_shlv_vec
,
4887 INDEX_op_shrv_vec
, INDEX_op_cmp_vec
, 0
4890 const GVecGen3 ushl_op
[4] = {
4891 { .fniv
= gen_ushl_vec
,
4892 .fno
= gen_helper_gvec_ushl_b
,
4893 .opt_opc
= ushl_list
,
4895 { .fniv
= gen_ushl_vec
,
4896 .fno
= gen_helper_gvec_ushl_h
,
4897 .opt_opc
= ushl_list
,
4899 { .fni4
= gen_ushl_i32
,
4900 .fniv
= gen_ushl_vec
,
4901 .opt_opc
= ushl_list
,
4903 { .fni8
= gen_ushl_i64
,
4904 .fniv
= gen_ushl_vec
,
4905 .opt_opc
= ushl_list
,
4909 void gen_sshl_i32(TCGv_i32 dst
, TCGv_i32 src
, TCGv_i32 shift
)
4911 TCGv_i32 lval
= tcg_temp_new_i32();
4912 TCGv_i32 rval
= tcg_temp_new_i32();
4913 TCGv_i32 lsh
= tcg_temp_new_i32();
4914 TCGv_i32 rsh
= tcg_temp_new_i32();
4915 TCGv_i32 zero
= tcg_const_i32(0);
4916 TCGv_i32 max
= tcg_const_i32(31);
4919 * Rely on the TCG guarantee that out of range shifts produce
4920 * unspecified results, not undefined behaviour (i.e. no trap).
4921 * Discard out-of-range results after the fact.
4923 tcg_gen_ext8s_i32(lsh
, shift
);
4924 tcg_gen_neg_i32(rsh
, lsh
);
4925 tcg_gen_shl_i32(lval
, src
, lsh
);
4926 tcg_gen_umin_i32(rsh
, rsh
, max
);
4927 tcg_gen_sar_i32(rval
, src
, rsh
);
4928 tcg_gen_movcond_i32(TCG_COND_LEU
, lval
, lsh
, max
, lval
, zero
);
4929 tcg_gen_movcond_i32(TCG_COND_LT
, dst
, lsh
, zero
, rval
, lval
);
4931 tcg_temp_free_i32(lval
);
4932 tcg_temp_free_i32(rval
);
4933 tcg_temp_free_i32(lsh
);
4934 tcg_temp_free_i32(rsh
);
4935 tcg_temp_free_i32(zero
);
4936 tcg_temp_free_i32(max
);
4939 void gen_sshl_i64(TCGv_i64 dst
, TCGv_i64 src
, TCGv_i64 shift
)
4941 TCGv_i64 lval
= tcg_temp_new_i64();
4942 TCGv_i64 rval
= tcg_temp_new_i64();
4943 TCGv_i64 lsh
= tcg_temp_new_i64();
4944 TCGv_i64 rsh
= tcg_temp_new_i64();
4945 TCGv_i64 zero
= tcg_const_i64(0);
4946 TCGv_i64 max
= tcg_const_i64(63);
4949 * Rely on the TCG guarantee that out of range shifts produce
4950 * unspecified results, not undefined behaviour (i.e. no trap).
4951 * Discard out-of-range results after the fact.
4953 tcg_gen_ext8s_i64(lsh
, shift
);
4954 tcg_gen_neg_i64(rsh
, lsh
);
4955 tcg_gen_shl_i64(lval
, src
, lsh
);
4956 tcg_gen_umin_i64(rsh
, rsh
, max
);
4957 tcg_gen_sar_i64(rval
, src
, rsh
);
4958 tcg_gen_movcond_i64(TCG_COND_LEU
, lval
, lsh
, max
, lval
, zero
);
4959 tcg_gen_movcond_i64(TCG_COND_LT
, dst
, lsh
, zero
, rval
, lval
);
4961 tcg_temp_free_i64(lval
);
4962 tcg_temp_free_i64(rval
);
4963 tcg_temp_free_i64(lsh
);
4964 tcg_temp_free_i64(rsh
);
4965 tcg_temp_free_i64(zero
);
4966 tcg_temp_free_i64(max
);
4969 static void gen_sshl_vec(unsigned vece
, TCGv_vec dst
,
4970 TCGv_vec src
, TCGv_vec shift
)
4972 TCGv_vec lval
= tcg_temp_new_vec_matching(dst
);
4973 TCGv_vec rval
= tcg_temp_new_vec_matching(dst
);
4974 TCGv_vec lsh
= tcg_temp_new_vec_matching(dst
);
4975 TCGv_vec rsh
= tcg_temp_new_vec_matching(dst
);
4976 TCGv_vec tmp
= tcg_temp_new_vec_matching(dst
);
4979 * Rely on the TCG guarantee that out of range shifts produce
4980 * unspecified results, not undefined behaviour (i.e. no trap).
4981 * Discard out-of-range results after the fact.
4983 tcg_gen_neg_vec(vece
, rsh
, shift
);
4985 tcg_gen_mov_vec(lsh
, shift
);
4987 tcg_gen_dupi_vec(vece
, tmp
, 0xff);
4988 tcg_gen_and_vec(vece
, lsh
, shift
, tmp
);
4989 tcg_gen_and_vec(vece
, rsh
, rsh
, tmp
);
4992 /* Bound rsh so out of bound right shift gets -1. */
4993 tcg_gen_dupi_vec(vece
, tmp
, (8 << vece
) - 1);
4994 tcg_gen_umin_vec(vece
, rsh
, rsh
, tmp
);
4995 tcg_gen_cmp_vec(TCG_COND_GT
, vece
, tmp
, lsh
, tmp
);
4997 tcg_gen_shlv_vec(vece
, lval
, src
, lsh
);
4998 tcg_gen_sarv_vec(vece
, rval
, src
, rsh
);
5000 /* Select in-bound left shift. */
5001 tcg_gen_andc_vec(vece
, lval
, lval
, tmp
);
5003 /* Select between left and right shift. */
5005 tcg_gen_dupi_vec(vece
, tmp
, 0);
5006 tcg_gen_cmpsel_vec(TCG_COND_LT
, vece
, dst
, lsh
, tmp
, rval
, lval
);
5008 tcg_gen_dupi_vec(vece
, tmp
, 0x80);
5009 tcg_gen_cmpsel_vec(TCG_COND_LT
, vece
, dst
, lsh
, tmp
, lval
, rval
);
5012 tcg_temp_free_vec(lval
);
5013 tcg_temp_free_vec(rval
);
5014 tcg_temp_free_vec(lsh
);
5015 tcg_temp_free_vec(rsh
);
5016 tcg_temp_free_vec(tmp
);
5019 static const TCGOpcode sshl_list
[] = {
5020 INDEX_op_neg_vec
, INDEX_op_umin_vec
, INDEX_op_shlv_vec
,
5021 INDEX_op_sarv_vec
, INDEX_op_cmp_vec
, INDEX_op_cmpsel_vec
, 0
5024 const GVecGen3 sshl_op
[4] = {
5025 { .fniv
= gen_sshl_vec
,
5026 .fno
= gen_helper_gvec_sshl_b
,
5027 .opt_opc
= sshl_list
,
5029 { .fniv
= gen_sshl_vec
,
5030 .fno
= gen_helper_gvec_sshl_h
,
5031 .opt_opc
= sshl_list
,
5033 { .fni4
= gen_sshl_i32
,
5034 .fniv
= gen_sshl_vec
,
5035 .opt_opc
= sshl_list
,
5037 { .fni8
= gen_sshl_i64
,
5038 .fniv
= gen_sshl_vec
,
5039 .opt_opc
= sshl_list
,
5043 static void gen_uqadd_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
5044 TCGv_vec a
, TCGv_vec b
)
5046 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
5047 tcg_gen_add_vec(vece
, x
, a
, b
);
5048 tcg_gen_usadd_vec(vece
, t
, a
, b
);
5049 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
5050 tcg_gen_or_vec(vece
, sat
, sat
, x
);
5051 tcg_temp_free_vec(x
);
5054 static const TCGOpcode vecop_list_uqadd
[] = {
5055 INDEX_op_usadd_vec
, INDEX_op_cmp_vec
, INDEX_op_add_vec
, 0
5058 const GVecGen4 uqadd_op
[4] = {
5059 { .fniv
= gen_uqadd_vec
,
5060 .fno
= gen_helper_gvec_uqadd_b
,
5062 .opt_opc
= vecop_list_uqadd
,
5064 { .fniv
= gen_uqadd_vec
,
5065 .fno
= gen_helper_gvec_uqadd_h
,
5067 .opt_opc
= vecop_list_uqadd
,
5069 { .fniv
= gen_uqadd_vec
,
5070 .fno
= gen_helper_gvec_uqadd_s
,
5072 .opt_opc
= vecop_list_uqadd
,
5074 { .fniv
= gen_uqadd_vec
,
5075 .fno
= gen_helper_gvec_uqadd_d
,
5077 .opt_opc
= vecop_list_uqadd
,
5081 static void gen_sqadd_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
5082 TCGv_vec a
, TCGv_vec b
)
5084 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
5085 tcg_gen_add_vec(vece
, x
, a
, b
);
5086 tcg_gen_ssadd_vec(vece
, t
, a
, b
);
5087 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
5088 tcg_gen_or_vec(vece
, sat
, sat
, x
);
5089 tcg_temp_free_vec(x
);
5092 static const TCGOpcode vecop_list_sqadd
[] = {
5093 INDEX_op_ssadd_vec
, INDEX_op_cmp_vec
, INDEX_op_add_vec
, 0
5096 const GVecGen4 sqadd_op
[4] = {
5097 { .fniv
= gen_sqadd_vec
,
5098 .fno
= gen_helper_gvec_sqadd_b
,
5099 .opt_opc
= vecop_list_sqadd
,
5102 { .fniv
= gen_sqadd_vec
,
5103 .fno
= gen_helper_gvec_sqadd_h
,
5104 .opt_opc
= vecop_list_sqadd
,
5107 { .fniv
= gen_sqadd_vec
,
5108 .fno
= gen_helper_gvec_sqadd_s
,
5109 .opt_opc
= vecop_list_sqadd
,
5112 { .fniv
= gen_sqadd_vec
,
5113 .fno
= gen_helper_gvec_sqadd_d
,
5114 .opt_opc
= vecop_list_sqadd
,
5119 static void gen_uqsub_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
5120 TCGv_vec a
, TCGv_vec b
)
5122 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
5123 tcg_gen_sub_vec(vece
, x
, a
, b
);
5124 tcg_gen_ussub_vec(vece
, t
, a
, b
);
5125 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
5126 tcg_gen_or_vec(vece
, sat
, sat
, x
);
5127 tcg_temp_free_vec(x
);
5130 static const TCGOpcode vecop_list_uqsub
[] = {
5131 INDEX_op_ussub_vec
, INDEX_op_cmp_vec
, INDEX_op_sub_vec
, 0
5134 const GVecGen4 uqsub_op
[4] = {
5135 { .fniv
= gen_uqsub_vec
,
5136 .fno
= gen_helper_gvec_uqsub_b
,
5137 .opt_opc
= vecop_list_uqsub
,
5140 { .fniv
= gen_uqsub_vec
,
5141 .fno
= gen_helper_gvec_uqsub_h
,
5142 .opt_opc
= vecop_list_uqsub
,
5145 { .fniv
= gen_uqsub_vec
,
5146 .fno
= gen_helper_gvec_uqsub_s
,
5147 .opt_opc
= vecop_list_uqsub
,
5150 { .fniv
= gen_uqsub_vec
,
5151 .fno
= gen_helper_gvec_uqsub_d
,
5152 .opt_opc
= vecop_list_uqsub
,
5157 static void gen_sqsub_vec(unsigned vece
, TCGv_vec t
, TCGv_vec sat
,
5158 TCGv_vec a
, TCGv_vec b
)
5160 TCGv_vec x
= tcg_temp_new_vec_matching(t
);
5161 tcg_gen_sub_vec(vece
, x
, a
, b
);
5162 tcg_gen_sssub_vec(vece
, t
, a
, b
);
5163 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, x
, x
, t
);
5164 tcg_gen_or_vec(vece
, sat
, sat
, x
);
5165 tcg_temp_free_vec(x
);
5168 static const TCGOpcode vecop_list_sqsub
[] = {
5169 INDEX_op_sssub_vec
, INDEX_op_cmp_vec
, INDEX_op_sub_vec
, 0
5172 const GVecGen4 sqsub_op
[4] = {
5173 { .fniv
= gen_sqsub_vec
,
5174 .fno
= gen_helper_gvec_sqsub_b
,
5175 .opt_opc
= vecop_list_sqsub
,
5178 { .fniv
= gen_sqsub_vec
,
5179 .fno
= gen_helper_gvec_sqsub_h
,
5180 .opt_opc
= vecop_list_sqsub
,
5183 { .fniv
= gen_sqsub_vec
,
5184 .fno
= gen_helper_gvec_sqsub_s
,
5185 .opt_opc
= vecop_list_sqsub
,
5188 { .fniv
= gen_sqsub_vec
,
5189 .fno
= gen_helper_gvec_sqsub_d
,
5190 .opt_opc
= vecop_list_sqsub
,
5195 /* Translate a NEON data processing instruction. Return nonzero if the
5196 instruction is invalid.
5197 We process data in a mixture of 32-bit and 64-bit chunks.
5198 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
5200 static int disas_neon_data_insn(DisasContext
*s
, uint32_t insn
)
5204 int rd
, rn
, rm
, rd_ofs
, rn_ofs
, rm_ofs
;
5213 TCGv_i32 tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
5214 TCGv_ptr ptr1
, ptr2
, ptr3
;
5217 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
5221 /* FIXME: this access check should not take precedence over UNDEF
5222 * for invalid encodings; we will generate incorrect syndrome information
5223 * for attempts to execute invalid vfp/neon encodings with FP disabled.
5225 if (s
->fp_excp_el
) {
5226 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
5227 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
5231 if (!s
->vfp_enabled
)
5233 q
= (insn
& (1 << 6)) != 0;
5234 u
= (insn
>> 24) & 1;
5235 VFP_DREG_D(rd
, insn
);
5236 VFP_DREG_N(rn
, insn
);
5237 VFP_DREG_M(rm
, insn
);
5238 size
= (insn
>> 20) & 3;
5239 vec_size
= q
? 16 : 8;
5240 rd_ofs
= neon_reg_offset(rd
, 0);
5241 rn_ofs
= neon_reg_offset(rn
, 0);
5242 rm_ofs
= neon_reg_offset(rm
, 0);
5244 if ((insn
& (1 << 23)) == 0) {
5245 /* Three register same length. */
5246 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
5247 /* Catch invalid op and bad size combinations: UNDEF */
5248 if ((neon_3r_sizes
[op
] & (1 << size
)) == 0) {
5251 /* All insns of this form UNDEF for either this condition or the
5252 * superset of cases "Q==1"; we catch the latter later.
5254 if (q
&& ((rd
| rn
| rm
) & 1)) {
5259 /* The SHA-1/SHA-256 3-register instructions require special
5260 * treatment here, as their size field is overloaded as an
5261 * op type selector, and they all consume their input in a
5267 if (!u
) { /* SHA-1 */
5268 if (!dc_isar_feature(aa32_sha1
, s
)) {
5271 ptr1
= vfp_reg_ptr(true, rd
);
5272 ptr2
= vfp_reg_ptr(true, rn
);
5273 ptr3
= vfp_reg_ptr(true, rm
);
5274 tmp4
= tcg_const_i32(size
);
5275 gen_helper_crypto_sha1_3reg(ptr1
, ptr2
, ptr3
, tmp4
);
5276 tcg_temp_free_i32(tmp4
);
5277 } else { /* SHA-256 */
5278 if (!dc_isar_feature(aa32_sha2
, s
) || size
== 3) {
5281 ptr1
= vfp_reg_ptr(true, rd
);
5282 ptr2
= vfp_reg_ptr(true, rn
);
5283 ptr3
= vfp_reg_ptr(true, rm
);
5286 gen_helper_crypto_sha256h(ptr1
, ptr2
, ptr3
);
5289 gen_helper_crypto_sha256h2(ptr1
, ptr2
, ptr3
);
5292 gen_helper_crypto_sha256su1(ptr1
, ptr2
, ptr3
);
5296 tcg_temp_free_ptr(ptr1
);
5297 tcg_temp_free_ptr(ptr2
);
5298 tcg_temp_free_ptr(ptr3
);
5301 case NEON_3R_VPADD_VQRDMLAH
:
5308 return do_v81_helper(s
, gen_helper_gvec_qrdmlah_s16
,
5311 return do_v81_helper(s
, gen_helper_gvec_qrdmlah_s32
,
5316 case NEON_3R_VFM_VQRDMLSH
:
5327 return do_v81_helper(s
, gen_helper_gvec_qrdmlsh_s16
,
5330 return do_v81_helper(s
, gen_helper_gvec_qrdmlsh_s32
,
5335 case NEON_3R_VADD_VSUB
:
5339 case NEON_3R_VTST_VCEQ
:
5347 /* Already handled by decodetree */
5352 /* 64-bit element instructions. */
5353 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5354 neon_load_reg64(cpu_V0
, rn
+ pass
);
5355 neon_load_reg64(cpu_V1
, rm
+ pass
);
5359 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
5362 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
5368 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
5370 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
5373 case NEON_3R_VQRSHL
:
5375 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_env
,
5378 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_env
,
5385 neon_store_reg64(cpu_V0
, rd
+ pass
);
5393 case NEON_3R_VQRSHL
:
5396 /* Shift instruction operands are reversed. */
5402 case NEON_3R_VPADD_VQRDMLAH
:
5407 case NEON_3R_FLOAT_ARITH
:
5408 pairwise
= (u
&& size
< 2); /* if VPADD (float) */
5410 case NEON_3R_FLOAT_MINMAX
:
5411 pairwise
= u
; /* if VPMIN/VPMAX (float) */
5413 case NEON_3R_FLOAT_CMP
:
5415 /* no encoding for U=0 C=1x */
5419 case NEON_3R_FLOAT_ACMP
:
5424 case NEON_3R_FLOAT_MISC
:
5425 /* VMAXNM/VMINNM in ARMv8 */
5426 if (u
&& !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
5430 case NEON_3R_VFM_VQRDMLSH
:
5431 if (!dc_isar_feature(aa32_simdfmac
, s
)) {
5439 if (pairwise
&& q
) {
5440 /* All the pairwise insns UNDEF if Q is set */
5444 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5449 tmp
= neon_load_reg(rn
, 0);
5450 tmp2
= neon_load_reg(rn
, 1);
5452 tmp
= neon_load_reg(rm
, 0);
5453 tmp2
= neon_load_reg(rm
, 1);
5457 tmp
= neon_load_reg(rn
, pass
);
5458 tmp2
= neon_load_reg(rm
, pass
);
5462 GEN_NEON_INTEGER_OP(hadd
);
5464 case NEON_3R_VRHADD
:
5465 GEN_NEON_INTEGER_OP(rhadd
);
5468 GEN_NEON_INTEGER_OP(hsub
);
5471 GEN_NEON_INTEGER_OP_ENV(qshl
);
5474 GEN_NEON_INTEGER_OP(rshl
);
5476 case NEON_3R_VQRSHL
:
5477 GEN_NEON_INTEGER_OP_ENV(qrshl
);
5480 GEN_NEON_INTEGER_OP(abd
);
5483 GEN_NEON_INTEGER_OP(abd
);
5484 tcg_temp_free_i32(tmp2
);
5485 tmp2
= neon_load_reg(rd
, pass
);
5486 gen_neon_add(size
, tmp
, tmp2
);
5489 GEN_NEON_INTEGER_OP(pmax
);
5492 GEN_NEON_INTEGER_OP(pmin
);
5494 case NEON_3R_VQDMULH_VQRDMULH
: /* Multiply high. */
5495 if (!u
) { /* VQDMULH */
5498 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5501 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5505 } else { /* VQRDMULH */
5508 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
5511 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
5517 case NEON_3R_VPADD_VQRDMLAH
:
5519 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
5520 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
5521 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
5525 case NEON_3R_FLOAT_ARITH
: /* Floating point arithmetic. */
5527 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5528 switch ((u
<< 2) | size
) {
5531 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5534 gen_helper_vfp_subs(tmp
, tmp
, tmp2
, fpstatus
);
5537 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
, fpstatus
);
5542 tcg_temp_free_ptr(fpstatus
);
5545 case NEON_3R_FLOAT_MULTIPLY
:
5547 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5548 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
5550 tcg_temp_free_i32(tmp2
);
5551 tmp2
= neon_load_reg(rd
, pass
);
5553 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
5555 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
5558 tcg_temp_free_ptr(fpstatus
);
5561 case NEON_3R_FLOAT_CMP
:
5563 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5565 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
5568 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5570 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5573 tcg_temp_free_ptr(fpstatus
);
5576 case NEON_3R_FLOAT_ACMP
:
5578 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5580 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
, fpstatus
);
5582 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
5584 tcg_temp_free_ptr(fpstatus
);
5587 case NEON_3R_FLOAT_MINMAX
:
5589 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5591 gen_helper_vfp_maxs(tmp
, tmp
, tmp2
, fpstatus
);
5593 gen_helper_vfp_mins(tmp
, tmp
, tmp2
, fpstatus
);
5595 tcg_temp_free_ptr(fpstatus
);
5598 case NEON_3R_FLOAT_MISC
:
5601 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5603 gen_helper_vfp_maxnums(tmp
, tmp
, tmp2
, fpstatus
);
5605 gen_helper_vfp_minnums(tmp
, tmp
, tmp2
, fpstatus
);
5607 tcg_temp_free_ptr(fpstatus
);
5610 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
5612 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
5616 case NEON_3R_VFM_VQRDMLSH
:
5618 /* VFMA, VFMS: fused multiply-add */
5619 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
5620 TCGv_i32 tmp3
= neon_load_reg(rd
, pass
);
5623 gen_helper_vfp_negs(tmp
, tmp
);
5625 gen_helper_vfp_muladds(tmp
, tmp
, tmp2
, tmp3
, fpstatus
);
5626 tcg_temp_free_i32(tmp3
);
5627 tcg_temp_free_ptr(fpstatus
);
5633 tcg_temp_free_i32(tmp2
);
5635 /* Save the result. For elementwise operations we can put it
5636 straight into the destination register. For pairwise operations
5637 we have to be careful to avoid clobbering the source operands. */
5638 if (pairwise
&& rd
== rm
) {
5639 neon_store_scratch(pass
, tmp
);
5641 neon_store_reg(rd
, pass
, tmp
);
5645 if (pairwise
&& rd
== rm
) {
5646 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5647 tmp
= neon_load_scratch(pass
);
5648 neon_store_reg(rd
, pass
, tmp
);
5651 /* End of 3 register same size operations. */
5652 } else if (insn
& (1 << 4)) {
5653 if ((insn
& 0x00380080) != 0) {
5654 /* Two registers and shift. */
5655 op
= (insn
>> 8) & 0xf;
5656 if (insn
& (1 << 7)) {
5664 while ((insn
& (1 << (size
+ 19))) == 0)
5667 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
5669 /* Shift by immediate:
5670 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
5671 if (q
&& ((rd
| rm
) & 1)) {
5674 if (!u
&& (op
== 4 || op
== 6)) {
5677 /* Right shifts are encoded as N - shift, where N is the
5678 element size in bits. */
5680 shift
= shift
- (1 << (size
+ 3));
5685 /* Right shift comes here negative. */
5687 /* Shifts larger than the element size are architecturally
5688 * valid. Unsigned results in all zeros; signed results
5692 tcg_gen_gvec_sari(size
, rd_ofs
, rm_ofs
,
5693 MIN(shift
, (8 << size
) - 1),
5694 vec_size
, vec_size
);
5695 } else if (shift
>= 8 << size
) {
5696 tcg_gen_gvec_dup_imm(MO_8
, rd_ofs
, vec_size
,
5699 tcg_gen_gvec_shri(size
, rd_ofs
, rm_ofs
, shift
,
5700 vec_size
, vec_size
);
5705 /* Right shift comes here negative. */
5708 gen_gvec_usra(size
, rd_ofs
, rm_ofs
, shift
,
5709 vec_size
, vec_size
);
5711 gen_gvec_ssra(size
, rd_ofs
, rm_ofs
, shift
,
5712 vec_size
, vec_size
);
5717 /* Right shift comes here negative. */
5720 gen_gvec_urshr(size
, rd_ofs
, rm_ofs
, shift
,
5721 vec_size
, vec_size
);
5723 gen_gvec_srshr(size
, rd_ofs
, rm_ofs
, shift
,
5724 vec_size
, vec_size
);
5729 /* Right shift comes here negative. */
5732 gen_gvec_ursra(size
, rd_ofs
, rm_ofs
, shift
,
5733 vec_size
, vec_size
);
5735 gen_gvec_srsra(size
, rd_ofs
, rm_ofs
, shift
,
5736 vec_size
, vec_size
);
5744 /* Right shift comes here negative. */
5746 gen_gvec_sri(size
, rd_ofs
, rm_ofs
, shift
,
5747 vec_size
, vec_size
);
5750 case 5: /* VSHL, VSLI */
5752 gen_gvec_sli(size
, rd_ofs
, rm_ofs
, shift
,
5753 vec_size
, vec_size
);
5755 tcg_gen_gvec_shli(size
, rd_ofs
, rm_ofs
, shift
,
5756 vec_size
, vec_size
);
5767 /* To avoid excessive duplication of ops we implement shift
5768 * by immediate using the variable shift operations.
5770 imm
= dup_const(size
, shift
);
5772 for (pass
= 0; pass
< count
; pass
++) {
5774 neon_load_reg64(cpu_V0
, rm
+ pass
);
5775 tcg_gen_movi_i64(cpu_V1
, imm
);
5777 case 6: /* VQSHLU */
5778 gen_helper_neon_qshlu_s64(cpu_V0
, cpu_env
,
5783 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
5786 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
5791 g_assert_not_reached();
5793 neon_store_reg64(cpu_V0
, rd
+ pass
);
5794 } else { /* size < 3 */
5795 /* Operands in T0 and T1. */
5796 tmp
= neon_load_reg(rm
, pass
);
5797 tmp2
= tcg_temp_new_i32();
5798 tcg_gen_movi_i32(tmp2
, imm
);
5800 case 6: /* VQSHLU */
5803 gen_helper_neon_qshlu_s8(tmp
, cpu_env
,
5807 gen_helper_neon_qshlu_s16(tmp
, cpu_env
,
5811 gen_helper_neon_qshlu_s32(tmp
, cpu_env
,
5819 GEN_NEON_INTEGER_OP_ENV(qshl
);
5822 g_assert_not_reached();
5824 tcg_temp_free_i32(tmp2
);
5825 neon_store_reg(rd
, pass
, tmp
);
5828 } else if (op
< 10) {
5829 /* Shift by immediate and narrow:
5830 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
5831 int input_unsigned
= (op
== 8) ? !u
: u
;
5835 shift
= shift
- (1 << (size
+ 3));
5838 tmp64
= tcg_const_i64(shift
);
5839 neon_load_reg64(cpu_V0
, rm
);
5840 neon_load_reg64(cpu_V1
, rm
+ 1);
5841 for (pass
= 0; pass
< 2; pass
++) {
5849 if (input_unsigned
) {
5850 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
5852 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
5855 if (input_unsigned
) {
5856 gen_ushl_i64(cpu_V0
, in
, tmp64
);
5858 gen_sshl_i64(cpu_V0
, in
, tmp64
);
5861 tmp
= tcg_temp_new_i32();
5862 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5863 neon_store_reg(rd
, pass
, tmp
);
5865 tcg_temp_free_i64(tmp64
);
5868 imm
= (uint16_t)shift
;
5872 imm
= (uint32_t)shift
;
5874 tmp2
= tcg_const_i32(imm
);
5875 tmp4
= neon_load_reg(rm
+ 1, 0);
5876 tmp5
= neon_load_reg(rm
+ 1, 1);
5877 for (pass
= 0; pass
< 2; pass
++) {
5879 tmp
= neon_load_reg(rm
, 0);
5883 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
5886 tmp3
= neon_load_reg(rm
, 1);
5890 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
5892 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
5893 tcg_temp_free_i32(tmp
);
5894 tcg_temp_free_i32(tmp3
);
5895 tmp
= tcg_temp_new_i32();
5896 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5897 neon_store_reg(rd
, pass
, tmp
);
5899 tcg_temp_free_i32(tmp2
);
5901 } else if (op
== 10) {
5903 if (q
|| (rd
& 1)) {
5906 tmp
= neon_load_reg(rm
, 0);
5907 tmp2
= neon_load_reg(rm
, 1);
5908 for (pass
= 0; pass
< 2; pass
++) {
5912 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5915 /* The shift is less than the width of the source
5916 type, so we can just shift the whole register. */
5917 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
5918 /* Widen the result of shift: we need to clear
5919 * the potential overflow bits resulting from
5920 * left bits of the narrow input appearing as
5921 * right bits of left the neighbour narrow
5923 if (size
< 2 || !u
) {
5926 imm
= (0xffu
>> (8 - shift
));
5928 } else if (size
== 1) {
5929 imm
= 0xffff >> (16 - shift
);
5932 imm
= 0xffffffff >> (32 - shift
);
5935 imm64
= imm
| (((uint64_t)imm
) << 32);
5939 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
5942 neon_store_reg64(cpu_V0
, rd
+ pass
);
5944 } else if (op
>= 14) {
5945 /* VCVT fixed-point. */
5948 VFPGenFixPointFn
*fn
;
5950 if (!(insn
& (1 << 21)) || (q
&& ((rd
| rm
) & 1))) {
5956 fn
= gen_helper_vfp_ultos
;
5958 fn
= gen_helper_vfp_sltos
;
5962 fn
= gen_helper_vfp_touls_round_to_zero
;
5964 fn
= gen_helper_vfp_tosls_round_to_zero
;
5968 /* We have already masked out the must-be-1 top bit of imm6,
5969 * hence this 32-shift where the ARM ARM has 64-imm6.
5972 fpst
= get_fpstatus_ptr(1);
5973 shiftv
= tcg_const_i32(shift
);
5974 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5975 TCGv_i32 tmpf
= neon_load_reg(rm
, pass
);
5976 fn(tmpf
, tmpf
, shiftv
, fpst
);
5977 neon_store_reg(rd
, pass
, tmpf
);
5979 tcg_temp_free_ptr(fpst
);
5980 tcg_temp_free_i32(shiftv
);
5984 } else { /* (insn & 0x00380080) == 0 */
5985 int invert
, reg_ofs
, vec_size
;
5987 if (q
&& (rd
& 1)) {
5991 op
= (insn
>> 8) & 0xf;
5992 /* One register and immediate. */
5993 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
5994 invert
= (insn
& (1 << 5)) != 0;
5995 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5996 * We choose to not special-case this and will behave as if a
5997 * valid constant encoding of 0 had been given.
6016 imm
= (imm
<< 8) | (imm
<< 24);
6019 imm
= (imm
<< 8) | 0xff;
6022 imm
= (imm
<< 16) | 0xffff;
6025 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
6034 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
6035 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
6042 reg_ofs
= neon_reg_offset(rd
, 0);
6043 vec_size
= q
? 16 : 8;
6045 if (op
& 1 && op
< 12) {
6047 /* The immediate value has already been inverted,
6048 * so BIC becomes AND.
6050 tcg_gen_gvec_andi(MO_32
, reg_ofs
, reg_ofs
, imm
,
6051 vec_size
, vec_size
);
6053 tcg_gen_gvec_ori(MO_32
, reg_ofs
, reg_ofs
, imm
,
6054 vec_size
, vec_size
);
6058 if (op
== 14 && invert
) {
6059 TCGv_i64 t64
= tcg_temp_new_i64();
6061 for (pass
= 0; pass
<= q
; ++pass
) {
6065 for (n
= 0; n
< 8; n
++) {
6066 if (imm
& (1 << (n
+ pass
* 8))) {
6067 val
|= 0xffull
<< (n
* 8);
6070 tcg_gen_movi_i64(t64
, val
);
6071 neon_store_reg64(t64
, rd
+ pass
);
6073 tcg_temp_free_i64(t64
);
6075 tcg_gen_gvec_dup_imm(MO_32
, reg_ofs
, vec_size
,
6080 } else { /* (insn & 0x00800010 == 0x00800000) */
6082 op
= (insn
>> 8) & 0xf;
6083 if ((insn
& (1 << 6)) == 0) {
6084 /* Three registers of different lengths. */
6088 /* undefreq: bit 0 : UNDEF if size == 0
6089 * bit 1 : UNDEF if size == 1
6090 * bit 2 : UNDEF if size == 2
6091 * bit 3 : UNDEF if U == 1
6092 * Note that [2:0] set implies 'always UNDEF'
6095 /* prewiden, src1_wide, src2_wide, undefreq */
6096 static const int neon_3reg_wide
[16][4] = {
6097 {1, 0, 0, 0}, /* VADDL */
6098 {1, 1, 0, 0}, /* VADDW */
6099 {1, 0, 0, 0}, /* VSUBL */
6100 {1, 1, 0, 0}, /* VSUBW */
6101 {0, 1, 1, 0}, /* VADDHN */
6102 {0, 0, 0, 0}, /* VABAL */
6103 {0, 1, 1, 0}, /* VSUBHN */
6104 {0, 0, 0, 0}, /* VABDL */
6105 {0, 0, 0, 0}, /* VMLAL */
6106 {0, 0, 0, 9}, /* VQDMLAL */
6107 {0, 0, 0, 0}, /* VMLSL */
6108 {0, 0, 0, 9}, /* VQDMLSL */
6109 {0, 0, 0, 0}, /* Integer VMULL */
6110 {0, 0, 0, 9}, /* VQDMULL */
6111 {0, 0, 0, 0xa}, /* Polynomial VMULL */
6112 {0, 0, 0, 7}, /* Reserved: always UNDEF */
6115 prewiden
= neon_3reg_wide
[op
][0];
6116 src1_wide
= neon_3reg_wide
[op
][1];
6117 src2_wide
= neon_3reg_wide
[op
][2];
6118 undefreq
= neon_3reg_wide
[op
][3];
6120 if ((undefreq
& (1 << size
)) ||
6121 ((undefreq
& 8) && u
)) {
6124 if ((src1_wide
&& (rn
& 1)) ||
6125 (src2_wide
&& (rm
& 1)) ||
6126 (!src2_wide
&& (rd
& 1))) {
6130 /* Handle polynomial VMULL in a single pass. */
6134 tcg_gen_gvec_3_ool(rd_ofs
, rn_ofs
, rm_ofs
, 16, 16,
6135 0, gen_helper_neon_pmull_h
);
6138 if (!dc_isar_feature(aa32_pmull
, s
)) {
6141 tcg_gen_gvec_3_ool(rd_ofs
, rn_ofs
, rm_ofs
, 16, 16,
6142 0, gen_helper_gvec_pmull_q
);
6147 /* Avoid overlapping operands. Wide source operands are
6148 always aligned so will never overlap with wide
6149 destinations in problematic ways. */
6150 if (rd
== rm
&& !src2_wide
) {
6151 tmp
= neon_load_reg(rm
, 1);
6152 neon_store_scratch(2, tmp
);
6153 } else if (rd
== rn
&& !src1_wide
) {
6154 tmp
= neon_load_reg(rn
, 1);
6155 neon_store_scratch(2, tmp
);
6158 for (pass
= 0; pass
< 2; pass
++) {
6160 neon_load_reg64(cpu_V0
, rn
+ pass
);
6163 if (pass
== 1 && rd
== rn
) {
6164 tmp
= neon_load_scratch(2);
6166 tmp
= neon_load_reg(rn
, pass
);
6169 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
6173 neon_load_reg64(cpu_V1
, rm
+ pass
);
6176 if (pass
== 1 && rd
== rm
) {
6177 tmp2
= neon_load_scratch(2);
6179 tmp2
= neon_load_reg(rm
, pass
);
6182 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
6186 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
6187 gen_neon_addl(size
);
6189 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
6190 gen_neon_subl(size
);
6192 case 5: case 7: /* VABAL, VABDL */
6193 switch ((size
<< 1) | u
) {
6195 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
6198 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
6201 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
6204 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
6207 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
6210 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
6214 tcg_temp_free_i32(tmp2
);
6215 tcg_temp_free_i32(tmp
);
6217 case 8: case 9: case 10: case 11: case 12: case 13:
6218 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
6219 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
6221 default: /* 15 is RESERVED: caught earlier */
6226 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6227 neon_store_reg64(cpu_V0
, rd
+ pass
);
6228 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
6230 neon_load_reg64(cpu_V1
, rd
+ pass
);
6232 case 10: /* VMLSL */
6233 gen_neon_negl(cpu_V0
, size
);
6235 case 5: case 8: /* VABAL, VMLAL */
6236 gen_neon_addl(size
);
6238 case 9: case 11: /* VQDMLAL, VQDMLSL */
6239 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6241 gen_neon_negl(cpu_V0
, size
);
6243 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
6248 neon_store_reg64(cpu_V0
, rd
+ pass
);
6249 } else if (op
== 4 || op
== 6) {
6250 /* Narrowing operation. */
6251 tmp
= tcg_temp_new_i32();
6255 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
6258 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
6261 tcg_gen_extrh_i64_i32(tmp
, cpu_V0
);
6268 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
6271 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
6274 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
6275 tcg_gen_extrh_i64_i32(tmp
, cpu_V0
);
6283 neon_store_reg(rd
, 0, tmp3
);
6284 neon_store_reg(rd
, 1, tmp
);
6287 /* Write back the result. */
6288 neon_store_reg64(cpu_V0
, rd
+ pass
);
6292 /* Two registers and a scalar. NB that for ops of this form
6293 * the ARM ARM labels bit 24 as Q, but it is in our variable
6300 case 1: /* Float VMLA scalar */
6301 case 5: /* Floating point VMLS scalar */
6302 case 9: /* Floating point VMUL scalar */
6307 case 0: /* Integer VMLA scalar */
6308 case 4: /* Integer VMLS scalar */
6309 case 8: /* Integer VMUL scalar */
6310 case 12: /* VQDMULH scalar */
6311 case 13: /* VQRDMULH scalar */
6312 if (u
&& ((rd
| rn
) & 1)) {
6315 tmp
= neon_get_scalar(size
, rm
);
6316 neon_store_scratch(0, tmp
);
6317 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
6318 tmp
= neon_load_scratch(0);
6319 tmp2
= neon_load_reg(rn
, pass
);
6322 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6324 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6326 } else if (op
== 13) {
6328 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6330 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6332 } else if (op
& 1) {
6333 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6334 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
6335 tcg_temp_free_ptr(fpstatus
);
6338 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
6339 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
6340 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
6344 tcg_temp_free_i32(tmp2
);
6347 tmp2
= neon_load_reg(rd
, pass
);
6350 gen_neon_add(size
, tmp
, tmp2
);
6354 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6355 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
6356 tcg_temp_free_ptr(fpstatus
);
6360 gen_neon_rsb(size
, tmp
, tmp2
);
6364 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6365 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
6366 tcg_temp_free_ptr(fpstatus
);
6372 tcg_temp_free_i32(tmp2
);
6374 neon_store_reg(rd
, pass
, tmp
);
6377 case 3: /* VQDMLAL scalar */
6378 case 7: /* VQDMLSL scalar */
6379 case 11: /* VQDMULL scalar */
6384 case 2: /* VMLAL sclar */
6385 case 6: /* VMLSL scalar */
6386 case 10: /* VMULL scalar */
6390 tmp2
= neon_get_scalar(size
, rm
);
6391 /* We need a copy of tmp2 because gen_neon_mull
6392 * deletes it during pass 0. */
6393 tmp4
= tcg_temp_new_i32();
6394 tcg_gen_mov_i32(tmp4
, tmp2
);
6395 tmp3
= neon_load_reg(rn
, 1);
6397 for (pass
= 0; pass
< 2; pass
++) {
6399 tmp
= neon_load_reg(rn
, 0);
6404 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
6406 neon_load_reg64(cpu_V1
, rd
+ pass
);
6410 gen_neon_negl(cpu_V0
, size
);
6413 gen_neon_addl(size
);
6416 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6418 gen_neon_negl(cpu_V0
, size
);
6420 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
6426 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
6431 neon_store_reg64(cpu_V0
, rd
+ pass
);
6434 case 14: /* VQRDMLAH scalar */
6435 case 15: /* VQRDMLSH scalar */
6437 NeonGenThreeOpEnvFn
*fn
;
6439 if (!dc_isar_feature(aa32_rdm
, s
)) {
6442 if (u
&& ((rd
| rn
) & 1)) {
6447 fn
= gen_helper_neon_qrdmlah_s16
;
6449 fn
= gen_helper_neon_qrdmlah_s32
;
6453 fn
= gen_helper_neon_qrdmlsh_s16
;
6455 fn
= gen_helper_neon_qrdmlsh_s32
;
6459 tmp2
= neon_get_scalar(size
, rm
);
6460 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
6461 tmp
= neon_load_reg(rn
, pass
);
6462 tmp3
= neon_load_reg(rd
, pass
);
6463 fn(tmp
, cpu_env
, tmp
, tmp2
, tmp3
);
6464 tcg_temp_free_i32(tmp3
);
6465 neon_store_reg(rd
, pass
, tmp
);
6467 tcg_temp_free_i32(tmp2
);
6471 g_assert_not_reached();
6474 } else { /* size == 3 */
6477 imm
= (insn
>> 8) & 0xf;
6482 if (q
&& ((rd
| rn
| rm
) & 1)) {
6487 neon_load_reg64(cpu_V0
, rn
);
6489 neon_load_reg64(cpu_V1
, rn
+ 1);
6491 } else if (imm
== 8) {
6492 neon_load_reg64(cpu_V0
, rn
+ 1);
6494 neon_load_reg64(cpu_V1
, rm
);
6497 tmp64
= tcg_temp_new_i64();
6499 neon_load_reg64(cpu_V0
, rn
);
6500 neon_load_reg64(tmp64
, rn
+ 1);
6502 neon_load_reg64(cpu_V0
, rn
+ 1);
6503 neon_load_reg64(tmp64
, rm
);
6505 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
6506 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
6507 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6509 neon_load_reg64(cpu_V1
, rm
);
6511 neon_load_reg64(cpu_V1
, rm
+ 1);
6514 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6515 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
6516 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
6517 tcg_temp_free_i64(tmp64
);
6520 neon_load_reg64(cpu_V0
, rn
);
6521 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
6522 neon_load_reg64(cpu_V1
, rm
);
6523 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
6524 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6526 neon_store_reg64(cpu_V0
, rd
);
6528 neon_store_reg64(cpu_V1
, rd
+ 1);
6530 } else if ((insn
& (1 << 11)) == 0) {
6531 /* Two register misc. */
6532 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
6533 size
= (insn
>> 18) & 3;
6534 /* UNDEF for unknown op values and bad op-size combinations */
6535 if ((neon_2rm_sizes
[op
] & (1 << size
)) == 0) {
6538 if (neon_2rm_is_v8_op(op
) &&
6539 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
6542 if ((op
!= NEON_2RM_VMOVN
&& op
!= NEON_2RM_VQMOVN
) &&
6543 q
&& ((rm
| rd
) & 1)) {
6547 case NEON_2RM_VREV64
:
6548 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
6549 tmp
= neon_load_reg(rm
, pass
* 2);
6550 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
6552 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
6553 case 1: gen_swap_half(tmp
); break;
6554 case 2: /* no-op */ break;
6557 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
6559 neon_store_reg(rd
, pass
* 2, tmp2
);
6562 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
6563 case 1: gen_swap_half(tmp2
); break;
6566 neon_store_reg(rd
, pass
* 2, tmp2
);
6570 case NEON_2RM_VPADDL
: case NEON_2RM_VPADDL_U
:
6571 case NEON_2RM_VPADAL
: case NEON_2RM_VPADAL_U
:
6572 for (pass
= 0; pass
< q
+ 1; pass
++) {
6573 tmp
= neon_load_reg(rm
, pass
* 2);
6574 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
6575 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
6576 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
6578 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
6579 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
6580 case 2: tcg_gen_add_i64(CPU_V001
); break;
6583 if (op
>= NEON_2RM_VPADAL
) {
6585 neon_load_reg64(cpu_V1
, rd
+ pass
);
6586 gen_neon_addl(size
);
6588 neon_store_reg64(cpu_V0
, rd
+ pass
);
6594 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
6595 tmp
= neon_load_reg(rm
, n
);
6596 tmp2
= neon_load_reg(rd
, n
+ 1);
6597 neon_store_reg(rm
, n
, tmp2
);
6598 neon_store_reg(rd
, n
+ 1, tmp
);
6605 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
6610 if (gen_neon_zip(rd
, rm
, size
, q
)) {
6614 case NEON_2RM_VMOVN
: case NEON_2RM_VQMOVN
:
6615 /* also VQMOVUN; op field and mnemonics don't line up */
6620 for (pass
= 0; pass
< 2; pass
++) {
6621 neon_load_reg64(cpu_V0
, rm
+ pass
);
6622 tmp
= tcg_temp_new_i32();
6623 gen_neon_narrow_op(op
== NEON_2RM_VMOVN
, q
, size
,
6628 neon_store_reg(rd
, 0, tmp2
);
6629 neon_store_reg(rd
, 1, tmp
);
6633 case NEON_2RM_VSHLL
:
6634 if (q
|| (rd
& 1)) {
6637 tmp
= neon_load_reg(rm
, 0);
6638 tmp2
= neon_load_reg(rm
, 1);
6639 for (pass
= 0; pass
< 2; pass
++) {
6642 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
6643 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
6644 neon_store_reg64(cpu_V0
, rd
+ pass
);
6647 case NEON_2RM_VCVT_F16_F32
:
6652 if (!dc_isar_feature(aa32_fp16_spconv
, s
) ||
6656 fpst
= get_fpstatus_ptr(true);
6657 ahp
= get_ahp_flag();
6658 tmp
= neon_load_reg(rm
, 0);
6659 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp
);
6660 tmp2
= neon_load_reg(rm
, 1);
6661 gen_helper_vfp_fcvt_f32_to_f16(tmp2
, tmp2
, fpst
, ahp
);
6662 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
6663 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
6664 tcg_temp_free_i32(tmp
);
6665 tmp
= neon_load_reg(rm
, 2);
6666 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp
);
6667 tmp3
= neon_load_reg(rm
, 3);
6668 neon_store_reg(rd
, 0, tmp2
);
6669 gen_helper_vfp_fcvt_f32_to_f16(tmp3
, tmp3
, fpst
, ahp
);
6670 tcg_gen_shli_i32(tmp3
, tmp3
, 16);
6671 tcg_gen_or_i32(tmp3
, tmp3
, tmp
);
6672 neon_store_reg(rd
, 1, tmp3
);
6673 tcg_temp_free_i32(tmp
);
6674 tcg_temp_free_i32(ahp
);
6675 tcg_temp_free_ptr(fpst
);
6678 case NEON_2RM_VCVT_F32_F16
:
6682 if (!dc_isar_feature(aa32_fp16_spconv
, s
) ||
6686 fpst
= get_fpstatus_ptr(true);
6687 ahp
= get_ahp_flag();
6688 tmp3
= tcg_temp_new_i32();
6689 tmp
= neon_load_reg(rm
, 0);
6690 tmp2
= neon_load_reg(rm
, 1);
6691 tcg_gen_ext16u_i32(tmp3
, tmp
);
6692 gen_helper_vfp_fcvt_f16_to_f32(tmp3
, tmp3
, fpst
, ahp
);
6693 neon_store_reg(rd
, 0, tmp3
);
6694 tcg_gen_shri_i32(tmp
, tmp
, 16);
6695 gen_helper_vfp_fcvt_f16_to_f32(tmp
, tmp
, fpst
, ahp
);
6696 neon_store_reg(rd
, 1, tmp
);
6697 tmp3
= tcg_temp_new_i32();
6698 tcg_gen_ext16u_i32(tmp3
, tmp2
);
6699 gen_helper_vfp_fcvt_f16_to_f32(tmp3
, tmp3
, fpst
, ahp
);
6700 neon_store_reg(rd
, 2, tmp3
);
6701 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
6702 gen_helper_vfp_fcvt_f16_to_f32(tmp2
, tmp2
, fpst
, ahp
);
6703 neon_store_reg(rd
, 3, tmp2
);
6704 tcg_temp_free_i32(ahp
);
6705 tcg_temp_free_ptr(fpst
);
6708 case NEON_2RM_AESE
: case NEON_2RM_AESMC
:
6709 if (!dc_isar_feature(aa32_aes
, s
) || ((rm
| rd
) & 1)) {
6712 ptr1
= vfp_reg_ptr(true, rd
);
6713 ptr2
= vfp_reg_ptr(true, rm
);
6715 /* Bit 6 is the lowest opcode bit; it distinguishes between
6716 * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
6718 tmp3
= tcg_const_i32(extract32(insn
, 6, 1));
6720 if (op
== NEON_2RM_AESE
) {
6721 gen_helper_crypto_aese(ptr1
, ptr2
, tmp3
);
6723 gen_helper_crypto_aesmc(ptr1
, ptr2
, tmp3
);
6725 tcg_temp_free_ptr(ptr1
);
6726 tcg_temp_free_ptr(ptr2
);
6727 tcg_temp_free_i32(tmp3
);
6729 case NEON_2RM_SHA1H
:
6730 if (!dc_isar_feature(aa32_sha1
, s
) || ((rm
| rd
) & 1)) {
6733 ptr1
= vfp_reg_ptr(true, rd
);
6734 ptr2
= vfp_reg_ptr(true, rm
);
6736 gen_helper_crypto_sha1h(ptr1
, ptr2
);
6738 tcg_temp_free_ptr(ptr1
);
6739 tcg_temp_free_ptr(ptr2
);
6741 case NEON_2RM_SHA1SU1
:
6742 if ((rm
| rd
) & 1) {
6745 /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
6747 if (!dc_isar_feature(aa32_sha2
, s
)) {
6750 } else if (!dc_isar_feature(aa32_sha1
, s
)) {
6753 ptr1
= vfp_reg_ptr(true, rd
);
6754 ptr2
= vfp_reg_ptr(true, rm
);
6756 gen_helper_crypto_sha256su0(ptr1
, ptr2
);
6758 gen_helper_crypto_sha1su1(ptr1
, ptr2
);
6760 tcg_temp_free_ptr(ptr1
);
6761 tcg_temp_free_ptr(ptr2
);
6765 tcg_gen_gvec_not(0, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
6768 tcg_gen_gvec_neg(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
6771 tcg_gen_gvec_abs(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
6774 case NEON_2RM_VCEQ0
:
6775 tcg_gen_gvec_2(rd_ofs
, rm_ofs
, vec_size
,
6776 vec_size
, &ceq0_op
[size
]);
6778 case NEON_2RM_VCGT0
:
6779 tcg_gen_gvec_2(rd_ofs
, rm_ofs
, vec_size
,
6780 vec_size
, &cgt0_op
[size
]);
6782 case NEON_2RM_VCLE0
:
6783 tcg_gen_gvec_2(rd_ofs
, rm_ofs
, vec_size
,
6784 vec_size
, &cle0_op
[size
]);
6786 case NEON_2RM_VCGE0
:
6787 tcg_gen_gvec_2(rd_ofs
, rm_ofs
, vec_size
,
6788 vec_size
, &cge0_op
[size
]);
6790 case NEON_2RM_VCLT0
:
6791 tcg_gen_gvec_2(rd_ofs
, rm_ofs
, vec_size
,
6792 vec_size
, &clt0_op
[size
]);
6797 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6798 tmp
= neon_load_reg(rm
, pass
);
6800 case NEON_2RM_VREV32
:
6802 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
6803 case 1: gen_swap_half(tmp
); break;
6807 case NEON_2RM_VREV16
:
6808 gen_rev16(tmp
, tmp
);
6812 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
6813 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
6814 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
6820 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
6821 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
6822 case 2: tcg_gen_clzi_i32(tmp
, tmp
, 32); break;
6827 gen_helper_neon_cnt_u8(tmp
, tmp
);
6829 case NEON_2RM_VQABS
:
6832 gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
);
6835 gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
);
6838 gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
);
6843 case NEON_2RM_VQNEG
:
6846 gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
);
6849 gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
);
6852 gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
);
6857 case NEON_2RM_VCGT0_F
:
6859 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6860 tmp2
= tcg_const_i32(0);
6861 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
6862 tcg_temp_free_i32(tmp2
);
6863 tcg_temp_free_ptr(fpstatus
);
6866 case NEON_2RM_VCGE0_F
:
6868 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6869 tmp2
= tcg_const_i32(0);
6870 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
6871 tcg_temp_free_i32(tmp2
);
6872 tcg_temp_free_ptr(fpstatus
);
6875 case NEON_2RM_VCEQ0_F
:
6877 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6878 tmp2
= tcg_const_i32(0);
6879 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
6880 tcg_temp_free_i32(tmp2
);
6881 tcg_temp_free_ptr(fpstatus
);
6884 case NEON_2RM_VCLE0_F
:
6886 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6887 tmp2
= tcg_const_i32(0);
6888 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
, fpstatus
);
6889 tcg_temp_free_i32(tmp2
);
6890 tcg_temp_free_ptr(fpstatus
);
6893 case NEON_2RM_VCLT0_F
:
6895 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6896 tmp2
= tcg_const_i32(0);
6897 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
, fpstatus
);
6898 tcg_temp_free_i32(tmp2
);
6899 tcg_temp_free_ptr(fpstatus
);
6902 case NEON_2RM_VABS_F
:
6903 gen_helper_vfp_abss(tmp
, tmp
);
6905 case NEON_2RM_VNEG_F
:
6906 gen_helper_vfp_negs(tmp
, tmp
);
6909 tmp2
= neon_load_reg(rd
, pass
);
6910 neon_store_reg(rm
, pass
, tmp2
);
6913 tmp2
= neon_load_reg(rd
, pass
);
6915 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
6916 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
6919 neon_store_reg(rm
, pass
, tmp2
);
6921 case NEON_2RM_VRINTN
:
6922 case NEON_2RM_VRINTA
:
6923 case NEON_2RM_VRINTM
:
6924 case NEON_2RM_VRINTP
:
6925 case NEON_2RM_VRINTZ
:
6928 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6931 if (op
== NEON_2RM_VRINTZ
) {
6932 rmode
= FPROUNDING_ZERO
;
6934 rmode
= fp_decode_rm
[((op
& 0x6) >> 1) ^ 1];
6937 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6938 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6940 gen_helper_rints(tmp
, tmp
, fpstatus
);
6941 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6943 tcg_temp_free_ptr(fpstatus
);
6944 tcg_temp_free_i32(tcg_rmode
);
6947 case NEON_2RM_VRINTX
:
6949 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6950 gen_helper_rints_exact(tmp
, tmp
, fpstatus
);
6951 tcg_temp_free_ptr(fpstatus
);
6954 case NEON_2RM_VCVTAU
:
6955 case NEON_2RM_VCVTAS
:
6956 case NEON_2RM_VCVTNU
:
6957 case NEON_2RM_VCVTNS
:
6958 case NEON_2RM_VCVTPU
:
6959 case NEON_2RM_VCVTPS
:
6960 case NEON_2RM_VCVTMU
:
6961 case NEON_2RM_VCVTMS
:
6963 bool is_signed
= !extract32(insn
, 7, 1);
6964 TCGv_ptr fpst
= get_fpstatus_ptr(1);
6965 TCGv_i32 tcg_rmode
, tcg_shift
;
6966 int rmode
= fp_decode_rm
[extract32(insn
, 8, 2)];
6968 tcg_shift
= tcg_const_i32(0);
6969 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6970 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6974 gen_helper_vfp_tosls(tmp
, tmp
,
6977 gen_helper_vfp_touls(tmp
, tmp
,
6981 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
6983 tcg_temp_free_i32(tcg_rmode
);
6984 tcg_temp_free_i32(tcg_shift
);
6985 tcg_temp_free_ptr(fpst
);
6988 case NEON_2RM_VRECPE
:
6990 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6991 gen_helper_recpe_u32(tmp
, tmp
, fpstatus
);
6992 tcg_temp_free_ptr(fpstatus
);
6995 case NEON_2RM_VRSQRTE
:
6997 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6998 gen_helper_rsqrte_u32(tmp
, tmp
, fpstatus
);
6999 tcg_temp_free_ptr(fpstatus
);
7002 case NEON_2RM_VRECPE_F
:
7004 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7005 gen_helper_recpe_f32(tmp
, tmp
, fpstatus
);
7006 tcg_temp_free_ptr(fpstatus
);
7009 case NEON_2RM_VRSQRTE_F
:
7011 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7012 gen_helper_rsqrte_f32(tmp
, tmp
, fpstatus
);
7013 tcg_temp_free_ptr(fpstatus
);
7016 case NEON_2RM_VCVT_FS
: /* VCVT.F32.S32 */
7018 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7019 gen_helper_vfp_sitos(tmp
, tmp
, fpstatus
);
7020 tcg_temp_free_ptr(fpstatus
);
7023 case NEON_2RM_VCVT_FU
: /* VCVT.F32.U32 */
7025 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7026 gen_helper_vfp_uitos(tmp
, tmp
, fpstatus
);
7027 tcg_temp_free_ptr(fpstatus
);
7030 case NEON_2RM_VCVT_SF
: /* VCVT.S32.F32 */
7032 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7033 gen_helper_vfp_tosizs(tmp
, tmp
, fpstatus
);
7034 tcg_temp_free_ptr(fpstatus
);
7037 case NEON_2RM_VCVT_UF
: /* VCVT.U32.F32 */
7039 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7040 gen_helper_vfp_touizs(tmp
, tmp
, fpstatus
);
7041 tcg_temp_free_ptr(fpstatus
);
7045 /* Reserved op values were caught by the
7046 * neon_2rm_sizes[] check earlier.
7050 neon_store_reg(rd
, pass
, tmp
);
7054 } else if ((insn
& (1 << 10)) == 0) {
7056 int n
= ((insn
>> 8) & 3) + 1;
7057 if ((rn
+ n
) > 32) {
7058 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
7059 * helper function running off the end of the register file.
7064 if (insn
& (1 << 6)) {
7065 tmp
= neon_load_reg(rd
, 0);
7067 tmp
= tcg_temp_new_i32();
7068 tcg_gen_movi_i32(tmp
, 0);
7070 tmp2
= neon_load_reg(rm
, 0);
7071 ptr1
= vfp_reg_ptr(true, rn
);
7072 tmp5
= tcg_const_i32(n
);
7073 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, ptr1
, tmp5
);
7074 tcg_temp_free_i32(tmp
);
7075 if (insn
& (1 << 6)) {
7076 tmp
= neon_load_reg(rd
, 1);
7078 tmp
= tcg_temp_new_i32();
7079 tcg_gen_movi_i32(tmp
, 0);
7081 tmp3
= neon_load_reg(rm
, 1);
7082 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, ptr1
, tmp5
);
7083 tcg_temp_free_i32(tmp5
);
7084 tcg_temp_free_ptr(ptr1
);
7085 neon_store_reg(rd
, 0, tmp2
);
7086 neon_store_reg(rd
, 1, tmp3
);
7087 tcg_temp_free_i32(tmp
);
7088 } else if ((insn
& 0x380) == 0) {
7093 if ((insn
& (7 << 16)) == 0 || (q
&& (rd
& 1))) {
7096 if (insn
& (1 << 16)) {
7098 element
= (insn
>> 17) & 7;
7099 } else if (insn
& (1 << 17)) {
7101 element
= (insn
>> 18) & 3;
7104 element
= (insn
>> 19) & 1;
7106 tcg_gen_gvec_dup_mem(size
, neon_reg_offset(rd
, 0),
7107 neon_element_offset(rm
, element
, size
),
7108 q
? 16 : 8, q
? 16 : 8);
7117 static int disas_coproc_insn(DisasContext
*s
, uint32_t insn
)
7119 int cpnum
, is64
, crn
, crm
, opc1
, opc2
, isread
, rt
, rt2
;
7120 const ARMCPRegInfo
*ri
;
7122 cpnum
= (insn
>> 8) & 0xf;
7124 /* First check for coprocessor space used for XScale/iwMMXt insns */
7125 if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && (cpnum
< 2)) {
7126 if (extract32(s
->c15_cpar
, cpnum
, 1) == 0) {
7129 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
7130 return disas_iwmmxt_insn(s
, insn
);
7131 } else if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
)) {
7132 return disas_dsp_insn(s
, insn
);
7137 /* Otherwise treat as a generic register access */
7138 is64
= (insn
& (1 << 25)) == 0;
7139 if (!is64
&& ((insn
& (1 << 4)) == 0)) {
7147 opc1
= (insn
>> 4) & 0xf;
7149 rt2
= (insn
>> 16) & 0xf;
7151 crn
= (insn
>> 16) & 0xf;
7152 opc1
= (insn
>> 21) & 7;
7153 opc2
= (insn
>> 5) & 7;
7156 isread
= (insn
>> 20) & 1;
7157 rt
= (insn
>> 12) & 0xf;
7159 ri
= get_arm_cp_reginfo(s
->cp_regs
,
7160 ENCODE_CP_REG(cpnum
, is64
, s
->ns
, crn
, crm
, opc1
, opc2
));
7164 /* Check access permissions */
7165 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
7169 if (s
->hstr_active
|| ri
->accessfn
||
7170 (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && cpnum
< 14)) {
7171 /* Emit code to perform further access permissions checks at
7172 * runtime; this may result in an exception.
7173 * Note that on XScale all cp0..c13 registers do an access check
7174 * call in order to handle c15_cpar.
7177 TCGv_i32 tcg_syn
, tcg_isread
;
7180 /* Note that since we are an implementation which takes an
7181 * exception on a trapped conditional instruction only if the
7182 * instruction passes its condition code check, we can take
7183 * advantage of the clause in the ARM ARM that allows us to set
7184 * the COND field in the instruction to 0xE in all cases.
7185 * We could fish the actual condition out of the insn (ARM)
7186 * or the condexec bits (Thumb) but it isn't necessary.
7191 syndrome
= syn_cp14_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
7194 syndrome
= syn_cp14_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
7200 syndrome
= syn_cp15_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
7203 syndrome
= syn_cp15_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
7208 /* ARMv8 defines that only coprocessors 14 and 15 exist,
7209 * so this can only happen if this is an ARMv7 or earlier CPU,
7210 * in which case the syndrome information won't actually be
7213 assert(!arm_dc_feature(s
, ARM_FEATURE_V8
));
7214 syndrome
= syn_uncategorized();
7218 gen_set_condexec(s
);
7219 gen_set_pc_im(s
, s
->pc_curr
);
7220 tmpptr
= tcg_const_ptr(ri
);
7221 tcg_syn
= tcg_const_i32(syndrome
);
7222 tcg_isread
= tcg_const_i32(isread
);
7223 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
,
7225 tcg_temp_free_ptr(tmpptr
);
7226 tcg_temp_free_i32(tcg_syn
);
7227 tcg_temp_free_i32(tcg_isread
);
7228 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
7230 * The readfn or writefn might raise an exception;
7231 * synchronize the CPU state in case it does.
7233 gen_set_condexec(s
);
7234 gen_set_pc_im(s
, s
->pc_curr
);
7237 /* Handle special cases first */
7238 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
7245 gen_set_pc_im(s
, s
->base
.pc_next
);
7246 s
->base
.is_jmp
= DISAS_WFI
;
7252 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
7261 if (ri
->type
& ARM_CP_CONST
) {
7262 tmp64
= tcg_const_i64(ri
->resetvalue
);
7263 } else if (ri
->readfn
) {
7265 tmp64
= tcg_temp_new_i64();
7266 tmpptr
= tcg_const_ptr(ri
);
7267 gen_helper_get_cp_reg64(tmp64
, cpu_env
, tmpptr
);
7268 tcg_temp_free_ptr(tmpptr
);
7270 tmp64
= tcg_temp_new_i64();
7271 tcg_gen_ld_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
7273 tmp
= tcg_temp_new_i32();
7274 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
7275 store_reg(s
, rt
, tmp
);
7276 tmp
= tcg_temp_new_i32();
7277 tcg_gen_extrh_i64_i32(tmp
, tmp64
);
7278 tcg_temp_free_i64(tmp64
);
7279 store_reg(s
, rt2
, tmp
);
7282 if (ri
->type
& ARM_CP_CONST
) {
7283 tmp
= tcg_const_i32(ri
->resetvalue
);
7284 } else if (ri
->readfn
) {
7286 tmp
= tcg_temp_new_i32();
7287 tmpptr
= tcg_const_ptr(ri
);
7288 gen_helper_get_cp_reg(tmp
, cpu_env
, tmpptr
);
7289 tcg_temp_free_ptr(tmpptr
);
7291 tmp
= load_cpu_offset(ri
->fieldoffset
);
7294 /* Destination register of r15 for 32 bit loads sets
7295 * the condition codes from the high 4 bits of the value
7298 tcg_temp_free_i32(tmp
);
7300 store_reg(s
, rt
, tmp
);
7305 if (ri
->type
& ARM_CP_CONST
) {
7306 /* If not forbidden by access permissions, treat as WI */
7311 TCGv_i32 tmplo
, tmphi
;
7312 TCGv_i64 tmp64
= tcg_temp_new_i64();
7313 tmplo
= load_reg(s
, rt
);
7314 tmphi
= load_reg(s
, rt2
);
7315 tcg_gen_concat_i32_i64(tmp64
, tmplo
, tmphi
);
7316 tcg_temp_free_i32(tmplo
);
7317 tcg_temp_free_i32(tmphi
);
7319 TCGv_ptr tmpptr
= tcg_const_ptr(ri
);
7320 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tmp64
);
7321 tcg_temp_free_ptr(tmpptr
);
7323 tcg_gen_st_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
7325 tcg_temp_free_i64(tmp64
);
7330 tmp
= load_reg(s
, rt
);
7331 tmpptr
= tcg_const_ptr(ri
);
7332 gen_helper_set_cp_reg(cpu_env
, tmpptr
, tmp
);
7333 tcg_temp_free_ptr(tmpptr
);
7334 tcg_temp_free_i32(tmp
);
7336 TCGv_i32 tmp
= load_reg(s
, rt
);
7337 store_cpu_offset(tmp
, ri
->fieldoffset
);
7342 /* I/O operations must end the TB here (whether read or write) */
7343 need_exit_tb
= ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) &&
7344 (ri
->type
& ARM_CP_IO
));
7346 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
7348 * A write to any coprocessor register that ends a TB
7349 * must rebuild the hflags for the next TB.
7351 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
7352 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
7353 gen_helper_rebuild_hflags_m32(cpu_env
, tcg_el
);
7355 if (ri
->type
& ARM_CP_NEWEL
) {
7356 gen_helper_rebuild_hflags_a32_newel(cpu_env
);
7358 gen_helper_rebuild_hflags_a32(cpu_env
, tcg_el
);
7361 tcg_temp_free_i32(tcg_el
);
7363 * We default to ending the TB on a coprocessor register write,
7364 * but allow this to be suppressed by the register definition
7365 * (usually only necessary to work around guest bugs).
7367 need_exit_tb
= true;
7376 /* Unknown register; this might be a guest error or a QEMU
7377 * unimplemented feature.
7380 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
7381 "64 bit system register cp:%d opc1: %d crm:%d "
7383 isread
? "read" : "write", cpnum
, opc1
, crm
,
7384 s
->ns
? "non-secure" : "secure");
7386 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
7387 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
7389 isread
? "read" : "write", cpnum
, opc1
, crn
, crm
, opc2
,
7390 s
->ns
? "non-secure" : "secure");
7397 /* Store a 64-bit value to a register pair. Clobbers val. */
7398 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
7401 tmp
= tcg_temp_new_i32();
7402 tcg_gen_extrl_i64_i32(tmp
, val
);
7403 store_reg(s
, rlow
, tmp
);
7404 tmp
= tcg_temp_new_i32();
7405 tcg_gen_extrh_i64_i32(tmp
, val
);
7406 store_reg(s
, rhigh
, tmp
);
7409 /* load and add a 64-bit value from a register pair. */
7410 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
7416 /* Load 64-bit value rd:rn. */
7417 tmpl
= load_reg(s
, rlow
);
7418 tmph
= load_reg(s
, rhigh
);
7419 tmp
= tcg_temp_new_i64();
7420 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
7421 tcg_temp_free_i32(tmpl
);
7422 tcg_temp_free_i32(tmph
);
7423 tcg_gen_add_i64(val
, val
, tmp
);
7424 tcg_temp_free_i64(tmp
);
7427 /* Set N and Z flags from hi|lo. */
7428 static void gen_logicq_cc(TCGv_i32 lo
, TCGv_i32 hi
)
7430 tcg_gen_mov_i32(cpu_NF
, hi
);
7431 tcg_gen_or_i32(cpu_ZF
, lo
, hi
);
7434 /* Load/Store exclusive instructions are implemented by remembering
7435 the value/address loaded, and seeing if these are the same
7436 when the store is performed. This should be sufficient to implement
7437 the architecturally mandated semantics, and avoids having to monitor
7438 regular stores. The compare vs the remembered value is done during
7439 the cmpxchg operation, but we must compare the addresses manually. */
7440 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
7441 TCGv_i32 addr
, int size
)
7443 TCGv_i32 tmp
= tcg_temp_new_i32();
7444 MemOp opc
= size
| MO_ALIGN
| s
->be_data
;
7449 TCGv_i32 tmp2
= tcg_temp_new_i32();
7450 TCGv_i64 t64
= tcg_temp_new_i64();
7452 /* For AArch32, architecturally the 32-bit word at the lowest
7453 * address is always Rt and the one at addr+4 is Rt2, even if
7454 * the CPU is big-endian. That means we don't want to do a
7455 * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if
7456 * for an architecturally 64-bit access, but instead do a
7457 * 64-bit access using MO_BE if appropriate and then split
7459 * This only makes a difference for BE32 user-mode, where
7460 * frob64() must not flip the two halves of the 64-bit data
7461 * but this code must treat BE32 user-mode like BE32 system.
7463 TCGv taddr
= gen_aa32_addr(s
, addr
, opc
);
7465 tcg_gen_qemu_ld_i64(t64
, taddr
, get_mem_index(s
), opc
);
7466 tcg_temp_free(taddr
);
7467 tcg_gen_mov_i64(cpu_exclusive_val
, t64
);
7468 if (s
->be_data
== MO_BE
) {
7469 tcg_gen_extr_i64_i32(tmp2
, tmp
, t64
);
7471 tcg_gen_extr_i64_i32(tmp
, tmp2
, t64
);
7473 tcg_temp_free_i64(t64
);
7475 store_reg(s
, rt2
, tmp2
);
7477 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), opc
);
7478 tcg_gen_extu_i32_i64(cpu_exclusive_val
, tmp
);
7481 store_reg(s
, rt
, tmp
);
7482 tcg_gen_extu_i32_i64(cpu_exclusive_addr
, addr
);
7485 static void gen_clrex(DisasContext
*s
)
7487 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7490 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
7491 TCGv_i32 addr
, int size
)
7493 TCGv_i32 t0
, t1
, t2
;
7496 TCGLabel
*done_label
;
7497 TCGLabel
*fail_label
;
7498 MemOp opc
= size
| MO_ALIGN
| s
->be_data
;
7500 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
7506 fail_label
= gen_new_label();
7507 done_label
= gen_new_label();
7508 extaddr
= tcg_temp_new_i64();
7509 tcg_gen_extu_i32_i64(extaddr
, addr
);
7510 tcg_gen_brcond_i64(TCG_COND_NE
, extaddr
, cpu_exclusive_addr
, fail_label
);
7511 tcg_temp_free_i64(extaddr
);
7513 taddr
= gen_aa32_addr(s
, addr
, opc
);
7514 t0
= tcg_temp_new_i32();
7515 t1
= load_reg(s
, rt
);
7517 TCGv_i64 o64
= tcg_temp_new_i64();
7518 TCGv_i64 n64
= tcg_temp_new_i64();
7520 t2
= load_reg(s
, rt2
);
7521 /* For AArch32, architecturally the 32-bit word at the lowest
7522 * address is always Rt and the one at addr+4 is Rt2, even if
7523 * the CPU is big-endian. Since we're going to treat this as a
7524 * single 64-bit BE store, we need to put the two halves in the
7525 * opposite order for BE to LE, so that they end up in the right
7527 * We don't want gen_aa32_frob64() because that does the wrong
7528 * thing for BE32 usermode.
7530 if (s
->be_data
== MO_BE
) {
7531 tcg_gen_concat_i32_i64(n64
, t2
, t1
);
7533 tcg_gen_concat_i32_i64(n64
, t1
, t2
);
7535 tcg_temp_free_i32(t2
);
7537 tcg_gen_atomic_cmpxchg_i64(o64
, taddr
, cpu_exclusive_val
, n64
,
7538 get_mem_index(s
), opc
);
7539 tcg_temp_free_i64(n64
);
7541 tcg_gen_setcond_i64(TCG_COND_NE
, o64
, o64
, cpu_exclusive_val
);
7542 tcg_gen_extrl_i64_i32(t0
, o64
);
7544 tcg_temp_free_i64(o64
);
7546 t2
= tcg_temp_new_i32();
7547 tcg_gen_extrl_i64_i32(t2
, cpu_exclusive_val
);
7548 tcg_gen_atomic_cmpxchg_i32(t0
, taddr
, t2
, t1
, get_mem_index(s
), opc
);
7549 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t2
);
7550 tcg_temp_free_i32(t2
);
7552 tcg_temp_free_i32(t1
);
7553 tcg_temp_free(taddr
);
7554 tcg_gen_mov_i32(cpu_R
[rd
], t0
);
7555 tcg_temp_free_i32(t0
);
7556 tcg_gen_br(done_label
);
7558 gen_set_label(fail_label
);
7559 tcg_gen_movi_i32(cpu_R
[rd
], 1);
7560 gen_set_label(done_label
);
7561 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
7567 * @mode: mode field from insn (which stack to store to)
7568 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
7569 * @writeback: true if writeback bit set
7571 * Generate code for the SRS (Store Return State) insn.
7573 static void gen_srs(DisasContext
*s
,
7574 uint32_t mode
, uint32_t amode
, bool writeback
)
7581 * - trapped to EL3 if EL3 is AArch64 and we are at Secure EL1
7582 * and specified mode is monitor mode
7583 * - UNDEFINED in Hyp mode
7584 * - UNPREDICTABLE in User or System mode
7585 * - UNPREDICTABLE if the specified mode is:
7586 * -- not implemented
7587 * -- not a valid mode number
7588 * -- a mode that's at a higher exception level
7589 * -- Monitor, if we are Non-secure
7590 * For the UNPREDICTABLE cases we choose to UNDEF.
7592 if (s
->current_el
== 1 && !s
->ns
&& mode
== ARM_CPU_MODE_MON
) {
7593 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(), 3);
7597 if (s
->current_el
== 0 || s
->current_el
== 2) {
7602 case ARM_CPU_MODE_USR
:
7603 case ARM_CPU_MODE_FIQ
:
7604 case ARM_CPU_MODE_IRQ
:
7605 case ARM_CPU_MODE_SVC
:
7606 case ARM_CPU_MODE_ABT
:
7607 case ARM_CPU_MODE_UND
:
7608 case ARM_CPU_MODE_SYS
:
7610 case ARM_CPU_MODE_HYP
:
7611 if (s
->current_el
== 1 || !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
7615 case ARM_CPU_MODE_MON
:
7616 /* No need to check specifically for "are we non-secure" because
7617 * we've already made EL0 UNDEF and handled the trap for S-EL1;
7618 * so if this isn't EL3 then we must be non-secure.
7620 if (s
->current_el
!= 3) {
7629 unallocated_encoding(s
);
7633 addr
= tcg_temp_new_i32();
7634 tmp
= tcg_const_i32(mode
);
7635 /* get_r13_banked() will raise an exception if called from System mode */
7636 gen_set_condexec(s
);
7637 gen_set_pc_im(s
, s
->pc_curr
);
7638 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7639 tcg_temp_free_i32(tmp
);
7656 tcg_gen_addi_i32(addr
, addr
, offset
);
7657 tmp
= load_reg(s
, 14);
7658 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
7659 tcg_temp_free_i32(tmp
);
7660 tmp
= load_cpu_field(spsr
);
7661 tcg_gen_addi_i32(addr
, addr
, 4);
7662 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
7663 tcg_temp_free_i32(tmp
);
7681 tcg_gen_addi_i32(addr
, addr
, offset
);
7682 tmp
= tcg_const_i32(mode
);
7683 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
7684 tcg_temp_free_i32(tmp
);
7686 tcg_temp_free_i32(addr
);
7687 s
->base
.is_jmp
= DISAS_UPDATE
;
7690 /* Generate a label used for skipping this instruction */
7691 static void arm_gen_condlabel(DisasContext
*s
)
7694 s
->condlabel
= gen_new_label();
7699 /* Skip this instruction if the ARM condition is false */
7700 static void arm_skip_unless(DisasContext
*s
, uint32_t cond
)
7702 arm_gen_condlabel(s
);
7703 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
7708 * Constant expanders for the decoders.
7711 static int negate(DisasContext
*s
, int x
)
7716 static int plus_2(DisasContext
*s
, int x
)
7721 static int times_2(DisasContext
*s
, int x
)
7726 static int times_4(DisasContext
*s
, int x
)
7731 /* Return only the rotation part of T32ExpandImm. */
7732 static int t32_expandimm_rot(DisasContext
*s
, int x
)
7734 return x
& 0xc00 ? extract32(x
, 7, 5) : 0;
7737 /* Return the unrotated immediate from T32ExpandImm. */
7738 static int t32_expandimm_imm(DisasContext
*s
, int x
)
7740 int imm
= extract32(x
, 0, 8);
7742 switch (extract32(x
, 8, 4)) {
7744 /* Nothing to do. */
7746 case 1: /* 00XY00XY */
7749 case 2: /* XY00XY00 */
7752 case 3: /* XYXYXYXY */
7756 /* Rotated constant. */
7763 static int t32_branch24(DisasContext
*s
, int x
)
7765 /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */
7766 x
^= !(x
< 0) * (3 << 21);
7767 /* Append the final zero. */
7771 static int t16_setflags(DisasContext
*s
)
7773 return s
->condexec_mask
== 0;
7776 static int t16_push_list(DisasContext
*s
, int x
)
7778 return (x
& 0xff) | (x
& 0x100) << (14 - 8);
7781 static int t16_pop_list(DisasContext
*s
, int x
)
7783 return (x
& 0xff) | (x
& 0x100) << (15 - 8);
7787 * Include the generated decoders.
7790 #include "decode-a32.inc.c"
7791 #include "decode-a32-uncond.inc.c"
7792 #include "decode-t32.inc.c"
7793 #include "decode-t16.inc.c"
7795 /* Helpers to swap operands for reverse-subtract. */
7796 static void gen_rsb(TCGv_i32 dst
, TCGv_i32 a
, TCGv_i32 b
)
7798 tcg_gen_sub_i32(dst
, b
, a
);
7801 static void gen_rsb_CC(TCGv_i32 dst
, TCGv_i32 a
, TCGv_i32 b
)
7803 gen_sub_CC(dst
, b
, a
);
7806 static void gen_rsc(TCGv_i32 dest
, TCGv_i32 a
, TCGv_i32 b
)
7808 gen_sub_carry(dest
, b
, a
);
7811 static void gen_rsc_CC(TCGv_i32 dest
, TCGv_i32 a
, TCGv_i32 b
)
7813 gen_sbc_CC(dest
, b
, a
);
7817 * Helpers for the data processing routines.
7819 * After the computation store the results back.
7820 * This may be suppressed altogether (STREG_NONE), require a runtime
7821 * check against the stack limits (STREG_SP_CHECK), or generate an
7822 * exception return. Oh, or store into a register.
7824 * Always return true, indicating success for a trans_* function.
7833 static bool store_reg_kind(DisasContext
*s
, int rd
,
7834 TCGv_i32 val
, StoreRegKind kind
)
7838 tcg_temp_free_i32(val
);
7841 /* See ALUWritePC: Interworking only from a32 mode. */
7843 store_reg(s
, rd
, val
);
7845 store_reg_bx(s
, rd
, val
);
7848 case STREG_SP_CHECK
:
7849 store_sp_checked(s
, val
);
7852 gen_exception_return(s
, val
);
7855 g_assert_not_reached();
7859 * Data Processing (register)
7861 * Operate, with set flags, one register source,
7862 * one immediate shifted register source, and a destination.
7864 static bool op_s_rrr_shi(DisasContext
*s
, arg_s_rrr_shi
*a
,
7865 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
),
7866 int logic_cc
, StoreRegKind kind
)
7868 TCGv_i32 tmp1
, tmp2
;
7870 tmp2
= load_reg(s
, a
->rm
);
7871 gen_arm_shift_im(tmp2
, a
->shty
, a
->shim
, logic_cc
);
7872 tmp1
= load_reg(s
, a
->rn
);
7874 gen(tmp1
, tmp1
, tmp2
);
7875 tcg_temp_free_i32(tmp2
);
7880 return store_reg_kind(s
, a
->rd
, tmp1
, kind
);
7883 static bool op_s_rxr_shi(DisasContext
*s
, arg_s_rrr_shi
*a
,
7884 void (*gen
)(TCGv_i32
, TCGv_i32
),
7885 int logic_cc
, StoreRegKind kind
)
7889 tmp
= load_reg(s
, a
->rm
);
7890 gen_arm_shift_im(tmp
, a
->shty
, a
->shim
, logic_cc
);
7896 return store_reg_kind(s
, a
->rd
, tmp
, kind
);
7900 * Data-processing (register-shifted register)
7902 * Operate, with set flags, one register source,
7903 * one register shifted register source, and a destination.
7905 static bool op_s_rrr_shr(DisasContext
*s
, arg_s_rrr_shr
*a
,
7906 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
),
7907 int logic_cc
, StoreRegKind kind
)
7909 TCGv_i32 tmp1
, tmp2
;
7911 tmp1
= load_reg(s
, a
->rs
);
7912 tmp2
= load_reg(s
, a
->rm
);
7913 gen_arm_shift_reg(tmp2
, a
->shty
, tmp1
, logic_cc
);
7914 tmp1
= load_reg(s
, a
->rn
);
7916 gen(tmp1
, tmp1
, tmp2
);
7917 tcg_temp_free_i32(tmp2
);
7922 return store_reg_kind(s
, a
->rd
, tmp1
, kind
);
7925 static bool op_s_rxr_shr(DisasContext
*s
, arg_s_rrr_shr
*a
,
7926 void (*gen
)(TCGv_i32
, TCGv_i32
),
7927 int logic_cc
, StoreRegKind kind
)
7929 TCGv_i32 tmp1
, tmp2
;
7931 tmp1
= load_reg(s
, a
->rs
);
7932 tmp2
= load_reg(s
, a
->rm
);
7933 gen_arm_shift_reg(tmp2
, a
->shty
, tmp1
, logic_cc
);
7939 return store_reg_kind(s
, a
->rd
, tmp2
, kind
);
7943 * Data-processing (immediate)
7945 * Operate, with set flags, one register source,
7946 * one rotated immediate, and a destination.
7948 * Note that logic_cc && a->rot setting CF based on the msb of the
7949 * immediate is the reason why we must pass in the unrotated form
7952 static bool op_s_rri_rot(DisasContext
*s
, arg_s_rri_rot
*a
,
7953 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
),
7954 int logic_cc
, StoreRegKind kind
)
7956 TCGv_i32 tmp1
, tmp2
;
7959 imm
= ror32(a
->imm
, a
->rot
);
7960 if (logic_cc
&& a
->rot
) {
7961 tcg_gen_movi_i32(cpu_CF
, imm
>> 31);
7963 tmp2
= tcg_const_i32(imm
);
7964 tmp1
= load_reg(s
, a
->rn
);
7966 gen(tmp1
, tmp1
, tmp2
);
7967 tcg_temp_free_i32(tmp2
);
7972 return store_reg_kind(s
, a
->rd
, tmp1
, kind
);
7975 static bool op_s_rxi_rot(DisasContext
*s
, arg_s_rri_rot
*a
,
7976 void (*gen
)(TCGv_i32
, TCGv_i32
),
7977 int logic_cc
, StoreRegKind kind
)
7982 imm
= ror32(a
->imm
, a
->rot
);
7983 if (logic_cc
&& a
->rot
) {
7984 tcg_gen_movi_i32(cpu_CF
, imm
>> 31);
7986 tmp
= tcg_const_i32(imm
);
7992 return store_reg_kind(s
, a
->rd
, tmp
, kind
);
7995 #define DO_ANY3(NAME, OP, L, K) \
7996 static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \
7997 { StoreRegKind k = (K); return op_s_rrr_shi(s, a, OP, L, k); } \
7998 static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \
7999 { StoreRegKind k = (K); return op_s_rrr_shr(s, a, OP, L, k); } \
8000 static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \
8001 { StoreRegKind k = (K); return op_s_rri_rot(s, a, OP, L, k); }
8003 #define DO_ANY2(NAME, OP, L, K) \
8004 static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \
8005 { StoreRegKind k = (K); return op_s_rxr_shi(s, a, OP, L, k); } \
8006 static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \
8007 { StoreRegKind k = (K); return op_s_rxr_shr(s, a, OP, L, k); } \
8008 static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \
8009 { StoreRegKind k = (K); return op_s_rxi_rot(s, a, OP, L, k); }
8011 #define DO_CMP2(NAME, OP, L) \
8012 static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \
8013 { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \
8014 static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \
8015 { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \
8016 static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \
8017 { return op_s_rri_rot(s, a, OP, L, STREG_NONE); }
8019 DO_ANY3(AND
, tcg_gen_and_i32
, a
->s
, STREG_NORMAL
)
8020 DO_ANY3(EOR
, tcg_gen_xor_i32
, a
->s
, STREG_NORMAL
)
8021 DO_ANY3(ORR
, tcg_gen_or_i32
, a
->s
, STREG_NORMAL
)
8022 DO_ANY3(BIC
, tcg_gen_andc_i32
, a
->s
, STREG_NORMAL
)
8024 DO_ANY3(RSB
, a
->s
? gen_rsb_CC
: gen_rsb
, false, STREG_NORMAL
)
8025 DO_ANY3(ADC
, a
->s
? gen_adc_CC
: gen_add_carry
, false, STREG_NORMAL
)
8026 DO_ANY3(SBC
, a
->s
? gen_sbc_CC
: gen_sub_carry
, false, STREG_NORMAL
)
8027 DO_ANY3(RSC
, a
->s
? gen_rsc_CC
: gen_rsc
, false, STREG_NORMAL
)
8029 DO_CMP2(TST
, tcg_gen_and_i32
, true)
8030 DO_CMP2(TEQ
, tcg_gen_xor_i32
, true)
8031 DO_CMP2(CMN
, gen_add_CC
, false)
8032 DO_CMP2(CMP
, gen_sub_CC
, false)
8034 DO_ANY3(ADD
, a
->s
? gen_add_CC
: tcg_gen_add_i32
, false,
8035 a
->rd
== 13 && a
->rn
== 13 ? STREG_SP_CHECK
: STREG_NORMAL
)
8038 * Note for the computation of StoreRegKind we return out of the
8039 * middle of the functions that are expanded by DO_ANY3, and that
8040 * we modify a->s via that parameter before it is used by OP.
8042 DO_ANY3(SUB
, a
->s
? gen_sub_CC
: tcg_gen_sub_i32
, false,
8044 StoreRegKind ret
= STREG_NORMAL
;
8045 if (a
->rd
== 15 && a
->s
) {
8047 * See ALUExceptionReturn:
8048 * In User mode, UNPREDICTABLE; we choose UNDEF.
8049 * In Hyp mode, UNDEFINED.
8051 if (IS_USER(s
) || s
->current_el
== 2) {
8052 unallocated_encoding(s
);
8055 /* There is no writeback of nzcv to PSTATE. */
8057 ret
= STREG_EXC_RET
;
8058 } else if (a
->rd
== 13 && a
->rn
== 13) {
8059 ret
= STREG_SP_CHECK
;
8064 DO_ANY2(MOV
, tcg_gen_mov_i32
, a
->s
,
8066 StoreRegKind ret
= STREG_NORMAL
;
8067 if (a
->rd
== 15 && a
->s
) {
8069 * See ALUExceptionReturn:
8070 * In User mode, UNPREDICTABLE; we choose UNDEF.
8071 * In Hyp mode, UNDEFINED.
8073 if (IS_USER(s
) || s
->current_el
== 2) {
8074 unallocated_encoding(s
);
8077 /* There is no writeback of nzcv to PSTATE. */
8079 ret
= STREG_EXC_RET
;
8080 } else if (a
->rd
== 13) {
8081 ret
= STREG_SP_CHECK
;
8086 DO_ANY2(MVN
, tcg_gen_not_i32
, a
->s
, STREG_NORMAL
)
8089 * ORN is only available with T32, so there is no register-shifted-register
8090 * form of the insn. Using the DO_ANY3 macro would create an unused function.
8092 static bool trans_ORN_rrri(DisasContext
*s
, arg_s_rrr_shi
*a
)
8094 return op_s_rrr_shi(s
, a
, tcg_gen_orc_i32
, a
->s
, STREG_NORMAL
);
8097 static bool trans_ORN_rri(DisasContext
*s
, arg_s_rri_rot
*a
)
8099 return op_s_rri_rot(s
, a
, tcg_gen_orc_i32
, a
->s
, STREG_NORMAL
);
8106 static bool trans_ADR(DisasContext
*s
, arg_ri
*a
)
8108 store_reg_bx(s
, a
->rd
, add_reg_for_lit(s
, 15, a
->imm
));
8112 static bool trans_MOVW(DisasContext
*s
, arg_MOVW
*a
)
8116 if (!ENABLE_ARCH_6T2
) {
8120 tmp
= tcg_const_i32(a
->imm
);
8121 store_reg(s
, a
->rd
, tmp
);
8125 static bool trans_MOVT(DisasContext
*s
, arg_MOVW
*a
)
8129 if (!ENABLE_ARCH_6T2
) {
8133 tmp
= load_reg(s
, a
->rd
);
8134 tcg_gen_ext16u_i32(tmp
, tmp
);
8135 tcg_gen_ori_i32(tmp
, tmp
, a
->imm
<< 16);
8136 store_reg(s
, a
->rd
, tmp
);
8141 * Multiply and multiply accumulate
8144 static bool op_mla(DisasContext
*s
, arg_s_rrrr
*a
, bool add
)
8148 t1
= load_reg(s
, a
->rn
);
8149 t2
= load_reg(s
, a
->rm
);
8150 tcg_gen_mul_i32(t1
, t1
, t2
);
8151 tcg_temp_free_i32(t2
);
8153 t2
= load_reg(s
, a
->ra
);
8154 tcg_gen_add_i32(t1
, t1
, t2
);
8155 tcg_temp_free_i32(t2
);
8160 store_reg(s
, a
->rd
, t1
);
8164 static bool trans_MUL(DisasContext
*s
, arg_MUL
*a
)
8166 return op_mla(s
, a
, false);
8169 static bool trans_MLA(DisasContext
*s
, arg_MLA
*a
)
8171 return op_mla(s
, a
, true);
8174 static bool trans_MLS(DisasContext
*s
, arg_MLS
*a
)
8178 if (!ENABLE_ARCH_6T2
) {
8181 t1
= load_reg(s
, a
->rn
);
8182 t2
= load_reg(s
, a
->rm
);
8183 tcg_gen_mul_i32(t1
, t1
, t2
);
8184 tcg_temp_free_i32(t2
);
8185 t2
= load_reg(s
, a
->ra
);
8186 tcg_gen_sub_i32(t1
, t2
, t1
);
8187 tcg_temp_free_i32(t2
);
8188 store_reg(s
, a
->rd
, t1
);
8192 static bool op_mlal(DisasContext
*s
, arg_s_rrrr
*a
, bool uns
, bool add
)
8194 TCGv_i32 t0
, t1
, t2
, t3
;
8196 t0
= load_reg(s
, a
->rm
);
8197 t1
= load_reg(s
, a
->rn
);
8199 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
8201 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
8204 t2
= load_reg(s
, a
->ra
);
8205 t3
= load_reg(s
, a
->rd
);
8206 tcg_gen_add2_i32(t0
, t1
, t0
, t1
, t2
, t3
);
8207 tcg_temp_free_i32(t2
);
8208 tcg_temp_free_i32(t3
);
8211 gen_logicq_cc(t0
, t1
);
8213 store_reg(s
, a
->ra
, t0
);
8214 store_reg(s
, a
->rd
, t1
);
8218 static bool trans_UMULL(DisasContext
*s
, arg_UMULL
*a
)
8220 return op_mlal(s
, a
, true, false);
8223 static bool trans_SMULL(DisasContext
*s
, arg_SMULL
*a
)
8225 return op_mlal(s
, a
, false, false);
8228 static bool trans_UMLAL(DisasContext
*s
, arg_UMLAL
*a
)
8230 return op_mlal(s
, a
, true, true);
8233 static bool trans_SMLAL(DisasContext
*s
, arg_SMLAL
*a
)
8235 return op_mlal(s
, a
, false, true);
8238 static bool trans_UMAAL(DisasContext
*s
, arg_UMAAL
*a
)
8240 TCGv_i32 t0
, t1
, t2
, zero
;
8243 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
8248 t0
= load_reg(s
, a
->rm
);
8249 t1
= load_reg(s
, a
->rn
);
8250 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
8251 zero
= tcg_const_i32(0);
8252 t2
= load_reg(s
, a
->ra
);
8253 tcg_gen_add2_i32(t0
, t1
, t0
, t1
, t2
, zero
);
8254 tcg_temp_free_i32(t2
);
8255 t2
= load_reg(s
, a
->rd
);
8256 tcg_gen_add2_i32(t0
, t1
, t0
, t1
, t2
, zero
);
8257 tcg_temp_free_i32(t2
);
8258 tcg_temp_free_i32(zero
);
8259 store_reg(s
, a
->ra
, t0
);
8260 store_reg(s
, a
->rd
, t1
);
8265 * Saturating addition and subtraction
8268 static bool op_qaddsub(DisasContext
*s
, arg_rrr
*a
, bool add
, bool doub
)
8273 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
8274 : !ENABLE_ARCH_5TE
) {
8278 t0
= load_reg(s
, a
->rm
);
8279 t1
= load_reg(s
, a
->rn
);
8281 gen_helper_add_saturate(t1
, cpu_env
, t1
, t1
);
8284 gen_helper_add_saturate(t0
, cpu_env
, t0
, t1
);
8286 gen_helper_sub_saturate(t0
, cpu_env
, t0
, t1
);
8288 tcg_temp_free_i32(t1
);
8289 store_reg(s
, a
->rd
, t0
);
8293 #define DO_QADDSUB(NAME, ADD, DOUB) \
8294 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
8296 return op_qaddsub(s, a, ADD, DOUB); \
8299 DO_QADDSUB(QADD
, true, false)
8300 DO_QADDSUB(QSUB
, false, false)
8301 DO_QADDSUB(QDADD
, true, true)
8302 DO_QADDSUB(QDSUB
, false, true)
8307 * Halfword multiply and multiply accumulate
8310 static bool op_smlaxxx(DisasContext
*s
, arg_rrrr
*a
,
8311 int add_long
, bool nt
, bool mt
)
8313 TCGv_i32 t0
, t1
, tl
, th
;
8316 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
8317 : !ENABLE_ARCH_5TE
) {
8321 t0
= load_reg(s
, a
->rn
);
8322 t1
= load_reg(s
, a
->rm
);
8323 gen_mulxy(t0
, t1
, nt
, mt
);
8324 tcg_temp_free_i32(t1
);
8328 store_reg(s
, a
->rd
, t0
);
8331 t1
= load_reg(s
, a
->ra
);
8332 gen_helper_add_setq(t0
, cpu_env
, t0
, t1
);
8333 tcg_temp_free_i32(t1
);
8334 store_reg(s
, a
->rd
, t0
);
8337 tl
= load_reg(s
, a
->ra
);
8338 th
= load_reg(s
, a
->rd
);
8339 /* Sign-extend the 32-bit product to 64 bits. */
8340 t1
= tcg_temp_new_i32();
8341 tcg_gen_sari_i32(t1
, t0
, 31);
8342 tcg_gen_add2_i32(tl
, th
, tl
, th
, t0
, t1
);
8343 tcg_temp_free_i32(t0
);
8344 tcg_temp_free_i32(t1
);
8345 store_reg(s
, a
->ra
, tl
);
8346 store_reg(s
, a
->rd
, th
);
8349 g_assert_not_reached();
8354 #define DO_SMLAX(NAME, add, nt, mt) \
8355 static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
8357 return op_smlaxxx(s, a, add, nt, mt); \
8360 DO_SMLAX(SMULBB
, 0, 0, 0)
8361 DO_SMLAX(SMULBT
, 0, 0, 1)
8362 DO_SMLAX(SMULTB
, 0, 1, 0)
8363 DO_SMLAX(SMULTT
, 0, 1, 1)
8365 DO_SMLAX(SMLABB
, 1, 0, 0)
8366 DO_SMLAX(SMLABT
, 1, 0, 1)
8367 DO_SMLAX(SMLATB
, 1, 1, 0)
8368 DO_SMLAX(SMLATT
, 1, 1, 1)
8370 DO_SMLAX(SMLALBB
, 2, 0, 0)
8371 DO_SMLAX(SMLALBT
, 2, 0, 1)
8372 DO_SMLAX(SMLALTB
, 2, 1, 0)
8373 DO_SMLAX(SMLALTT
, 2, 1, 1)
8377 static bool op_smlawx(DisasContext
*s
, arg_rrrr
*a
, bool add
, bool mt
)
8381 if (!ENABLE_ARCH_5TE
) {
8385 t0
= load_reg(s
, a
->rn
);
8386 t1
= load_reg(s
, a
->rm
);
8388 * Since the nominal result is product<47:16>, shift the 16-bit
8389 * input up by 16 bits, so that the result is at product<63:32>.
8392 tcg_gen_andi_i32(t1
, t1
, 0xffff0000);
8394 tcg_gen_shli_i32(t1
, t1
, 16);
8396 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
8397 tcg_temp_free_i32(t0
);
8399 t0
= load_reg(s
, a
->ra
);
8400 gen_helper_add_setq(t1
, cpu_env
, t1
, t0
);
8401 tcg_temp_free_i32(t0
);
8403 store_reg(s
, a
->rd
, t1
);
8407 #define DO_SMLAWX(NAME, add, mt) \
8408 static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
8410 return op_smlawx(s, a, add, mt); \
8413 DO_SMLAWX(SMULWB
, 0, 0)
8414 DO_SMLAWX(SMULWT
, 0, 1)
8415 DO_SMLAWX(SMLAWB
, 1, 0)
8416 DO_SMLAWX(SMLAWT
, 1, 1)
8421 * MSR (immediate) and hints
8424 static bool trans_YIELD(DisasContext
*s
, arg_YIELD
*a
)
8427 * When running single-threaded TCG code, use the helper to ensure that
8428 * the next round-robin scheduled vCPU gets a crack. When running in
8429 * MTTCG we don't generate jumps to the helper as it won't affect the
8430 * scheduling of other vCPUs.
8432 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
8433 gen_set_pc_im(s
, s
->base
.pc_next
);
8434 s
->base
.is_jmp
= DISAS_YIELD
;
8439 static bool trans_WFE(DisasContext
*s
, arg_WFE
*a
)
8442 * When running single-threaded TCG code, use the helper to ensure that
8443 * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we
8444 * just skip this instruction. Currently the SEV/SEVL instructions,
8445 * which are *one* of many ways to wake the CPU from WFE, are not
8446 * implemented so we can't sleep like WFI does.
8448 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
8449 gen_set_pc_im(s
, s
->base
.pc_next
);
8450 s
->base
.is_jmp
= DISAS_WFE
;
8455 static bool trans_WFI(DisasContext
*s
, arg_WFI
*a
)
8457 /* For WFI, halt the vCPU until an IRQ. */
8458 gen_set_pc_im(s
, s
->base
.pc_next
);
8459 s
->base
.is_jmp
= DISAS_WFI
;
8463 static bool trans_NOP(DisasContext
*s
, arg_NOP
*a
)
8468 static bool trans_MSR_imm(DisasContext
*s
, arg_MSR_imm
*a
)
8470 uint32_t val
= ror32(a
->imm
, a
->rot
* 2);
8471 uint32_t mask
= msr_mask(s
, a
->mask
, a
->r
);
8473 if (gen_set_psr_im(s
, mask
, a
->r
, val
)) {
8474 unallocated_encoding(s
);
8480 * Cyclic Redundancy Check
8483 static bool op_crc32(DisasContext
*s
, arg_rrr
*a
, bool c
, MemOp sz
)
8485 TCGv_i32 t1
, t2
, t3
;
8487 if (!dc_isar_feature(aa32_crc32
, s
)) {
8491 t1
= load_reg(s
, a
->rn
);
8492 t2
= load_reg(s
, a
->rm
);
8503 g_assert_not_reached();
8505 t3
= tcg_const_i32(1 << sz
);
8507 gen_helper_crc32c(t1
, t1
, t2
, t3
);
8509 gen_helper_crc32(t1
, t1
, t2
, t3
);
8511 tcg_temp_free_i32(t2
);
8512 tcg_temp_free_i32(t3
);
8513 store_reg(s
, a
->rd
, t1
);
8517 #define DO_CRC32(NAME, c, sz) \
8518 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
8519 { return op_crc32(s, a, c, sz); }
8521 DO_CRC32(CRC32B
, false, MO_8
)
8522 DO_CRC32(CRC32H
, false, MO_16
)
8523 DO_CRC32(CRC32W
, false, MO_32
)
8524 DO_CRC32(CRC32CB
, true, MO_8
)
8525 DO_CRC32(CRC32CH
, true, MO_16
)
8526 DO_CRC32(CRC32CW
, true, MO_32
)
8531 * Miscellaneous instructions
8534 static bool trans_MRS_bank(DisasContext
*s
, arg_MRS_bank
*a
)
8536 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
8539 gen_mrs_banked(s
, a
->r
, a
->sysm
, a
->rd
);
8543 static bool trans_MSR_bank(DisasContext
*s
, arg_MSR_bank
*a
)
8545 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
8548 gen_msr_banked(s
, a
->r
, a
->sysm
, a
->rn
);
8552 static bool trans_MRS_reg(DisasContext
*s
, arg_MRS_reg
*a
)
8556 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
8561 unallocated_encoding(s
);
8564 tmp
= load_cpu_field(spsr
);
8566 tmp
= tcg_temp_new_i32();
8567 gen_helper_cpsr_read(tmp
, cpu_env
);
8569 store_reg(s
, a
->rd
, tmp
);
8573 static bool trans_MSR_reg(DisasContext
*s
, arg_MSR_reg
*a
)
8576 uint32_t mask
= msr_mask(s
, a
->mask
, a
->r
);
8578 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
8581 tmp
= load_reg(s
, a
->rn
);
8582 if (gen_set_psr(s
, mask
, a
->r
, tmp
)) {
8583 unallocated_encoding(s
);
8588 static bool trans_MRS_v7m(DisasContext
*s
, arg_MRS_v7m
*a
)
8592 if (!arm_dc_feature(s
, ARM_FEATURE_M
)) {
8595 tmp
= tcg_const_i32(a
->sysm
);
8596 gen_helper_v7m_mrs(tmp
, cpu_env
, tmp
);
8597 store_reg(s
, a
->rd
, tmp
);
8601 static bool trans_MSR_v7m(DisasContext
*s
, arg_MSR_v7m
*a
)
8605 if (!arm_dc_feature(s
, ARM_FEATURE_M
)) {
8608 addr
= tcg_const_i32((a
->mask
<< 10) | a
->sysm
);
8609 reg
= load_reg(s
, a
->rn
);
8610 gen_helper_v7m_msr(cpu_env
, addr
, reg
);
8611 tcg_temp_free_i32(addr
);
8612 tcg_temp_free_i32(reg
);
8613 /* If we wrote to CONTROL, the EL might have changed */
8614 gen_helper_rebuild_hflags_m32_newel(cpu_env
);
8619 static bool trans_BX(DisasContext
*s
, arg_BX
*a
)
8621 if (!ENABLE_ARCH_4T
) {
8624 gen_bx_excret(s
, load_reg(s
, a
->rm
));
8628 static bool trans_BXJ(DisasContext
*s
, arg_BXJ
*a
)
8630 if (!ENABLE_ARCH_5J
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
8633 /* Trivial implementation equivalent to bx. */
8634 gen_bx(s
, load_reg(s
, a
->rm
));
8638 static bool trans_BLX_r(DisasContext
*s
, arg_BLX_r
*a
)
8642 if (!ENABLE_ARCH_5
) {
8645 tmp
= load_reg(s
, a
->rm
);
8646 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| s
->thumb
);
8652 * BXNS/BLXNS: only exist for v8M with the security extensions,
8653 * and always UNDEF if NonSecure. We don't implement these in
8654 * the user-only mode either (in theory you can use them from
8655 * Secure User mode but they are too tied in to system emulation).
8657 static bool trans_BXNS(DisasContext
*s
, arg_BXNS
*a
)
8659 if (!s
->v8m_secure
|| IS_USER_ONLY
) {
8660 unallocated_encoding(s
);
8667 static bool trans_BLXNS(DisasContext
*s
, arg_BLXNS
*a
)
8669 if (!s
->v8m_secure
|| IS_USER_ONLY
) {
8670 unallocated_encoding(s
);
8672 gen_blxns(s
, a
->rm
);
8677 static bool trans_CLZ(DisasContext
*s
, arg_CLZ
*a
)
8681 if (!ENABLE_ARCH_5
) {
8684 tmp
= load_reg(s
, a
->rm
);
8685 tcg_gen_clzi_i32(tmp
, tmp
, 32);
8686 store_reg(s
, a
->rd
, tmp
);
8690 static bool trans_ERET(DisasContext
*s
, arg_ERET
*a
)
8694 if (!arm_dc_feature(s
, ARM_FEATURE_V7VE
)) {
8698 unallocated_encoding(s
);
8701 if (s
->current_el
== 2) {
8702 /* ERET from Hyp uses ELR_Hyp, not LR */
8703 tmp
= load_cpu_field(elr_el
[2]);
8705 tmp
= load_reg(s
, 14);
8707 gen_exception_return(s
, tmp
);
8711 static bool trans_HLT(DisasContext
*s
, arg_HLT
*a
)
8717 static bool trans_BKPT(DisasContext
*s
, arg_BKPT
*a
)
8719 if (!ENABLE_ARCH_5
) {
8722 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
8723 semihosting_enabled() &&
8724 #ifndef CONFIG_USER_ONLY
8728 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
8730 gen_exception_bkpt_insn(s
, syn_aa32_bkpt(a
->imm
, false));
8735 static bool trans_HVC(DisasContext
*s
, arg_HVC
*a
)
8737 if (!ENABLE_ARCH_7
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
8741 unallocated_encoding(s
);
8748 static bool trans_SMC(DisasContext
*s
, arg_SMC
*a
)
8750 if (!ENABLE_ARCH_6K
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
8754 unallocated_encoding(s
);
8761 static bool trans_SG(DisasContext
*s
, arg_SG
*a
)
8763 if (!arm_dc_feature(s
, ARM_FEATURE_M
) ||
8764 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
8769 * The bulk of the behaviour for this instruction is implemented
8770 * in v7m_handle_execute_nsc(), which deals with the insn when
8771 * it is executed by a CPU in non-secure state from memory
8772 * which is Secure & NonSecure-Callable.
8773 * Here we only need to handle the remaining cases:
8774 * * in NS memory (including the "security extension not
8775 * implemented" case) : NOP
8776 * * in S memory but CPU already secure (clear IT bits)
8777 * We know that the attribute for the memory this insn is
8778 * in must match the current CPU state, because otherwise
8779 * get_phys_addr_pmsav8 would have generated an exception.
8781 if (s
->v8m_secure
) {
8782 /* Like the IT insn, we don't need to generate any code */
8783 s
->condexec_cond
= 0;
8784 s
->condexec_mask
= 0;
8789 static bool trans_TT(DisasContext
*s
, arg_TT
*a
)
8793 if (!arm_dc_feature(s
, ARM_FEATURE_M
) ||
8794 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
8797 if (a
->rd
== 13 || a
->rd
== 15 || a
->rn
== 15) {
8798 /* We UNDEF for these UNPREDICTABLE cases */
8799 unallocated_encoding(s
);
8802 if (a
->A
&& !s
->v8m_secure
) {
8803 /* This case is UNDEFINED. */
8804 unallocated_encoding(s
);
8808 addr
= load_reg(s
, a
->rn
);
8809 tmp
= tcg_const_i32((a
->A
<< 1) | a
->T
);
8810 gen_helper_v7m_tt(tmp
, cpu_env
, addr
, tmp
);
8811 tcg_temp_free_i32(addr
);
8812 store_reg(s
, a
->rd
, tmp
);
8817 * Load/store register index
8820 static ISSInfo
make_issinfo(DisasContext
*s
, int rd
, bool p
, bool w
)
8824 /* ISS not valid if writeback */
8827 if (s
->base
.pc_next
- s
->pc_curr
== 2) {
8836 static TCGv_i32
op_addr_rr_pre(DisasContext
*s
, arg_ldst_rr
*a
)
8838 TCGv_i32 addr
= load_reg(s
, a
->rn
);
8840 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
8841 gen_helper_v8m_stackcheck(cpu_env
, addr
);
8845 TCGv_i32 ofs
= load_reg(s
, a
->rm
);
8846 gen_arm_shift_im(ofs
, a
->shtype
, a
->shimm
, 0);
8848 tcg_gen_add_i32(addr
, addr
, ofs
);
8850 tcg_gen_sub_i32(addr
, addr
, ofs
);
8852 tcg_temp_free_i32(ofs
);
8857 static void op_addr_rr_post(DisasContext
*s
, arg_ldst_rr
*a
,
8858 TCGv_i32 addr
, int address_offset
)
8861 TCGv_i32 ofs
= load_reg(s
, a
->rm
);
8862 gen_arm_shift_im(ofs
, a
->shtype
, a
->shimm
, 0);
8864 tcg_gen_add_i32(addr
, addr
, ofs
);
8866 tcg_gen_sub_i32(addr
, addr
, ofs
);
8868 tcg_temp_free_i32(ofs
);
8870 tcg_temp_free_i32(addr
);
8873 tcg_gen_addi_i32(addr
, addr
, address_offset
);
8874 store_reg(s
, a
->rn
, addr
);
8877 static bool op_load_rr(DisasContext
*s
, arg_ldst_rr
*a
,
8878 MemOp mop
, int mem_idx
)
8880 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
);
8883 addr
= op_addr_rr_pre(s
, a
);
8885 tmp
= tcg_temp_new_i32();
8886 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
8887 disas_set_da_iss(s
, mop
, issinfo
);
8890 * Perform base writeback before the loaded value to
8891 * ensure correct behavior with overlapping index registers.
8893 op_addr_rr_post(s
, a
, addr
, 0);
8894 store_reg_from_load(s
, a
->rt
, tmp
);
8898 static bool op_store_rr(DisasContext
*s
, arg_ldst_rr
*a
,
8899 MemOp mop
, int mem_idx
)
8901 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
) | ISSIsWrite
;
8904 addr
= op_addr_rr_pre(s
, a
);
8906 tmp
= load_reg(s
, a
->rt
);
8907 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
8908 disas_set_da_iss(s
, mop
, issinfo
);
8909 tcg_temp_free_i32(tmp
);
8911 op_addr_rr_post(s
, a
, addr
, 0);
8915 static bool trans_LDRD_rr(DisasContext
*s
, arg_ldst_rr
*a
)
8917 int mem_idx
= get_mem_index(s
);
8920 if (!ENABLE_ARCH_5TE
) {
8924 unallocated_encoding(s
);
8927 addr
= op_addr_rr_pre(s
, a
);
8929 tmp
= tcg_temp_new_i32();
8930 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8931 store_reg(s
, a
->rt
, tmp
);
8933 tcg_gen_addi_i32(addr
, addr
, 4);
8935 tmp
= tcg_temp_new_i32();
8936 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8937 store_reg(s
, a
->rt
+ 1, tmp
);
8939 /* LDRD w/ base writeback is undefined if the registers overlap. */
8940 op_addr_rr_post(s
, a
, addr
, -4);
8944 static bool trans_STRD_rr(DisasContext
*s
, arg_ldst_rr
*a
)
8946 int mem_idx
= get_mem_index(s
);
8949 if (!ENABLE_ARCH_5TE
) {
8953 unallocated_encoding(s
);
8956 addr
= op_addr_rr_pre(s
, a
);
8958 tmp
= load_reg(s
, a
->rt
);
8959 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8960 tcg_temp_free_i32(tmp
);
8962 tcg_gen_addi_i32(addr
, addr
, 4);
8964 tmp
= load_reg(s
, a
->rt
+ 1);
8965 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
8966 tcg_temp_free_i32(tmp
);
8968 op_addr_rr_post(s
, a
, addr
, -4);
8973 * Load/store immediate index
8976 static TCGv_i32
op_addr_ri_pre(DisasContext
*s
, arg_ldst_ri
*a
)
8984 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
8986 * Stackcheck. Here we know 'addr' is the current SP;
8987 * U is set if we're moving SP up, else down. It is
8988 * UNKNOWN whether the limit check triggers when SP starts
8989 * below the limit and ends up above it; we chose to do so.
8992 TCGv_i32 newsp
= tcg_temp_new_i32();
8993 tcg_gen_addi_i32(newsp
, cpu_R
[13], ofs
);
8994 gen_helper_v8m_stackcheck(cpu_env
, newsp
);
8995 tcg_temp_free_i32(newsp
);
8997 gen_helper_v8m_stackcheck(cpu_env
, cpu_R
[13]);
9001 return add_reg_for_lit(s
, a
->rn
, a
->p
? ofs
: 0);
9004 static void op_addr_ri_post(DisasContext
*s
, arg_ldst_ri
*a
,
9005 TCGv_i32 addr
, int address_offset
)
9009 address_offset
+= a
->imm
;
9011 address_offset
-= a
->imm
;
9014 tcg_temp_free_i32(addr
);
9017 tcg_gen_addi_i32(addr
, addr
, address_offset
);
9018 store_reg(s
, a
->rn
, addr
);
9021 static bool op_load_ri(DisasContext
*s
, arg_ldst_ri
*a
,
9022 MemOp mop
, int mem_idx
)
9024 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
);
9027 addr
= op_addr_ri_pre(s
, a
);
9029 tmp
= tcg_temp_new_i32();
9030 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
9031 disas_set_da_iss(s
, mop
, issinfo
);
9034 * Perform base writeback before the loaded value to
9035 * ensure correct behavior with overlapping index registers.
9037 op_addr_ri_post(s
, a
, addr
, 0);
9038 store_reg_from_load(s
, a
->rt
, tmp
);
9042 static bool op_store_ri(DisasContext
*s
, arg_ldst_ri
*a
,
9043 MemOp mop
, int mem_idx
)
9045 ISSInfo issinfo
= make_issinfo(s
, a
->rt
, a
->p
, a
->w
) | ISSIsWrite
;
9048 addr
= op_addr_ri_pre(s
, a
);
9050 tmp
= load_reg(s
, a
->rt
);
9051 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, mop
| s
->be_data
);
9052 disas_set_da_iss(s
, mop
, issinfo
);
9053 tcg_temp_free_i32(tmp
);
9055 op_addr_ri_post(s
, a
, addr
, 0);
9059 static bool op_ldrd_ri(DisasContext
*s
, arg_ldst_ri
*a
, int rt2
)
9061 int mem_idx
= get_mem_index(s
);
9064 addr
= op_addr_ri_pre(s
, a
);
9066 tmp
= tcg_temp_new_i32();
9067 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
9068 store_reg(s
, a
->rt
, tmp
);
9070 tcg_gen_addi_i32(addr
, addr
, 4);
9072 tmp
= tcg_temp_new_i32();
9073 gen_aa32_ld_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
9074 store_reg(s
, rt2
, tmp
);
9076 /* LDRD w/ base writeback is undefined if the registers overlap. */
9077 op_addr_ri_post(s
, a
, addr
, -4);
9081 static bool trans_LDRD_ri_a32(DisasContext
*s
, arg_ldst_ri
*a
)
9083 if (!ENABLE_ARCH_5TE
|| (a
->rt
& 1)) {
9086 return op_ldrd_ri(s
, a
, a
->rt
+ 1);
9089 static bool trans_LDRD_ri_t32(DisasContext
*s
, arg_ldst_ri2
*a
)
9092 .u
= a
->u
, .w
= a
->w
, .p
= a
->p
,
9093 .rn
= a
->rn
, .rt
= a
->rt
, .imm
= a
->imm
9095 return op_ldrd_ri(s
, &b
, a
->rt2
);
9098 static bool op_strd_ri(DisasContext
*s
, arg_ldst_ri
*a
, int rt2
)
9100 int mem_idx
= get_mem_index(s
);
9103 addr
= op_addr_ri_pre(s
, a
);
9105 tmp
= load_reg(s
, a
->rt
);
9106 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
9107 tcg_temp_free_i32(tmp
);
9109 tcg_gen_addi_i32(addr
, addr
, 4);
9111 tmp
= load_reg(s
, rt2
);
9112 gen_aa32_st_i32(s
, tmp
, addr
, mem_idx
, MO_UL
| s
->be_data
);
9113 tcg_temp_free_i32(tmp
);
9115 op_addr_ri_post(s
, a
, addr
, -4);
9119 static bool trans_STRD_ri_a32(DisasContext
*s
, arg_ldst_ri
*a
)
9121 if (!ENABLE_ARCH_5TE
|| (a
->rt
& 1)) {
9124 return op_strd_ri(s
, a
, a
->rt
+ 1);
9127 static bool trans_STRD_ri_t32(DisasContext
*s
, arg_ldst_ri2
*a
)
9130 .u
= a
->u
, .w
= a
->w
, .p
= a
->p
,
9131 .rn
= a
->rn
, .rt
= a
->rt
, .imm
= a
->imm
9133 return op_strd_ri(s
, &b
, a
->rt2
);
9136 #define DO_LDST(NAME, WHICH, MEMOP) \
9137 static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \
9139 return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \
9141 static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \
9143 return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \
9145 static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \
9147 return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \
9149 static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \
9151 return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \
9154 DO_LDST(LDR
, load
, MO_UL
)
9155 DO_LDST(LDRB
, load
, MO_UB
)
9156 DO_LDST(LDRH
, load
, MO_UW
)
9157 DO_LDST(LDRSB
, load
, MO_SB
)
9158 DO_LDST(LDRSH
, load
, MO_SW
)
9160 DO_LDST(STR
, store
, MO_UL
)
9161 DO_LDST(STRB
, store
, MO_UB
)
9162 DO_LDST(STRH
, store
, MO_UW
)
9167 * Synchronization primitives
9170 static bool op_swp(DisasContext
*s
, arg_SWP
*a
, MemOp opc
)
9176 addr
= load_reg(s
, a
->rn
);
9177 taddr
= gen_aa32_addr(s
, addr
, opc
);
9178 tcg_temp_free_i32(addr
);
9180 tmp
= load_reg(s
, a
->rt2
);
9181 tcg_gen_atomic_xchg_i32(tmp
, taddr
, tmp
, get_mem_index(s
), opc
);
9182 tcg_temp_free(taddr
);
9184 store_reg(s
, a
->rt
, tmp
);
9188 static bool trans_SWP(DisasContext
*s
, arg_SWP
*a
)
9190 return op_swp(s
, a
, MO_UL
| MO_ALIGN
);
9193 static bool trans_SWPB(DisasContext
*s
, arg_SWP
*a
)
9195 return op_swp(s
, a
, MO_UB
);
9199 * Load/Store Exclusive and Load-Acquire/Store-Release
9202 static bool op_strex(DisasContext
*s
, arg_STREX
*a
, MemOp mop
, bool rel
)
9205 /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
9206 bool v8a
= ENABLE_ARCH_8
&& !arm_dc_feature(s
, ARM_FEATURE_M
);
9208 /* We UNDEF for these UNPREDICTABLE cases. */
9209 if (a
->rd
== 15 || a
->rn
== 15 || a
->rt
== 15
9210 || a
->rd
== a
->rn
|| a
->rd
== a
->rt
9211 || (!v8a
&& s
->thumb
&& (a
->rd
== 13 || a
->rt
== 13))
9215 || (!v8a
&& s
->thumb
&& a
->rt2
== 13)))) {
9216 unallocated_encoding(s
);
9221 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
9224 addr
= tcg_temp_local_new_i32();
9225 load_reg_var(s
, addr
, a
->rn
);
9226 tcg_gen_addi_i32(addr
, addr
, a
->imm
);
9228 gen_store_exclusive(s
, a
->rd
, a
->rt
, a
->rt2
, addr
, mop
);
9229 tcg_temp_free_i32(addr
);
9233 static bool trans_STREX(DisasContext
*s
, arg_STREX
*a
)
9235 if (!ENABLE_ARCH_6
) {
9238 return op_strex(s
, a
, MO_32
, false);
9241 static bool trans_STREXD_a32(DisasContext
*s
, arg_STREX
*a
)
9243 if (!ENABLE_ARCH_6K
) {
9246 /* We UNDEF for these UNPREDICTABLE cases. */
9248 unallocated_encoding(s
);
9252 return op_strex(s
, a
, MO_64
, false);
9255 static bool trans_STREXD_t32(DisasContext
*s
, arg_STREX
*a
)
9257 return op_strex(s
, a
, MO_64
, false);
9260 static bool trans_STREXB(DisasContext
*s
, arg_STREX
*a
)
9262 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
9265 return op_strex(s
, a
, MO_8
, false);
9268 static bool trans_STREXH(DisasContext
*s
, arg_STREX
*a
)
9270 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
9273 return op_strex(s
, a
, MO_16
, false);
9276 static bool trans_STLEX(DisasContext
*s
, arg_STREX
*a
)
9278 if (!ENABLE_ARCH_8
) {
9281 return op_strex(s
, a
, MO_32
, true);
9284 static bool trans_STLEXD_a32(DisasContext
*s
, arg_STREX
*a
)
9286 if (!ENABLE_ARCH_8
) {
9289 /* We UNDEF for these UNPREDICTABLE cases. */
9291 unallocated_encoding(s
);
9295 return op_strex(s
, a
, MO_64
, true);
9298 static bool trans_STLEXD_t32(DisasContext
*s
, arg_STREX
*a
)
9300 if (!ENABLE_ARCH_8
) {
9303 return op_strex(s
, a
, MO_64
, true);
9306 static bool trans_STLEXB(DisasContext
*s
, arg_STREX
*a
)
9308 if (!ENABLE_ARCH_8
) {
9311 return op_strex(s
, a
, MO_8
, true);
9314 static bool trans_STLEXH(DisasContext
*s
, arg_STREX
*a
)
9316 if (!ENABLE_ARCH_8
) {
9319 return op_strex(s
, a
, MO_16
, true);
9322 static bool op_stl(DisasContext
*s
, arg_STL
*a
, MemOp mop
)
9326 if (!ENABLE_ARCH_8
) {
9329 /* We UNDEF for these UNPREDICTABLE cases. */
9330 if (a
->rn
== 15 || a
->rt
== 15) {
9331 unallocated_encoding(s
);
9335 addr
= load_reg(s
, a
->rn
);
9336 tmp
= load_reg(s
, a
->rt
);
9337 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
9338 gen_aa32_st_i32(s
, tmp
, addr
, get_mem_index(s
), mop
| s
->be_data
);
9339 disas_set_da_iss(s
, mop
, a
->rt
| ISSIsAcqRel
| ISSIsWrite
);
9341 tcg_temp_free_i32(tmp
);
9342 tcg_temp_free_i32(addr
);
9346 static bool trans_STL(DisasContext
*s
, arg_STL
*a
)
9348 return op_stl(s
, a
, MO_UL
);
9351 static bool trans_STLB(DisasContext
*s
, arg_STL
*a
)
9353 return op_stl(s
, a
, MO_UB
);
9356 static bool trans_STLH(DisasContext
*s
, arg_STL
*a
)
9358 return op_stl(s
, a
, MO_UW
);
9361 static bool op_ldrex(DisasContext
*s
, arg_LDREX
*a
, MemOp mop
, bool acq
)
9364 /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
9365 bool v8a
= ENABLE_ARCH_8
&& !arm_dc_feature(s
, ARM_FEATURE_M
);
9367 /* We UNDEF for these UNPREDICTABLE cases. */
9368 if (a
->rn
== 15 || a
->rt
== 15
9369 || (!v8a
&& s
->thumb
&& a
->rt
== 13)
9371 && (a
->rt2
== 15 || a
->rt
== a
->rt2
9372 || (!v8a
&& s
->thumb
&& a
->rt2
== 13)))) {
9373 unallocated_encoding(s
);
9377 addr
= tcg_temp_local_new_i32();
9378 load_reg_var(s
, addr
, a
->rn
);
9379 tcg_gen_addi_i32(addr
, addr
, a
->imm
);
9381 gen_load_exclusive(s
, a
->rt
, a
->rt2
, addr
, mop
);
9382 tcg_temp_free_i32(addr
);
9385 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
9390 static bool trans_LDREX(DisasContext
*s
, arg_LDREX
*a
)
9392 if (!ENABLE_ARCH_6
) {
9395 return op_ldrex(s
, a
, MO_32
, false);
9398 static bool trans_LDREXD_a32(DisasContext
*s
, arg_LDREX
*a
)
9400 if (!ENABLE_ARCH_6K
) {
9403 /* We UNDEF for these UNPREDICTABLE cases. */
9405 unallocated_encoding(s
);
9409 return op_ldrex(s
, a
, MO_64
, false);
9412 static bool trans_LDREXD_t32(DisasContext
*s
, arg_LDREX
*a
)
9414 return op_ldrex(s
, a
, MO_64
, false);
9417 static bool trans_LDREXB(DisasContext
*s
, arg_LDREX
*a
)
9419 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
9422 return op_ldrex(s
, a
, MO_8
, false);
9425 static bool trans_LDREXH(DisasContext
*s
, arg_LDREX
*a
)
9427 if (s
->thumb
? !ENABLE_ARCH_7
: !ENABLE_ARCH_6K
) {
9430 return op_ldrex(s
, a
, MO_16
, false);
9433 static bool trans_LDAEX(DisasContext
*s
, arg_LDREX
*a
)
9435 if (!ENABLE_ARCH_8
) {
9438 return op_ldrex(s
, a
, MO_32
, true);
9441 static bool trans_LDAEXD_a32(DisasContext
*s
, arg_LDREX
*a
)
9443 if (!ENABLE_ARCH_8
) {
9446 /* We UNDEF for these UNPREDICTABLE cases. */
9448 unallocated_encoding(s
);
9452 return op_ldrex(s
, a
, MO_64
, true);
9455 static bool trans_LDAEXD_t32(DisasContext
*s
, arg_LDREX
*a
)
9457 if (!ENABLE_ARCH_8
) {
9460 return op_ldrex(s
, a
, MO_64
, true);
9463 static bool trans_LDAEXB(DisasContext
*s
, arg_LDREX
*a
)
9465 if (!ENABLE_ARCH_8
) {
9468 return op_ldrex(s
, a
, MO_8
, true);
9471 static bool trans_LDAEXH(DisasContext
*s
, arg_LDREX
*a
)
9473 if (!ENABLE_ARCH_8
) {
9476 return op_ldrex(s
, a
, MO_16
, true);
9479 static bool op_lda(DisasContext
*s
, arg_LDA
*a
, MemOp mop
)
9483 if (!ENABLE_ARCH_8
) {
9486 /* We UNDEF for these UNPREDICTABLE cases. */
9487 if (a
->rn
== 15 || a
->rt
== 15) {
9488 unallocated_encoding(s
);
9492 addr
= load_reg(s
, a
->rn
);
9493 tmp
= tcg_temp_new_i32();
9494 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), mop
| s
->be_data
);
9495 disas_set_da_iss(s
, mop
, a
->rt
| ISSIsAcqRel
);
9496 tcg_temp_free_i32(addr
);
9498 store_reg(s
, a
->rt
, tmp
);
9499 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
9503 static bool trans_LDA(DisasContext
*s
, arg_LDA
*a
)
9505 return op_lda(s
, a
, MO_UL
);
9508 static bool trans_LDAB(DisasContext
*s
, arg_LDA
*a
)
9510 return op_lda(s
, a
, MO_UB
);
9513 static bool trans_LDAH(DisasContext
*s
, arg_LDA
*a
)
9515 return op_lda(s
, a
, MO_UW
);
9519 * Media instructions
9522 static bool trans_USADA8(DisasContext
*s
, arg_USADA8
*a
)
9526 if (!ENABLE_ARCH_6
) {
9530 t1
= load_reg(s
, a
->rn
);
9531 t2
= load_reg(s
, a
->rm
);
9532 gen_helper_usad8(t1
, t1
, t2
);
9533 tcg_temp_free_i32(t2
);
9535 t2
= load_reg(s
, a
->ra
);
9536 tcg_gen_add_i32(t1
, t1
, t2
);
9537 tcg_temp_free_i32(t2
);
9539 store_reg(s
, a
->rd
, t1
);
9543 static bool op_bfx(DisasContext
*s
, arg_UBFX
*a
, bool u
)
9546 int width
= a
->widthm1
+ 1;
9549 if (!ENABLE_ARCH_6T2
) {
9552 if (shift
+ width
> 32) {
9553 /* UNPREDICTABLE; we choose to UNDEF */
9554 unallocated_encoding(s
);
9558 tmp
= load_reg(s
, a
->rn
);
9560 tcg_gen_extract_i32(tmp
, tmp
, shift
, width
);
9562 tcg_gen_sextract_i32(tmp
, tmp
, shift
, width
);
9564 store_reg(s
, a
->rd
, tmp
);
9568 static bool trans_SBFX(DisasContext
*s
, arg_SBFX
*a
)
9570 return op_bfx(s
, a
, false);
9573 static bool trans_UBFX(DisasContext
*s
, arg_UBFX
*a
)
9575 return op_bfx(s
, a
, true);
9578 static bool trans_BFCI(DisasContext
*s
, arg_BFCI
*a
)
9581 int msb
= a
->msb
, lsb
= a
->lsb
;
9584 if (!ENABLE_ARCH_6T2
) {
9588 /* UNPREDICTABLE; we choose to UNDEF */
9589 unallocated_encoding(s
);
9593 width
= msb
+ 1 - lsb
;
9596 tmp
= tcg_const_i32(0);
9599 tmp
= load_reg(s
, a
->rn
);
9602 TCGv_i32 tmp2
= load_reg(s
, a
->rd
);
9603 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, lsb
, width
);
9604 tcg_temp_free_i32(tmp2
);
9606 store_reg(s
, a
->rd
, tmp
);
9610 static bool trans_UDF(DisasContext
*s
, arg_UDF
*a
)
9612 unallocated_encoding(s
);
9617 * Parallel addition and subtraction
9620 static bool op_par_addsub(DisasContext
*s
, arg_rrr
*a
,
9621 void (*gen
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
9626 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
9631 t0
= load_reg(s
, a
->rn
);
9632 t1
= load_reg(s
, a
->rm
);
9636 tcg_temp_free_i32(t1
);
9637 store_reg(s
, a
->rd
, t0
);
9641 static bool op_par_addsub_ge(DisasContext
*s
, arg_rrr
*a
,
9642 void (*gen
)(TCGv_i32
, TCGv_i32
,
9643 TCGv_i32
, TCGv_ptr
))
9649 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
9654 t0
= load_reg(s
, a
->rn
);
9655 t1
= load_reg(s
, a
->rm
);
9657 ge
= tcg_temp_new_ptr();
9658 tcg_gen_addi_ptr(ge
, cpu_env
, offsetof(CPUARMState
, GE
));
9659 gen(t0
, t0
, t1
, ge
);
9661 tcg_temp_free_ptr(ge
);
9662 tcg_temp_free_i32(t1
);
9663 store_reg(s
, a
->rd
, t0
);
9667 #define DO_PAR_ADDSUB(NAME, helper) \
9668 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
9670 return op_par_addsub(s, a, helper); \
9673 #define DO_PAR_ADDSUB_GE(NAME, helper) \
9674 static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
9676 return op_par_addsub_ge(s, a, helper); \
9679 DO_PAR_ADDSUB_GE(SADD16
, gen_helper_sadd16
)
9680 DO_PAR_ADDSUB_GE(SASX
, gen_helper_saddsubx
)
9681 DO_PAR_ADDSUB_GE(SSAX
, gen_helper_ssubaddx
)
9682 DO_PAR_ADDSUB_GE(SSUB16
, gen_helper_ssub16
)
9683 DO_PAR_ADDSUB_GE(SADD8
, gen_helper_sadd8
)
9684 DO_PAR_ADDSUB_GE(SSUB8
, gen_helper_ssub8
)
9686 DO_PAR_ADDSUB_GE(UADD16
, gen_helper_uadd16
)
9687 DO_PAR_ADDSUB_GE(UASX
, gen_helper_uaddsubx
)
9688 DO_PAR_ADDSUB_GE(USAX
, gen_helper_usubaddx
)
9689 DO_PAR_ADDSUB_GE(USUB16
, gen_helper_usub16
)
9690 DO_PAR_ADDSUB_GE(UADD8
, gen_helper_uadd8
)
9691 DO_PAR_ADDSUB_GE(USUB8
, gen_helper_usub8
)
9693 DO_PAR_ADDSUB(QADD16
, gen_helper_qadd16
)
9694 DO_PAR_ADDSUB(QASX
, gen_helper_qaddsubx
)
9695 DO_PAR_ADDSUB(QSAX
, gen_helper_qsubaddx
)
9696 DO_PAR_ADDSUB(QSUB16
, gen_helper_qsub16
)
9697 DO_PAR_ADDSUB(QADD8
, gen_helper_qadd8
)
9698 DO_PAR_ADDSUB(QSUB8
, gen_helper_qsub8
)
9700 DO_PAR_ADDSUB(UQADD16
, gen_helper_uqadd16
)
9701 DO_PAR_ADDSUB(UQASX
, gen_helper_uqaddsubx
)
9702 DO_PAR_ADDSUB(UQSAX
, gen_helper_uqsubaddx
)
9703 DO_PAR_ADDSUB(UQSUB16
, gen_helper_uqsub16
)
9704 DO_PAR_ADDSUB(UQADD8
, gen_helper_uqadd8
)
9705 DO_PAR_ADDSUB(UQSUB8
, gen_helper_uqsub8
)
9707 DO_PAR_ADDSUB(SHADD16
, gen_helper_shadd16
)
9708 DO_PAR_ADDSUB(SHASX
, gen_helper_shaddsubx
)
9709 DO_PAR_ADDSUB(SHSAX
, gen_helper_shsubaddx
)
9710 DO_PAR_ADDSUB(SHSUB16
, gen_helper_shsub16
)
9711 DO_PAR_ADDSUB(SHADD8
, gen_helper_shadd8
)
9712 DO_PAR_ADDSUB(SHSUB8
, gen_helper_shsub8
)
9714 DO_PAR_ADDSUB(UHADD16
, gen_helper_uhadd16
)
9715 DO_PAR_ADDSUB(UHASX
, gen_helper_uhaddsubx
)
9716 DO_PAR_ADDSUB(UHSAX
, gen_helper_uhsubaddx
)
9717 DO_PAR_ADDSUB(UHSUB16
, gen_helper_uhsub16
)
9718 DO_PAR_ADDSUB(UHADD8
, gen_helper_uhadd8
)
9719 DO_PAR_ADDSUB(UHSUB8
, gen_helper_uhsub8
)
9721 #undef DO_PAR_ADDSUB
9722 #undef DO_PAR_ADDSUB_GE
9725 * Packing, unpacking, saturation, and reversal
9728 static bool trans_PKH(DisasContext
*s
, arg_PKH
*a
)
9734 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
9739 tn
= load_reg(s
, a
->rn
);
9740 tm
= load_reg(s
, a
->rm
);
9746 tcg_gen_sari_i32(tm
, tm
, shift
);
9747 tcg_gen_deposit_i32(tn
, tn
, tm
, 0, 16);
9750 tcg_gen_shli_i32(tm
, tm
, shift
);
9751 tcg_gen_deposit_i32(tn
, tm
, tn
, 0, 16);
9753 tcg_temp_free_i32(tm
);
9754 store_reg(s
, a
->rd
, tn
);
9758 static bool op_sat(DisasContext
*s
, arg_sat
*a
,
9759 void (*gen
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
9761 TCGv_i32 tmp
, satimm
;
9764 if (!ENABLE_ARCH_6
) {
9768 tmp
= load_reg(s
, a
->rn
);
9770 tcg_gen_sari_i32(tmp
, tmp
, shift
? shift
: 31);
9772 tcg_gen_shli_i32(tmp
, tmp
, shift
);
9775 satimm
= tcg_const_i32(a
->satimm
);
9776 gen(tmp
, cpu_env
, tmp
, satimm
);
9777 tcg_temp_free_i32(satimm
);
9779 store_reg(s
, a
->rd
, tmp
);
9783 static bool trans_SSAT(DisasContext
*s
, arg_sat
*a
)
9785 return op_sat(s
, a
, gen_helper_ssat
);
9788 static bool trans_USAT(DisasContext
*s
, arg_sat
*a
)
9790 return op_sat(s
, a
, gen_helper_usat
);
9793 static bool trans_SSAT16(DisasContext
*s
, arg_sat
*a
)
9795 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9798 return op_sat(s
, a
, gen_helper_ssat16
);
9801 static bool trans_USAT16(DisasContext
*s
, arg_sat
*a
)
9803 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9806 return op_sat(s
, a
, gen_helper_usat16
);
9809 static bool op_xta(DisasContext
*s
, arg_rrr_rot
*a
,
9810 void (*gen_extract
)(TCGv_i32
, TCGv_i32
),
9811 void (*gen_add
)(TCGv_i32
, TCGv_i32
, TCGv_i32
))
9815 if (!ENABLE_ARCH_6
) {
9819 tmp
= load_reg(s
, a
->rm
);
9821 * TODO: In many cases we could do a shift instead of a rotate.
9822 * Combined with a simple extend, that becomes an extract.
9824 tcg_gen_rotri_i32(tmp
, tmp
, a
->rot
* 8);
9825 gen_extract(tmp
, tmp
);
9828 TCGv_i32 tmp2
= load_reg(s
, a
->rn
);
9829 gen_add(tmp
, tmp
, tmp2
);
9830 tcg_temp_free_i32(tmp2
);
9832 store_reg(s
, a
->rd
, tmp
);
9836 static bool trans_SXTAB(DisasContext
*s
, arg_rrr_rot
*a
)
9838 return op_xta(s
, a
, tcg_gen_ext8s_i32
, tcg_gen_add_i32
);
9841 static bool trans_SXTAH(DisasContext
*s
, arg_rrr_rot
*a
)
9843 return op_xta(s
, a
, tcg_gen_ext16s_i32
, tcg_gen_add_i32
);
9846 static bool trans_SXTAB16(DisasContext
*s
, arg_rrr_rot
*a
)
9848 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9851 return op_xta(s
, a
, gen_helper_sxtb16
, gen_add16
);
9854 static bool trans_UXTAB(DisasContext
*s
, arg_rrr_rot
*a
)
9856 return op_xta(s
, a
, tcg_gen_ext8u_i32
, tcg_gen_add_i32
);
9859 static bool trans_UXTAH(DisasContext
*s
, arg_rrr_rot
*a
)
9861 return op_xta(s
, a
, tcg_gen_ext16u_i32
, tcg_gen_add_i32
);
9864 static bool trans_UXTAB16(DisasContext
*s
, arg_rrr_rot
*a
)
9866 if (s
->thumb
&& !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
9869 return op_xta(s
, a
, gen_helper_uxtb16
, gen_add16
);
9872 static bool trans_SEL(DisasContext
*s
, arg_rrr
*a
)
9874 TCGv_i32 t1
, t2
, t3
;
9877 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
9882 t1
= load_reg(s
, a
->rn
);
9883 t2
= load_reg(s
, a
->rm
);
9884 t3
= tcg_temp_new_i32();
9885 tcg_gen_ld_i32(t3
, cpu_env
, offsetof(CPUARMState
, GE
));
9886 gen_helper_sel_flags(t1
, t3
, t1
, t2
);
9887 tcg_temp_free_i32(t3
);
9888 tcg_temp_free_i32(t2
);
9889 store_reg(s
, a
->rd
, t1
);
9893 static bool op_rr(DisasContext
*s
, arg_rr
*a
,
9894 void (*gen
)(TCGv_i32
, TCGv_i32
))
9898 tmp
= load_reg(s
, a
->rm
);
9900 store_reg(s
, a
->rd
, tmp
);
9904 static bool trans_REV(DisasContext
*s
, arg_rr
*a
)
9906 if (!ENABLE_ARCH_6
) {
9909 return op_rr(s
, a
, tcg_gen_bswap32_i32
);
9912 static bool trans_REV16(DisasContext
*s
, arg_rr
*a
)
9914 if (!ENABLE_ARCH_6
) {
9917 return op_rr(s
, a
, gen_rev16
);
9920 static bool trans_REVSH(DisasContext
*s
, arg_rr
*a
)
9922 if (!ENABLE_ARCH_6
) {
9925 return op_rr(s
, a
, gen_revsh
);
9928 static bool trans_RBIT(DisasContext
*s
, arg_rr
*a
)
9930 if (!ENABLE_ARCH_6T2
) {
9933 return op_rr(s
, a
, gen_helper_rbit
);
9937 * Signed multiply, signed and unsigned divide
9940 static bool op_smlad(DisasContext
*s
, arg_rrrr
*a
, bool m_swap
, bool sub
)
9944 if (!ENABLE_ARCH_6
) {
9948 t1
= load_reg(s
, a
->rn
);
9949 t2
= load_reg(s
, a
->rm
);
9953 gen_smul_dual(t1
, t2
);
9956 /* This subtraction cannot overflow. */
9957 tcg_gen_sub_i32(t1
, t1
, t2
);
9960 * This addition cannot overflow 32 bits; however it may
9961 * overflow considered as a signed operation, in which case
9962 * we must set the Q flag.
9964 gen_helper_add_setq(t1
, cpu_env
, t1
, t2
);
9966 tcg_temp_free_i32(t2
);
9969 t2
= load_reg(s
, a
->ra
);
9970 gen_helper_add_setq(t1
, cpu_env
, t1
, t2
);
9971 tcg_temp_free_i32(t2
);
9973 store_reg(s
, a
->rd
, t1
);
9977 static bool trans_SMLAD(DisasContext
*s
, arg_rrrr
*a
)
9979 return op_smlad(s
, a
, false, false);
9982 static bool trans_SMLADX(DisasContext
*s
, arg_rrrr
*a
)
9984 return op_smlad(s
, a
, true, false);
9987 static bool trans_SMLSD(DisasContext
*s
, arg_rrrr
*a
)
9989 return op_smlad(s
, a
, false, true);
9992 static bool trans_SMLSDX(DisasContext
*s
, arg_rrrr
*a
)
9994 return op_smlad(s
, a
, true, true);
9997 static bool op_smlald(DisasContext
*s
, arg_rrrr
*a
, bool m_swap
, bool sub
)
10002 if (!ENABLE_ARCH_6
) {
10006 t1
= load_reg(s
, a
->rn
);
10007 t2
= load_reg(s
, a
->rm
);
10011 gen_smul_dual(t1
, t2
);
10013 l1
= tcg_temp_new_i64();
10014 l2
= tcg_temp_new_i64();
10015 tcg_gen_ext_i32_i64(l1
, t1
);
10016 tcg_gen_ext_i32_i64(l2
, t2
);
10017 tcg_temp_free_i32(t1
);
10018 tcg_temp_free_i32(t2
);
10021 tcg_gen_sub_i64(l1
, l1
, l2
);
10023 tcg_gen_add_i64(l1
, l1
, l2
);
10025 tcg_temp_free_i64(l2
);
10027 gen_addq(s
, l1
, a
->ra
, a
->rd
);
10028 gen_storeq_reg(s
, a
->ra
, a
->rd
, l1
);
10029 tcg_temp_free_i64(l1
);
10033 static bool trans_SMLALD(DisasContext
*s
, arg_rrrr
*a
)
10035 return op_smlald(s
, a
, false, false);
10038 static bool trans_SMLALDX(DisasContext
*s
, arg_rrrr
*a
)
10040 return op_smlald(s
, a
, true, false);
10043 static bool trans_SMLSLD(DisasContext
*s
, arg_rrrr
*a
)
10045 return op_smlald(s
, a
, false, true);
10048 static bool trans_SMLSLDX(DisasContext
*s
, arg_rrrr
*a
)
10050 return op_smlald(s
, a
, true, true);
10053 static bool op_smmla(DisasContext
*s
, arg_rrrr
*a
, bool round
, bool sub
)
10058 ? !arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)
10059 : !ENABLE_ARCH_6
) {
10063 t1
= load_reg(s
, a
->rn
);
10064 t2
= load_reg(s
, a
->rm
);
10065 tcg_gen_muls2_i32(t2
, t1
, t1
, t2
);
10068 TCGv_i32 t3
= load_reg(s
, a
->ra
);
10071 * For SMMLS, we need a 64-bit subtract. Borrow caused by
10072 * a non-zero multiplicand lowpart, and the correct result
10073 * lowpart for rounding.
10075 TCGv_i32 zero
= tcg_const_i32(0);
10076 tcg_gen_sub2_i32(t2
, t1
, zero
, t3
, t2
, t1
);
10077 tcg_temp_free_i32(zero
);
10079 tcg_gen_add_i32(t1
, t1
, t3
);
10081 tcg_temp_free_i32(t3
);
10085 * Adding 0x80000000 to the 64-bit quantity means that we have
10086 * carry in to the high word when the low word has the msb set.
10088 tcg_gen_shri_i32(t2
, t2
, 31);
10089 tcg_gen_add_i32(t1
, t1
, t2
);
10091 tcg_temp_free_i32(t2
);
10092 store_reg(s
, a
->rd
, t1
);
10096 static bool trans_SMMLA(DisasContext
*s
, arg_rrrr
*a
)
10098 return op_smmla(s
, a
, false, false);
10101 static bool trans_SMMLAR(DisasContext
*s
, arg_rrrr
*a
)
10103 return op_smmla(s
, a
, true, false);
10106 static bool trans_SMMLS(DisasContext
*s
, arg_rrrr
*a
)
10108 return op_smmla(s
, a
, false, true);
10111 static bool trans_SMMLSR(DisasContext
*s
, arg_rrrr
*a
)
10113 return op_smmla(s
, a
, true, true);
10116 static bool op_div(DisasContext
*s
, arg_rrr
*a
, bool u
)
10121 ? !dc_isar_feature(aa32_thumb_div
, s
)
10122 : !dc_isar_feature(aa32_arm_div
, s
)) {
10126 t1
= load_reg(s
, a
->rn
);
10127 t2
= load_reg(s
, a
->rm
);
10129 gen_helper_udiv(t1
, t1
, t2
);
10131 gen_helper_sdiv(t1
, t1
, t2
);
10133 tcg_temp_free_i32(t2
);
10134 store_reg(s
, a
->rd
, t1
);
10138 static bool trans_SDIV(DisasContext
*s
, arg_rrr
*a
)
10140 return op_div(s
, a
, false);
10143 static bool trans_UDIV(DisasContext
*s
, arg_rrr
*a
)
10145 return op_div(s
, a
, true);
10149 * Block data transfer
10152 static TCGv_i32
op_addr_block_pre(DisasContext
*s
, arg_ldst_block
*a
, int n
)
10154 TCGv_i32 addr
= load_reg(s
, a
->rn
);
10158 /* pre increment */
10159 tcg_gen_addi_i32(addr
, addr
, 4);
10161 /* pre decrement */
10162 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
10164 } else if (!a
->i
&& n
!= 1) {
10165 /* post decrement */
10166 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
10169 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
10171 * If the writeback is incrementing SP rather than
10172 * decrementing it, and the initial SP is below the
10173 * stack limit but the final written-back SP would
10174 * be above, then then we must not perform any memory
10175 * accesses, but it is IMPDEF whether we generate
10176 * an exception. We choose to do so in this case.
10177 * At this point 'addr' is the lowest address, so
10178 * either the original SP (if incrementing) or our
10179 * final SP (if decrementing), so that's what we check.
10181 gen_helper_v8m_stackcheck(cpu_env
, addr
);
10187 static void op_addr_block_post(DisasContext
*s
, arg_ldst_block
*a
,
10188 TCGv_i32 addr
, int n
)
10194 /* post increment */
10195 tcg_gen_addi_i32(addr
, addr
, 4);
10197 /* post decrement */
10198 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
10200 } else if (!a
->i
&& n
!= 1) {
10201 /* pre decrement */
10202 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
10204 store_reg(s
, a
->rn
, addr
);
10206 tcg_temp_free_i32(addr
);
10210 static bool op_stm(DisasContext
*s
, arg_ldst_block
*a
, int min_n
)
10212 int i
, j
, n
, list
, mem_idx
;
10214 TCGv_i32 addr
, tmp
, tmp2
;
10219 /* Only usable in supervisor mode. */
10220 unallocated_encoding(s
);
10227 if (n
< min_n
|| a
->rn
== 15) {
10228 unallocated_encoding(s
);
10232 addr
= op_addr_block_pre(s
, a
, n
);
10233 mem_idx
= get_mem_index(s
);
10235 for (i
= j
= 0; i
< 16; i
++) {
10236 if (!(list
& (1 << i
))) {
10240 if (user
&& i
!= 15) {
10241 tmp
= tcg_temp_new_i32();
10242 tmp2
= tcg_const_i32(i
);
10243 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
10244 tcg_temp_free_i32(tmp2
);
10246 tmp
= load_reg(s
, i
);
10248 gen_aa32_st32(s
, tmp
, addr
, mem_idx
);
10249 tcg_temp_free_i32(tmp
);
10251 /* No need to add after the last transfer. */
10253 tcg_gen_addi_i32(addr
, addr
, 4);
10257 op_addr_block_post(s
, a
, addr
, n
);
10261 static bool trans_STM(DisasContext
*s
, arg_ldst_block
*a
)
10263 /* BitCount(list) < 1 is UNPREDICTABLE */
10264 return op_stm(s
, a
, 1);
10267 static bool trans_STM_t32(DisasContext
*s
, arg_ldst_block
*a
)
10269 /* Writeback register in register list is UNPREDICTABLE for T32. */
10270 if (a
->w
&& (a
->list
& (1 << a
->rn
))) {
10271 unallocated_encoding(s
);
10274 /* BitCount(list) < 2 is UNPREDICTABLE */
10275 return op_stm(s
, a
, 2);
10278 static bool do_ldm(DisasContext
*s
, arg_ldst_block
*a
, int min_n
)
10280 int i
, j
, n
, list
, mem_idx
;
10283 bool exc_return
= false;
10284 TCGv_i32 addr
, tmp
, tmp2
, loaded_var
;
10287 /* LDM (user), LDM (exception return) */
10289 /* Only usable in supervisor mode. */
10290 unallocated_encoding(s
);
10293 if (extract32(a
->list
, 15, 1)) {
10297 /* LDM (user) does not allow writeback. */
10299 unallocated_encoding(s
);
10307 if (n
< min_n
|| a
->rn
== 15) {
10308 unallocated_encoding(s
);
10312 addr
= op_addr_block_pre(s
, a
, n
);
10313 mem_idx
= get_mem_index(s
);
10314 loaded_base
= false;
10317 for (i
= j
= 0; i
< 16; i
++) {
10318 if (!(list
& (1 << i
))) {
10322 tmp
= tcg_temp_new_i32();
10323 gen_aa32_ld32u(s
, tmp
, addr
, mem_idx
);
10325 tmp2
= tcg_const_i32(i
);
10326 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
10327 tcg_temp_free_i32(tmp2
);
10328 tcg_temp_free_i32(tmp
);
10329 } else if (i
== a
->rn
) {
10331 loaded_base
= true;
10332 } else if (i
== 15 && exc_return
) {
10333 store_pc_exc_ret(s
, tmp
);
10335 store_reg_from_load(s
, i
, tmp
);
10338 /* No need to add after the last transfer. */
10340 tcg_gen_addi_i32(addr
, addr
, 4);
10344 op_addr_block_post(s
, a
, addr
, n
);
10347 /* Note that we reject base == pc above. */
10348 store_reg(s
, a
->rn
, loaded_var
);
10352 /* Restore CPSR from SPSR. */
10353 tmp
= load_cpu_field(spsr
);
10354 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
10357 gen_helper_cpsr_write_eret(cpu_env
, tmp
);
10358 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
10361 tcg_temp_free_i32(tmp
);
10362 /* Must exit loop to check un-masked IRQs */
10363 s
->base
.is_jmp
= DISAS_EXIT
;
10368 static bool trans_LDM_a32(DisasContext
*s
, arg_ldst_block
*a
)
10371 * Writeback register in register list is UNPREDICTABLE
10372 * for ArchVersion() >= 7. Prior to v7, A32 would write
10373 * an UNKNOWN value to the base register.
10375 if (ENABLE_ARCH_7
&& a
->w
&& (a
->list
& (1 << a
->rn
))) {
10376 unallocated_encoding(s
);
10379 /* BitCount(list) < 1 is UNPREDICTABLE */
10380 return do_ldm(s
, a
, 1);
10383 static bool trans_LDM_t32(DisasContext
*s
, arg_ldst_block
*a
)
10385 /* Writeback register in register list is UNPREDICTABLE for T32. */
10386 if (a
->w
&& (a
->list
& (1 << a
->rn
))) {
10387 unallocated_encoding(s
);
10390 /* BitCount(list) < 2 is UNPREDICTABLE */
10391 return do_ldm(s
, a
, 2);
10394 static bool trans_LDM_t16(DisasContext
*s
, arg_ldst_block
*a
)
10396 /* Writeback is conditional on the base register not being loaded. */
10397 a
->w
= !(a
->list
& (1 << a
->rn
));
10398 /* BitCount(list) < 1 is UNPREDICTABLE */
10399 return do_ldm(s
, a
, 1);
10403 * Branch, branch with link
10406 static bool trans_B(DisasContext
*s
, arg_i
*a
)
10408 gen_jmp(s
, read_pc(s
) + a
->imm
);
10412 static bool trans_B_cond_thumb(DisasContext
*s
, arg_ci
*a
)
10414 /* This has cond from encoding, required to be outside IT block. */
10415 if (a
->cond
>= 0xe) {
10418 if (s
->condexec_mask
) {
10419 unallocated_encoding(s
);
10422 arm_skip_unless(s
, a
->cond
);
10423 gen_jmp(s
, read_pc(s
) + a
->imm
);
10427 static bool trans_BL(DisasContext
*s
, arg_i
*a
)
10429 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| s
->thumb
);
10430 gen_jmp(s
, read_pc(s
) + a
->imm
);
10434 static bool trans_BLX_i(DisasContext
*s
, arg_BLX_i
*a
)
10438 /* For A32, ARCH(5) is checked near the start of the uncond block. */
10439 if (s
->thumb
&& (a
->imm
& 2)) {
10442 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| s
->thumb
);
10443 tmp
= tcg_const_i32(!s
->thumb
);
10444 store_cpu_field(tmp
, thumb
);
10445 gen_jmp(s
, (read_pc(s
) & ~3) + a
->imm
);
10449 static bool trans_BL_BLX_prefix(DisasContext
*s
, arg_BL_BLX_prefix
*a
)
10451 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
10452 tcg_gen_movi_i32(cpu_R
[14], read_pc(s
) + (a
->imm
<< 12));
10456 static bool trans_BL_suffix(DisasContext
*s
, arg_BL_suffix
*a
)
10458 TCGv_i32 tmp
= tcg_temp_new_i32();
10460 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
10461 tcg_gen_addi_i32(tmp
, cpu_R
[14], (a
->imm
<< 1) | 1);
10462 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| 1);
10467 static bool trans_BLX_suffix(DisasContext
*s
, arg_BLX_suffix
*a
)
10471 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
10472 if (!ENABLE_ARCH_5
) {
10475 tmp
= tcg_temp_new_i32();
10476 tcg_gen_addi_i32(tmp
, cpu_R
[14], a
->imm
<< 1);
10477 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
10478 tcg_gen_movi_i32(cpu_R
[14], s
->base
.pc_next
| 1);
10483 static bool op_tbranch(DisasContext
*s
, arg_tbranch
*a
, bool half
)
10485 TCGv_i32 addr
, tmp
;
10487 tmp
= load_reg(s
, a
->rm
);
10489 tcg_gen_add_i32(tmp
, tmp
, tmp
);
10491 addr
= load_reg(s
, a
->rn
);
10492 tcg_gen_add_i32(addr
, addr
, tmp
);
10494 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
),
10495 half
? MO_UW
| s
->be_data
: MO_UB
);
10496 tcg_temp_free_i32(addr
);
10498 tcg_gen_add_i32(tmp
, tmp
, tmp
);
10499 tcg_gen_addi_i32(tmp
, tmp
, read_pc(s
));
10500 store_reg(s
, 15, tmp
);
10504 static bool trans_TBB(DisasContext
*s
, arg_tbranch
*a
)
10506 return op_tbranch(s
, a
, false);
10509 static bool trans_TBH(DisasContext
*s
, arg_tbranch
*a
)
10511 return op_tbranch(s
, a
, true);
10514 static bool trans_CBZ(DisasContext
*s
, arg_CBZ
*a
)
10516 TCGv_i32 tmp
= load_reg(s
, a
->rn
);
10518 arm_gen_condlabel(s
);
10519 tcg_gen_brcondi_i32(a
->nz
? TCG_COND_EQ
: TCG_COND_NE
,
10520 tmp
, 0, s
->condlabel
);
10521 tcg_temp_free_i32(tmp
);
10522 gen_jmp(s
, read_pc(s
) + a
->imm
);
10527 * Supervisor call - both T32 & A32 come here so we need to check
10528 * which mode we are in when checking for semihosting.
10531 static bool trans_SVC(DisasContext
*s
, arg_SVC
*a
)
10533 const uint32_t semihost_imm
= s
->thumb
? 0xab : 0x123456;
10535 if (!arm_dc_feature(s
, ARM_FEATURE_M
) && semihosting_enabled() &&
10536 #ifndef CONFIG_USER_ONLY
10539 (a
->imm
== semihost_imm
)) {
10540 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
10542 gen_set_pc_im(s
, s
->base
.pc_next
);
10543 s
->svc_imm
= a
->imm
;
10544 s
->base
.is_jmp
= DISAS_SWI
;
10550 * Unconditional system instructions
10553 static bool trans_RFE(DisasContext
*s
, arg_RFE
*a
)
10555 static const int8_t pre_offset
[4] = {
10556 /* DA */ -4, /* IA */ 0, /* DB */ -8, /* IB */ 4
10558 static const int8_t post_offset
[4] = {
10559 /* DA */ -8, /* IA */ 4, /* DB */ -4, /* IB */ 0
10561 TCGv_i32 addr
, t1
, t2
;
10563 if (!ENABLE_ARCH_6
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
10567 unallocated_encoding(s
);
10571 addr
= load_reg(s
, a
->rn
);
10572 tcg_gen_addi_i32(addr
, addr
, pre_offset
[a
->pu
]);
10574 /* Load PC into tmp and CPSR into tmp2. */
10575 t1
= tcg_temp_new_i32();
10576 gen_aa32_ld32u(s
, t1
, addr
, get_mem_index(s
));
10577 tcg_gen_addi_i32(addr
, addr
, 4);
10578 t2
= tcg_temp_new_i32();
10579 gen_aa32_ld32u(s
, t2
, addr
, get_mem_index(s
));
10582 /* Base writeback. */
10583 tcg_gen_addi_i32(addr
, addr
, post_offset
[a
->pu
]);
10584 store_reg(s
, a
->rn
, addr
);
10586 tcg_temp_free_i32(addr
);
10588 gen_rfe(s
, t1
, t2
);
10592 static bool trans_SRS(DisasContext
*s
, arg_SRS
*a
)
10594 if (!ENABLE_ARCH_6
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
10597 gen_srs(s
, a
->mode
, a
->pu
, a
->w
);
10601 static bool trans_CPS(DisasContext
*s
, arg_CPS
*a
)
10603 uint32_t mask
, val
;
10605 if (!ENABLE_ARCH_6
|| arm_dc_feature(s
, ARM_FEATURE_M
)) {
10609 /* Implemented as NOP in user mode. */
10612 /* TODO: There are quite a lot of UNPREDICTABLE argument combinations. */
10634 gen_set_psr_im(s
, mask
, 0, val
);
10639 static bool trans_CPS_v7m(DisasContext
*s
, arg_CPS_v7m
*a
)
10641 TCGv_i32 tmp
, addr
, el
;
10643 if (!arm_dc_feature(s
, ARM_FEATURE_M
)) {
10647 /* Implemented as NOP in user mode. */
10651 tmp
= tcg_const_i32(a
->im
);
10654 addr
= tcg_const_i32(19);
10655 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
10656 tcg_temp_free_i32(addr
);
10660 addr
= tcg_const_i32(16);
10661 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
10662 tcg_temp_free_i32(addr
);
10664 el
= tcg_const_i32(s
->current_el
);
10665 gen_helper_rebuild_hflags_m32(cpu_env
, el
);
10666 tcg_temp_free_i32(el
);
10667 tcg_temp_free_i32(tmp
);
10673 * Clear-Exclusive, Barriers
10676 static bool trans_CLREX(DisasContext
*s
, arg_CLREX
*a
)
10679 ? !ENABLE_ARCH_7
&& !arm_dc_feature(s
, ARM_FEATURE_M
)
10680 : !ENABLE_ARCH_6K
) {
10687 static bool trans_DSB(DisasContext
*s
, arg_DSB
*a
)
10689 if (!ENABLE_ARCH_7
&& !arm_dc_feature(s
, ARM_FEATURE_M
)) {
10692 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
10696 static bool trans_DMB(DisasContext
*s
, arg_DMB
*a
)
10698 return trans_DSB(s
, NULL
);
10701 static bool trans_ISB(DisasContext
*s
, arg_ISB
*a
)
10703 if (!ENABLE_ARCH_7
&& !arm_dc_feature(s
, ARM_FEATURE_M
)) {
10707 * We need to break the TB after this insn to execute
10708 * self-modifying code correctly and also to take
10709 * any pending interrupts immediately.
10711 gen_goto_tb(s
, 0, s
->base
.pc_next
);
10715 static bool trans_SB(DisasContext
*s
, arg_SB
*a
)
10717 if (!dc_isar_feature(aa32_sb
, s
)) {
10721 * TODO: There is no speculation barrier opcode
10722 * for TCG; MB and end the TB instead.
10724 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
10725 gen_goto_tb(s
, 0, s
->base
.pc_next
);
10729 static bool trans_SETEND(DisasContext
*s
, arg_SETEND
*a
)
10731 if (!ENABLE_ARCH_6
) {
10734 if (a
->E
!= (s
->be_data
== MO_BE
)) {
10735 gen_helper_setend(cpu_env
);
10736 s
->base
.is_jmp
= DISAS_UPDATE
;
10742 * Preload instructions
10743 * All are nops, contingent on the appropriate arch level.
10746 static bool trans_PLD(DisasContext
*s
, arg_PLD
*a
)
10748 return ENABLE_ARCH_5TE
;
10751 static bool trans_PLDW(DisasContext
*s
, arg_PLD
*a
)
10753 return arm_dc_feature(s
, ARM_FEATURE_V7MP
);
10756 static bool trans_PLI(DisasContext
*s
, arg_PLD
*a
)
10758 return ENABLE_ARCH_7
;
10765 static bool trans_IT(DisasContext
*s
, arg_IT
*a
)
10767 int cond_mask
= a
->cond_mask
;
10770 * No actual code generated for this insn, just setup state.
10772 * Combinations of firstcond and mask which set up an 0b1111
10773 * condition are UNPREDICTABLE; we take the CONSTRAINED
10774 * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110,
10775 * i.e. both meaning "execute always".
10777 s
->condexec_cond
= (cond_mask
>> 4) & 0xe;
10778 s
->condexec_mask
= cond_mask
& 0x1f;
10786 static void disas_arm_insn(DisasContext
*s
, unsigned int insn
)
10788 unsigned int cond
= insn
>> 28;
10790 /* M variants do not implement ARM mode; this must raise the INVSTATE
10791 * UsageFault exception.
10793 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10794 gen_exception_insn(s
, s
->pc_curr
, EXCP_INVSTATE
, syn_uncategorized(),
10795 default_exception_el(s
));
10800 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
10801 * choose to UNDEF. In ARMv5 and above the space is used
10802 * for miscellaneous unconditional instructions.
10806 /* Unconditional instructions. */
10807 /* TODO: Perhaps merge these into one decodetree output file. */
10808 if (disas_a32_uncond(s
, insn
) ||
10809 disas_vfp_uncond(s
, insn
) ||
10810 disas_neon_dp(s
, insn
) ||
10811 disas_neon_ls(s
, insn
) ||
10812 disas_neon_shared(s
, insn
)) {
10815 /* fall back to legacy decoder */
10817 if (((insn
>> 25) & 7) == 1) {
10818 /* NEON Data processing. */
10819 if (disas_neon_data_insn(s
, insn
)) {
10824 if ((insn
& 0x0e000f00) == 0x0c000100) {
10825 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
10826 /* iWMMXt register transfer. */
10827 if (extract32(s
->c15_cpar
, 1, 1)) {
10828 if (!disas_iwmmxt_insn(s
, insn
)) {
10837 /* if not always execute, we generate a conditional jump to
10838 next instruction */
10839 arm_skip_unless(s
, cond
);
10842 /* TODO: Perhaps merge these into one decodetree output file. */
10843 if (disas_a32(s
, insn
) ||
10844 disas_vfp(s
, insn
)) {
10847 /* fall back to legacy decoder */
10849 switch ((insn
>> 24) & 0xf) {
10853 if (((insn
>> 8) & 0xe) == 10) {
10854 /* VFP, but failed disas_vfp. */
10857 if (disas_coproc_insn(s
, insn
)) {
10864 unallocated_encoding(s
);
10869 static bool thumb_insn_is_16bit(DisasContext
*s
, uint32_t pc
, uint32_t insn
)
10872 * Return true if this is a 16 bit instruction. We must be precise
10873 * about this (matching the decode).
10875 if ((insn
>> 11) < 0x1d) {
10876 /* Definitely a 16-bit instruction */
10880 /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
10881 * first half of a 32-bit Thumb insn. Thumb-1 cores might
10882 * end up actually treating this as two 16-bit insns, though,
10883 * if it's half of a bl/blx pair that might span a page boundary.
10885 if (arm_dc_feature(s
, ARM_FEATURE_THUMB2
) ||
10886 arm_dc_feature(s
, ARM_FEATURE_M
)) {
10887 /* Thumb2 cores (including all M profile ones) always treat
10888 * 32-bit insns as 32-bit.
10893 if ((insn
>> 11) == 0x1e && pc
- s
->page_start
< TARGET_PAGE_SIZE
- 3) {
10894 /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
10895 * is not on the next page; we merge this into a 32-bit
10900 /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
10901 * 0b1111_1xxx_xxxx_xxxx : BL suffix;
10902 * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
10903 * -- handle as single 16 bit insn
10908 /* Translate a 32-bit thumb instruction. */
10909 static void disas_thumb2_insn(DisasContext
*s
, uint32_t insn
)
10912 * ARMv6-M supports a limited subset of Thumb2 instructions.
10913 * Other Thumb1 architectures allow only 32-bit
10914 * combined BL/BLX prefix and suffix.
10916 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
10917 !arm_dc_feature(s
, ARM_FEATURE_V7
)) {
10919 bool found
= false;
10920 static const uint32_t armv6m_insn
[] = {0xf3808000 /* msr */,
10921 0xf3b08040 /* dsb */,
10922 0xf3b08050 /* dmb */,
10923 0xf3b08060 /* isb */,
10924 0xf3e08000 /* mrs */,
10925 0xf000d000 /* bl */};
10926 static const uint32_t armv6m_mask
[] = {0xffe0d000,
10933 for (i
= 0; i
< ARRAY_SIZE(armv6m_insn
); i
++) {
10934 if ((insn
& armv6m_mask
[i
]) == armv6m_insn
[i
]) {
10942 } else if ((insn
& 0xf800e800) != 0xf000e800) {
10946 if ((insn
& 0xef000000) == 0xef000000) {
10948 * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
10950 * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
10952 uint32_t a32_insn
= (insn
& 0xe2ffffff) |
10953 ((insn
& (1 << 28)) >> 4) | (1 << 28);
10955 if (disas_neon_dp(s
, a32_insn
)) {
10960 if ((insn
& 0xff100000) == 0xf9000000) {
10962 * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
10964 * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
10966 uint32_t a32_insn
= (insn
& 0x00ffffff) | 0xf4000000;
10968 if (disas_neon_ls(s
, a32_insn
)) {
10974 * TODO: Perhaps merge these into one decodetree output file.
10975 * Note disas_vfp is written for a32 with cond field in the
10976 * top nibble. The t32 encoding requires 0xe in the top nibble.
10978 if (disas_t32(s
, insn
) ||
10979 disas_vfp_uncond(s
, insn
) ||
10980 disas_neon_shared(s
, insn
) ||
10981 ((insn
>> 28) == 0xe && disas_vfp(s
, insn
))) {
10984 /* fall back to legacy decoder */
10986 switch ((insn
>> 25) & 0xf) {
10987 case 0: case 1: case 2: case 3:
10988 /* 16-bit instructions. Should never happen. */
10990 case 6: case 7: case 14: case 15:
10992 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
10993 /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */
10994 if (extract32(insn
, 24, 2) == 3) {
10995 goto illegal_op
; /* op0 = 0b11 : unallocated */
10998 if (((insn
>> 8) & 0xe) == 10 &&
10999 dc_isar_feature(aa32_fpsp_v2
, s
)) {
11000 /* FP, and the CPU supports it */
11003 /* All other insns: NOCP */
11004 gen_exception_insn(s
, s
->pc_curr
, EXCP_NOCP
,
11005 syn_uncategorized(),
11006 default_exception_el(s
));
11010 if (((insn
>> 24) & 3) == 3) {
11011 /* Translate into the equivalent ARM encoding. */
11012 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
11013 if (disas_neon_data_insn(s
, insn
)) {
11016 } else if (((insn
>> 8) & 0xe) == 10) {
11017 /* VFP, but failed disas_vfp. */
11020 if (insn
& (1 << 28))
11022 if (disas_coproc_insn(s
, insn
)) {
11031 unallocated_encoding(s
);
11035 static void disas_thumb_insn(DisasContext
*s
, uint32_t insn
)
11037 if (!disas_t16(s
, insn
)) {
11038 unallocated_encoding(s
);
11042 static bool insn_crosses_page(CPUARMState
*env
, DisasContext
*s
)
11044 /* Return true if the insn at dc->base.pc_next might cross a page boundary.
11045 * (False positives are OK, false negatives are not.)
11046 * We know this is a Thumb insn, and our caller ensures we are
11047 * only called if dc->base.pc_next is less than 4 bytes from the page
11048 * boundary, so we cross the page if the first 16 bits indicate
11049 * that this is a 32 bit insn.
11051 uint16_t insn
= arm_lduw_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
11053 return !thumb_insn_is_16bit(s
, s
->base
.pc_next
, insn
);
11056 static void arm_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
11058 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11059 CPUARMState
*env
= cs
->env_ptr
;
11060 ARMCPU
*cpu
= env_archcpu(env
);
11061 uint32_t tb_flags
= dc
->base
.tb
->flags
;
11062 uint32_t condexec
, core_mmu_idx
;
11064 dc
->isar
= &cpu
->isar
;
11068 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11069 * there is no secure EL1, so we route exceptions to EL3.
11071 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11072 !arm_el_is_aa64(env
, 3);
11073 dc
->thumb
= FIELD_EX32(tb_flags
, TBFLAG_AM32
, THUMB
);
11074 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
11075 condexec
= FIELD_EX32(tb_flags
, TBFLAG_AM32
, CONDEXEC
);
11076 dc
->condexec_mask
= (condexec
& 0xf) << 1;
11077 dc
->condexec_cond
= condexec
>> 4;
11079 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
11080 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
11081 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11082 #if !defined(CONFIG_USER_ONLY)
11083 dc
->user
= (dc
->current_el
== 0);
11085 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
11087 if (arm_feature(env
, ARM_FEATURE_M
)) {
11088 dc
->vfp_enabled
= 1;
11089 dc
->be_data
= MO_TE
;
11090 dc
->v7m_handler_mode
= FIELD_EX32(tb_flags
, TBFLAG_M32
, HANDLER
);
11091 dc
->v8m_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
11092 regime_is_secure(env
, dc
->mmu_idx
);
11093 dc
->v8m_stackcheck
= FIELD_EX32(tb_flags
, TBFLAG_M32
, STACKCHECK
);
11094 dc
->v8m_fpccr_s_wrong
=
11095 FIELD_EX32(tb_flags
, TBFLAG_M32
, FPCCR_S_WRONG
);
11096 dc
->v7m_new_fp_ctxt_needed
=
11097 FIELD_EX32(tb_flags
, TBFLAG_M32
, NEW_FP_CTXT_NEEDED
);
11098 dc
->v7m_lspact
= FIELD_EX32(tb_flags
, TBFLAG_M32
, LSPACT
);
11101 FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
11102 dc
->debug_target_el
=
11103 FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
11104 dc
->sctlr_b
= FIELD_EX32(tb_flags
, TBFLAG_A32
, SCTLR_B
);
11105 dc
->hstr_active
= FIELD_EX32(tb_flags
, TBFLAG_A32
, HSTR_ACTIVE
);
11106 dc
->ns
= FIELD_EX32(tb_flags
, TBFLAG_A32
, NS
);
11107 dc
->vfp_enabled
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VFPEN
);
11108 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
11109 dc
->c15_cpar
= FIELD_EX32(tb_flags
, TBFLAG_A32
, XSCALE_CPAR
);
11111 dc
->vec_len
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VECLEN
);
11112 dc
->vec_stride
= FIELD_EX32(tb_flags
, TBFLAG_A32
, VECSTRIDE
);
11115 dc
->cp_regs
= cpu
->cp_regs
;
11116 dc
->features
= env
->features
;
11118 /* Single step state. The code-generation logic here is:
11120 * generate code with no special handling for single-stepping (except
11121 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11122 * this happens anyway because those changes are all system register or
11124 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11125 * emit code for one insn
11126 * emit code to clear PSTATE.SS
11127 * emit code to generate software step exception for completed step
11128 * end TB (as usual for having generated an exception)
11129 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11130 * emit code to generate a software step exception
11133 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
11134 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
11135 dc
->is_ldex
= false;
11137 dc
->page_start
= dc
->base
.pc_first
& TARGET_PAGE_MASK
;
11139 /* If architectural single step active, limit to 1. */
11140 if (is_singlestepping(dc
)) {
11141 dc
->base
.max_insns
= 1;
11144 /* ARM is a fixed-length ISA. Bound the number of insns to execute
11145 to those left on the page. */
11147 int bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
11148 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
11151 cpu_V0
= tcg_temp_new_i64();
11152 cpu_V1
= tcg_temp_new_i64();
11153 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
11154 cpu_M0
= tcg_temp_new_i64();
11157 static void arm_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11159 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11161 /* A note on handling of the condexec (IT) bits:
11163 * We want to avoid the overhead of having to write the updated condexec
11164 * bits back to the CPUARMState for every instruction in an IT block. So:
11165 * (1) if the condexec bits are not already zero then we write
11166 * zero back into the CPUARMState now. This avoids complications trying
11167 * to do it at the end of the block. (For example if we don't do this
11168 * it's hard to identify whether we can safely skip writing condexec
11169 * at the end of the TB, which we definitely want to do for the case
11170 * where a TB doesn't do anything with the IT state at all.)
11171 * (2) if we are going to leave the TB then we call gen_set_condexec()
11172 * which will write the correct value into CPUARMState if zero is wrong.
11173 * This is done both for leaving the TB at the end, and for leaving
11174 * it because of an exception we know will happen, which is done in
11175 * gen_exception_insn(). The latter is necessary because we need to
11176 * leave the TB with the PC/IT state just prior to execution of the
11177 * instruction which caused the exception.
11178 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
11179 * then the CPUARMState will be wrong and we need to reset it.
11180 * This is handled in the same way as restoration of the
11181 * PC in these situations; we save the value of the condexec bits
11182 * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()
11183 * then uses this to restore them after an exception.
11185 * Note that there are no instructions which can read the condexec
11186 * bits, and none which can write non-static values to them, so
11187 * we don't need to care about whether CPUARMState is correct in the
11191 /* Reset the conditional execution bits immediately. This avoids
11192 complications trying to do it at the end of the block. */
11193 if (dc
->condexec_mask
|| dc
->condexec_cond
) {
11194 TCGv_i32 tmp
= tcg_temp_new_i32();
11195 tcg_gen_movi_i32(tmp
, 0);
11196 store_cpu_field(tmp
, condexec_bits
);
11200 static void arm_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
11202 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11204 tcg_gen_insn_start(dc
->base
.pc_next
,
11205 (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1),
11207 dc
->insn_start
= tcg_last_op();
11210 static bool arm_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
11211 const CPUBreakpoint
*bp
)
11213 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11215 if (bp
->flags
& BP_CPU
) {
11216 gen_set_condexec(dc
);
11217 gen_set_pc_im(dc
, dc
->base
.pc_next
);
11218 gen_helper_check_breakpoints(cpu_env
);
11219 /* End the TB early; it's likely not going to be executed */
11220 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
11222 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
11223 /* The address covered by the breakpoint must be
11224 included in [tb->pc, tb->pc + tb->size) in order
11225 to for it to be properly cleared -- thus we
11226 increment the PC here so that the logic setting
11227 tb->size below does the right thing. */
11228 /* TODO: Advance PC by correct instruction length to
11229 * avoid disassembler error messages */
11230 dc
->base
.pc_next
+= 2;
11231 dc
->base
.is_jmp
= DISAS_NORETURN
;
11237 static bool arm_pre_translate_insn(DisasContext
*dc
)
11239 #ifdef CONFIG_USER_ONLY
11240 /* Intercept jump to the magic kernel page. */
11241 if (dc
->base
.pc_next
>= 0xffff0000) {
11242 /* We always get here via a jump, so know we are not in a
11243 conditional execution block. */
11244 gen_exception_internal(EXCP_KERNEL_TRAP
);
11245 dc
->base
.is_jmp
= DISAS_NORETURN
;
11250 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11251 /* Singlestep state is Active-pending.
11252 * If we're in this state at the start of a TB then either
11253 * a) we just took an exception to an EL which is being debugged
11254 * and this is the first insn in the exception handler
11255 * b) debug exceptions were masked and we just unmasked them
11256 * without changing EL (eg by clearing PSTATE.D)
11257 * In either case we're going to take a swstep exception in the
11258 * "did not step an insn" case, and so the syndrome ISV and EX
11259 * bits should be zero.
11261 assert(dc
->base
.num_insns
== 1);
11262 gen_swstep_exception(dc
, 0, 0);
11263 dc
->base
.is_jmp
= DISAS_NORETURN
;
11270 static void arm_post_translate_insn(DisasContext
*dc
)
11272 if (dc
->condjmp
&& !dc
->base
.is_jmp
) {
11273 gen_set_label(dc
->condlabel
);
11276 translator_loop_temp_check(&dc
->base
);
11279 static void arm_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
11281 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11282 CPUARMState
*env
= cpu
->env_ptr
;
11285 if (arm_pre_translate_insn(dc
)) {
11289 dc
->pc_curr
= dc
->base
.pc_next
;
11290 insn
= arm_ldl_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
11292 dc
->base
.pc_next
+= 4;
11293 disas_arm_insn(dc
, insn
);
11295 arm_post_translate_insn(dc
);
11297 /* ARM is a fixed-length ISA. We performed the cross-page check
11298 in init_disas_context by adjusting max_insns. */
11301 static bool thumb_insn_is_unconditional(DisasContext
*s
, uint32_t insn
)
11303 /* Return true if this Thumb insn is always unconditional,
11304 * even inside an IT block. This is true of only a very few
11305 * instructions: BKPT, HLT, and SG.
11307 * A larger class of instructions are UNPREDICTABLE if used
11308 * inside an IT block; we do not need to detect those here, because
11309 * what we do by default (perform the cc check and update the IT
11310 * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
11311 * choice for those situations.
11313 * insn is either a 16-bit or a 32-bit instruction; the two are
11314 * distinguishable because for the 16-bit case the top 16 bits
11315 * are zeroes, and that isn't a valid 32-bit encoding.
11317 if ((insn
& 0xffffff00) == 0xbe00) {
11322 if ((insn
& 0xffffffc0) == 0xba80 && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
11323 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
11324 /* HLT: v8A only. This is unconditional even when it is going to
11325 * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
11326 * For v7 cores this was a plain old undefined encoding and so
11327 * honours its cc check. (We might be using the encoding as
11328 * a semihosting trap, but we don't change the cc check behaviour
11329 * on that account, because a debugger connected to a real v7A
11330 * core and emulating semihosting traps by catching the UNDEF
11331 * exception would also only see cases where the cc check passed.
11332 * No guest code should be trying to do a HLT semihosting trap
11333 * in an IT block anyway.
11338 if (insn
== 0xe97fe97f && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
11339 arm_dc_feature(s
, ARM_FEATURE_M
)) {
11347 static void thumb_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
11349 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11350 CPUARMState
*env
= cpu
->env_ptr
;
11354 if (arm_pre_translate_insn(dc
)) {
11358 dc
->pc_curr
= dc
->base
.pc_next
;
11359 insn
= arm_lduw_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
11360 is_16bit
= thumb_insn_is_16bit(dc
, dc
->base
.pc_next
, insn
);
11361 dc
->base
.pc_next
+= 2;
11363 uint32_t insn2
= arm_lduw_code(env
, dc
->base
.pc_next
, dc
->sctlr_b
);
11365 insn
= insn
<< 16 | insn2
;
11366 dc
->base
.pc_next
+= 2;
11370 if (dc
->condexec_mask
&& !thumb_insn_is_unconditional(dc
, insn
)) {
11371 uint32_t cond
= dc
->condexec_cond
;
11374 * Conditionally skip the insn. Note that both 0xe and 0xf mean
11375 * "always"; 0xf is not "never".
11378 arm_skip_unless(dc
, cond
);
11383 disas_thumb_insn(dc
, insn
);
11385 disas_thumb2_insn(dc
, insn
);
11388 /* Advance the Thumb condexec condition. */
11389 if (dc
->condexec_mask
) {
11390 dc
->condexec_cond
= ((dc
->condexec_cond
& 0xe) |
11391 ((dc
->condexec_mask
>> 4) & 1));
11392 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
11393 if (dc
->condexec_mask
== 0) {
11394 dc
->condexec_cond
= 0;
11398 arm_post_translate_insn(dc
);
11400 /* Thumb is a variable-length ISA. Stop translation when the next insn
11401 * will touch a new page. This ensures that prefetch aborts occur at
11404 * We want to stop the TB if the next insn starts in a new page,
11405 * or if it spans between this page and the next. This means that
11406 * if we're looking at the last halfword in the page we need to
11407 * see if it's a 16-bit Thumb insn (which will fit in this TB)
11408 * or a 32-bit Thumb insn (which won't).
11409 * This is to avoid generating a silly TB with a single 16-bit insn
11410 * in it at the end of this page (which would execute correctly
11411 * but isn't very efficient).
11413 if (dc
->base
.is_jmp
== DISAS_NEXT
11414 && (dc
->base
.pc_next
- dc
->page_start
>= TARGET_PAGE_SIZE
11415 || (dc
->base
.pc_next
- dc
->page_start
>= TARGET_PAGE_SIZE
- 3
11416 && insn_crosses_page(env
, dc
)))) {
11417 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
11421 static void arm_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
11423 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11425 if (tb_cflags(dc
->base
.tb
) & CF_LAST_IO
&& dc
->condjmp
) {
11426 /* FIXME: This can theoretically happen with self-modifying code. */
11427 cpu_abort(cpu
, "IO on conditional branch instruction");
11430 /* At this stage dc->condjmp will only be set when the skipped
11431 instruction was a conditional branch or trap, and the PC has
11432 already been written. */
11433 gen_set_condexec(dc
);
11434 if (dc
->base
.is_jmp
== DISAS_BX_EXCRET
) {
11435 /* Exception return branches need some special case code at the
11436 * end of the TB, which is complex enough that it has to
11437 * handle the single-step vs not and the condition-failed
11438 * insn codepath itself.
11440 gen_bx_excret_final_code(dc
);
11441 } else if (unlikely(is_singlestepping(dc
))) {
11442 /* Unconditional and "condition passed" instruction codepath. */
11443 switch (dc
->base
.is_jmp
) {
11445 gen_ss_advance(dc
);
11446 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
11447 default_exception_el(dc
));
11450 gen_ss_advance(dc
);
11451 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
11454 gen_ss_advance(dc
);
11455 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
11458 case DISAS_TOO_MANY
:
11460 gen_set_pc_im(dc
, dc
->base
.pc_next
);
11463 /* FIXME: Single stepping a WFI insn will not halt the CPU. */
11464 gen_singlestep_exception(dc
);
11466 case DISAS_NORETURN
:
11470 /* While branches must always occur at the end of an IT block,
11471 there are a few other things that can cause us to terminate
11472 the TB in the middle of an IT block:
11473 - Exception generating instructions (bkpt, swi, undefined).
11475 - Hardware watchpoints.
11476 Hardware breakpoints have already been handled and skip this code.
11478 switch(dc
->base
.is_jmp
) {
11480 case DISAS_TOO_MANY
:
11481 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
11487 gen_set_pc_im(dc
, dc
->base
.pc_next
);
11490 /* indicate that the hash table must be used to find the next TB */
11491 tcg_gen_exit_tb(NULL
, 0);
11493 case DISAS_NORETURN
:
11494 /* nothing more to generate */
11498 TCGv_i32 tmp
= tcg_const_i32((dc
->thumb
&&
11499 !(dc
->insn
& (1U << 31))) ? 2 : 4);
11501 gen_helper_wfi(cpu_env
, tmp
);
11502 tcg_temp_free_i32(tmp
);
11503 /* The helper doesn't necessarily throw an exception, but we
11504 * must go back to the main loop to check for interrupts anyway.
11506 tcg_gen_exit_tb(NULL
, 0);
11510 gen_helper_wfe(cpu_env
);
11513 gen_helper_yield(cpu_env
);
11516 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
11517 default_exception_el(dc
));
11520 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
11523 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
11529 /* "Condition failed" instruction codepath for the branch/trap insn */
11530 gen_set_label(dc
->condlabel
);
11531 gen_set_condexec(dc
);
11532 if (unlikely(is_singlestepping(dc
))) {
11533 gen_set_pc_im(dc
, dc
->base
.pc_next
);
11534 gen_singlestep_exception(dc
);
11536 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
11541 static void arm_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
11543 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
11545 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
11546 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
11549 static const TranslatorOps arm_translator_ops
= {
11550 .init_disas_context
= arm_tr_init_disas_context
,
11551 .tb_start
= arm_tr_tb_start
,
11552 .insn_start
= arm_tr_insn_start
,
11553 .breakpoint_check
= arm_tr_breakpoint_check
,
11554 .translate_insn
= arm_tr_translate_insn
,
11555 .tb_stop
= arm_tr_tb_stop
,
11556 .disas_log
= arm_tr_disas_log
,
11559 static const TranslatorOps thumb_translator_ops
= {
11560 .init_disas_context
= arm_tr_init_disas_context
,
11561 .tb_start
= arm_tr_tb_start
,
11562 .insn_start
= arm_tr_insn_start
,
11563 .breakpoint_check
= arm_tr_breakpoint_check
,
11564 .translate_insn
= thumb_tr_translate_insn
,
11565 .tb_stop
= arm_tr_tb_stop
,
11566 .disas_log
= arm_tr_disas_log
,
11569 /* generate intermediate code for basic block 'tb'. */
11570 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int max_insns
)
11572 DisasContext dc
= { };
11573 const TranslatorOps
*ops
= &arm_translator_ops
;
11575 if (FIELD_EX32(tb
->flags
, TBFLAG_AM32
, THUMB
)) {
11576 ops
= &thumb_translator_ops
;
11578 #ifdef TARGET_AARCH64
11579 if (FIELD_EX32(tb
->flags
, TBFLAG_ANY
, AARCH64_STATE
)) {
11580 ops
= &aarch64_translator_ops
;
11584 translator_loop(ops
, &dc
.base
, cpu
, tb
, max_insns
);
11587 void restore_state_to_opc(CPUARMState
*env
, TranslationBlock
*tb
,
11588 target_ulong
*data
)
11592 env
->condexec_bits
= 0;
11593 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
11595 env
->regs
[15] = data
[0];
11596 env
->condexec_bits
= data
[1];
11597 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;