4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "internals.h"
25 #include "disas/disas.h"
26 #include "exec/exec-all.h"
28 #include "tcg-op-gvec.h"
30 #include "qemu/bitops.h"
32 #include "exec/semihost.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
41 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T)
42 #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5)
43 /* currently all emulated v5 cores are also v5TE, so don't bother */
44 #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5)
45 #define ENABLE_ARCH_5J dc_isar_feature(jazelle, s)
46 #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6)
47 #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K)
48 #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2)
49 #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7)
50 #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8)
52 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
54 #include "translate.h"
56 #if defined(CONFIG_USER_ONLY)
59 #define IS_USER(s) (s->user)
62 /* We reuse the same 64-bit temporaries for efficiency. */
63 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
64 static TCGv_i32 cpu_R
[16];
65 TCGv_i32 cpu_CF
, cpu_NF
, cpu_VF
, cpu_ZF
;
66 TCGv_i64 cpu_exclusive_addr
;
67 TCGv_i64 cpu_exclusive_val
;
69 /* FIXME: These should be removed. */
70 static TCGv_i32 cpu_F0s
, cpu_F1s
;
71 static TCGv_i64 cpu_F0d
, cpu_F1d
;
73 #include "exec/gen-icount.h"
75 static const char * const regnames
[] =
76 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
79 /* Function prototypes for gen_ functions calling Neon helpers. */
80 typedef void NeonGenThreeOpEnvFn(TCGv_i32
, TCGv_env
, TCGv_i32
,
83 /* initialize TCG globals. */
84 void arm_translate_init(void)
88 for (i
= 0; i
< 16; i
++) {
89 cpu_R
[i
] = tcg_global_mem_new_i32(cpu_env
,
90 offsetof(CPUARMState
, regs
[i
]),
93 cpu_CF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, CF
), "CF");
94 cpu_NF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, NF
), "NF");
95 cpu_VF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, VF
), "VF");
96 cpu_ZF
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUARMState
, ZF
), "ZF");
98 cpu_exclusive_addr
= tcg_global_mem_new_i64(cpu_env
,
99 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
100 cpu_exclusive_val
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
103 a64_translate_init();
106 /* Flags for the disas_set_da_iss info argument:
107 * lower bits hold the Rt register number, higher bits are flags.
109 typedef enum ISSInfo
{
112 ISSInvalid
= (1 << 5),
113 ISSIsAcqRel
= (1 << 6),
114 ISSIsWrite
= (1 << 7),
115 ISSIs16Bit
= (1 << 8),
118 /* Save the syndrome information for a Data Abort */
119 static void disas_set_da_iss(DisasContext
*s
, TCGMemOp memop
, ISSInfo issinfo
)
122 int sas
= memop
& MO_SIZE
;
123 bool sse
= memop
& MO_SIGN
;
124 bool is_acqrel
= issinfo
& ISSIsAcqRel
;
125 bool is_write
= issinfo
& ISSIsWrite
;
126 bool is_16bit
= issinfo
& ISSIs16Bit
;
127 int srt
= issinfo
& ISSRegMask
;
129 if (issinfo
& ISSInvalid
) {
130 /* Some callsites want to conditionally provide ISS info,
131 * eg "only if this was not a writeback"
137 /* For AArch32, insns where the src/dest is R15 never generate
138 * ISS information. Catching that here saves checking at all
144 syn
= syn_data_abort_with_iss(0, sas
, sse
, srt
, 0, is_acqrel
,
145 0, 0, 0, is_write
, 0, is_16bit
);
146 disas_set_insn_syndrome(s
, syn
);
149 static inline int get_a32_user_mem_index(DisasContext
*s
)
151 /* Return the core mmu_idx to use for A32/T32 "unprivileged load/store"
153 * if PL2, UNPREDICTABLE (we choose to implement as if PL0)
154 * otherwise, access as if at PL0.
156 switch (s
->mmu_idx
) {
157 case ARMMMUIdx_S1E2
: /* this one is UNPREDICTABLE */
158 case ARMMMUIdx_S12NSE0
:
159 case ARMMMUIdx_S12NSE1
:
160 return arm_to_core_mmu_idx(ARMMMUIdx_S12NSE0
);
162 case ARMMMUIdx_S1SE0
:
163 case ARMMMUIdx_S1SE1
:
164 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0
);
165 case ARMMMUIdx_MUser
:
166 case ARMMMUIdx_MPriv
:
167 return arm_to_core_mmu_idx(ARMMMUIdx_MUser
);
168 case ARMMMUIdx_MUserNegPri
:
169 case ARMMMUIdx_MPrivNegPri
:
170 return arm_to_core_mmu_idx(ARMMMUIdx_MUserNegPri
);
171 case ARMMMUIdx_MSUser
:
172 case ARMMMUIdx_MSPriv
:
173 return arm_to_core_mmu_idx(ARMMMUIdx_MSUser
);
174 case ARMMMUIdx_MSUserNegPri
:
175 case ARMMMUIdx_MSPrivNegPri
:
176 return arm_to_core_mmu_idx(ARMMMUIdx_MSUserNegPri
);
179 g_assert_not_reached();
183 static inline TCGv_i32
load_cpu_offset(int offset
)
185 TCGv_i32 tmp
= tcg_temp_new_i32();
186 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
190 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
192 static inline void store_cpu_offset(TCGv_i32 var
, int offset
)
194 tcg_gen_st_i32(var
, cpu_env
, offset
);
195 tcg_temp_free_i32(var
);
198 #define store_cpu_field(var, name) \
199 store_cpu_offset(var, offsetof(CPUARMState, name))
201 /* Set a variable to the value of a CPU register. */
202 static void load_reg_var(DisasContext
*s
, TCGv_i32 var
, int reg
)
206 /* normally, since we updated PC, we need only to add one insn */
208 addr
= (long)s
->pc
+ 2;
210 addr
= (long)s
->pc
+ 4;
211 tcg_gen_movi_i32(var
, addr
);
213 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
217 /* Create a new temporary and set it to the value of a CPU register. */
218 static inline TCGv_i32
load_reg(DisasContext
*s
, int reg
)
220 TCGv_i32 tmp
= tcg_temp_new_i32();
221 load_reg_var(s
, tmp
, reg
);
225 /* Set a CPU register. The source must be a temporary and will be
227 static void store_reg(DisasContext
*s
, int reg
, TCGv_i32 var
)
230 /* In Thumb mode, we must ignore bit 0.
231 * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0]
232 * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0].
233 * We choose to ignore [1:0] in ARM mode for all architecture versions.
235 tcg_gen_andi_i32(var
, var
, s
->thumb
? ~1 : ~3);
236 s
->base
.is_jmp
= DISAS_JUMP
;
238 tcg_gen_mov_i32(cpu_R
[reg
], var
);
239 tcg_temp_free_i32(var
);
243 * Variant of store_reg which applies v8M stack-limit checks before updating
244 * SP. If the check fails this will result in an exception being taken.
245 * We disable the stack checks for CONFIG_USER_ONLY because we have
246 * no idea what the stack limits should be in that case.
247 * If stack checking is not being done this just acts like store_reg().
249 static void store_sp_checked(DisasContext
*s
, TCGv_i32 var
)
251 #ifndef CONFIG_USER_ONLY
252 if (s
->v8m_stackcheck
) {
253 gen_helper_v8m_stackcheck(cpu_env
, var
);
256 store_reg(s
, 13, var
);
259 /* Value extensions. */
260 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
261 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
262 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
263 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
265 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
266 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
269 static inline void gen_set_cpsr(TCGv_i32 var
, uint32_t mask
)
271 TCGv_i32 tmp_mask
= tcg_const_i32(mask
);
272 gen_helper_cpsr_write(cpu_env
, var
, tmp_mask
);
273 tcg_temp_free_i32(tmp_mask
);
275 /* Set NZCV flags from the high 4 bits of var. */
276 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
278 static void gen_exception_internal(int excp
)
280 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
282 assert(excp_is_internal(excp
));
283 gen_helper_exception_internal(cpu_env
, tcg_excp
);
284 tcg_temp_free_i32(tcg_excp
);
287 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
289 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
290 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
291 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
293 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
296 tcg_temp_free_i32(tcg_el
);
297 tcg_temp_free_i32(tcg_syn
);
298 tcg_temp_free_i32(tcg_excp
);
301 static void gen_ss_advance(DisasContext
*s
)
303 /* If the singlestep state is Active-not-pending, advance to
308 gen_helper_clear_pstate_ss(cpu_env
);
312 static void gen_step_complete_exception(DisasContext
*s
)
314 /* We just completed step of an insn. Move from Active-not-pending
315 * to Active-pending, and then also take the swstep exception.
316 * This corresponds to making the (IMPDEF) choice to prioritize
317 * swstep exceptions over asynchronous exceptions taken to an exception
318 * level where debug is disabled. This choice has the advantage that
319 * we do not need to maintain internal state corresponding to the
320 * ISV/EX syndrome bits between completion of the step and generation
321 * of the exception, and our syndrome information is always correct.
324 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
325 default_exception_el(s
));
326 s
->base
.is_jmp
= DISAS_NORETURN
;
329 static void gen_singlestep_exception(DisasContext
*s
)
331 /* Generate the right kind of exception for singlestep, which is
332 * either the architectural singlestep or EXCP_DEBUG for QEMU's
333 * gdb singlestepping.
336 gen_step_complete_exception(s
);
338 gen_exception_internal(EXCP_DEBUG
);
342 static inline bool is_singlestepping(DisasContext
*s
)
344 /* Return true if we are singlestepping either because of
345 * architectural singlestep or QEMU gdbstub singlestep. This does
346 * not include the command line '-singlestep' mode which is rather
347 * misnamed as it only means "one instruction per TB" and doesn't
348 * affect the code we generate.
350 return s
->base
.singlestep_enabled
|| s
->ss_active
;
353 static void gen_smul_dual(TCGv_i32 a
, TCGv_i32 b
)
355 TCGv_i32 tmp1
= tcg_temp_new_i32();
356 TCGv_i32 tmp2
= tcg_temp_new_i32();
357 tcg_gen_ext16s_i32(tmp1
, a
);
358 tcg_gen_ext16s_i32(tmp2
, b
);
359 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
360 tcg_temp_free_i32(tmp2
);
361 tcg_gen_sari_i32(a
, a
, 16);
362 tcg_gen_sari_i32(b
, b
, 16);
363 tcg_gen_mul_i32(b
, b
, a
);
364 tcg_gen_mov_i32(a
, tmp1
);
365 tcg_temp_free_i32(tmp1
);
368 /* Byteswap each halfword. */
369 static void gen_rev16(TCGv_i32 var
)
371 TCGv_i32 tmp
= tcg_temp_new_i32();
372 TCGv_i32 mask
= tcg_const_i32(0x00ff00ff);
373 tcg_gen_shri_i32(tmp
, var
, 8);
374 tcg_gen_and_i32(tmp
, tmp
, mask
);
375 tcg_gen_and_i32(var
, var
, mask
);
376 tcg_gen_shli_i32(var
, var
, 8);
377 tcg_gen_or_i32(var
, var
, tmp
);
378 tcg_temp_free_i32(mask
);
379 tcg_temp_free_i32(tmp
);
382 /* Byteswap low halfword and sign extend. */
383 static void gen_revsh(TCGv_i32 var
)
385 tcg_gen_ext16u_i32(var
, var
);
386 tcg_gen_bswap16_i32(var
, var
);
387 tcg_gen_ext16s_i32(var
, var
);
390 /* Return (b << 32) + a. Mark inputs as dead */
391 static TCGv_i64
gen_addq_msw(TCGv_i64 a
, TCGv_i32 b
)
393 TCGv_i64 tmp64
= tcg_temp_new_i64();
395 tcg_gen_extu_i32_i64(tmp64
, b
);
396 tcg_temp_free_i32(b
);
397 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
398 tcg_gen_add_i64(a
, tmp64
, a
);
400 tcg_temp_free_i64(tmp64
);
404 /* Return (b << 32) - a. Mark inputs as dead. */
405 static TCGv_i64
gen_subq_msw(TCGv_i64 a
, TCGv_i32 b
)
407 TCGv_i64 tmp64
= tcg_temp_new_i64();
409 tcg_gen_extu_i32_i64(tmp64
, b
);
410 tcg_temp_free_i32(b
);
411 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
412 tcg_gen_sub_i64(a
, tmp64
, a
);
414 tcg_temp_free_i64(tmp64
);
418 /* 32x32->64 multiply. Marks inputs as dead. */
419 static TCGv_i64
gen_mulu_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
421 TCGv_i32 lo
= tcg_temp_new_i32();
422 TCGv_i32 hi
= tcg_temp_new_i32();
425 tcg_gen_mulu2_i32(lo
, hi
, a
, b
);
426 tcg_temp_free_i32(a
);
427 tcg_temp_free_i32(b
);
429 ret
= tcg_temp_new_i64();
430 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
431 tcg_temp_free_i32(lo
);
432 tcg_temp_free_i32(hi
);
437 static TCGv_i64
gen_muls_i64_i32(TCGv_i32 a
, TCGv_i32 b
)
439 TCGv_i32 lo
= tcg_temp_new_i32();
440 TCGv_i32 hi
= tcg_temp_new_i32();
443 tcg_gen_muls2_i32(lo
, hi
, a
, b
);
444 tcg_temp_free_i32(a
);
445 tcg_temp_free_i32(b
);
447 ret
= tcg_temp_new_i64();
448 tcg_gen_concat_i32_i64(ret
, lo
, hi
);
449 tcg_temp_free_i32(lo
);
450 tcg_temp_free_i32(hi
);
455 /* Swap low and high halfwords. */
456 static void gen_swap_half(TCGv_i32 var
)
458 TCGv_i32 tmp
= tcg_temp_new_i32();
459 tcg_gen_shri_i32(tmp
, var
, 16);
460 tcg_gen_shli_i32(var
, var
, 16);
461 tcg_gen_or_i32(var
, var
, tmp
);
462 tcg_temp_free_i32(tmp
);
465 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
466 tmp = (t0 ^ t1) & 0x8000;
469 t0 = (t0 + t1) ^ tmp;
472 static void gen_add16(TCGv_i32 t0
, TCGv_i32 t1
)
474 TCGv_i32 tmp
= tcg_temp_new_i32();
475 tcg_gen_xor_i32(tmp
, t0
, t1
);
476 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
477 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
478 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
479 tcg_gen_add_i32(t0
, t0
, t1
);
480 tcg_gen_xor_i32(t0
, t0
, tmp
);
481 tcg_temp_free_i32(tmp
);
482 tcg_temp_free_i32(t1
);
485 /* Set CF to the top bit of var. */
486 static void gen_set_CF_bit31(TCGv_i32 var
)
488 tcg_gen_shri_i32(cpu_CF
, var
, 31);
491 /* Set N and Z flags from var. */
492 static inline void gen_logic_CC(TCGv_i32 var
)
494 tcg_gen_mov_i32(cpu_NF
, var
);
495 tcg_gen_mov_i32(cpu_ZF
, var
);
499 static void gen_adc(TCGv_i32 t0
, TCGv_i32 t1
)
501 tcg_gen_add_i32(t0
, t0
, t1
);
502 tcg_gen_add_i32(t0
, t0
, cpu_CF
);
505 /* dest = T0 + T1 + CF. */
506 static void gen_add_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
508 tcg_gen_add_i32(dest
, t0
, t1
);
509 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
512 /* dest = T0 - T1 + CF - 1. */
513 static void gen_sub_carry(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
515 tcg_gen_sub_i32(dest
, t0
, t1
);
516 tcg_gen_add_i32(dest
, dest
, cpu_CF
);
517 tcg_gen_subi_i32(dest
, dest
, 1);
520 /* dest = T0 + T1. Compute C, N, V and Z flags */
521 static void gen_add_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
523 TCGv_i32 tmp
= tcg_temp_new_i32();
524 tcg_gen_movi_i32(tmp
, 0);
525 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, t1
, tmp
);
526 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
527 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
528 tcg_gen_xor_i32(tmp
, t0
, t1
);
529 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
530 tcg_temp_free_i32(tmp
);
531 tcg_gen_mov_i32(dest
, cpu_NF
);
534 /* dest = T0 + T1 + CF. Compute C, N, V and Z flags */
535 static void gen_adc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
537 TCGv_i32 tmp
= tcg_temp_new_i32();
538 if (TCG_TARGET_HAS_add2_i32
) {
539 tcg_gen_movi_i32(tmp
, 0);
540 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0
, tmp
, cpu_CF
, tmp
);
541 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1
, tmp
);
543 TCGv_i64 q0
= tcg_temp_new_i64();
544 TCGv_i64 q1
= tcg_temp_new_i64();
545 tcg_gen_extu_i32_i64(q0
, t0
);
546 tcg_gen_extu_i32_i64(q1
, t1
);
547 tcg_gen_add_i64(q0
, q0
, q1
);
548 tcg_gen_extu_i32_i64(q1
, cpu_CF
);
549 tcg_gen_add_i64(q0
, q0
, q1
);
550 tcg_gen_extr_i64_i32(cpu_NF
, cpu_CF
, q0
);
551 tcg_temp_free_i64(q0
);
552 tcg_temp_free_i64(q1
);
554 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
555 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
556 tcg_gen_xor_i32(tmp
, t0
, t1
);
557 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
558 tcg_temp_free_i32(tmp
);
559 tcg_gen_mov_i32(dest
, cpu_NF
);
562 /* dest = T0 - T1. Compute C, N, V and Z flags */
563 static void gen_sub_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
566 tcg_gen_sub_i32(cpu_NF
, t0
, t1
);
567 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
568 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0
, t1
);
569 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0
);
570 tmp
= tcg_temp_new_i32();
571 tcg_gen_xor_i32(tmp
, t0
, t1
);
572 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
573 tcg_temp_free_i32(tmp
);
574 tcg_gen_mov_i32(dest
, cpu_NF
);
577 /* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */
578 static void gen_sbc_CC(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
580 TCGv_i32 tmp
= tcg_temp_new_i32();
581 tcg_gen_not_i32(tmp
, t1
);
582 gen_adc_CC(dest
, t0
, tmp
);
583 tcg_temp_free_i32(tmp
);
586 #define GEN_SHIFT(name) \
587 static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \
589 TCGv_i32 tmp1, tmp2, tmp3; \
590 tmp1 = tcg_temp_new_i32(); \
591 tcg_gen_andi_i32(tmp1, t1, 0xff); \
592 tmp2 = tcg_const_i32(0); \
593 tmp3 = tcg_const_i32(0x1f); \
594 tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \
595 tcg_temp_free_i32(tmp3); \
596 tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \
597 tcg_gen_##name##_i32(dest, tmp2, tmp1); \
598 tcg_temp_free_i32(tmp2); \
599 tcg_temp_free_i32(tmp1); \
605 static void gen_sar(TCGv_i32 dest
, TCGv_i32 t0
, TCGv_i32 t1
)
608 tmp1
= tcg_temp_new_i32();
609 tcg_gen_andi_i32(tmp1
, t1
, 0xff);
610 tmp2
= tcg_const_i32(0x1f);
611 tcg_gen_movcond_i32(TCG_COND_GTU
, tmp1
, tmp1
, tmp2
, tmp2
, tmp1
);
612 tcg_temp_free_i32(tmp2
);
613 tcg_gen_sar_i32(dest
, t0
, tmp1
);
614 tcg_temp_free_i32(tmp1
);
617 static void tcg_gen_abs_i32(TCGv_i32 dest
, TCGv_i32 src
)
619 TCGv_i32 c0
= tcg_const_i32(0);
620 TCGv_i32 tmp
= tcg_temp_new_i32();
621 tcg_gen_neg_i32(tmp
, src
);
622 tcg_gen_movcond_i32(TCG_COND_GT
, dest
, src
, c0
, src
, tmp
);
623 tcg_temp_free_i32(c0
);
624 tcg_temp_free_i32(tmp
);
627 static void shifter_out_im(TCGv_i32 var
, int shift
)
630 tcg_gen_andi_i32(cpu_CF
, var
, 1);
632 tcg_gen_shri_i32(cpu_CF
, var
, shift
);
634 tcg_gen_andi_i32(cpu_CF
, cpu_CF
, 1);
639 /* Shift by immediate. Includes special handling for shift == 0. */
640 static inline void gen_arm_shift_im(TCGv_i32 var
, int shiftop
,
641 int shift
, int flags
)
647 shifter_out_im(var
, 32 - shift
);
648 tcg_gen_shli_i32(var
, var
, shift
);
654 tcg_gen_shri_i32(cpu_CF
, var
, 31);
656 tcg_gen_movi_i32(var
, 0);
659 shifter_out_im(var
, shift
- 1);
660 tcg_gen_shri_i32(var
, var
, shift
);
667 shifter_out_im(var
, shift
- 1);
670 tcg_gen_sari_i32(var
, var
, shift
);
672 case 3: /* ROR/RRX */
675 shifter_out_im(var
, shift
- 1);
676 tcg_gen_rotri_i32(var
, var
, shift
); break;
678 TCGv_i32 tmp
= tcg_temp_new_i32();
679 tcg_gen_shli_i32(tmp
, cpu_CF
, 31);
681 shifter_out_im(var
, 0);
682 tcg_gen_shri_i32(var
, var
, 1);
683 tcg_gen_or_i32(var
, var
, tmp
);
684 tcg_temp_free_i32(tmp
);
689 static inline void gen_arm_shift_reg(TCGv_i32 var
, int shiftop
,
690 TCGv_i32 shift
, int flags
)
694 case 0: gen_helper_shl_cc(var
, cpu_env
, var
, shift
); break;
695 case 1: gen_helper_shr_cc(var
, cpu_env
, var
, shift
); break;
696 case 2: gen_helper_sar_cc(var
, cpu_env
, var
, shift
); break;
697 case 3: gen_helper_ror_cc(var
, cpu_env
, var
, shift
); break;
702 gen_shl(var
, var
, shift
);
705 gen_shr(var
, var
, shift
);
708 gen_sar(var
, var
, shift
);
710 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
711 tcg_gen_rotr_i32(var
, var
, shift
); break;
714 tcg_temp_free_i32(shift
);
717 #define PAS_OP(pfx) \
719 case 0: gen_pas_helper(glue(pfx,add16)); break; \
720 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
721 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
722 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
723 case 4: gen_pas_helper(glue(pfx,add8)); break; \
724 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
726 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
731 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
733 tmp
= tcg_temp_new_ptr();
734 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
736 tcg_temp_free_ptr(tmp
);
739 tmp
= tcg_temp_new_ptr();
740 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
742 tcg_temp_free_ptr(tmp
);
744 #undef gen_pas_helper
745 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
758 #undef gen_pas_helper
763 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
764 #define PAS_OP(pfx) \
766 case 0: gen_pas_helper(glue(pfx,add8)); break; \
767 case 1: gen_pas_helper(glue(pfx,add16)); break; \
768 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
769 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
770 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
771 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
773 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv_i32 a
, TCGv_i32 b
)
778 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
780 tmp
= tcg_temp_new_ptr();
781 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
783 tcg_temp_free_ptr(tmp
);
786 tmp
= tcg_temp_new_ptr();
787 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUARMState
, GE
));
789 tcg_temp_free_ptr(tmp
);
791 #undef gen_pas_helper
792 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
805 #undef gen_pas_helper
811 * Generate a conditional based on ARM condition code cc.
812 * This is common between ARM and Aarch64 targets.
814 void arm_test_cc(DisasCompare
*cmp
, int cc
)
845 case 8: /* hi: C && !Z */
846 case 9: /* ls: !C || Z -> !(C && !Z) */
848 value
= tcg_temp_new_i32();
850 /* CF is 1 for C, so -CF is an all-bits-set mask for C;
851 ZF is non-zero for !Z; so AND the two subexpressions. */
852 tcg_gen_neg_i32(value
, cpu_CF
);
853 tcg_gen_and_i32(value
, value
, cpu_ZF
);
856 case 10: /* ge: N == V -> N ^ V == 0 */
857 case 11: /* lt: N != V -> N ^ V != 0 */
858 /* Since we're only interested in the sign bit, == 0 is >= 0. */
860 value
= tcg_temp_new_i32();
862 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
865 case 12: /* gt: !Z && N == V */
866 case 13: /* le: Z || N != V */
868 value
= tcg_temp_new_i32();
870 /* (N == V) is equal to the sign bit of ~(NF ^ VF). Propagate
871 * the sign bit then AND with ZF to yield the result. */
872 tcg_gen_xor_i32(value
, cpu_VF
, cpu_NF
);
873 tcg_gen_sari_i32(value
, value
, 31);
874 tcg_gen_andc_i32(value
, cpu_ZF
, value
);
877 case 14: /* always */
878 case 15: /* always */
879 /* Use the ALWAYS condition, which will fold early.
880 * It doesn't matter what we use for the value. */
881 cond
= TCG_COND_ALWAYS
;
886 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
891 cond
= tcg_invert_cond(cond
);
897 cmp
->value_global
= global
;
900 void arm_free_cc(DisasCompare
*cmp
)
902 if (!cmp
->value_global
) {
903 tcg_temp_free_i32(cmp
->value
);
907 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
)
909 tcg_gen_brcondi_i32(cmp
->cond
, cmp
->value
, 0, label
);
912 void arm_gen_test_cc(int cc
, TCGLabel
*label
)
915 arm_test_cc(&cmp
, cc
);
916 arm_jump_cc(&cmp
, label
);
920 static const uint8_t table_logic_cc
[16] = {
939 static inline void gen_set_condexec(DisasContext
*s
)
941 if (s
->condexec_mask
) {
942 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
943 TCGv_i32 tmp
= tcg_temp_new_i32();
944 tcg_gen_movi_i32(tmp
, val
);
945 store_cpu_field(tmp
, condexec_bits
);
949 static inline void gen_set_pc_im(DisasContext
*s
, target_ulong val
)
951 tcg_gen_movi_i32(cpu_R
[15], val
);
954 /* Set PC and Thumb state from an immediate address. */
955 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
959 s
->base
.is_jmp
= DISAS_JUMP
;
960 if (s
->thumb
!= (addr
& 1)) {
961 tmp
= tcg_temp_new_i32();
962 tcg_gen_movi_i32(tmp
, addr
& 1);
963 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUARMState
, thumb
));
964 tcg_temp_free_i32(tmp
);
966 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
969 /* Set PC and Thumb state from var. var is marked as dead. */
970 static inline void gen_bx(DisasContext
*s
, TCGv_i32 var
)
972 s
->base
.is_jmp
= DISAS_JUMP
;
973 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
974 tcg_gen_andi_i32(var
, var
, 1);
975 store_cpu_field(var
, thumb
);
978 /* Set PC and Thumb state from var. var is marked as dead.
979 * For M-profile CPUs, include logic to detect exception-return
980 * branches and handle them. This is needed for Thumb POP/LDM to PC, LDR to PC,
981 * and BX reg, and no others, and happens only for code in Handler mode.
983 static inline void gen_bx_excret(DisasContext
*s
, TCGv_i32 var
)
985 /* Generate the same code here as for a simple bx, but flag via
986 * s->base.is_jmp that we need to do the rest of the work later.
989 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
) ||
990 (s
->v7m_handler_mode
&& arm_dc_feature(s
, ARM_FEATURE_M
))) {
991 s
->base
.is_jmp
= DISAS_BX_EXCRET
;
995 static inline void gen_bx_excret_final_code(DisasContext
*s
)
997 /* Generate the code to finish possible exception return and end the TB */
998 TCGLabel
*excret_label
= gen_new_label();
1001 if (arm_dc_feature(s
, ARM_FEATURE_M_SECURITY
)) {
1002 /* Covers FNC_RETURN and EXC_RETURN magic */
1003 min_magic
= FNC_RETURN_MIN_MAGIC
;
1005 /* EXC_RETURN magic only */
1006 min_magic
= EXC_RETURN_MIN_MAGIC
;
1009 /* Is the new PC value in the magic range indicating exception return? */
1010 tcg_gen_brcondi_i32(TCG_COND_GEU
, cpu_R
[15], min_magic
, excret_label
);
1011 /* No: end the TB as we would for a DISAS_JMP */
1012 if (is_singlestepping(s
)) {
1013 gen_singlestep_exception(s
);
1015 tcg_gen_exit_tb(NULL
, 0);
1017 gen_set_label(excret_label
);
1018 /* Yes: this is an exception return.
1019 * At this point in runtime env->regs[15] and env->thumb will hold
1020 * the exception-return magic number, which do_v7m_exception_exit()
1021 * will read. Nothing else will be able to see those values because
1022 * the cpu-exec main loop guarantees that we will always go straight
1023 * from raising the exception to the exception-handling code.
1025 * gen_ss_advance(s) does nothing on M profile currently but
1026 * calling it is conceptually the right thing as we have executed
1027 * this instruction (compare SWI, HVC, SMC handling).
1030 gen_exception_internal(EXCP_EXCEPTION_EXIT
);
1033 static inline void gen_bxns(DisasContext
*s
, int rm
)
1035 TCGv_i32 var
= load_reg(s
, rm
);
1037 /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
1038 * we need to sync state before calling it, but:
1039 * - we don't need to do gen_set_pc_im() because the bxns helper will
1040 * always set the PC itself
1041 * - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
1042 * unless it's outside an IT block or the last insn in an IT block,
1043 * so we know that condexec == 0 (already set at the top of the TB)
1044 * is correct in the non-UNPREDICTABLE cases, and we can choose
1045 * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
1047 gen_helper_v7m_bxns(cpu_env
, var
);
1048 tcg_temp_free_i32(var
);
1049 s
->base
.is_jmp
= DISAS_EXIT
;
1052 static inline void gen_blxns(DisasContext
*s
, int rm
)
1054 TCGv_i32 var
= load_reg(s
, rm
);
1056 /* We don't need to sync condexec state, for the same reason as bxns.
1057 * We do however need to set the PC, because the blxns helper reads it.
1058 * The blxns helper may throw an exception.
1060 gen_set_pc_im(s
, s
->pc
);
1061 gen_helper_v7m_blxns(cpu_env
, var
);
1062 tcg_temp_free_i32(var
);
1063 s
->base
.is_jmp
= DISAS_EXIT
;
1066 /* Variant of store_reg which uses branch&exchange logic when storing
1067 to r15 in ARM architecture v7 and above. The source must be a temporary
1068 and will be marked as dead. */
1069 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv_i32 var
)
1071 if (reg
== 15 && ENABLE_ARCH_7
) {
1074 store_reg(s
, reg
, var
);
1078 /* Variant of store_reg which uses branch&exchange logic when storing
1079 * to r15 in ARM architecture v5T and above. This is used for storing
1080 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
1081 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
1082 static inline void store_reg_from_load(DisasContext
*s
, int reg
, TCGv_i32 var
)
1084 if (reg
== 15 && ENABLE_ARCH_5
) {
1085 gen_bx_excret(s
, var
);
1087 store_reg(s
, reg
, var
);
1091 #ifdef CONFIG_USER_ONLY
1092 #define IS_USER_ONLY 1
1094 #define IS_USER_ONLY 0
1097 /* Abstractions of "generate code to do a guest load/store for
1098 * AArch32", where a vaddr is always 32 bits (and is zero
1099 * extended if we're a 64 bit core) and data is also
1100 * 32 bits unless specifically doing a 64 bit access.
1101 * These functions work like tcg_gen_qemu_{ld,st}* except
1102 * that the address argument is TCGv_i32 rather than TCGv.
1105 static inline TCGv
gen_aa32_addr(DisasContext
*s
, TCGv_i32 a32
, TCGMemOp op
)
1107 TCGv addr
= tcg_temp_new();
1108 tcg_gen_extu_i32_tl(addr
, a32
);
1110 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1111 if (!IS_USER_ONLY
&& s
->sctlr_b
&& (op
& MO_SIZE
) < MO_32
) {
1112 tcg_gen_xori_tl(addr
, addr
, 4 - (1 << (op
& MO_SIZE
)));
1117 static void gen_aa32_ld_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
1118 int index
, TCGMemOp opc
)
1122 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
1123 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
1127 addr
= gen_aa32_addr(s
, a32
, opc
);
1128 tcg_gen_qemu_ld_i32(val
, addr
, index
, opc
);
1129 tcg_temp_free(addr
);
1132 static void gen_aa32_st_i32(DisasContext
*s
, TCGv_i32 val
, TCGv_i32 a32
,
1133 int index
, TCGMemOp opc
)
1137 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
1138 !arm_dc_feature(s
, ARM_FEATURE_M_MAIN
)) {
1142 addr
= gen_aa32_addr(s
, a32
, opc
);
1143 tcg_gen_qemu_st_i32(val
, addr
, index
, opc
);
1144 tcg_temp_free(addr
);
1147 #define DO_GEN_LD(SUFF, OPC) \
1148 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
1149 TCGv_i32 a32, int index) \
1151 gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
1153 static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \
1155 TCGv_i32 a32, int index, \
1158 gen_aa32_ld##SUFF(s, val, a32, index); \
1159 disas_set_da_iss(s, OPC, issinfo); \
1162 #define DO_GEN_ST(SUFF, OPC) \
1163 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
1164 TCGv_i32 a32, int index) \
1166 gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
1168 static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \
1170 TCGv_i32 a32, int index, \
1173 gen_aa32_st##SUFF(s, val, a32, index); \
1174 disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \
1177 static inline void gen_aa32_frob64(DisasContext
*s
, TCGv_i64 val
)
1179 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1180 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1181 tcg_gen_rotri_i64(val
, val
, 32);
1185 static void gen_aa32_ld_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1186 int index
, TCGMemOp opc
)
1188 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1189 tcg_gen_qemu_ld_i64(val
, addr
, index
, opc
);
1190 gen_aa32_frob64(s
, val
);
1191 tcg_temp_free(addr
);
1194 static inline void gen_aa32_ld64(DisasContext
*s
, TCGv_i64 val
,
1195 TCGv_i32 a32
, int index
)
1197 gen_aa32_ld_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1200 static void gen_aa32_st_i64(DisasContext
*s
, TCGv_i64 val
, TCGv_i32 a32
,
1201 int index
, TCGMemOp opc
)
1203 TCGv addr
= gen_aa32_addr(s
, a32
, opc
);
1205 /* Not needed for user-mode BE32, where we use MO_BE instead. */
1206 if (!IS_USER_ONLY
&& s
->sctlr_b
) {
1207 TCGv_i64 tmp
= tcg_temp_new_i64();
1208 tcg_gen_rotri_i64(tmp
, val
, 32);
1209 tcg_gen_qemu_st_i64(tmp
, addr
, index
, opc
);
1210 tcg_temp_free_i64(tmp
);
1212 tcg_gen_qemu_st_i64(val
, addr
, index
, opc
);
1214 tcg_temp_free(addr
);
1217 static inline void gen_aa32_st64(DisasContext
*s
, TCGv_i64 val
,
1218 TCGv_i32 a32
, int index
)
1220 gen_aa32_st_i64(s
, val
, a32
, index
, MO_Q
| s
->be_data
);
1223 DO_GEN_LD(8s
, MO_SB
)
1224 DO_GEN_LD(8u, MO_UB
)
1225 DO_GEN_LD(16s
, MO_SW
)
1226 DO_GEN_LD(16u, MO_UW
)
1227 DO_GEN_LD(32u, MO_UL
)
1229 DO_GEN_ST(16, MO_UW
)
1230 DO_GEN_ST(32, MO_UL
)
1232 static inline void gen_hvc(DisasContext
*s
, int imm16
)
1234 /* The pre HVC helper handles cases when HVC gets trapped
1235 * as an undefined insn by runtime configuration (ie before
1236 * the insn really executes).
1238 gen_set_pc_im(s
, s
->pc
- 4);
1239 gen_helper_pre_hvc(cpu_env
);
1240 /* Otherwise we will treat this as a real exception which
1241 * happens after execution of the insn. (The distinction matters
1242 * for the PC value reported to the exception handler and also
1243 * for single stepping.)
1246 gen_set_pc_im(s
, s
->pc
);
1247 s
->base
.is_jmp
= DISAS_HVC
;
1250 static inline void gen_smc(DisasContext
*s
)
1252 /* As with HVC, we may take an exception either before or after
1253 * the insn executes.
1257 gen_set_pc_im(s
, s
->pc
- 4);
1258 tmp
= tcg_const_i32(syn_aa32_smc());
1259 gen_helper_pre_smc(cpu_env
, tmp
);
1260 tcg_temp_free_i32(tmp
);
1261 gen_set_pc_im(s
, s
->pc
);
1262 s
->base
.is_jmp
= DISAS_SMC
;
1265 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
1267 gen_set_condexec(s
);
1268 gen_set_pc_im(s
, s
->pc
- offset
);
1269 gen_exception_internal(excp
);
1270 s
->base
.is_jmp
= DISAS_NORETURN
;
1273 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
1274 int syn
, uint32_t target_el
)
1276 gen_set_condexec(s
);
1277 gen_set_pc_im(s
, s
->pc
- offset
);
1278 gen_exception(excp
, syn
, target_el
);
1279 s
->base
.is_jmp
= DISAS_NORETURN
;
1282 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
, uint32_t syn
)
1286 gen_set_condexec(s
);
1287 gen_set_pc_im(s
, s
->pc
- offset
);
1288 tcg_syn
= tcg_const_i32(syn
);
1289 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
1290 tcg_temp_free_i32(tcg_syn
);
1291 s
->base
.is_jmp
= DISAS_NORETURN
;
1294 /* Force a TB lookup after an instruction that changes the CPU state. */
1295 static inline void gen_lookup_tb(DisasContext
*s
)
1297 tcg_gen_movi_i32(cpu_R
[15], s
->pc
& ~1);
1298 s
->base
.is_jmp
= DISAS_EXIT
;
1301 static inline void gen_hlt(DisasContext
*s
, int imm
)
1303 /* HLT. This has two purposes.
1304 * Architecturally, it is an external halting debug instruction.
1305 * Since QEMU doesn't implement external debug, we treat this as
1306 * it is required for halting debug disabled: it will UNDEF.
1307 * Secondly, "HLT 0x3C" is a T32 semihosting trap instruction,
1308 * and "HLT 0xF000" is an A32 semihosting syscall. These traps
1309 * must trigger semihosting even for ARMv7 and earlier, where
1310 * HLT was an undefined encoding.
1311 * In system mode, we don't allow userspace access to
1312 * semihosting, to provide some semblance of security
1313 * (and for consistency with our 32-bit semihosting).
1315 if (semihosting_enabled() &&
1316 #ifndef CONFIG_USER_ONLY
1317 s
->current_el
!= 0 &&
1319 (imm
== (s
->thumb
? 0x3c : 0xf000))) {
1320 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1324 gen_exception_insn(s
, s
->thumb
? 2 : 4, EXCP_UDEF
, syn_uncategorized(),
1325 default_exception_el(s
));
1328 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
1331 int val
, rm
, shift
, shiftop
;
1334 if (!(insn
& (1 << 25))) {
1337 if (!(insn
& (1 << 23)))
1340 tcg_gen_addi_i32(var
, var
, val
);
1342 /* shift/register */
1344 shift
= (insn
>> 7) & 0x1f;
1345 shiftop
= (insn
>> 5) & 3;
1346 offset
= load_reg(s
, rm
);
1347 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
1348 if (!(insn
& (1 << 23)))
1349 tcg_gen_sub_i32(var
, var
, offset
);
1351 tcg_gen_add_i32(var
, var
, offset
);
1352 tcg_temp_free_i32(offset
);
1356 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
1357 int extra
, TCGv_i32 var
)
1362 if (insn
& (1 << 22)) {
1364 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
1365 if (!(insn
& (1 << 23)))
1369 tcg_gen_addi_i32(var
, var
, val
);
1373 tcg_gen_addi_i32(var
, var
, extra
);
1375 offset
= load_reg(s
, rm
);
1376 if (!(insn
& (1 << 23)))
1377 tcg_gen_sub_i32(var
, var
, offset
);
1379 tcg_gen_add_i32(var
, var
, offset
);
1380 tcg_temp_free_i32(offset
);
1384 static TCGv_ptr
get_fpstatus_ptr(int neon
)
1386 TCGv_ptr statusptr
= tcg_temp_new_ptr();
1389 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
1391 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
1393 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
1397 #define VFP_OP2(name) \
1398 static inline void gen_vfp_##name(int dp) \
1400 TCGv_ptr fpst = get_fpstatus_ptr(0); \
1402 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, fpst); \
1404 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, fpst); \
1406 tcg_temp_free_ptr(fpst); \
1416 static inline void gen_vfp_F1_mul(int dp
)
1418 /* Like gen_vfp_mul() but put result in F1 */
1419 TCGv_ptr fpst
= get_fpstatus_ptr(0);
1421 gen_helper_vfp_muld(cpu_F1d
, cpu_F0d
, cpu_F1d
, fpst
);
1423 gen_helper_vfp_muls(cpu_F1s
, cpu_F0s
, cpu_F1s
, fpst
);
1425 tcg_temp_free_ptr(fpst
);
1428 static inline void gen_vfp_F1_neg(int dp
)
1430 /* Like gen_vfp_neg() but put result in F1 */
1432 gen_helper_vfp_negd(cpu_F1d
, cpu_F0d
);
1434 gen_helper_vfp_negs(cpu_F1s
, cpu_F0s
);
1438 static inline void gen_vfp_abs(int dp
)
1441 gen_helper_vfp_absd(cpu_F0d
, cpu_F0d
);
1443 gen_helper_vfp_abss(cpu_F0s
, cpu_F0s
);
1446 static inline void gen_vfp_neg(int dp
)
1449 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
1451 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
1454 static inline void gen_vfp_sqrt(int dp
)
1457 gen_helper_vfp_sqrtd(cpu_F0d
, cpu_F0d
, cpu_env
);
1459 gen_helper_vfp_sqrts(cpu_F0s
, cpu_F0s
, cpu_env
);
1462 static inline void gen_vfp_cmp(int dp
)
1465 gen_helper_vfp_cmpd(cpu_F0d
, cpu_F1d
, cpu_env
);
1467 gen_helper_vfp_cmps(cpu_F0s
, cpu_F1s
, cpu_env
);
1470 static inline void gen_vfp_cmpe(int dp
)
1473 gen_helper_vfp_cmped(cpu_F0d
, cpu_F1d
, cpu_env
);
1475 gen_helper_vfp_cmpes(cpu_F0s
, cpu_F1s
, cpu_env
);
1478 static inline void gen_vfp_F1_ld0(int dp
)
1481 tcg_gen_movi_i64(cpu_F1d
, 0);
1483 tcg_gen_movi_i32(cpu_F1s
, 0);
1486 #define VFP_GEN_ITOF(name) \
1487 static inline void gen_vfp_##name(int dp, int neon) \
1489 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1491 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \
1493 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1495 tcg_temp_free_ptr(statusptr); \
1502 #define VFP_GEN_FTOI(name) \
1503 static inline void gen_vfp_##name(int dp, int neon) \
1505 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1507 gen_helper_vfp_##name##d(cpu_F0s, cpu_F0d, statusptr); \
1509 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
1511 tcg_temp_free_ptr(statusptr); \
1520 #define VFP_GEN_FIX(name, round) \
1521 static inline void gen_vfp_##name(int dp, int shift, int neon) \
1523 TCGv_i32 tmp_shift = tcg_const_i32(shift); \
1524 TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
1526 gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \
1529 gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \
1532 tcg_temp_free_i32(tmp_shift); \
1533 tcg_temp_free_ptr(statusptr); \
1535 VFP_GEN_FIX(tosh
, _round_to_zero
)
1536 VFP_GEN_FIX(tosl
, _round_to_zero
)
1537 VFP_GEN_FIX(touh
, _round_to_zero
)
1538 VFP_GEN_FIX(toul
, _round_to_zero
)
1545 static inline void gen_vfp_ld(DisasContext
*s
, int dp
, TCGv_i32 addr
)
1548 gen_aa32_ld64(s
, cpu_F0d
, addr
, get_mem_index(s
));
1550 gen_aa32_ld32u(s
, cpu_F0s
, addr
, get_mem_index(s
));
1554 static inline void gen_vfp_st(DisasContext
*s
, int dp
, TCGv_i32 addr
)
1557 gen_aa32_st64(s
, cpu_F0d
, addr
, get_mem_index(s
));
1559 gen_aa32_st32(s
, cpu_F0s
, addr
, get_mem_index(s
));
1563 static inline long vfp_reg_offset(bool dp
, unsigned reg
)
1566 return offsetof(CPUARMState
, vfp
.zregs
[reg
>> 1].d
[reg
& 1]);
1568 long ofs
= offsetof(CPUARMState
, vfp
.zregs
[reg
>> 2].d
[(reg
>> 1) & 1]);
1570 ofs
+= offsetof(CPU_DoubleU
, l
.upper
);
1572 ofs
+= offsetof(CPU_DoubleU
, l
.lower
);
1578 /* Return the offset of a 32-bit piece of a NEON register.
1579 zero is the least significant end of the register. */
1581 neon_reg_offset (int reg
, int n
)
1585 return vfp_reg_offset(0, sreg
);
1588 /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
1589 * where 0 is the least significant end of the register.
1592 neon_element_offset(int reg
, int element
, TCGMemOp size
)
1594 int element_size
= 1 << size
;
1595 int ofs
= element
* element_size
;
1596 #ifdef HOST_WORDS_BIGENDIAN
1597 /* Calculate the offset assuming fully little-endian,
1598 * then XOR to account for the order of the 8-byte units.
1600 if (element_size
< 8) {
1601 ofs
^= 8 - element_size
;
1604 return neon_reg_offset(reg
, 0) + ofs
;
1607 static TCGv_i32
neon_load_reg(int reg
, int pass
)
1609 TCGv_i32 tmp
= tcg_temp_new_i32();
1610 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1614 static void neon_store_reg(int reg
, int pass
, TCGv_i32 var
)
1616 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1617 tcg_temp_free_i32(var
);
1620 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1622 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1625 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1627 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1630 static TCGv_ptr
vfp_reg_ptr(bool dp
, int reg
)
1632 TCGv_ptr ret
= tcg_temp_new_ptr();
1633 tcg_gen_addi_ptr(ret
, cpu_env
, vfp_reg_offset(dp
, reg
));
1637 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1638 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1639 #define tcg_gen_st_f32 tcg_gen_st_i32
1640 #define tcg_gen_st_f64 tcg_gen_st_i64
1642 static inline void gen_mov_F0_vreg(int dp
, int reg
)
1645 tcg_gen_ld_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1647 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1650 static inline void gen_mov_F1_vreg(int dp
, int reg
)
1653 tcg_gen_ld_f64(cpu_F1d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1655 tcg_gen_ld_f32(cpu_F1s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1658 static inline void gen_mov_vreg_F0(int dp
, int reg
)
1661 tcg_gen_st_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1663 tcg_gen_st_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1666 #define ARM_CP_RW_BIT (1 << 20)
1668 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1670 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1673 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1675 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.regs
[reg
]));
1678 static inline TCGv_i32
iwmmxt_load_creg(int reg
)
1680 TCGv_i32 var
= tcg_temp_new_i32();
1681 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1685 static inline void iwmmxt_store_creg(int reg
, TCGv_i32 var
)
1687 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, iwmmxt
.cregs
[reg
]));
1688 tcg_temp_free_i32(var
);
1691 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1693 iwmmxt_store_reg(cpu_M0
, rn
);
1696 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1698 iwmmxt_load_reg(cpu_M0
, rn
);
1701 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1703 iwmmxt_load_reg(cpu_V1
, rn
);
1704 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1707 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1709 iwmmxt_load_reg(cpu_V1
, rn
);
1710 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1713 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1715 iwmmxt_load_reg(cpu_V1
, rn
);
1716 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1719 #define IWMMXT_OP(name) \
1720 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1722 iwmmxt_load_reg(cpu_V1, rn); \
1723 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1726 #define IWMMXT_OP_ENV(name) \
1727 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1729 iwmmxt_load_reg(cpu_V1, rn); \
1730 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \
1733 #define IWMMXT_OP_ENV_SIZE(name) \
1734 IWMMXT_OP_ENV(name##b) \
1735 IWMMXT_OP_ENV(name##w) \
1736 IWMMXT_OP_ENV(name##l)
1738 #define IWMMXT_OP_ENV1(name) \
1739 static inline void gen_op_iwmmxt_##name##_M0(void) \
1741 gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \
1755 IWMMXT_OP_ENV_SIZE(unpackl
)
1756 IWMMXT_OP_ENV_SIZE(unpackh
)
1758 IWMMXT_OP_ENV1(unpacklub
)
1759 IWMMXT_OP_ENV1(unpackluw
)
1760 IWMMXT_OP_ENV1(unpacklul
)
1761 IWMMXT_OP_ENV1(unpackhub
)
1762 IWMMXT_OP_ENV1(unpackhuw
)
1763 IWMMXT_OP_ENV1(unpackhul
)
1764 IWMMXT_OP_ENV1(unpacklsb
)
1765 IWMMXT_OP_ENV1(unpacklsw
)
1766 IWMMXT_OP_ENV1(unpacklsl
)
1767 IWMMXT_OP_ENV1(unpackhsb
)
1768 IWMMXT_OP_ENV1(unpackhsw
)
1769 IWMMXT_OP_ENV1(unpackhsl
)
1771 IWMMXT_OP_ENV_SIZE(cmpeq
)
1772 IWMMXT_OP_ENV_SIZE(cmpgtu
)
1773 IWMMXT_OP_ENV_SIZE(cmpgts
)
1775 IWMMXT_OP_ENV_SIZE(mins
)
1776 IWMMXT_OP_ENV_SIZE(minu
)
1777 IWMMXT_OP_ENV_SIZE(maxs
)
1778 IWMMXT_OP_ENV_SIZE(maxu
)
1780 IWMMXT_OP_ENV_SIZE(subn
)
1781 IWMMXT_OP_ENV_SIZE(addn
)
1782 IWMMXT_OP_ENV_SIZE(subu
)
1783 IWMMXT_OP_ENV_SIZE(addu
)
1784 IWMMXT_OP_ENV_SIZE(subs
)
1785 IWMMXT_OP_ENV_SIZE(adds
)
1787 IWMMXT_OP_ENV(avgb0
)
1788 IWMMXT_OP_ENV(avgb1
)
1789 IWMMXT_OP_ENV(avgw0
)
1790 IWMMXT_OP_ENV(avgw1
)
1792 IWMMXT_OP_ENV(packuw
)
1793 IWMMXT_OP_ENV(packul
)
1794 IWMMXT_OP_ENV(packuq
)
1795 IWMMXT_OP_ENV(packsw
)
1796 IWMMXT_OP_ENV(packsl
)
1797 IWMMXT_OP_ENV(packsq
)
1799 static void gen_op_iwmmxt_set_mup(void)
1802 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1803 tcg_gen_ori_i32(tmp
, tmp
, 2);
1804 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1807 static void gen_op_iwmmxt_set_cup(void)
1810 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1811 tcg_gen_ori_i32(tmp
, tmp
, 1);
1812 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1815 static void gen_op_iwmmxt_setpsr_nz(void)
1817 TCGv_i32 tmp
= tcg_temp_new_i32();
1818 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1819 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1822 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1824 iwmmxt_load_reg(cpu_V1
, rn
);
1825 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1826 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1829 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
,
1836 rd
= (insn
>> 16) & 0xf;
1837 tmp
= load_reg(s
, rd
);
1839 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1840 if (insn
& (1 << 24)) {
1842 if (insn
& (1 << 23))
1843 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1845 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1846 tcg_gen_mov_i32(dest
, tmp
);
1847 if (insn
& (1 << 21))
1848 store_reg(s
, rd
, tmp
);
1850 tcg_temp_free_i32(tmp
);
1851 } else if (insn
& (1 << 21)) {
1853 tcg_gen_mov_i32(dest
, tmp
);
1854 if (insn
& (1 << 23))
1855 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1857 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1858 store_reg(s
, rd
, tmp
);
1859 } else if (!(insn
& (1 << 23)))
1864 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv_i32 dest
)
1866 int rd
= (insn
>> 0) & 0xf;
1869 if (insn
& (1 << 8)) {
1870 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1873 tmp
= iwmmxt_load_creg(rd
);
1876 tmp
= tcg_temp_new_i32();
1877 iwmmxt_load_reg(cpu_V0
, rd
);
1878 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
1880 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1881 tcg_gen_mov_i32(dest
, tmp
);
1882 tcg_temp_free_i32(tmp
);
1886 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
1887 (ie. an undefined instruction). */
1888 static int disas_iwmmxt_insn(DisasContext
*s
, uint32_t insn
)
1891 int rdhi
, rdlo
, rd0
, rd1
, i
;
1893 TCGv_i32 tmp
, tmp2
, tmp3
;
1895 if ((insn
& 0x0e000e00) == 0x0c000000) {
1896 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1898 rdlo
= (insn
>> 12) & 0xf;
1899 rdhi
= (insn
>> 16) & 0xf;
1900 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1901 iwmmxt_load_reg(cpu_V0
, wrd
);
1902 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1903 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
1904 tcg_gen_extrl_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1905 } else { /* TMCRR */
1906 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1907 iwmmxt_store_reg(cpu_V0
, wrd
);
1908 gen_op_iwmmxt_set_mup();
1913 wrd
= (insn
>> 12) & 0xf;
1914 addr
= tcg_temp_new_i32();
1915 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1916 tcg_temp_free_i32(addr
);
1919 if (insn
& ARM_CP_RW_BIT
) {
1920 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1921 tmp
= tcg_temp_new_i32();
1922 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1923 iwmmxt_store_creg(wrd
, tmp
);
1926 if (insn
& (1 << 8)) {
1927 if (insn
& (1 << 22)) { /* WLDRD */
1928 gen_aa32_ld64(s
, cpu_M0
, addr
, get_mem_index(s
));
1930 } else { /* WLDRW wRd */
1931 tmp
= tcg_temp_new_i32();
1932 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
1935 tmp
= tcg_temp_new_i32();
1936 if (insn
& (1 << 22)) { /* WLDRH */
1937 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
1938 } else { /* WLDRB */
1939 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
1943 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1944 tcg_temp_free_i32(tmp
);
1946 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1949 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1950 tmp
= iwmmxt_load_creg(wrd
);
1951 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1953 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1954 tmp
= tcg_temp_new_i32();
1955 if (insn
& (1 << 8)) {
1956 if (insn
& (1 << 22)) { /* WSTRD */
1957 gen_aa32_st64(s
, cpu_M0
, addr
, get_mem_index(s
));
1958 } else { /* WSTRW wRd */
1959 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1960 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
1963 if (insn
& (1 << 22)) { /* WSTRH */
1964 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1965 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
1966 } else { /* WSTRB */
1967 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
1968 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
1972 tcg_temp_free_i32(tmp
);
1974 tcg_temp_free_i32(addr
);
1978 if ((insn
& 0x0f000000) != 0x0e000000)
1981 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1982 case 0x000: /* WOR */
1983 wrd
= (insn
>> 12) & 0xf;
1984 rd0
= (insn
>> 0) & 0xf;
1985 rd1
= (insn
>> 16) & 0xf;
1986 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1987 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1988 gen_op_iwmmxt_setpsr_nz();
1989 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1990 gen_op_iwmmxt_set_mup();
1991 gen_op_iwmmxt_set_cup();
1993 case 0x011: /* TMCR */
1996 rd
= (insn
>> 12) & 0xf;
1997 wrd
= (insn
>> 16) & 0xf;
1999 case ARM_IWMMXT_wCID
:
2000 case ARM_IWMMXT_wCASF
:
2002 case ARM_IWMMXT_wCon
:
2003 gen_op_iwmmxt_set_cup();
2005 case ARM_IWMMXT_wCSSF
:
2006 tmp
= iwmmxt_load_creg(wrd
);
2007 tmp2
= load_reg(s
, rd
);
2008 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
2009 tcg_temp_free_i32(tmp2
);
2010 iwmmxt_store_creg(wrd
, tmp
);
2012 case ARM_IWMMXT_wCGR0
:
2013 case ARM_IWMMXT_wCGR1
:
2014 case ARM_IWMMXT_wCGR2
:
2015 case ARM_IWMMXT_wCGR3
:
2016 gen_op_iwmmxt_set_cup();
2017 tmp
= load_reg(s
, rd
);
2018 iwmmxt_store_creg(wrd
, tmp
);
2024 case 0x100: /* WXOR */
2025 wrd
= (insn
>> 12) & 0xf;
2026 rd0
= (insn
>> 0) & 0xf;
2027 rd1
= (insn
>> 16) & 0xf;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2029 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
2030 gen_op_iwmmxt_setpsr_nz();
2031 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2032 gen_op_iwmmxt_set_mup();
2033 gen_op_iwmmxt_set_cup();
2035 case 0x111: /* TMRC */
2038 rd
= (insn
>> 12) & 0xf;
2039 wrd
= (insn
>> 16) & 0xf;
2040 tmp
= iwmmxt_load_creg(wrd
);
2041 store_reg(s
, rd
, tmp
);
2043 case 0x300: /* WANDN */
2044 wrd
= (insn
>> 12) & 0xf;
2045 rd0
= (insn
>> 0) & 0xf;
2046 rd1
= (insn
>> 16) & 0xf;
2047 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2048 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
2049 gen_op_iwmmxt_andq_M0_wRn(rd1
);
2050 gen_op_iwmmxt_setpsr_nz();
2051 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2052 gen_op_iwmmxt_set_mup();
2053 gen_op_iwmmxt_set_cup();
2055 case 0x200: /* WAND */
2056 wrd
= (insn
>> 12) & 0xf;
2057 rd0
= (insn
>> 0) & 0xf;
2058 rd1
= (insn
>> 16) & 0xf;
2059 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2060 gen_op_iwmmxt_andq_M0_wRn(rd1
);
2061 gen_op_iwmmxt_setpsr_nz();
2062 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2063 gen_op_iwmmxt_set_mup();
2064 gen_op_iwmmxt_set_cup();
2066 case 0x810: case 0xa10: /* WMADD */
2067 wrd
= (insn
>> 12) & 0xf;
2068 rd0
= (insn
>> 0) & 0xf;
2069 rd1
= (insn
>> 16) & 0xf;
2070 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2071 if (insn
& (1 << 21))
2072 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
2074 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
2075 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2076 gen_op_iwmmxt_set_mup();
2078 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
2079 wrd
= (insn
>> 12) & 0xf;
2080 rd0
= (insn
>> 16) & 0xf;
2081 rd1
= (insn
>> 0) & 0xf;
2082 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2083 switch ((insn
>> 22) & 3) {
2085 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
2088 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
2091 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
2096 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2097 gen_op_iwmmxt_set_mup();
2098 gen_op_iwmmxt_set_cup();
2100 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
2101 wrd
= (insn
>> 12) & 0xf;
2102 rd0
= (insn
>> 16) & 0xf;
2103 rd1
= (insn
>> 0) & 0xf;
2104 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2105 switch ((insn
>> 22) & 3) {
2107 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
2110 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
2113 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
2118 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2119 gen_op_iwmmxt_set_mup();
2120 gen_op_iwmmxt_set_cup();
2122 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
2123 wrd
= (insn
>> 12) & 0xf;
2124 rd0
= (insn
>> 16) & 0xf;
2125 rd1
= (insn
>> 0) & 0xf;
2126 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2127 if (insn
& (1 << 22))
2128 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
2130 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
2131 if (!(insn
& (1 << 20)))
2132 gen_op_iwmmxt_addl_M0_wRn(wrd
);
2133 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2134 gen_op_iwmmxt_set_mup();
2136 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
2137 wrd
= (insn
>> 12) & 0xf;
2138 rd0
= (insn
>> 16) & 0xf;
2139 rd1
= (insn
>> 0) & 0xf;
2140 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2141 if (insn
& (1 << 21)) {
2142 if (insn
& (1 << 20))
2143 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
2145 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
2147 if (insn
& (1 << 20))
2148 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
2150 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
2152 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2153 gen_op_iwmmxt_set_mup();
2155 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
2156 wrd
= (insn
>> 12) & 0xf;
2157 rd0
= (insn
>> 16) & 0xf;
2158 rd1
= (insn
>> 0) & 0xf;
2159 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2160 if (insn
& (1 << 21))
2161 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
2163 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
2164 if (!(insn
& (1 << 20))) {
2165 iwmmxt_load_reg(cpu_V1
, wrd
);
2166 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
2168 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2169 gen_op_iwmmxt_set_mup();
2171 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
2172 wrd
= (insn
>> 12) & 0xf;
2173 rd0
= (insn
>> 16) & 0xf;
2174 rd1
= (insn
>> 0) & 0xf;
2175 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2176 switch ((insn
>> 22) & 3) {
2178 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
2181 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
2184 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
2189 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2190 gen_op_iwmmxt_set_mup();
2191 gen_op_iwmmxt_set_cup();
2193 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
2194 wrd
= (insn
>> 12) & 0xf;
2195 rd0
= (insn
>> 16) & 0xf;
2196 rd1
= (insn
>> 0) & 0xf;
2197 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2198 if (insn
& (1 << 22)) {
2199 if (insn
& (1 << 20))
2200 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
2202 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
2204 if (insn
& (1 << 20))
2205 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
2207 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
2209 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2210 gen_op_iwmmxt_set_mup();
2211 gen_op_iwmmxt_set_cup();
2213 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
2214 wrd
= (insn
>> 12) & 0xf;
2215 rd0
= (insn
>> 16) & 0xf;
2216 rd1
= (insn
>> 0) & 0xf;
2217 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2218 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
2219 tcg_gen_andi_i32(tmp
, tmp
, 7);
2220 iwmmxt_load_reg(cpu_V1
, rd1
);
2221 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2222 tcg_temp_free_i32(tmp
);
2223 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2224 gen_op_iwmmxt_set_mup();
2226 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
2227 if (((insn
>> 6) & 3) == 3)
2229 rd
= (insn
>> 12) & 0xf;
2230 wrd
= (insn
>> 16) & 0xf;
2231 tmp
= load_reg(s
, rd
);
2232 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2233 switch ((insn
>> 6) & 3) {
2235 tmp2
= tcg_const_i32(0xff);
2236 tmp3
= tcg_const_i32((insn
& 7) << 3);
2239 tmp2
= tcg_const_i32(0xffff);
2240 tmp3
= tcg_const_i32((insn
& 3) << 4);
2243 tmp2
= tcg_const_i32(0xffffffff);
2244 tmp3
= tcg_const_i32((insn
& 1) << 5);
2250 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
2251 tcg_temp_free_i32(tmp3
);
2252 tcg_temp_free_i32(tmp2
);
2253 tcg_temp_free_i32(tmp
);
2254 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2255 gen_op_iwmmxt_set_mup();
2257 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
2258 rd
= (insn
>> 12) & 0xf;
2259 wrd
= (insn
>> 16) & 0xf;
2260 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
2262 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2263 tmp
= tcg_temp_new_i32();
2264 switch ((insn
>> 22) & 3) {
2266 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
2267 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2269 tcg_gen_ext8s_i32(tmp
, tmp
);
2271 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
2275 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
2276 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2278 tcg_gen_ext16s_i32(tmp
, tmp
);
2280 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
2284 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
2285 tcg_gen_extrl_i64_i32(tmp
, cpu_M0
);
2288 store_reg(s
, rd
, tmp
);
2290 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
2291 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2293 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2294 switch ((insn
>> 22) & 3) {
2296 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
2299 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
2302 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
2305 tcg_gen_shli_i32(tmp
, tmp
, 28);
2307 tcg_temp_free_i32(tmp
);
2309 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
2310 if (((insn
>> 6) & 3) == 3)
2312 rd
= (insn
>> 12) & 0xf;
2313 wrd
= (insn
>> 16) & 0xf;
2314 tmp
= load_reg(s
, rd
);
2315 switch ((insn
>> 6) & 3) {
2317 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
2320 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
2323 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
2326 tcg_temp_free_i32(tmp
);
2327 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2328 gen_op_iwmmxt_set_mup();
2330 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
2331 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2333 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2334 tmp2
= tcg_temp_new_i32();
2335 tcg_gen_mov_i32(tmp2
, tmp
);
2336 switch ((insn
>> 22) & 3) {
2338 for (i
= 0; i
< 7; i
++) {
2339 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2340 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2344 for (i
= 0; i
< 3; i
++) {
2345 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2346 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2350 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2351 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
2355 tcg_temp_free_i32(tmp2
);
2356 tcg_temp_free_i32(tmp
);
2358 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
2359 wrd
= (insn
>> 12) & 0xf;
2360 rd0
= (insn
>> 16) & 0xf;
2361 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2362 switch ((insn
>> 22) & 3) {
2364 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
2367 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
2370 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
2375 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2376 gen_op_iwmmxt_set_mup();
2378 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
2379 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
2381 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
2382 tmp2
= tcg_temp_new_i32();
2383 tcg_gen_mov_i32(tmp2
, tmp
);
2384 switch ((insn
>> 22) & 3) {
2386 for (i
= 0; i
< 7; i
++) {
2387 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
2388 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2392 for (i
= 0; i
< 3; i
++) {
2393 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
2394 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2398 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
2399 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
2403 tcg_temp_free_i32(tmp2
);
2404 tcg_temp_free_i32(tmp
);
2406 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2407 rd
= (insn
>> 12) & 0xf;
2408 rd0
= (insn
>> 16) & 0xf;
2409 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
2411 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2412 tmp
= tcg_temp_new_i32();
2413 switch ((insn
>> 22) & 3) {
2415 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
2418 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
2421 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
2424 store_reg(s
, rd
, tmp
);
2426 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2427 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2428 wrd
= (insn
>> 12) & 0xf;
2429 rd0
= (insn
>> 16) & 0xf;
2430 rd1
= (insn
>> 0) & 0xf;
2431 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2432 switch ((insn
>> 22) & 3) {
2434 if (insn
& (1 << 21))
2435 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
2437 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
2440 if (insn
& (1 << 21))
2441 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
2443 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
2446 if (insn
& (1 << 21))
2447 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
2449 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
2454 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2455 gen_op_iwmmxt_set_mup();
2456 gen_op_iwmmxt_set_cup();
2458 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2459 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2460 wrd
= (insn
>> 12) & 0xf;
2461 rd0
= (insn
>> 16) & 0xf;
2462 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2463 switch ((insn
>> 22) & 3) {
2465 if (insn
& (1 << 21))
2466 gen_op_iwmmxt_unpacklsb_M0();
2468 gen_op_iwmmxt_unpacklub_M0();
2471 if (insn
& (1 << 21))
2472 gen_op_iwmmxt_unpacklsw_M0();
2474 gen_op_iwmmxt_unpackluw_M0();
2477 if (insn
& (1 << 21))
2478 gen_op_iwmmxt_unpacklsl_M0();
2480 gen_op_iwmmxt_unpacklul_M0();
2485 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2486 gen_op_iwmmxt_set_mup();
2487 gen_op_iwmmxt_set_cup();
2489 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2490 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2491 wrd
= (insn
>> 12) & 0xf;
2492 rd0
= (insn
>> 16) & 0xf;
2493 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2494 switch ((insn
>> 22) & 3) {
2496 if (insn
& (1 << 21))
2497 gen_op_iwmmxt_unpackhsb_M0();
2499 gen_op_iwmmxt_unpackhub_M0();
2502 if (insn
& (1 << 21))
2503 gen_op_iwmmxt_unpackhsw_M0();
2505 gen_op_iwmmxt_unpackhuw_M0();
2508 if (insn
& (1 << 21))
2509 gen_op_iwmmxt_unpackhsl_M0();
2511 gen_op_iwmmxt_unpackhul_M0();
2516 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2517 gen_op_iwmmxt_set_mup();
2518 gen_op_iwmmxt_set_cup();
2520 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2521 case 0x214: case 0x614: case 0xa14: case 0xe14:
2522 if (((insn
>> 22) & 3) == 0)
2524 wrd
= (insn
>> 12) & 0xf;
2525 rd0
= (insn
>> 16) & 0xf;
2526 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2527 tmp
= tcg_temp_new_i32();
2528 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2529 tcg_temp_free_i32(tmp
);
2532 switch ((insn
>> 22) & 3) {
2534 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2537 gen_helper_iwmmxt_srll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2540 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2543 tcg_temp_free_i32(tmp
);
2544 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2545 gen_op_iwmmxt_set_mup();
2546 gen_op_iwmmxt_set_cup();
2548 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2549 case 0x014: case 0x414: case 0x814: case 0xc14:
2550 if (((insn
>> 22) & 3) == 0)
2552 wrd
= (insn
>> 12) & 0xf;
2553 rd0
= (insn
>> 16) & 0xf;
2554 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2555 tmp
= tcg_temp_new_i32();
2556 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2557 tcg_temp_free_i32(tmp
);
2560 switch ((insn
>> 22) & 3) {
2562 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2565 gen_helper_iwmmxt_sral(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2568 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2571 tcg_temp_free_i32(tmp
);
2572 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2573 gen_op_iwmmxt_set_mup();
2574 gen_op_iwmmxt_set_cup();
2576 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2577 case 0x114: case 0x514: case 0x914: case 0xd14:
2578 if (((insn
>> 22) & 3) == 0)
2580 wrd
= (insn
>> 12) & 0xf;
2581 rd0
= (insn
>> 16) & 0xf;
2582 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2583 tmp
= tcg_temp_new_i32();
2584 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2585 tcg_temp_free_i32(tmp
);
2588 switch ((insn
>> 22) & 3) {
2590 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2593 gen_helper_iwmmxt_slll(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2596 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2599 tcg_temp_free_i32(tmp
);
2600 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2601 gen_op_iwmmxt_set_mup();
2602 gen_op_iwmmxt_set_cup();
2604 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2605 case 0x314: case 0x714: case 0xb14: case 0xf14:
2606 if (((insn
>> 22) & 3) == 0)
2608 wrd
= (insn
>> 12) & 0xf;
2609 rd0
= (insn
>> 16) & 0xf;
2610 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2611 tmp
= tcg_temp_new_i32();
2612 switch ((insn
>> 22) & 3) {
2614 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2615 tcg_temp_free_i32(tmp
);
2618 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2621 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2622 tcg_temp_free_i32(tmp
);
2625 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2628 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2629 tcg_temp_free_i32(tmp
);
2632 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2635 tcg_temp_free_i32(tmp
);
2636 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2637 gen_op_iwmmxt_set_mup();
2638 gen_op_iwmmxt_set_cup();
2640 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2641 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2642 wrd
= (insn
>> 12) & 0xf;
2643 rd0
= (insn
>> 16) & 0xf;
2644 rd1
= (insn
>> 0) & 0xf;
2645 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2646 switch ((insn
>> 22) & 3) {
2648 if (insn
& (1 << 21))
2649 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2651 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2654 if (insn
& (1 << 21))
2655 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2657 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2660 if (insn
& (1 << 21))
2661 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2663 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2668 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2669 gen_op_iwmmxt_set_mup();
2671 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2672 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2673 wrd
= (insn
>> 12) & 0xf;
2674 rd0
= (insn
>> 16) & 0xf;
2675 rd1
= (insn
>> 0) & 0xf;
2676 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2677 switch ((insn
>> 22) & 3) {
2679 if (insn
& (1 << 21))
2680 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2682 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2685 if (insn
& (1 << 21))
2686 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2688 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2691 if (insn
& (1 << 21))
2692 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2694 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2699 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2700 gen_op_iwmmxt_set_mup();
2702 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2703 case 0x402: case 0x502: case 0x602: case 0x702:
2704 wrd
= (insn
>> 12) & 0xf;
2705 rd0
= (insn
>> 16) & 0xf;
2706 rd1
= (insn
>> 0) & 0xf;
2707 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2708 tmp
= tcg_const_i32((insn
>> 20) & 3);
2709 iwmmxt_load_reg(cpu_V1
, rd1
);
2710 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2711 tcg_temp_free_i32(tmp
);
2712 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2713 gen_op_iwmmxt_set_mup();
2715 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2716 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2717 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2718 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2719 wrd
= (insn
>> 12) & 0xf;
2720 rd0
= (insn
>> 16) & 0xf;
2721 rd1
= (insn
>> 0) & 0xf;
2722 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2723 switch ((insn
>> 20) & 0xf) {
2725 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2728 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2731 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2734 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2737 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2740 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2743 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2746 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2749 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2754 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2755 gen_op_iwmmxt_set_mup();
2756 gen_op_iwmmxt_set_cup();
2758 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2759 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2760 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2761 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2762 wrd
= (insn
>> 12) & 0xf;
2763 rd0
= (insn
>> 16) & 0xf;
2764 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2765 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2766 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_env
, cpu_M0
, tmp
);
2767 tcg_temp_free_i32(tmp
);
2768 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2769 gen_op_iwmmxt_set_mup();
2770 gen_op_iwmmxt_set_cup();
2772 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2773 case 0x418: case 0x518: case 0x618: case 0x718:
2774 case 0x818: case 0x918: case 0xa18: case 0xb18:
2775 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2776 wrd
= (insn
>> 12) & 0xf;
2777 rd0
= (insn
>> 16) & 0xf;
2778 rd1
= (insn
>> 0) & 0xf;
2779 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2780 switch ((insn
>> 20) & 0xf) {
2782 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2785 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2788 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2791 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2794 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2797 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2800 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2803 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2806 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2811 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2812 gen_op_iwmmxt_set_mup();
2813 gen_op_iwmmxt_set_cup();
2815 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2816 case 0x408: case 0x508: case 0x608: case 0x708:
2817 case 0x808: case 0x908: case 0xa08: case 0xb08:
2818 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2819 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2821 wrd
= (insn
>> 12) & 0xf;
2822 rd0
= (insn
>> 16) & 0xf;
2823 rd1
= (insn
>> 0) & 0xf;
2824 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2825 switch ((insn
>> 22) & 3) {
2827 if (insn
& (1 << 21))
2828 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2830 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2833 if (insn
& (1 << 21))
2834 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2836 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2839 if (insn
& (1 << 21))
2840 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2842 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2845 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2846 gen_op_iwmmxt_set_mup();
2847 gen_op_iwmmxt_set_cup();
2849 case 0x201: case 0x203: case 0x205: case 0x207:
2850 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2851 case 0x211: case 0x213: case 0x215: case 0x217:
2852 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2853 wrd
= (insn
>> 5) & 0xf;
2854 rd0
= (insn
>> 12) & 0xf;
2855 rd1
= (insn
>> 0) & 0xf;
2856 if (rd0
== 0xf || rd1
== 0xf)
2858 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2859 tmp
= load_reg(s
, rd0
);
2860 tmp2
= load_reg(s
, rd1
);
2861 switch ((insn
>> 16) & 0xf) {
2862 case 0x0: /* TMIA */
2863 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2865 case 0x8: /* TMIAPH */
2866 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2868 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2869 if (insn
& (1 << 16))
2870 tcg_gen_shri_i32(tmp
, tmp
, 16);
2871 if (insn
& (1 << 17))
2872 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2873 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2876 tcg_temp_free_i32(tmp2
);
2877 tcg_temp_free_i32(tmp
);
2880 tcg_temp_free_i32(tmp2
);
2881 tcg_temp_free_i32(tmp
);
2882 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2883 gen_op_iwmmxt_set_mup();
2892 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
2893 (ie. an undefined instruction). */
2894 static int disas_dsp_insn(DisasContext
*s
, uint32_t insn
)
2896 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2899 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2900 /* Multiply with Internal Accumulate Format */
2901 rd0
= (insn
>> 12) & 0xf;
2903 acc
= (insn
>> 5) & 7;
2908 tmp
= load_reg(s
, rd0
);
2909 tmp2
= load_reg(s
, rd1
);
2910 switch ((insn
>> 16) & 0xf) {
2912 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2914 case 0x8: /* MIAPH */
2915 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2917 case 0xc: /* MIABB */
2918 case 0xd: /* MIABT */
2919 case 0xe: /* MIATB */
2920 case 0xf: /* MIATT */
2921 if (insn
& (1 << 16))
2922 tcg_gen_shri_i32(tmp
, tmp
, 16);
2923 if (insn
& (1 << 17))
2924 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2925 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2930 tcg_temp_free_i32(tmp2
);
2931 tcg_temp_free_i32(tmp
);
2933 gen_op_iwmmxt_movq_wRn_M0(acc
);
2937 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2938 /* Internal Accumulator Access Format */
2939 rdhi
= (insn
>> 16) & 0xf;
2940 rdlo
= (insn
>> 12) & 0xf;
2946 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2947 iwmmxt_load_reg(cpu_V0
, acc
);
2948 tcg_gen_extrl_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2949 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
2950 tcg_gen_extrl_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2951 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2953 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2954 iwmmxt_store_reg(cpu_V0
, acc
);
2962 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2963 #define VFP_SREG(insn, bigbit, smallbit) \
2964 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2965 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2966 if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
2967 reg = (((insn) >> (bigbit)) & 0x0f) \
2968 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2970 if (insn & (1 << (smallbit))) \
2972 reg = ((insn) >> (bigbit)) & 0x0f; \
2975 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2976 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2977 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2978 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2979 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2980 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2982 /* Move between integer and VFP cores. */
2983 static TCGv_i32
gen_vfp_mrs(void)
2985 TCGv_i32 tmp
= tcg_temp_new_i32();
2986 tcg_gen_mov_i32(tmp
, cpu_F0s
);
2990 static void gen_vfp_msr(TCGv_i32 tmp
)
2992 tcg_gen_mov_i32(cpu_F0s
, tmp
);
2993 tcg_temp_free_i32(tmp
);
2996 static void gen_neon_dup_u8(TCGv_i32 var
, int shift
)
2998 TCGv_i32 tmp
= tcg_temp_new_i32();
3000 tcg_gen_shri_i32(var
, var
, shift
);
3001 tcg_gen_ext8u_i32(var
, var
);
3002 tcg_gen_shli_i32(tmp
, var
, 8);
3003 tcg_gen_or_i32(var
, var
, tmp
);
3004 tcg_gen_shli_i32(tmp
, var
, 16);
3005 tcg_gen_or_i32(var
, var
, tmp
);
3006 tcg_temp_free_i32(tmp
);
3009 static void gen_neon_dup_low16(TCGv_i32 var
)
3011 TCGv_i32 tmp
= tcg_temp_new_i32();
3012 tcg_gen_ext16u_i32(var
, var
);
3013 tcg_gen_shli_i32(tmp
, var
, 16);
3014 tcg_gen_or_i32(var
, var
, tmp
);
3015 tcg_temp_free_i32(tmp
);
3018 static void gen_neon_dup_high16(TCGv_i32 var
)
3020 TCGv_i32 tmp
= tcg_temp_new_i32();
3021 tcg_gen_andi_i32(var
, var
, 0xffff0000);
3022 tcg_gen_shri_i32(tmp
, var
, 16);
3023 tcg_gen_or_i32(var
, var
, tmp
);
3024 tcg_temp_free_i32(tmp
);
3027 static TCGv_i32
gen_load_and_replicate(DisasContext
*s
, TCGv_i32 addr
, int size
)
3029 /* Load a single Neon element and replicate into a 32 bit TCG reg */
3030 TCGv_i32 tmp
= tcg_temp_new_i32();
3033 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
3034 gen_neon_dup_u8(tmp
, 0);
3037 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
3038 gen_neon_dup_low16(tmp
);
3041 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
3043 default: /* Avoid compiler warnings. */
3049 static int handle_vsel(uint32_t insn
, uint32_t rd
, uint32_t rn
, uint32_t rm
,
3052 uint32_t cc
= extract32(insn
, 20, 2);
3055 TCGv_i64 frn
, frm
, dest
;
3056 TCGv_i64 tmp
, zero
, zf
, nf
, vf
;
3058 zero
= tcg_const_i64(0);
3060 frn
= tcg_temp_new_i64();
3061 frm
= tcg_temp_new_i64();
3062 dest
= tcg_temp_new_i64();
3064 zf
= tcg_temp_new_i64();
3065 nf
= tcg_temp_new_i64();
3066 vf
= tcg_temp_new_i64();
3068 tcg_gen_extu_i32_i64(zf
, cpu_ZF
);
3069 tcg_gen_ext_i32_i64(nf
, cpu_NF
);
3070 tcg_gen_ext_i32_i64(vf
, cpu_VF
);
3072 tcg_gen_ld_f64(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
3073 tcg_gen_ld_f64(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
3076 tcg_gen_movcond_i64(TCG_COND_EQ
, dest
, zf
, zero
,
3080 tcg_gen_movcond_i64(TCG_COND_LT
, dest
, vf
, zero
,
3083 case 2: /* ge: N == V -> N ^ V == 0 */
3084 tmp
= tcg_temp_new_i64();
3085 tcg_gen_xor_i64(tmp
, vf
, nf
);
3086 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
3088 tcg_temp_free_i64(tmp
);
3090 case 3: /* gt: !Z && N == V */
3091 tcg_gen_movcond_i64(TCG_COND_NE
, dest
, zf
, zero
,
3093 tmp
= tcg_temp_new_i64();
3094 tcg_gen_xor_i64(tmp
, vf
, nf
);
3095 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
3097 tcg_temp_free_i64(tmp
);
3100 tcg_gen_st_f64(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
3101 tcg_temp_free_i64(frn
);
3102 tcg_temp_free_i64(frm
);
3103 tcg_temp_free_i64(dest
);
3105 tcg_temp_free_i64(zf
);
3106 tcg_temp_free_i64(nf
);
3107 tcg_temp_free_i64(vf
);
3109 tcg_temp_free_i64(zero
);
3111 TCGv_i32 frn
, frm
, dest
;
3114 zero
= tcg_const_i32(0);
3116 frn
= tcg_temp_new_i32();
3117 frm
= tcg_temp_new_i32();
3118 dest
= tcg_temp_new_i32();
3119 tcg_gen_ld_f32(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
3120 tcg_gen_ld_f32(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
3123 tcg_gen_movcond_i32(TCG_COND_EQ
, dest
, cpu_ZF
, zero
,
3127 tcg_gen_movcond_i32(TCG_COND_LT
, dest
, cpu_VF
, zero
,
3130 case 2: /* ge: N == V -> N ^ V == 0 */
3131 tmp
= tcg_temp_new_i32();
3132 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
3133 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
3135 tcg_temp_free_i32(tmp
);
3137 case 3: /* gt: !Z && N == V */
3138 tcg_gen_movcond_i32(TCG_COND_NE
, dest
, cpu_ZF
, zero
,
3140 tmp
= tcg_temp_new_i32();
3141 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
3142 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
3144 tcg_temp_free_i32(tmp
);
3147 tcg_gen_st_f32(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
3148 tcg_temp_free_i32(frn
);
3149 tcg_temp_free_i32(frm
);
3150 tcg_temp_free_i32(dest
);
3152 tcg_temp_free_i32(zero
);
3158 static int handle_vminmaxnm(uint32_t insn
, uint32_t rd
, uint32_t rn
,
3159 uint32_t rm
, uint32_t dp
)
3161 uint32_t vmin
= extract32(insn
, 6, 1);
3162 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3165 TCGv_i64 frn
, frm
, dest
;
3167 frn
= tcg_temp_new_i64();
3168 frm
= tcg_temp_new_i64();
3169 dest
= tcg_temp_new_i64();
3171 tcg_gen_ld_f64(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
3172 tcg_gen_ld_f64(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
3174 gen_helper_vfp_minnumd(dest
, frn
, frm
, fpst
);
3176 gen_helper_vfp_maxnumd(dest
, frn
, frm
, fpst
);
3178 tcg_gen_st_f64(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
3179 tcg_temp_free_i64(frn
);
3180 tcg_temp_free_i64(frm
);
3181 tcg_temp_free_i64(dest
);
3183 TCGv_i32 frn
, frm
, dest
;
3185 frn
= tcg_temp_new_i32();
3186 frm
= tcg_temp_new_i32();
3187 dest
= tcg_temp_new_i32();
3189 tcg_gen_ld_f32(frn
, cpu_env
, vfp_reg_offset(dp
, rn
));
3190 tcg_gen_ld_f32(frm
, cpu_env
, vfp_reg_offset(dp
, rm
));
3192 gen_helper_vfp_minnums(dest
, frn
, frm
, fpst
);
3194 gen_helper_vfp_maxnums(dest
, frn
, frm
, fpst
);
3196 tcg_gen_st_f32(dest
, cpu_env
, vfp_reg_offset(dp
, rd
));
3197 tcg_temp_free_i32(frn
);
3198 tcg_temp_free_i32(frm
);
3199 tcg_temp_free_i32(dest
);
3202 tcg_temp_free_ptr(fpst
);
3206 static int handle_vrint(uint32_t insn
, uint32_t rd
, uint32_t rm
, uint32_t dp
,
3209 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3212 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
3213 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3218 tcg_op
= tcg_temp_new_i64();
3219 tcg_res
= tcg_temp_new_i64();
3220 tcg_gen_ld_f64(tcg_op
, cpu_env
, vfp_reg_offset(dp
, rm
));
3221 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
3222 tcg_gen_st_f64(tcg_res
, cpu_env
, vfp_reg_offset(dp
, rd
));
3223 tcg_temp_free_i64(tcg_op
);
3224 tcg_temp_free_i64(tcg_res
);
3228 tcg_op
= tcg_temp_new_i32();
3229 tcg_res
= tcg_temp_new_i32();
3230 tcg_gen_ld_f32(tcg_op
, cpu_env
, vfp_reg_offset(dp
, rm
));
3231 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
3232 tcg_gen_st_f32(tcg_res
, cpu_env
, vfp_reg_offset(dp
, rd
));
3233 tcg_temp_free_i32(tcg_op
);
3234 tcg_temp_free_i32(tcg_res
);
3237 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3238 tcg_temp_free_i32(tcg_rmode
);
3240 tcg_temp_free_ptr(fpst
);
3244 static int handle_vcvt(uint32_t insn
, uint32_t rd
, uint32_t rm
, uint32_t dp
,
3247 bool is_signed
= extract32(insn
, 7, 1);
3248 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3249 TCGv_i32 tcg_rmode
, tcg_shift
;
3251 tcg_shift
= tcg_const_i32(0);
3253 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
3254 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3257 TCGv_i64 tcg_double
, tcg_res
;
3259 /* Rd is encoded as a single precision register even when the source
3260 * is double precision.
3262 rd
= ((rd
<< 1) & 0x1e) | ((rd
>> 4) & 0x1);
3263 tcg_double
= tcg_temp_new_i64();
3264 tcg_res
= tcg_temp_new_i64();
3265 tcg_tmp
= tcg_temp_new_i32();
3266 tcg_gen_ld_f64(tcg_double
, cpu_env
, vfp_reg_offset(1, rm
));
3268 gen_helper_vfp_tosld(tcg_res
, tcg_double
, tcg_shift
, fpst
);
3270 gen_helper_vfp_tould(tcg_res
, tcg_double
, tcg_shift
, fpst
);
3272 tcg_gen_extrl_i64_i32(tcg_tmp
, tcg_res
);
3273 tcg_gen_st_f32(tcg_tmp
, cpu_env
, vfp_reg_offset(0, rd
));
3274 tcg_temp_free_i32(tcg_tmp
);
3275 tcg_temp_free_i64(tcg_res
);
3276 tcg_temp_free_i64(tcg_double
);
3278 TCGv_i32 tcg_single
, tcg_res
;
3279 tcg_single
= tcg_temp_new_i32();
3280 tcg_res
= tcg_temp_new_i32();
3281 tcg_gen_ld_f32(tcg_single
, cpu_env
, vfp_reg_offset(0, rm
));
3283 gen_helper_vfp_tosls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
3285 gen_helper_vfp_touls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
3287 tcg_gen_st_f32(tcg_res
, cpu_env
, vfp_reg_offset(0, rd
));
3288 tcg_temp_free_i32(tcg_res
);
3289 tcg_temp_free_i32(tcg_single
);
3292 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3293 tcg_temp_free_i32(tcg_rmode
);
3295 tcg_temp_free_i32(tcg_shift
);
3297 tcg_temp_free_ptr(fpst
);
3302 /* Table for converting the most common AArch32 encoding of
3303 * rounding mode to arm_fprounding order (which matches the
3304 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
3306 static const uint8_t fp_decode_rm
[] = {
3313 static int disas_vfp_v8_insn(DisasContext
*s
, uint32_t insn
)
3315 uint32_t rd
, rn
, rm
, dp
= extract32(insn
, 8, 1);
3317 if (!arm_dc_feature(s
, ARM_FEATURE_V8
)) {
3322 VFP_DREG_D(rd
, insn
);
3323 VFP_DREG_N(rn
, insn
);
3324 VFP_DREG_M(rm
, insn
);
3326 rd
= VFP_SREG_D(insn
);
3327 rn
= VFP_SREG_N(insn
);
3328 rm
= VFP_SREG_M(insn
);
3331 if ((insn
& 0x0f800e50) == 0x0e000a00) {
3332 return handle_vsel(insn
, rd
, rn
, rm
, dp
);
3333 } else if ((insn
& 0x0fb00e10) == 0x0e800a00) {
3334 return handle_vminmaxnm(insn
, rd
, rn
, rm
, dp
);
3335 } else if ((insn
& 0x0fbc0ed0) == 0x0eb80a40) {
3336 /* VRINTA, VRINTN, VRINTP, VRINTM */
3337 int rounding
= fp_decode_rm
[extract32(insn
, 16, 2)];
3338 return handle_vrint(insn
, rd
, rm
, dp
, rounding
);
3339 } else if ((insn
& 0x0fbc0e50) == 0x0ebc0a40) {
3340 /* VCVTA, VCVTN, VCVTP, VCVTM */
3341 int rounding
= fp_decode_rm
[extract32(insn
, 16, 2)];
3342 return handle_vcvt(insn
, rd
, rm
, dp
, rounding
);
3347 /* Disassemble a VFP instruction. Returns nonzero if an error occurred
3348 (ie. an undefined instruction). */
3349 static int disas_vfp_insn(DisasContext
*s
, uint32_t insn
)
3351 uint32_t rd
, rn
, rm
, op
, i
, n
, offset
, delta_d
, delta_m
, bank_mask
;
3357 if (!arm_dc_feature(s
, ARM_FEATURE_VFP
)) {
3361 /* FIXME: this access check should not take precedence over UNDEF
3362 * for invalid encodings; we will generate incorrect syndrome information
3363 * for attempts to execute invalid vfp/neon encodings with FP disabled.
3365 if (s
->fp_excp_el
) {
3366 gen_exception_insn(s
, 4, EXCP_UDEF
,
3367 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
3371 if (!s
->vfp_enabled
) {
3372 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
3373 if ((insn
& 0x0fe00fff) != 0x0ee00a10)
3375 rn
= (insn
>> 16) & 0xf;
3376 if (rn
!= ARM_VFP_FPSID
&& rn
!= ARM_VFP_FPEXC
&& rn
!= ARM_VFP_MVFR2
3377 && rn
!= ARM_VFP_MVFR1
&& rn
!= ARM_VFP_MVFR0
) {
3382 if (extract32(insn
, 28, 4) == 0xf) {
3383 /* Encodings with T=1 (Thumb) or unconditional (ARM):
3384 * only used in v8 and above.
3386 return disas_vfp_v8_insn(s
, insn
);
3389 dp
= ((insn
& 0xf00) == 0xb00);
3390 switch ((insn
>> 24) & 0xf) {
3392 if (insn
& (1 << 4)) {
3393 /* single register transfer */
3394 rd
= (insn
>> 12) & 0xf;
3399 VFP_DREG_N(rn
, insn
);
3402 if (insn
& 0x00c00060
3403 && !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
3407 pass
= (insn
>> 21) & 1;
3408 if (insn
& (1 << 22)) {
3410 offset
= ((insn
>> 5) & 3) * 8;
3411 } else if (insn
& (1 << 5)) {
3413 offset
= (insn
& (1 << 6)) ? 16 : 0;
3418 if (insn
& ARM_CP_RW_BIT
) {
3420 tmp
= neon_load_reg(rn
, pass
);
3424 tcg_gen_shri_i32(tmp
, tmp
, offset
);
3425 if (insn
& (1 << 23))
3431 if (insn
& (1 << 23)) {
3433 tcg_gen_shri_i32(tmp
, tmp
, 16);
3439 tcg_gen_sari_i32(tmp
, tmp
, 16);
3448 store_reg(s
, rd
, tmp
);
3451 tmp
= load_reg(s
, rd
);
3452 if (insn
& (1 << 23)) {
3454 int vec_size
= pass
? 16 : 8;
3455 tcg_gen_gvec_dup_i32(size
, neon_reg_offset(rn
, 0),
3456 vec_size
, vec_size
, tmp
);
3457 tcg_temp_free_i32(tmp
);
3462 tmp2
= neon_load_reg(rn
, pass
);
3463 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 8);
3464 tcg_temp_free_i32(tmp2
);
3467 tmp2
= neon_load_reg(rn
, pass
);
3468 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 16);
3469 tcg_temp_free_i32(tmp2
);
3474 neon_store_reg(rn
, pass
, tmp
);
3478 if ((insn
& 0x6f) != 0x00)
3480 rn
= VFP_SREG_N(insn
);
3481 if (insn
& ARM_CP_RW_BIT
) {
3483 if (insn
& (1 << 21)) {
3484 /* system register */
3489 /* VFP2 allows access to FSID from userspace.
3490 VFP3 restricts all id registers to privileged
3493 && arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3496 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3501 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3503 case ARM_VFP_FPINST
:
3504 case ARM_VFP_FPINST2
:
3505 /* Not present in VFP3. */
3507 || arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3510 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3514 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
3515 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
3517 tmp
= tcg_temp_new_i32();
3518 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
3522 if (!arm_dc_feature(s
, ARM_FEATURE_V8
)) {
3529 || !arm_dc_feature(s
, ARM_FEATURE_MVFR
)) {
3532 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
3538 gen_mov_F0_vreg(0, rn
);
3539 tmp
= gen_vfp_mrs();
3542 /* Set the 4 flag bits in the CPSR. */
3544 tcg_temp_free_i32(tmp
);
3546 store_reg(s
, rd
, tmp
);
3550 if (insn
& (1 << 21)) {
3552 /* system register */
3557 /* Writes are ignored. */
3560 tmp
= load_reg(s
, rd
);
3561 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
3562 tcg_temp_free_i32(tmp
);
3568 /* TODO: VFP subarchitecture support.
3569 * For now, keep the EN bit only */
3570 tmp
= load_reg(s
, rd
);
3571 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
3572 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
3575 case ARM_VFP_FPINST
:
3576 case ARM_VFP_FPINST2
:
3580 tmp
= load_reg(s
, rd
);
3581 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
3587 tmp
= load_reg(s
, rd
);
3589 gen_mov_vreg_F0(0, rn
);
3594 /* data processing */
3595 /* The opcode is in bits 23, 21, 20 and 6. */
3596 op
= ((insn
>> 20) & 8) | ((insn
>> 19) & 6) | ((insn
>> 6) & 1);
3600 rn
= ((insn
>> 15) & 0x1e) | ((insn
>> 7) & 1);
3602 /* rn is register number */
3603 VFP_DREG_N(rn
, insn
);
3606 if (op
== 15 && (rn
== 15 || ((rn
& 0x1c) == 0x18) ||
3607 ((rn
& 0x1e) == 0x6))) {
3608 /* Integer or single/half precision destination. */
3609 rd
= VFP_SREG_D(insn
);
3611 VFP_DREG_D(rd
, insn
);
3614 (((rn
& 0x1c) == 0x10) || ((rn
& 0x14) == 0x14) ||
3615 ((rn
& 0x1e) == 0x4))) {
3616 /* VCVT from int or half precision is always from S reg
3617 * regardless of dp bit. VCVT with immediate frac_bits
3618 * has same format as SREG_M.
3620 rm
= VFP_SREG_M(insn
);
3622 VFP_DREG_M(rm
, insn
);
3625 rn
= VFP_SREG_N(insn
);
3626 if (op
== 15 && rn
== 15) {
3627 /* Double precision destination. */
3628 VFP_DREG_D(rd
, insn
);
3630 rd
= VFP_SREG_D(insn
);
3632 /* NB that we implicitly rely on the encoding for the frac_bits
3633 * in VCVT of fixed to float being the same as that of an SREG_M
3635 rm
= VFP_SREG_M(insn
);
3638 veclen
= s
->vec_len
;
3639 if (op
== 15 && rn
> 3)
3642 /* Shut up compiler warnings. */
3653 /* Figure out what type of vector operation this is. */
3654 if ((rd
& bank_mask
) == 0) {
3659 delta_d
= (s
->vec_stride
>> 1) + 1;
3661 delta_d
= s
->vec_stride
+ 1;
3663 if ((rm
& bank_mask
) == 0) {
3664 /* mixed scalar/vector */
3673 /* Load the initial operands. */
3678 /* Integer source */
3679 gen_mov_F0_vreg(0, rm
);
3684 gen_mov_F0_vreg(dp
, rd
);
3685 gen_mov_F1_vreg(dp
, rm
);
3689 /* Compare with zero */
3690 gen_mov_F0_vreg(dp
, rd
);
3701 /* Source and destination the same. */
3702 gen_mov_F0_vreg(dp
, rd
);
3708 /* VCVTB, VCVTT: only present with the halfprec extension
3709 * UNPREDICTABLE if bit 8 is set prior to ARMv8
3710 * (we choose to UNDEF)
3712 if ((dp
&& !arm_dc_feature(s
, ARM_FEATURE_V8
)) ||
3713 !arm_dc_feature(s
, ARM_FEATURE_VFP_FP16
)) {
3716 if (!extract32(rn
, 1, 1)) {
3717 /* Half precision source. */
3718 gen_mov_F0_vreg(0, rm
);
3721 /* Otherwise fall through */
3723 /* One source operand. */
3724 gen_mov_F0_vreg(dp
, rm
);
3728 /* Two source operands. */
3729 gen_mov_F0_vreg(dp
, rn
);
3730 gen_mov_F1_vreg(dp
, rm
);
3734 /* Perform the calculation. */
3736 case 0: /* VMLA: fd + (fn * fm) */
3737 /* Note that order of inputs to the add matters for NaNs */
3739 gen_mov_F0_vreg(dp
, rd
);
3742 case 1: /* VMLS: fd + -(fn * fm) */
3745 gen_mov_F0_vreg(dp
, rd
);
3748 case 2: /* VNMLS: -fd + (fn * fm) */
3749 /* Note that it isn't valid to replace (-A + B) with (B - A)
3750 * or similar plausible looking simplifications
3751 * because this will give wrong results for NaNs.
3754 gen_mov_F0_vreg(dp
, rd
);
3758 case 3: /* VNMLA: -fd + -(fn * fm) */
3761 gen_mov_F0_vreg(dp
, rd
);
3765 case 4: /* mul: fn * fm */
3768 case 5: /* nmul: -(fn * fm) */
3772 case 6: /* add: fn + fm */
3775 case 7: /* sub: fn - fm */
3778 case 8: /* div: fn / fm */
3781 case 10: /* VFNMA : fd = muladd(-fd, fn, fm) */
3782 case 11: /* VFNMS : fd = muladd(-fd, -fn, fm) */
3783 case 12: /* VFMA : fd = muladd( fd, fn, fm) */
3784 case 13: /* VFMS : fd = muladd( fd, -fn, fm) */
3785 /* These are fused multiply-add, and must be done as one
3786 * floating point operation with no rounding between the
3787 * multiplication and addition steps.
3788 * NB that doing the negations here as separate steps is
3789 * correct : an input NaN should come out with its sign bit
3790 * flipped if it is a negated-input.
3792 if (!arm_dc_feature(s
, ARM_FEATURE_VFP4
)) {
3800 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
3802 frd
= tcg_temp_new_i64();
3803 tcg_gen_ld_f64(frd
, cpu_env
, vfp_reg_offset(dp
, rd
));
3806 gen_helper_vfp_negd(frd
, frd
);
3808 fpst
= get_fpstatus_ptr(0);
3809 gen_helper_vfp_muladdd(cpu_F0d
, cpu_F0d
,
3810 cpu_F1d
, frd
, fpst
);
3811 tcg_temp_free_ptr(fpst
);
3812 tcg_temp_free_i64(frd
);
3818 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
3820 frd
= tcg_temp_new_i32();
3821 tcg_gen_ld_f32(frd
, cpu_env
, vfp_reg_offset(dp
, rd
));
3823 gen_helper_vfp_negs(frd
, frd
);
3825 fpst
= get_fpstatus_ptr(0);
3826 gen_helper_vfp_muladds(cpu_F0s
, cpu_F0s
,
3827 cpu_F1s
, frd
, fpst
);
3828 tcg_temp_free_ptr(fpst
);
3829 tcg_temp_free_i32(frd
);
3832 case 14: /* fconst */
3833 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
3837 n
= (insn
<< 12) & 0x80000000;
3838 i
= ((insn
>> 12) & 0x70) | (insn
& 0xf);
3845 tcg_gen_movi_i64(cpu_F0d
, ((uint64_t)n
) << 32);
3852 tcg_gen_movi_i32(cpu_F0s
, n
);
3855 case 15: /* extension space */
3869 case 4: /* vcvtb.f32.f16, vcvtb.f64.f16 */
3871 TCGv_ptr fpst
= get_fpstatus_ptr(false);
3872 TCGv_i32 ahp_mode
= get_ahp_flag();
3873 tmp
= gen_vfp_mrs();
3874 tcg_gen_ext16u_i32(tmp
, tmp
);
3876 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d
, tmp
,
3879 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
,
3882 tcg_temp_free_i32(ahp_mode
);
3883 tcg_temp_free_ptr(fpst
);
3884 tcg_temp_free_i32(tmp
);
3887 case 5: /* vcvtt.f32.f16, vcvtt.f64.f16 */
3889 TCGv_ptr fpst
= get_fpstatus_ptr(false);
3890 TCGv_i32 ahp
= get_ahp_flag();
3891 tmp
= gen_vfp_mrs();
3892 tcg_gen_shri_i32(tmp
, tmp
, 16);
3894 gen_helper_vfp_fcvt_f16_to_f64(cpu_F0d
, tmp
,
3897 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
,
3900 tcg_temp_free_i32(tmp
);
3901 tcg_temp_free_i32(ahp
);
3902 tcg_temp_free_ptr(fpst
);
3905 case 6: /* vcvtb.f16.f32, vcvtb.f16.f64 */
3907 TCGv_ptr fpst
= get_fpstatus_ptr(false);
3908 TCGv_i32 ahp
= get_ahp_flag();
3909 tmp
= tcg_temp_new_i32();
3912 gen_helper_vfp_fcvt_f64_to_f16(tmp
, cpu_F0d
,
3915 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
,
3918 tcg_temp_free_i32(ahp
);
3919 tcg_temp_free_ptr(fpst
);
3920 gen_mov_F0_vreg(0, rd
);
3921 tmp2
= gen_vfp_mrs();
3922 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
3923 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3924 tcg_temp_free_i32(tmp2
);
3928 case 7: /* vcvtt.f16.f32, vcvtt.f16.f64 */
3930 TCGv_ptr fpst
= get_fpstatus_ptr(false);
3931 TCGv_i32 ahp
= get_ahp_flag();
3932 tmp
= tcg_temp_new_i32();
3934 gen_helper_vfp_fcvt_f64_to_f16(tmp
, cpu_F0d
,
3937 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
,
3940 tcg_temp_free_i32(ahp
);
3941 tcg_temp_free_ptr(fpst
);
3942 tcg_gen_shli_i32(tmp
, tmp
, 16);
3943 gen_mov_F0_vreg(0, rd
);
3944 tmp2
= gen_vfp_mrs();
3945 tcg_gen_ext16u_i32(tmp2
, tmp2
);
3946 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3947 tcg_temp_free_i32(tmp2
);
3960 case 11: /* cmpez */
3964 case 12: /* vrintr */
3966 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3968 gen_helper_rintd(cpu_F0d
, cpu_F0d
, fpst
);
3970 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpst
);
3972 tcg_temp_free_ptr(fpst
);
3975 case 13: /* vrintz */
3977 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3979 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
3980 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3982 gen_helper_rintd(cpu_F0d
, cpu_F0d
, fpst
);
3984 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpst
);
3986 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3987 tcg_temp_free_i32(tcg_rmode
);
3988 tcg_temp_free_ptr(fpst
);
3991 case 14: /* vrintx */
3993 TCGv_ptr fpst
= get_fpstatus_ptr(0);
3995 gen_helper_rintd_exact(cpu_F0d
, cpu_F0d
, fpst
);
3997 gen_helper_rints_exact(cpu_F0s
, cpu_F0s
, fpst
);
3999 tcg_temp_free_ptr(fpst
);
4002 case 15: /* single<->double conversion */
4004 gen_helper_vfp_fcvtsd(cpu_F0s
, cpu_F0d
, cpu_env
);
4006 gen_helper_vfp_fcvtds(cpu_F0d
, cpu_F0s
, cpu_env
);
4008 case 16: /* fuito */
4009 gen_vfp_uito(dp
, 0);
4011 case 17: /* fsito */
4012 gen_vfp_sito(dp
, 0);
4014 case 20: /* fshto */
4015 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4018 gen_vfp_shto(dp
, 16 - rm
, 0);
4020 case 21: /* fslto */
4021 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4024 gen_vfp_slto(dp
, 32 - rm
, 0);
4026 case 22: /* fuhto */
4027 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4030 gen_vfp_uhto(dp
, 16 - rm
, 0);
4032 case 23: /* fulto */
4033 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4036 gen_vfp_ulto(dp
, 32 - rm
, 0);
4038 case 24: /* ftoui */
4039 gen_vfp_toui(dp
, 0);
4041 case 25: /* ftouiz */
4042 gen_vfp_touiz(dp
, 0);
4044 case 26: /* ftosi */
4045 gen_vfp_tosi(dp
, 0);
4047 case 27: /* ftosiz */
4048 gen_vfp_tosiz(dp
, 0);
4050 case 28: /* ftosh */
4051 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4054 gen_vfp_tosh(dp
, 16 - rm
, 0);
4056 case 29: /* ftosl */
4057 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4060 gen_vfp_tosl(dp
, 32 - rm
, 0);
4062 case 30: /* ftouh */
4063 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4066 gen_vfp_touh(dp
, 16 - rm
, 0);
4068 case 31: /* ftoul */
4069 if (!arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
4072 gen_vfp_toul(dp
, 32 - rm
, 0);
4074 default: /* undefined */
4078 default: /* undefined */
4082 /* Write back the result. */
4083 if (op
== 15 && (rn
>= 8 && rn
<= 11)) {
4084 /* Comparison, do nothing. */
4085 } else if (op
== 15 && dp
&& ((rn
& 0x1c) == 0x18 ||
4086 (rn
& 0x1e) == 0x6)) {
4087 /* VCVT double to int: always integer result.
4088 * VCVT double to half precision is always a single
4091 gen_mov_vreg_F0(0, rd
);
4092 } else if (op
== 15 && rn
== 15) {
4094 gen_mov_vreg_F0(!dp
, rd
);
4096 gen_mov_vreg_F0(dp
, rd
);
4099 /* break out of the loop if we have finished */
4103 if (op
== 15 && delta_m
== 0) {
4104 /* single source one-many */
4106 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
4108 gen_mov_vreg_F0(dp
, rd
);
4112 /* Setup the next operands. */
4114 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
4118 /* One source operand. */
4119 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
4121 gen_mov_F0_vreg(dp
, rm
);
4123 /* Two source operands. */
4124 rn
= ((rn
+ delta_d
) & (bank_mask
- 1))
4126 gen_mov_F0_vreg(dp
, rn
);
4128 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
4130 gen_mov_F1_vreg(dp
, rm
);
4138 if ((insn
& 0x03e00000) == 0x00400000) {
4139 /* two-register transfer */
4140 rn
= (insn
>> 16) & 0xf;
4141 rd
= (insn
>> 12) & 0xf;
4143 VFP_DREG_M(rm
, insn
);
4145 rm
= VFP_SREG_M(insn
);
4148 if (insn
& ARM_CP_RW_BIT
) {
4151 gen_mov_F0_vreg(0, rm
* 2);
4152 tmp
= gen_vfp_mrs();
4153 store_reg(s
, rd
, tmp
);
4154 gen_mov_F0_vreg(0, rm
* 2 + 1);
4155 tmp
= gen_vfp_mrs();
4156 store_reg(s
, rn
, tmp
);
4158 gen_mov_F0_vreg(0, rm
);
4159 tmp
= gen_vfp_mrs();
4160 store_reg(s
, rd
, tmp
);
4161 gen_mov_F0_vreg(0, rm
+ 1);
4162 tmp
= gen_vfp_mrs();
4163 store_reg(s
, rn
, tmp
);
4168 tmp
= load_reg(s
, rd
);
4170 gen_mov_vreg_F0(0, rm
* 2);
4171 tmp
= load_reg(s
, rn
);
4173 gen_mov_vreg_F0(0, rm
* 2 + 1);
4175 tmp
= load_reg(s
, rd
);
4177 gen_mov_vreg_F0(0, rm
);
4178 tmp
= load_reg(s
, rn
);
4180 gen_mov_vreg_F0(0, rm
+ 1);
4185 rn
= (insn
>> 16) & 0xf;
4187 VFP_DREG_D(rd
, insn
);
4189 rd
= VFP_SREG_D(insn
);
4190 if ((insn
& 0x01200000) == 0x01000000) {
4191 /* Single load/store */
4192 offset
= (insn
& 0xff) << 2;
4193 if ((insn
& (1 << 23)) == 0)
4195 if (s
->thumb
&& rn
== 15) {
4196 /* This is actually UNPREDICTABLE */
4197 addr
= tcg_temp_new_i32();
4198 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
4200 addr
= load_reg(s
, rn
);
4202 tcg_gen_addi_i32(addr
, addr
, offset
);
4203 if (insn
& (1 << 20)) {
4204 gen_vfp_ld(s
, dp
, addr
);
4205 gen_mov_vreg_F0(dp
, rd
);
4207 gen_mov_F0_vreg(dp
, rd
);
4208 gen_vfp_st(s
, dp
, addr
);
4210 tcg_temp_free_i32(addr
);
4212 /* load/store multiple */
4213 int w
= insn
& (1 << 21);
4215 n
= (insn
>> 1) & 0x7f;
4219 if (w
&& !(((insn
>> 23) ^ (insn
>> 24)) & 1)) {
4220 /* P == U , W == 1 => UNDEF */
4223 if (n
== 0 || (rd
+ n
) > 32 || (dp
&& n
> 16)) {
4224 /* UNPREDICTABLE cases for bad immediates: we choose to
4225 * UNDEF to avoid generating huge numbers of TCG ops
4229 if (rn
== 15 && w
) {
4230 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
4234 if (s
->thumb
&& rn
== 15) {
4235 /* This is actually UNPREDICTABLE */
4236 addr
= tcg_temp_new_i32();
4237 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
4239 addr
= load_reg(s
, rn
);
4241 if (insn
& (1 << 24)) /* pre-decrement */
4242 tcg_gen_addi_i32(addr
, addr
, -((insn
& 0xff) << 2));
4244 if (s
->v8m_stackcheck
&& rn
== 13 && w
) {
4246 * Here 'addr' is the lowest address we will store to,
4247 * and is either the old SP (if post-increment) or
4248 * the new SP (if pre-decrement). For post-increment
4249 * where the old value is below the limit and the new
4250 * value is above, it is UNKNOWN whether the limit check
4251 * triggers; we choose to trigger.
4253 gen_helper_v8m_stackcheck(cpu_env
, addr
);
4260 for (i
= 0; i
< n
; i
++) {
4261 if (insn
& ARM_CP_RW_BIT
) {
4263 gen_vfp_ld(s
, dp
, addr
);
4264 gen_mov_vreg_F0(dp
, rd
+ i
);
4267 gen_mov_F0_vreg(dp
, rd
+ i
);
4268 gen_vfp_st(s
, dp
, addr
);
4270 tcg_gen_addi_i32(addr
, addr
, offset
);
4274 if (insn
& (1 << 24))
4275 offset
= -offset
* n
;
4276 else if (dp
&& (insn
& 1))
4282 tcg_gen_addi_i32(addr
, addr
, offset
);
4283 store_reg(s
, rn
, addr
);
4285 tcg_temp_free_i32(addr
);
4291 /* Should never happen. */
4297 static inline bool use_goto_tb(DisasContext
*s
, target_ulong dest
)
4299 #ifndef CONFIG_USER_ONLY
4300 return (s
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) ||
4301 ((s
->pc
- 1) & TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
4307 static void gen_goto_ptr(void)
4309 tcg_gen_lookup_and_goto_ptr();
4312 /* This will end the TB but doesn't guarantee we'll return to
4313 * cpu_loop_exec. Any live exit_requests will be processed as we
4314 * enter the next TB.
4316 static void gen_goto_tb(DisasContext
*s
, int n
, target_ulong dest
)
4318 if (use_goto_tb(s
, dest
)) {
4320 gen_set_pc_im(s
, dest
);
4321 tcg_gen_exit_tb(s
->base
.tb
, n
);
4323 gen_set_pc_im(s
, dest
);
4326 s
->base
.is_jmp
= DISAS_NORETURN
;
4329 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
4331 if (unlikely(is_singlestepping(s
))) {
4332 /* An indirect jump so that we still trigger the debug exception. */
4337 gen_goto_tb(s
, 0, dest
);
4341 static inline void gen_mulxy(TCGv_i32 t0
, TCGv_i32 t1
, int x
, int y
)
4344 tcg_gen_sari_i32(t0
, t0
, 16);
4348 tcg_gen_sari_i32(t1
, t1
, 16);
4351 tcg_gen_mul_i32(t0
, t0
, t1
);
4354 /* Return the mask of PSR bits set by a MSR instruction. */
4355 static uint32_t msr_mask(DisasContext
*s
, int flags
, int spsr
)
4360 if (flags
& (1 << 0))
4362 if (flags
& (1 << 1))
4364 if (flags
& (1 << 2))
4366 if (flags
& (1 << 3))
4369 /* Mask out undefined bits. */
4370 mask
&= ~CPSR_RESERVED
;
4371 if (!arm_dc_feature(s
, ARM_FEATURE_V4T
)) {
4374 if (!arm_dc_feature(s
, ARM_FEATURE_V5
)) {
4375 mask
&= ~CPSR_Q
; /* V5TE in reality*/
4377 if (!arm_dc_feature(s
, ARM_FEATURE_V6
)) {
4378 mask
&= ~(CPSR_E
| CPSR_GE
);
4380 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB2
)) {
4383 /* Mask out execution state and reserved bits. */
4385 mask
&= ~(CPSR_EXEC
| CPSR_RESERVED
);
4387 /* Mask out privileged bits. */
4393 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
4394 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv_i32 t0
)
4398 /* ??? This is also undefined in system mode. */
4402 tmp
= load_cpu_field(spsr
);
4403 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
4404 tcg_gen_andi_i32(t0
, t0
, mask
);
4405 tcg_gen_or_i32(tmp
, tmp
, t0
);
4406 store_cpu_field(tmp
, spsr
);
4408 gen_set_cpsr(t0
, mask
);
4410 tcg_temp_free_i32(t0
);
4415 /* Returns nonzero if access to the PSR is not permitted. */
4416 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
4419 tmp
= tcg_temp_new_i32();
4420 tcg_gen_movi_i32(tmp
, val
);
4421 return gen_set_psr(s
, mask
, spsr
, tmp
);
4424 static bool msr_banked_access_decode(DisasContext
*s
, int r
, int sysm
, int rn
,
4425 int *tgtmode
, int *regno
)
4427 /* Decode the r and sysm fields of MSR/MRS banked accesses into
4428 * the target mode and register number, and identify the various
4429 * unpredictable cases.
4430 * MSR (banked) and MRS (banked) are CONSTRAINED UNPREDICTABLE if:
4431 * + executed in user mode
4432 * + using R15 as the src/dest register
4433 * + accessing an unimplemented register
4434 * + accessing a register that's inaccessible at current PL/security state*
4435 * + accessing a register that you could access with a different insn
4436 * We choose to UNDEF in all these cases.
4437 * Since we don't know which of the various AArch32 modes we are in
4438 * we have to defer some checks to runtime.
4439 * Accesses to Monitor mode registers from Secure EL1 (which implies
4440 * that EL3 is AArch64) must trap to EL3.
4442 * If the access checks fail this function will emit code to take
4443 * an exception and return false. Otherwise it will return true,
4444 * and set *tgtmode and *regno appropriately.
4446 int exc_target
= default_exception_el(s
);
4448 /* These instructions are present only in ARMv8, or in ARMv7 with the
4449 * Virtualization Extensions.
4451 if (!arm_dc_feature(s
, ARM_FEATURE_V8
) &&
4452 !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
4456 if (IS_USER(s
) || rn
== 15) {
4460 /* The table in the v8 ARM ARM section F5.2.3 describes the encoding
4461 * of registers into (r, sysm).
4464 /* SPSRs for other modes */
4466 case 0xe: /* SPSR_fiq */
4467 *tgtmode
= ARM_CPU_MODE_FIQ
;
4469 case 0x10: /* SPSR_irq */
4470 *tgtmode
= ARM_CPU_MODE_IRQ
;
4472 case 0x12: /* SPSR_svc */
4473 *tgtmode
= ARM_CPU_MODE_SVC
;
4475 case 0x14: /* SPSR_abt */
4476 *tgtmode
= ARM_CPU_MODE_ABT
;
4478 case 0x16: /* SPSR_und */
4479 *tgtmode
= ARM_CPU_MODE_UND
;
4481 case 0x1c: /* SPSR_mon */
4482 *tgtmode
= ARM_CPU_MODE_MON
;
4484 case 0x1e: /* SPSR_hyp */
4485 *tgtmode
= ARM_CPU_MODE_HYP
;
4487 default: /* unallocated */
4490 /* We arbitrarily assign SPSR a register number of 16. */
4493 /* general purpose registers for other modes */
4495 case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */
4496 *tgtmode
= ARM_CPU_MODE_USR
;
4499 case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */
4500 *tgtmode
= ARM_CPU_MODE_FIQ
;
4503 case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */
4504 *tgtmode
= ARM_CPU_MODE_IRQ
;
4505 *regno
= sysm
& 1 ? 13 : 14;
4507 case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */
4508 *tgtmode
= ARM_CPU_MODE_SVC
;
4509 *regno
= sysm
& 1 ? 13 : 14;
4511 case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */
4512 *tgtmode
= ARM_CPU_MODE_ABT
;
4513 *regno
= sysm
& 1 ? 13 : 14;
4515 case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */
4516 *tgtmode
= ARM_CPU_MODE_UND
;
4517 *regno
= sysm
& 1 ? 13 : 14;
4519 case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */
4520 *tgtmode
= ARM_CPU_MODE_MON
;
4521 *regno
= sysm
& 1 ? 13 : 14;
4523 case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */
4524 *tgtmode
= ARM_CPU_MODE_HYP
;
4525 /* Arbitrarily pick 17 for ELR_Hyp (which is not a banked LR!) */
4526 *regno
= sysm
& 1 ? 13 : 17;
4528 default: /* unallocated */
4533 /* Catch the 'accessing inaccessible register' cases we can detect
4534 * at translate time.
4537 case ARM_CPU_MODE_MON
:
4538 if (!arm_dc_feature(s
, ARM_FEATURE_EL3
) || s
->ns
) {
4541 if (s
->current_el
== 1) {
4542 /* If we're in Secure EL1 (which implies that EL3 is AArch64)
4543 * then accesses to Mon registers trap to EL3
4549 case ARM_CPU_MODE_HYP
:
4551 * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
4552 * (and so we can forbid accesses from EL2 or below). elr_hyp
4553 * can be accessed also from Hyp mode, so forbid accesses from
4556 if (!arm_dc_feature(s
, ARM_FEATURE_EL2
) || s
->current_el
< 2 ||
4557 (s
->current_el
< 3 && *regno
!= 17)) {
4568 /* If we get here then some access check did not pass */
4569 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(), exc_target
);
4573 static void gen_msr_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
4575 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
4576 int tgtmode
= 0, regno
= 0;
4578 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
4582 /* Sync state because msr_banked() can raise exceptions */
4583 gen_set_condexec(s
);
4584 gen_set_pc_im(s
, s
->pc
- 4);
4585 tcg_reg
= load_reg(s
, rn
);
4586 tcg_tgtmode
= tcg_const_i32(tgtmode
);
4587 tcg_regno
= tcg_const_i32(regno
);
4588 gen_helper_msr_banked(cpu_env
, tcg_reg
, tcg_tgtmode
, tcg_regno
);
4589 tcg_temp_free_i32(tcg_tgtmode
);
4590 tcg_temp_free_i32(tcg_regno
);
4591 tcg_temp_free_i32(tcg_reg
);
4592 s
->base
.is_jmp
= DISAS_UPDATE
;
4595 static void gen_mrs_banked(DisasContext
*s
, int r
, int sysm
, int rn
)
4597 TCGv_i32 tcg_reg
, tcg_tgtmode
, tcg_regno
;
4598 int tgtmode
= 0, regno
= 0;
4600 if (!msr_banked_access_decode(s
, r
, sysm
, rn
, &tgtmode
, ®no
)) {
4604 /* Sync state because mrs_banked() can raise exceptions */
4605 gen_set_condexec(s
);
4606 gen_set_pc_im(s
, s
->pc
- 4);
4607 tcg_reg
= tcg_temp_new_i32();
4608 tcg_tgtmode
= tcg_const_i32(tgtmode
);
4609 tcg_regno
= tcg_const_i32(regno
);
4610 gen_helper_mrs_banked(tcg_reg
, cpu_env
, tcg_tgtmode
, tcg_regno
);
4611 tcg_temp_free_i32(tcg_tgtmode
);
4612 tcg_temp_free_i32(tcg_regno
);
4613 store_reg(s
, rn
, tcg_reg
);
4614 s
->base
.is_jmp
= DISAS_UPDATE
;
4617 /* Store value to PC as for an exception return (ie don't
4618 * mask bits). The subsequent call to gen_helper_cpsr_write_eret()
4619 * will do the masking based on the new value of the Thumb bit.
4621 static void store_pc_exc_ret(DisasContext
*s
, TCGv_i32 pc
)
4623 tcg_gen_mov_i32(cpu_R
[15], pc
);
4624 tcg_temp_free_i32(pc
);
4627 /* Generate a v6 exception return. Marks both values as dead. */
4628 static void gen_rfe(DisasContext
*s
, TCGv_i32 pc
, TCGv_i32 cpsr
)
4630 store_pc_exc_ret(s
, pc
);
4631 /* The cpsr_write_eret helper will mask the low bits of PC
4632 * appropriately depending on the new Thumb bit, so it must
4633 * be called after storing the new PC.
4635 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
4638 gen_helper_cpsr_write_eret(cpu_env
, cpsr
);
4639 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
4642 tcg_temp_free_i32(cpsr
);
4643 /* Must exit loop to check un-masked IRQs */
4644 s
->base
.is_jmp
= DISAS_EXIT
;
4647 /* Generate an old-style exception return. Marks pc as dead. */
4648 static void gen_exception_return(DisasContext
*s
, TCGv_i32 pc
)
4650 gen_rfe(s
, pc
, load_cpu_field(spsr
));
4654 * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we
4655 * only call the helper when running single threaded TCG code to ensure
4656 * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we
4657 * just skip this instruction. Currently the SEV/SEVL instructions
4658 * which are *one* of many ways to wake the CPU from WFE are not
4659 * implemented so we can't sleep like WFI does.
4661 static void gen_nop_hint(DisasContext
*s
, int val
)
4664 /* When running in MTTCG we don't generate jumps to the yield and
4665 * WFE helpers as it won't affect the scheduling of other vCPUs.
4666 * If we wanted to more completely model WFE/SEV so we don't busy
4667 * spin unnecessarily we would need to do something more involved.
4670 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
4671 gen_set_pc_im(s
, s
->pc
);
4672 s
->base
.is_jmp
= DISAS_YIELD
;
4676 gen_set_pc_im(s
, s
->pc
);
4677 s
->base
.is_jmp
= DISAS_WFI
;
4680 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
4681 gen_set_pc_im(s
, s
->pc
);
4682 s
->base
.is_jmp
= DISAS_WFE
;
4687 /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. */
4693 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
4695 static inline void gen_neon_add(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
4698 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
4699 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
4700 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
4705 static inline void gen_neon_rsb(int size
, TCGv_i32 t0
, TCGv_i32 t1
)
4708 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
4709 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
4710 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
4715 /* 32-bit pairwise ops end up the same as the elementwise versions. */
4716 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
4717 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
4718 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
4719 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
4721 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
4722 switch ((size << 1) | u) { \
4724 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
4727 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
4730 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
4733 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
4736 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
4739 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
4741 default: return 1; \
4744 #define GEN_NEON_INTEGER_OP(name) do { \
4745 switch ((size << 1) | u) { \
4747 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
4750 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
4753 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
4756 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
4759 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
4762 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
4764 default: return 1; \
4767 static TCGv_i32
neon_load_scratch(int scratch
)
4769 TCGv_i32 tmp
= tcg_temp_new_i32();
4770 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
4774 static void neon_store_scratch(int scratch
, TCGv_i32 var
)
4776 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
4777 tcg_temp_free_i32(var
);
4780 static inline TCGv_i32
neon_get_scalar(int size
, int reg
)
4784 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
4786 gen_neon_dup_high16(tmp
);
4788 gen_neon_dup_low16(tmp
);
4791 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
4796 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
4800 if (!q
&& size
== 2) {
4803 pd
= vfp_reg_ptr(true, rd
);
4804 pm
= vfp_reg_ptr(true, rm
);
4808 gen_helper_neon_qunzip8(pd
, pm
);
4811 gen_helper_neon_qunzip16(pd
, pm
);
4814 gen_helper_neon_qunzip32(pd
, pm
);
4822 gen_helper_neon_unzip8(pd
, pm
);
4825 gen_helper_neon_unzip16(pd
, pm
);
4831 tcg_temp_free_ptr(pd
);
4832 tcg_temp_free_ptr(pm
);
4836 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
4840 if (!q
&& size
== 2) {
4843 pd
= vfp_reg_ptr(true, rd
);
4844 pm
= vfp_reg_ptr(true, rm
);
4848 gen_helper_neon_qzip8(pd
, pm
);
4851 gen_helper_neon_qzip16(pd
, pm
);
4854 gen_helper_neon_qzip32(pd
, pm
);
4862 gen_helper_neon_zip8(pd
, pm
);
4865 gen_helper_neon_zip16(pd
, pm
);
4871 tcg_temp_free_ptr(pd
);
4872 tcg_temp_free_ptr(pm
);
4876 static void gen_neon_trn_u8(TCGv_i32 t0
, TCGv_i32 t1
)
4880 rd
= tcg_temp_new_i32();
4881 tmp
= tcg_temp_new_i32();
4883 tcg_gen_shli_i32(rd
, t0
, 8);
4884 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
4885 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
4886 tcg_gen_or_i32(rd
, rd
, tmp
);
4888 tcg_gen_shri_i32(t1
, t1
, 8);
4889 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
4890 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
4891 tcg_gen_or_i32(t1
, t1
, tmp
);
4892 tcg_gen_mov_i32(t0
, rd
);
4894 tcg_temp_free_i32(tmp
);
4895 tcg_temp_free_i32(rd
);
4898 static void gen_neon_trn_u16(TCGv_i32 t0
, TCGv_i32 t1
)
4902 rd
= tcg_temp_new_i32();
4903 tmp
= tcg_temp_new_i32();
4905 tcg_gen_shli_i32(rd
, t0
, 16);
4906 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
4907 tcg_gen_or_i32(rd
, rd
, tmp
);
4908 tcg_gen_shri_i32(t1
, t1
, 16);
4909 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
4910 tcg_gen_or_i32(t1
, t1
, tmp
);
4911 tcg_gen_mov_i32(t0
, rd
);
4913 tcg_temp_free_i32(tmp
);
4914 tcg_temp_free_i32(rd
);
4922 } const neon_ls_element_type
[11] = {
4936 /* Translate a NEON load/store element instruction. Return nonzero if the
4937 instruction is invalid. */
4938 static int disas_neon_ls_insn(DisasContext
*s
, uint32_t insn
)
4957 /* FIXME: this access check should not take precedence over UNDEF
4958 * for invalid encodings; we will generate incorrect syndrome information
4959 * for attempts to execute invalid vfp/neon encodings with FP disabled.
4961 if (s
->fp_excp_el
) {
4962 gen_exception_insn(s
, 4, EXCP_UDEF
,
4963 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
4967 if (!s
->vfp_enabled
)
4969 VFP_DREG_D(rd
, insn
);
4970 rn
= (insn
>> 16) & 0xf;
4972 load
= (insn
& (1 << 21)) != 0;
4973 if ((insn
& (1 << 23)) == 0) {
4974 /* Load store all elements. */
4975 op
= (insn
>> 8) & 0xf;
4976 size
= (insn
>> 6) & 3;
4979 /* Catch UNDEF cases for bad values of align field */
4982 if (((insn
>> 5) & 1) == 1) {
4987 if (((insn
>> 4) & 3) == 3) {
4994 nregs
= neon_ls_element_type
[op
].nregs
;
4995 interleave
= neon_ls_element_type
[op
].interleave
;
4996 spacing
= neon_ls_element_type
[op
].spacing
;
4997 if (size
== 3 && (interleave
| spacing
) != 1)
4999 addr
= tcg_temp_new_i32();
5000 load_reg_var(s
, addr
, rn
);
5001 stride
= (1 << size
) * interleave
;
5002 for (reg
= 0; reg
< nregs
; reg
++) {
5003 if (interleave
> 2 || (interleave
== 2 && nregs
== 2)) {
5004 load_reg_var(s
, addr
, rn
);
5005 tcg_gen_addi_i32(addr
, addr
, (1 << size
) * reg
);
5006 } else if (interleave
== 2 && nregs
== 4 && reg
== 2) {
5007 load_reg_var(s
, addr
, rn
);
5008 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
5011 tmp64
= tcg_temp_new_i64();
5013 gen_aa32_ld64(s
, tmp64
, addr
, get_mem_index(s
));
5014 neon_store_reg64(tmp64
, rd
);
5016 neon_load_reg64(tmp64
, rd
);
5017 gen_aa32_st64(s
, tmp64
, addr
, get_mem_index(s
));
5019 tcg_temp_free_i64(tmp64
);
5020 tcg_gen_addi_i32(addr
, addr
, stride
);
5022 for (pass
= 0; pass
< 2; pass
++) {
5025 tmp
= tcg_temp_new_i32();
5026 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
5027 neon_store_reg(rd
, pass
, tmp
);
5029 tmp
= neon_load_reg(rd
, pass
);
5030 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
5031 tcg_temp_free_i32(tmp
);
5033 tcg_gen_addi_i32(addr
, addr
, stride
);
5034 } else if (size
== 1) {
5036 tmp
= tcg_temp_new_i32();
5037 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
5038 tcg_gen_addi_i32(addr
, addr
, stride
);
5039 tmp2
= tcg_temp_new_i32();
5040 gen_aa32_ld16u(s
, tmp2
, addr
, get_mem_index(s
));
5041 tcg_gen_addi_i32(addr
, addr
, stride
);
5042 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5043 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
5044 tcg_temp_free_i32(tmp2
);
5045 neon_store_reg(rd
, pass
, tmp
);
5047 tmp
= neon_load_reg(rd
, pass
);
5048 tmp2
= tcg_temp_new_i32();
5049 tcg_gen_shri_i32(tmp2
, tmp
, 16);
5050 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
5051 tcg_temp_free_i32(tmp
);
5052 tcg_gen_addi_i32(addr
, addr
, stride
);
5053 gen_aa32_st16(s
, tmp2
, addr
, get_mem_index(s
));
5054 tcg_temp_free_i32(tmp2
);
5055 tcg_gen_addi_i32(addr
, addr
, stride
);
5057 } else /* size == 0 */ {
5060 for (n
= 0; n
< 4; n
++) {
5061 tmp
= tcg_temp_new_i32();
5062 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
5063 tcg_gen_addi_i32(addr
, addr
, stride
);
5067 tcg_gen_shli_i32(tmp
, tmp
, n
* 8);
5068 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5069 tcg_temp_free_i32(tmp
);
5072 neon_store_reg(rd
, pass
, tmp2
);
5074 tmp2
= neon_load_reg(rd
, pass
);
5075 for (n
= 0; n
< 4; n
++) {
5076 tmp
= tcg_temp_new_i32();
5078 tcg_gen_mov_i32(tmp
, tmp2
);
5080 tcg_gen_shri_i32(tmp
, tmp2
, n
* 8);
5082 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
5083 tcg_temp_free_i32(tmp
);
5084 tcg_gen_addi_i32(addr
, addr
, stride
);
5086 tcg_temp_free_i32(tmp2
);
5093 tcg_temp_free_i32(addr
);
5096 size
= (insn
>> 10) & 3;
5098 /* Load single element to all lanes. */
5099 int a
= (insn
>> 4) & 1;
5103 size
= (insn
>> 6) & 3;
5104 nregs
= ((insn
>> 8) & 3) + 1;
5107 if (nregs
!= 4 || a
== 0) {
5110 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
5113 if (nregs
== 1 && a
== 1 && size
== 0) {
5116 if (nregs
== 3 && a
== 1) {
5119 addr
= tcg_temp_new_i32();
5120 load_reg_var(s
, addr
, rn
);
5122 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
5123 tmp
= gen_load_and_replicate(s
, addr
, size
);
5124 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
5125 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
5126 if (insn
& (1 << 5)) {
5127 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 0));
5128 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 1));
5130 tcg_temp_free_i32(tmp
);
5132 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
5133 stride
= (insn
& (1 << 5)) ? 2 : 1;
5134 for (reg
= 0; reg
< nregs
; reg
++) {
5135 tmp
= gen_load_and_replicate(s
, addr
, size
);
5136 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
5137 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
5138 tcg_temp_free_i32(tmp
);
5139 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
5143 tcg_temp_free_i32(addr
);
5144 stride
= (1 << size
) * nregs
;
5146 /* Single element. */
5147 int idx
= (insn
>> 4) & 0xf;
5148 pass
= (insn
>> 7) & 1;
5151 shift
= ((insn
>> 5) & 3) * 8;
5155 shift
= ((insn
>> 6) & 1) * 16;
5156 stride
= (insn
& (1 << 5)) ? 2 : 1;
5160 stride
= (insn
& (1 << 6)) ? 2 : 1;
5165 nregs
= ((insn
>> 8) & 3) + 1;
5166 /* Catch the UNDEF cases. This is unavoidably a bit messy. */
5169 if (((idx
& (1 << size
)) != 0) ||
5170 (size
== 2 && ((idx
& 3) == 1 || (idx
& 3) == 2))) {
5175 if ((idx
& 1) != 0) {
5180 if (size
== 2 && (idx
& 2) != 0) {
5185 if ((size
== 2) && ((idx
& 3) == 3)) {
5192 if ((rd
+ stride
* (nregs
- 1)) > 31) {
5193 /* Attempts to write off the end of the register file
5194 * are UNPREDICTABLE; we choose to UNDEF because otherwise
5195 * the neon_load_reg() would write off the end of the array.
5199 addr
= tcg_temp_new_i32();
5200 load_reg_var(s
, addr
, rn
);
5201 for (reg
= 0; reg
< nregs
; reg
++) {
5203 tmp
= tcg_temp_new_i32();
5206 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
5209 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
5212 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
5214 default: /* Avoid compiler warnings. */
5218 tmp2
= neon_load_reg(rd
, pass
);
5219 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
,
5220 shift
, size
? 16 : 8);
5221 tcg_temp_free_i32(tmp2
);
5223 neon_store_reg(rd
, pass
, tmp
);
5224 } else { /* Store */
5225 tmp
= neon_load_reg(rd
, pass
);
5227 tcg_gen_shri_i32(tmp
, tmp
, shift
);
5230 gen_aa32_st8(s
, tmp
, addr
, get_mem_index(s
));
5233 gen_aa32_st16(s
, tmp
, addr
, get_mem_index(s
));
5236 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
5239 tcg_temp_free_i32(tmp
);
5242 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
5244 tcg_temp_free_i32(addr
);
5245 stride
= nregs
* (1 << size
);
5251 base
= load_reg(s
, rn
);
5253 tcg_gen_addi_i32(base
, base
, stride
);
5256 index
= load_reg(s
, rm
);
5257 tcg_gen_add_i32(base
, base
, index
);
5258 tcg_temp_free_i32(index
);
5260 store_reg(s
, rn
, base
);
5265 static inline void gen_neon_narrow(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5268 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
5269 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
5270 case 2: tcg_gen_extrl_i64_i32(dest
, src
); break;
5275 static inline void gen_neon_narrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5278 case 0: gen_helper_neon_narrow_sat_s8(dest
, cpu_env
, src
); break;
5279 case 1: gen_helper_neon_narrow_sat_s16(dest
, cpu_env
, src
); break;
5280 case 2: gen_helper_neon_narrow_sat_s32(dest
, cpu_env
, src
); break;
5285 static inline void gen_neon_narrow_satu(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5288 case 0: gen_helper_neon_narrow_sat_u8(dest
, cpu_env
, src
); break;
5289 case 1: gen_helper_neon_narrow_sat_u16(dest
, cpu_env
, src
); break;
5290 case 2: gen_helper_neon_narrow_sat_u32(dest
, cpu_env
, src
); break;
5295 static inline void gen_neon_unarrow_sats(int size
, TCGv_i32 dest
, TCGv_i64 src
)
5298 case 0: gen_helper_neon_unarrow_sat8(dest
, cpu_env
, src
); break;
5299 case 1: gen_helper_neon_unarrow_sat16(dest
, cpu_env
, src
); break;
5300 case 2: gen_helper_neon_unarrow_sat32(dest
, cpu_env
, src
); break;
5305 static inline void gen_neon_shift_narrow(int size
, TCGv_i32 var
, TCGv_i32 shift
,
5311 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
5312 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
5317 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
5318 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
5325 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
5326 case 2: gen_helper_neon_shl_u32(var
, var
, shift
); break;
5331 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
5332 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
5339 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv_i32 src
, int size
, int u
)
5343 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
5344 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
5345 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
5350 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
5351 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
5352 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
5356 tcg_temp_free_i32(src
);
5359 static inline void gen_neon_addl(int size
)
5362 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
5363 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
5364 case 2: tcg_gen_add_i64(CPU_V001
); break;
5369 static inline void gen_neon_subl(int size
)
5372 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
5373 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
5374 case 2: tcg_gen_sub_i64(CPU_V001
); break;
5379 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
5382 case 0: gen_helper_neon_negl_u16(var
, var
); break;
5383 case 1: gen_helper_neon_negl_u32(var
, var
); break;
5385 tcg_gen_neg_i64(var
, var
);
5391 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
5394 case 1: gen_helper_neon_addl_saturate_s32(op0
, cpu_env
, op0
, op1
); break;
5395 case 2: gen_helper_neon_addl_saturate_s64(op0
, cpu_env
, op0
, op1
); break;
5400 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv_i32 a
, TCGv_i32 b
,
5405 switch ((size
<< 1) | u
) {
5406 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
5407 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
5408 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
5409 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
5411 tmp
= gen_muls_i64_i32(a
, b
);
5412 tcg_gen_mov_i64(dest
, tmp
);
5413 tcg_temp_free_i64(tmp
);
5416 tmp
= gen_mulu_i64_i32(a
, b
);
5417 tcg_gen_mov_i64(dest
, tmp
);
5418 tcg_temp_free_i64(tmp
);
5423 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
5424 Don't forget to clean them now. */
5426 tcg_temp_free_i32(a
);
5427 tcg_temp_free_i32(b
);
5431 static void gen_neon_narrow_op(int op
, int u
, int size
,
5432 TCGv_i32 dest
, TCGv_i64 src
)
5436 gen_neon_unarrow_sats(size
, dest
, src
);
5438 gen_neon_narrow(size
, dest
, src
);
5442 gen_neon_narrow_satu(size
, dest
, src
);
5444 gen_neon_narrow_sats(size
, dest
, src
);
5449 /* Symbolic constants for op fields for Neon 3-register same-length.
5450 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
5453 #define NEON_3R_VHADD 0
5454 #define NEON_3R_VQADD 1
5455 #define NEON_3R_VRHADD 2
5456 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
5457 #define NEON_3R_VHSUB 4
5458 #define NEON_3R_VQSUB 5
5459 #define NEON_3R_VCGT 6
5460 #define NEON_3R_VCGE 7
5461 #define NEON_3R_VSHL 8
5462 #define NEON_3R_VQSHL 9
5463 #define NEON_3R_VRSHL 10
5464 #define NEON_3R_VQRSHL 11
5465 #define NEON_3R_VMAX 12
5466 #define NEON_3R_VMIN 13
5467 #define NEON_3R_VABD 14
5468 #define NEON_3R_VABA 15
5469 #define NEON_3R_VADD_VSUB 16
5470 #define NEON_3R_VTST_VCEQ 17
5471 #define NEON_3R_VML 18 /* VMLA, VMLS */
5472 #define NEON_3R_VMUL 19
5473 #define NEON_3R_VPMAX 20
5474 #define NEON_3R_VPMIN 21
5475 #define NEON_3R_VQDMULH_VQRDMULH 22
5476 #define NEON_3R_VPADD_VQRDMLAH 23
5477 #define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
5478 #define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */
5479 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
5480 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
5481 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
5482 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
5483 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
5484 #define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
5486 static const uint8_t neon_3r_sizes
[] = {
5487 [NEON_3R_VHADD
] = 0x7,
5488 [NEON_3R_VQADD
] = 0xf,
5489 [NEON_3R_VRHADD
] = 0x7,
5490 [NEON_3R_LOGIC
] = 0xf, /* size field encodes op type */
5491 [NEON_3R_VHSUB
] = 0x7,
5492 [NEON_3R_VQSUB
] = 0xf,
5493 [NEON_3R_VCGT
] = 0x7,
5494 [NEON_3R_VCGE
] = 0x7,
5495 [NEON_3R_VSHL
] = 0xf,
5496 [NEON_3R_VQSHL
] = 0xf,
5497 [NEON_3R_VRSHL
] = 0xf,
5498 [NEON_3R_VQRSHL
] = 0xf,
5499 [NEON_3R_VMAX
] = 0x7,
5500 [NEON_3R_VMIN
] = 0x7,
5501 [NEON_3R_VABD
] = 0x7,
5502 [NEON_3R_VABA
] = 0x7,
5503 [NEON_3R_VADD_VSUB
] = 0xf,
5504 [NEON_3R_VTST_VCEQ
] = 0x7,
5505 [NEON_3R_VML
] = 0x7,
5506 [NEON_3R_VMUL
] = 0x7,
5507 [NEON_3R_VPMAX
] = 0x7,
5508 [NEON_3R_VPMIN
] = 0x7,
5509 [NEON_3R_VQDMULH_VQRDMULH
] = 0x6,
5510 [NEON_3R_VPADD_VQRDMLAH
] = 0x7,
5511 [NEON_3R_SHA
] = 0xf, /* size field encodes op type */
5512 [NEON_3R_VFM_VQRDMLSH
] = 0x7, /* For VFM, size bit 1 encodes op */
5513 [NEON_3R_FLOAT_ARITH
] = 0x5, /* size bit 1 encodes op */
5514 [NEON_3R_FLOAT_MULTIPLY
] = 0x5, /* size bit 1 encodes op */
5515 [NEON_3R_FLOAT_CMP
] = 0x5, /* size bit 1 encodes op */
5516 [NEON_3R_FLOAT_ACMP
] = 0x5, /* size bit 1 encodes op */
5517 [NEON_3R_FLOAT_MINMAX
] = 0x5, /* size bit 1 encodes op */
5518 [NEON_3R_FLOAT_MISC
] = 0x5, /* size bit 1 encodes op */
5521 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
5522 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
5525 #define NEON_2RM_VREV64 0
5526 #define NEON_2RM_VREV32 1
5527 #define NEON_2RM_VREV16 2
5528 #define NEON_2RM_VPADDL 4
5529 #define NEON_2RM_VPADDL_U 5
5530 #define NEON_2RM_AESE 6 /* Includes AESD */
5531 #define NEON_2RM_AESMC 7 /* Includes AESIMC */
5532 #define NEON_2RM_VCLS 8
5533 #define NEON_2RM_VCLZ 9
5534 #define NEON_2RM_VCNT 10
5535 #define NEON_2RM_VMVN 11
5536 #define NEON_2RM_VPADAL 12
5537 #define NEON_2RM_VPADAL_U 13
5538 #define NEON_2RM_VQABS 14
5539 #define NEON_2RM_VQNEG 15
5540 #define NEON_2RM_VCGT0 16
5541 #define NEON_2RM_VCGE0 17
5542 #define NEON_2RM_VCEQ0 18
5543 #define NEON_2RM_VCLE0 19
5544 #define NEON_2RM_VCLT0 20
5545 #define NEON_2RM_SHA1H 21
5546 #define NEON_2RM_VABS 22
5547 #define NEON_2RM_VNEG 23
5548 #define NEON_2RM_VCGT0_F 24
5549 #define NEON_2RM_VCGE0_F 25
5550 #define NEON_2RM_VCEQ0_F 26
5551 #define NEON_2RM_VCLE0_F 27
5552 #define NEON_2RM_VCLT0_F 28
5553 #define NEON_2RM_VABS_F 30
5554 #define NEON_2RM_VNEG_F 31
5555 #define NEON_2RM_VSWP 32
5556 #define NEON_2RM_VTRN 33
5557 #define NEON_2RM_VUZP 34
5558 #define NEON_2RM_VZIP 35
5559 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
5560 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
5561 #define NEON_2RM_VSHLL 38
5562 #define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
5563 #define NEON_2RM_VRINTN 40
5564 #define NEON_2RM_VRINTX 41
5565 #define NEON_2RM_VRINTA 42
5566 #define NEON_2RM_VRINTZ 43
5567 #define NEON_2RM_VCVT_F16_F32 44
5568 #define NEON_2RM_VRINTM 45
5569 #define NEON_2RM_VCVT_F32_F16 46
5570 #define NEON_2RM_VRINTP 47
5571 #define NEON_2RM_VCVTAU 48
5572 #define NEON_2RM_VCVTAS 49
5573 #define NEON_2RM_VCVTNU 50
5574 #define NEON_2RM_VCVTNS 51
5575 #define NEON_2RM_VCVTPU 52
5576 #define NEON_2RM_VCVTPS 53
5577 #define NEON_2RM_VCVTMU 54
5578 #define NEON_2RM_VCVTMS 55
5579 #define NEON_2RM_VRECPE 56
5580 #define NEON_2RM_VRSQRTE 57
5581 #define NEON_2RM_VRECPE_F 58
5582 #define NEON_2RM_VRSQRTE_F 59
5583 #define NEON_2RM_VCVT_FS 60
5584 #define NEON_2RM_VCVT_FU 61
5585 #define NEON_2RM_VCVT_SF 62
5586 #define NEON_2RM_VCVT_UF 63
5588 static int neon_2rm_is_float_op(int op
)
5590 /* Return true if this neon 2reg-misc op is float-to-float */
5591 return (op
== NEON_2RM_VABS_F
|| op
== NEON_2RM_VNEG_F
||
5592 (op
>= NEON_2RM_VRINTN
&& op
<= NEON_2RM_VRINTZ
) ||
5593 op
== NEON_2RM_VRINTM
||
5594 (op
>= NEON_2RM_VRINTP
&& op
<= NEON_2RM_VCVTMS
) ||
5595 op
>= NEON_2RM_VRECPE_F
);
5598 static bool neon_2rm_is_v8_op(int op
)
5600 /* Return true if this neon 2reg-misc op is ARMv8 and up */
5602 case NEON_2RM_VRINTN
:
5603 case NEON_2RM_VRINTA
:
5604 case NEON_2RM_VRINTM
:
5605 case NEON_2RM_VRINTP
:
5606 case NEON_2RM_VRINTZ
:
5607 case NEON_2RM_VRINTX
:
5608 case NEON_2RM_VCVTAU
:
5609 case NEON_2RM_VCVTAS
:
5610 case NEON_2RM_VCVTNU
:
5611 case NEON_2RM_VCVTNS
:
5612 case NEON_2RM_VCVTPU
:
5613 case NEON_2RM_VCVTPS
:
5614 case NEON_2RM_VCVTMU
:
5615 case NEON_2RM_VCVTMS
:
5622 /* Each entry in this array has bit n set if the insn allows
5623 * size value n (otherwise it will UNDEF). Since unallocated
5624 * op values will have no bits set they always UNDEF.
5626 static const uint8_t neon_2rm_sizes
[] = {
5627 [NEON_2RM_VREV64
] = 0x7,
5628 [NEON_2RM_VREV32
] = 0x3,
5629 [NEON_2RM_VREV16
] = 0x1,
5630 [NEON_2RM_VPADDL
] = 0x7,
5631 [NEON_2RM_VPADDL_U
] = 0x7,
5632 [NEON_2RM_AESE
] = 0x1,
5633 [NEON_2RM_AESMC
] = 0x1,
5634 [NEON_2RM_VCLS
] = 0x7,
5635 [NEON_2RM_VCLZ
] = 0x7,
5636 [NEON_2RM_VCNT
] = 0x1,
5637 [NEON_2RM_VMVN
] = 0x1,
5638 [NEON_2RM_VPADAL
] = 0x7,
5639 [NEON_2RM_VPADAL_U
] = 0x7,
5640 [NEON_2RM_VQABS
] = 0x7,
5641 [NEON_2RM_VQNEG
] = 0x7,
5642 [NEON_2RM_VCGT0
] = 0x7,
5643 [NEON_2RM_VCGE0
] = 0x7,
5644 [NEON_2RM_VCEQ0
] = 0x7,
5645 [NEON_2RM_VCLE0
] = 0x7,
5646 [NEON_2RM_VCLT0
] = 0x7,
5647 [NEON_2RM_SHA1H
] = 0x4,
5648 [NEON_2RM_VABS
] = 0x7,
5649 [NEON_2RM_VNEG
] = 0x7,
5650 [NEON_2RM_VCGT0_F
] = 0x4,
5651 [NEON_2RM_VCGE0_F
] = 0x4,
5652 [NEON_2RM_VCEQ0_F
] = 0x4,
5653 [NEON_2RM_VCLE0_F
] = 0x4,
5654 [NEON_2RM_VCLT0_F
] = 0x4,
5655 [NEON_2RM_VABS_F
] = 0x4,
5656 [NEON_2RM_VNEG_F
] = 0x4,
5657 [NEON_2RM_VSWP
] = 0x1,
5658 [NEON_2RM_VTRN
] = 0x7,
5659 [NEON_2RM_VUZP
] = 0x7,
5660 [NEON_2RM_VZIP
] = 0x7,
5661 [NEON_2RM_VMOVN
] = 0x7,
5662 [NEON_2RM_VQMOVN
] = 0x7,
5663 [NEON_2RM_VSHLL
] = 0x7,
5664 [NEON_2RM_SHA1SU1
] = 0x4,
5665 [NEON_2RM_VRINTN
] = 0x4,
5666 [NEON_2RM_VRINTX
] = 0x4,
5667 [NEON_2RM_VRINTA
] = 0x4,
5668 [NEON_2RM_VRINTZ
] = 0x4,
5669 [NEON_2RM_VCVT_F16_F32
] = 0x2,
5670 [NEON_2RM_VRINTM
] = 0x4,
5671 [NEON_2RM_VCVT_F32_F16
] = 0x2,
5672 [NEON_2RM_VRINTP
] = 0x4,
5673 [NEON_2RM_VCVTAU
] = 0x4,
5674 [NEON_2RM_VCVTAS
] = 0x4,
5675 [NEON_2RM_VCVTNU
] = 0x4,
5676 [NEON_2RM_VCVTNS
] = 0x4,
5677 [NEON_2RM_VCVTPU
] = 0x4,
5678 [NEON_2RM_VCVTPS
] = 0x4,
5679 [NEON_2RM_VCVTMU
] = 0x4,
5680 [NEON_2RM_VCVTMS
] = 0x4,
5681 [NEON_2RM_VRECPE
] = 0x4,
5682 [NEON_2RM_VRSQRTE
] = 0x4,
5683 [NEON_2RM_VRECPE_F
] = 0x4,
5684 [NEON_2RM_VRSQRTE_F
] = 0x4,
5685 [NEON_2RM_VCVT_FS
] = 0x4,
5686 [NEON_2RM_VCVT_FU
] = 0x4,
5687 [NEON_2RM_VCVT_SF
] = 0x4,
5688 [NEON_2RM_VCVT_UF
] = 0x4,
5692 /* Expand v8.1 simd helper. */
5693 static int do_v81_helper(DisasContext
*s
, gen_helper_gvec_3_ptr
*fn
,
5694 int q
, int rd
, int rn
, int rm
)
5696 if (dc_isar_feature(aa32_rdm
, s
)) {
5697 int opr_sz
= (1 + q
) * 8;
5698 tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd
),
5699 vfp_reg_offset(1, rn
),
5700 vfp_reg_offset(1, rm
), cpu_env
,
5701 opr_sz
, opr_sz
, 0, fn
);
5708 * Expanders for VBitOps_VBIF, VBIT, VBSL.
5710 static void gen_bsl_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
5712 tcg_gen_xor_i64(rn
, rn
, rm
);
5713 tcg_gen_and_i64(rn
, rn
, rd
);
5714 tcg_gen_xor_i64(rd
, rm
, rn
);
5717 static void gen_bit_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
5719 tcg_gen_xor_i64(rn
, rn
, rd
);
5720 tcg_gen_and_i64(rn
, rn
, rm
);
5721 tcg_gen_xor_i64(rd
, rd
, rn
);
5724 static void gen_bif_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
5726 tcg_gen_xor_i64(rn
, rn
, rd
);
5727 tcg_gen_andc_i64(rn
, rn
, rm
);
5728 tcg_gen_xor_i64(rd
, rd
, rn
);
5731 static void gen_bsl_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
5733 tcg_gen_xor_vec(vece
, rn
, rn
, rm
);
5734 tcg_gen_and_vec(vece
, rn
, rn
, rd
);
5735 tcg_gen_xor_vec(vece
, rd
, rm
, rn
);
5738 static void gen_bit_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
5740 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
5741 tcg_gen_and_vec(vece
, rn
, rn
, rm
);
5742 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
5745 static void gen_bif_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
5747 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
5748 tcg_gen_andc_vec(vece
, rn
, rn
, rm
);
5749 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
5752 const GVecGen3 bsl_op
= {
5753 .fni8
= gen_bsl_i64
,
5754 .fniv
= gen_bsl_vec
,
5755 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5759 const GVecGen3 bit_op
= {
5760 .fni8
= gen_bit_i64
,
5761 .fniv
= gen_bit_vec
,
5762 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5766 const GVecGen3 bif_op
= {
5767 .fni8
= gen_bif_i64
,
5768 .fniv
= gen_bif_vec
,
5769 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5773 static void gen_ssra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5775 tcg_gen_vec_sar8i_i64(a
, a
, shift
);
5776 tcg_gen_vec_add8_i64(d
, d
, a
);
5779 static void gen_ssra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5781 tcg_gen_vec_sar16i_i64(a
, a
, shift
);
5782 tcg_gen_vec_add16_i64(d
, d
, a
);
5785 static void gen_ssra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
5787 tcg_gen_sari_i32(a
, a
, shift
);
5788 tcg_gen_add_i32(d
, d
, a
);
5791 static void gen_ssra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5793 tcg_gen_sari_i64(a
, a
, shift
);
5794 tcg_gen_add_i64(d
, d
, a
);
5797 static void gen_ssra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
5799 tcg_gen_sari_vec(vece
, a
, a
, sh
);
5800 tcg_gen_add_vec(vece
, d
, d
, a
);
5803 const GVecGen2i ssra_op
[4] = {
5804 { .fni8
= gen_ssra8_i64
,
5805 .fniv
= gen_ssra_vec
,
5807 .opc
= INDEX_op_sari_vec
,
5809 { .fni8
= gen_ssra16_i64
,
5810 .fniv
= gen_ssra_vec
,
5812 .opc
= INDEX_op_sari_vec
,
5814 { .fni4
= gen_ssra32_i32
,
5815 .fniv
= gen_ssra_vec
,
5817 .opc
= INDEX_op_sari_vec
,
5819 { .fni8
= gen_ssra64_i64
,
5820 .fniv
= gen_ssra_vec
,
5821 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5823 .opc
= INDEX_op_sari_vec
,
5827 static void gen_usra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5829 tcg_gen_vec_shr8i_i64(a
, a
, shift
);
5830 tcg_gen_vec_add8_i64(d
, d
, a
);
5833 static void gen_usra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5835 tcg_gen_vec_shr16i_i64(a
, a
, shift
);
5836 tcg_gen_vec_add16_i64(d
, d
, a
);
5839 static void gen_usra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
5841 tcg_gen_shri_i32(a
, a
, shift
);
5842 tcg_gen_add_i32(d
, d
, a
);
5845 static void gen_usra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5847 tcg_gen_shri_i64(a
, a
, shift
);
5848 tcg_gen_add_i64(d
, d
, a
);
5851 static void gen_usra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
5853 tcg_gen_shri_vec(vece
, a
, a
, sh
);
5854 tcg_gen_add_vec(vece
, d
, d
, a
);
5857 const GVecGen2i usra_op
[4] = {
5858 { .fni8
= gen_usra8_i64
,
5859 .fniv
= gen_usra_vec
,
5861 .opc
= INDEX_op_shri_vec
,
5863 { .fni8
= gen_usra16_i64
,
5864 .fniv
= gen_usra_vec
,
5866 .opc
= INDEX_op_shri_vec
,
5868 { .fni4
= gen_usra32_i32
,
5869 .fniv
= gen_usra_vec
,
5871 .opc
= INDEX_op_shri_vec
,
5873 { .fni8
= gen_usra64_i64
,
5874 .fniv
= gen_usra_vec
,
5875 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5877 .opc
= INDEX_op_shri_vec
,
5881 static void gen_shr8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5883 uint64_t mask
= dup_const(MO_8
, 0xff >> shift
);
5884 TCGv_i64 t
= tcg_temp_new_i64();
5886 tcg_gen_shri_i64(t
, a
, shift
);
5887 tcg_gen_andi_i64(t
, t
, mask
);
5888 tcg_gen_andi_i64(d
, d
, ~mask
);
5889 tcg_gen_or_i64(d
, d
, t
);
5890 tcg_temp_free_i64(t
);
5893 static void gen_shr16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5895 uint64_t mask
= dup_const(MO_16
, 0xffff >> shift
);
5896 TCGv_i64 t
= tcg_temp_new_i64();
5898 tcg_gen_shri_i64(t
, a
, shift
);
5899 tcg_gen_andi_i64(t
, t
, mask
);
5900 tcg_gen_andi_i64(d
, d
, ~mask
);
5901 tcg_gen_or_i64(d
, d
, t
);
5902 tcg_temp_free_i64(t
);
5905 static void gen_shr32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
5907 tcg_gen_shri_i32(a
, a
, shift
);
5908 tcg_gen_deposit_i32(d
, d
, a
, 0, 32 - shift
);
5911 static void gen_shr64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5913 tcg_gen_shri_i64(a
, a
, shift
);
5914 tcg_gen_deposit_i64(d
, d
, a
, 0, 64 - shift
);
5917 static void gen_shr_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
5920 tcg_gen_mov_vec(d
, a
);
5922 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
5923 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
5925 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK((8 << vece
) - sh
, sh
));
5926 tcg_gen_shri_vec(vece
, t
, a
, sh
);
5927 tcg_gen_and_vec(vece
, d
, d
, m
);
5928 tcg_gen_or_vec(vece
, d
, d
, t
);
5930 tcg_temp_free_vec(t
);
5931 tcg_temp_free_vec(m
);
5935 const GVecGen2i sri_op
[4] = {
5936 { .fni8
= gen_shr8_ins_i64
,
5937 .fniv
= gen_shr_ins_vec
,
5939 .opc
= INDEX_op_shri_vec
,
5941 { .fni8
= gen_shr16_ins_i64
,
5942 .fniv
= gen_shr_ins_vec
,
5944 .opc
= INDEX_op_shri_vec
,
5946 { .fni4
= gen_shr32_ins_i32
,
5947 .fniv
= gen_shr_ins_vec
,
5949 .opc
= INDEX_op_shri_vec
,
5951 { .fni8
= gen_shr64_ins_i64
,
5952 .fniv
= gen_shr_ins_vec
,
5953 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
5955 .opc
= INDEX_op_shri_vec
,
5959 static void gen_shl8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5961 uint64_t mask
= dup_const(MO_8
, 0xff << shift
);
5962 TCGv_i64 t
= tcg_temp_new_i64();
5964 tcg_gen_shli_i64(t
, a
, shift
);
5965 tcg_gen_andi_i64(t
, t
, mask
);
5966 tcg_gen_andi_i64(d
, d
, ~mask
);
5967 tcg_gen_or_i64(d
, d
, t
);
5968 tcg_temp_free_i64(t
);
5971 static void gen_shl16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5973 uint64_t mask
= dup_const(MO_16
, 0xffff << shift
);
5974 TCGv_i64 t
= tcg_temp_new_i64();
5976 tcg_gen_shli_i64(t
, a
, shift
);
5977 tcg_gen_andi_i64(t
, t
, mask
);
5978 tcg_gen_andi_i64(d
, d
, ~mask
);
5979 tcg_gen_or_i64(d
, d
, t
);
5980 tcg_temp_free_i64(t
);
5983 static void gen_shl32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
5985 tcg_gen_deposit_i32(d
, d
, a
, shift
, 32 - shift
);
5988 static void gen_shl64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
5990 tcg_gen_deposit_i64(d
, d
, a
, shift
, 64 - shift
);
5993 static void gen_shl_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
5996 tcg_gen_mov_vec(d
, a
);
5998 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
5999 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
6001 tcg_gen_dupi_vec(vece
, m
, MAKE_64BIT_MASK(0, sh
));
6002 tcg_gen_shli_vec(vece
, t
, a
, sh
);
6003 tcg_gen_and_vec(vece
, d
, d
, m
);
6004 tcg_gen_or_vec(vece
, d
, d
, t
);
6006 tcg_temp_free_vec(t
);
6007 tcg_temp_free_vec(m
);
6011 const GVecGen2i sli_op
[4] = {
6012 { .fni8
= gen_shl8_ins_i64
,
6013 .fniv
= gen_shl_ins_vec
,
6015 .opc
= INDEX_op_shli_vec
,
6017 { .fni8
= gen_shl16_ins_i64
,
6018 .fniv
= gen_shl_ins_vec
,
6020 .opc
= INDEX_op_shli_vec
,
6022 { .fni4
= gen_shl32_ins_i32
,
6023 .fniv
= gen_shl_ins_vec
,
6025 .opc
= INDEX_op_shli_vec
,
6027 { .fni8
= gen_shl64_ins_i64
,
6028 .fniv
= gen_shl_ins_vec
,
6029 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
6031 .opc
= INDEX_op_shli_vec
,
6035 static void gen_mla8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
6037 gen_helper_neon_mul_u8(a
, a
, b
);
6038 gen_helper_neon_add_u8(d
, d
, a
);
6041 static void gen_mls8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
6043 gen_helper_neon_mul_u8(a
, a
, b
);
6044 gen_helper_neon_sub_u8(d
, d
, a
);
6047 static void gen_mla16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
6049 gen_helper_neon_mul_u16(a
, a
, b
);
6050 gen_helper_neon_add_u16(d
, d
, a
);
6053 static void gen_mls16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
6055 gen_helper_neon_mul_u16(a
, a
, b
);
6056 gen_helper_neon_sub_u16(d
, d
, a
);
6059 static void gen_mla32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
6061 tcg_gen_mul_i32(a
, a
, b
);
6062 tcg_gen_add_i32(d
, d
, a
);
6065 static void gen_mls32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
6067 tcg_gen_mul_i32(a
, a
, b
);
6068 tcg_gen_sub_i32(d
, d
, a
);
6071 static void gen_mla64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
6073 tcg_gen_mul_i64(a
, a
, b
);
6074 tcg_gen_add_i64(d
, d
, a
);
6077 static void gen_mls64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
6079 tcg_gen_mul_i64(a
, a
, b
);
6080 tcg_gen_sub_i64(d
, d
, a
);
6083 static void gen_mla_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
6085 tcg_gen_mul_vec(vece
, a
, a
, b
);
6086 tcg_gen_add_vec(vece
, d
, d
, a
);
6089 static void gen_mls_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
6091 tcg_gen_mul_vec(vece
, a
, a
, b
);
6092 tcg_gen_sub_vec(vece
, d
, d
, a
);
6095 /* Note that while NEON does not support VMLA and VMLS as 64-bit ops,
6096 * these tables are shared with AArch64 which does support them.
6098 const GVecGen3 mla_op
[4] = {
6099 { .fni4
= gen_mla8_i32
,
6100 .fniv
= gen_mla_vec
,
6101 .opc
= INDEX_op_mul_vec
,
6104 { .fni4
= gen_mla16_i32
,
6105 .fniv
= gen_mla_vec
,
6106 .opc
= INDEX_op_mul_vec
,
6109 { .fni4
= gen_mla32_i32
,
6110 .fniv
= gen_mla_vec
,
6111 .opc
= INDEX_op_mul_vec
,
6114 { .fni8
= gen_mla64_i64
,
6115 .fniv
= gen_mla_vec
,
6116 .opc
= INDEX_op_mul_vec
,
6117 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
6122 const GVecGen3 mls_op
[4] = {
6123 { .fni4
= gen_mls8_i32
,
6124 .fniv
= gen_mls_vec
,
6125 .opc
= INDEX_op_mul_vec
,
6128 { .fni4
= gen_mls16_i32
,
6129 .fniv
= gen_mls_vec
,
6130 .opc
= INDEX_op_mul_vec
,
6133 { .fni4
= gen_mls32_i32
,
6134 .fniv
= gen_mls_vec
,
6135 .opc
= INDEX_op_mul_vec
,
6138 { .fni8
= gen_mls64_i64
,
6139 .fniv
= gen_mls_vec
,
6140 .opc
= INDEX_op_mul_vec
,
6141 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
6146 /* CMTST : test is "if (X & Y != 0)". */
6147 static void gen_cmtst_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
6149 tcg_gen_and_i32(d
, a
, b
);
6150 tcg_gen_setcondi_i32(TCG_COND_NE
, d
, d
, 0);
6151 tcg_gen_neg_i32(d
, d
);
6154 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
6156 tcg_gen_and_i64(d
, a
, b
);
6157 tcg_gen_setcondi_i64(TCG_COND_NE
, d
, d
, 0);
6158 tcg_gen_neg_i64(d
, d
);
6161 static void gen_cmtst_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
6163 tcg_gen_and_vec(vece
, d
, a
, b
);
6164 tcg_gen_dupi_vec(vece
, a
, 0);
6165 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, d
, d
, a
);
6168 const GVecGen3 cmtst_op
[4] = {
6169 { .fni4
= gen_helper_neon_tst_u8
,
6170 .fniv
= gen_cmtst_vec
,
6172 { .fni4
= gen_helper_neon_tst_u16
,
6173 .fniv
= gen_cmtst_vec
,
6175 { .fni4
= gen_cmtst_i32
,
6176 .fniv
= gen_cmtst_vec
,
6178 { .fni8
= gen_cmtst_i64
,
6179 .fniv
= gen_cmtst_vec
,
6180 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
6184 /* Translate a NEON data processing instruction. Return nonzero if the
6185 instruction is invalid.
6186 We process data in a mixture of 32-bit and 64-bit chunks.
6187 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
6189 static int disas_neon_data_insn(DisasContext
*s
, uint32_t insn
)
6193 int rd
, rn
, rm
, rd_ofs
, rn_ofs
, rm_ofs
;
6202 TCGv_i32 tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
6203 TCGv_ptr ptr1
, ptr2
, ptr3
;
6206 /* FIXME: this access check should not take precedence over UNDEF
6207 * for invalid encodings; we will generate incorrect syndrome information
6208 * for attempts to execute invalid vfp/neon encodings with FP disabled.
6210 if (s
->fp_excp_el
) {
6211 gen_exception_insn(s
, 4, EXCP_UDEF
,
6212 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
6216 if (!s
->vfp_enabled
)
6218 q
= (insn
& (1 << 6)) != 0;
6219 u
= (insn
>> 24) & 1;
6220 VFP_DREG_D(rd
, insn
);
6221 VFP_DREG_N(rn
, insn
);
6222 VFP_DREG_M(rm
, insn
);
6223 size
= (insn
>> 20) & 3;
6224 vec_size
= q
? 16 : 8;
6225 rd_ofs
= neon_reg_offset(rd
, 0);
6226 rn_ofs
= neon_reg_offset(rn
, 0);
6227 rm_ofs
= neon_reg_offset(rm
, 0);
6229 if ((insn
& (1 << 23)) == 0) {
6230 /* Three register same length. */
6231 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
6232 /* Catch invalid op and bad size combinations: UNDEF */
6233 if ((neon_3r_sizes
[op
] & (1 << size
)) == 0) {
6236 /* All insns of this form UNDEF for either this condition or the
6237 * superset of cases "Q==1"; we catch the latter later.
6239 if (q
&& ((rd
| rn
| rm
) & 1)) {
6244 /* The SHA-1/SHA-256 3-register instructions require special
6245 * treatment here, as their size field is overloaded as an
6246 * op type selector, and they all consume their input in a
6252 if (!u
) { /* SHA-1 */
6253 if (!dc_isar_feature(aa32_sha1
, s
)) {
6256 ptr1
= vfp_reg_ptr(true, rd
);
6257 ptr2
= vfp_reg_ptr(true, rn
);
6258 ptr3
= vfp_reg_ptr(true, rm
);
6259 tmp4
= tcg_const_i32(size
);
6260 gen_helper_crypto_sha1_3reg(ptr1
, ptr2
, ptr3
, tmp4
);
6261 tcg_temp_free_i32(tmp4
);
6262 } else { /* SHA-256 */
6263 if (!dc_isar_feature(aa32_sha2
, s
) || size
== 3) {
6266 ptr1
= vfp_reg_ptr(true, rd
);
6267 ptr2
= vfp_reg_ptr(true, rn
);
6268 ptr3
= vfp_reg_ptr(true, rm
);
6271 gen_helper_crypto_sha256h(ptr1
, ptr2
, ptr3
);
6274 gen_helper_crypto_sha256h2(ptr1
, ptr2
, ptr3
);
6277 gen_helper_crypto_sha256su1(ptr1
, ptr2
, ptr3
);
6281 tcg_temp_free_ptr(ptr1
);
6282 tcg_temp_free_ptr(ptr2
);
6283 tcg_temp_free_ptr(ptr3
);
6286 case NEON_3R_VPADD_VQRDMLAH
:
6293 return do_v81_helper(s
, gen_helper_gvec_qrdmlah_s16
,
6296 return do_v81_helper(s
, gen_helper_gvec_qrdmlah_s32
,
6301 case NEON_3R_VFM_VQRDMLSH
:
6312 return do_v81_helper(s
, gen_helper_gvec_qrdmlsh_s16
,
6315 return do_v81_helper(s
, gen_helper_gvec_qrdmlsh_s32
,
6320 case NEON_3R_LOGIC
: /* Logic ops. */
6321 switch ((u
<< 2) | size
) {
6323 tcg_gen_gvec_and(0, rd_ofs
, rn_ofs
, rm_ofs
,
6324 vec_size
, vec_size
);
6327 tcg_gen_gvec_andc(0, rd_ofs
, rn_ofs
, rm_ofs
,
6328 vec_size
, vec_size
);
6333 tcg_gen_gvec_mov(0, rd_ofs
, rn_ofs
, vec_size
, vec_size
);
6336 tcg_gen_gvec_or(0, rd_ofs
, rn_ofs
, rm_ofs
,
6337 vec_size
, vec_size
);
6341 tcg_gen_gvec_orc(0, rd_ofs
, rn_ofs
, rm_ofs
,
6342 vec_size
, vec_size
);
6345 tcg_gen_gvec_xor(0, rd_ofs
, rn_ofs
, rm_ofs
,
6346 vec_size
, vec_size
);
6349 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
,
6350 vec_size
, vec_size
, &bsl_op
);
6353 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
,
6354 vec_size
, vec_size
, &bit_op
);
6357 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
,
6358 vec_size
, vec_size
, &bif_op
);
6363 case NEON_3R_VADD_VSUB
:
6365 tcg_gen_gvec_sub(size
, rd_ofs
, rn_ofs
, rm_ofs
,
6366 vec_size
, vec_size
);
6368 tcg_gen_gvec_add(size
, rd_ofs
, rn_ofs
, rm_ofs
,
6369 vec_size
, vec_size
);
6373 case NEON_3R_VMUL
: /* VMUL */
6375 /* Polynomial case allows only P8 and is handled below. */
6380 tcg_gen_gvec_mul(size
, rd_ofs
, rn_ofs
, rm_ofs
,
6381 vec_size
, vec_size
);
6386 case NEON_3R_VML
: /* VMLA, VMLS */
6387 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, vec_size
, vec_size
,
6388 u
? &mls_op
[size
] : &mla_op
[size
]);
6391 case NEON_3R_VTST_VCEQ
:
6393 tcg_gen_gvec_cmp(TCG_COND_EQ
, size
, rd_ofs
, rn_ofs
, rm_ofs
,
6394 vec_size
, vec_size
);
6396 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
,
6397 vec_size
, vec_size
, &cmtst_op
[size
]);
6402 tcg_gen_gvec_cmp(u
? TCG_COND_GTU
: TCG_COND_GT
, size
,
6403 rd_ofs
, rn_ofs
, rm_ofs
, vec_size
, vec_size
);
6407 tcg_gen_gvec_cmp(u
? TCG_COND_GEU
: TCG_COND_GE
, size
,
6408 rd_ofs
, rn_ofs
, rm_ofs
, vec_size
, vec_size
);
6413 /* 64-bit element instructions. */
6414 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
6415 neon_load_reg64(cpu_V0
, rn
+ pass
);
6416 neon_load_reg64(cpu_V1
, rm
+ pass
);
6420 gen_helper_neon_qadd_u64(cpu_V0
, cpu_env
,
6423 gen_helper_neon_qadd_s64(cpu_V0
, cpu_env
,
6429 gen_helper_neon_qsub_u64(cpu_V0
, cpu_env
,
6432 gen_helper_neon_qsub_s64(cpu_V0
, cpu_env
,
6438 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
6440 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
6445 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
6448 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
6454 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
6456 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
6459 case NEON_3R_VQRSHL
:
6461 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_env
,
6464 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_env
,
6471 neon_store_reg64(cpu_V0
, rd
+ pass
);
6480 case NEON_3R_VQRSHL
:
6483 /* Shift instruction operands are reversed. */
6489 case NEON_3R_VPADD_VQRDMLAH
:
6494 case NEON_3R_FLOAT_ARITH
:
6495 pairwise
= (u
&& size
< 2); /* if VPADD (float) */
6497 case NEON_3R_FLOAT_MINMAX
:
6498 pairwise
= u
; /* if VPMIN/VPMAX (float) */
6500 case NEON_3R_FLOAT_CMP
:
6502 /* no encoding for U=0 C=1x */
6506 case NEON_3R_FLOAT_ACMP
:
6511 case NEON_3R_FLOAT_MISC
:
6512 /* VMAXNM/VMINNM in ARMv8 */
6513 if (u
&& !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
6517 case NEON_3R_VFM_VQRDMLSH
:
6518 if (!arm_dc_feature(s
, ARM_FEATURE_VFP4
)) {
6526 if (pairwise
&& q
) {
6527 /* All the pairwise insns UNDEF if Q is set */
6531 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6536 tmp
= neon_load_reg(rn
, 0);
6537 tmp2
= neon_load_reg(rn
, 1);
6539 tmp
= neon_load_reg(rm
, 0);
6540 tmp2
= neon_load_reg(rm
, 1);
6544 tmp
= neon_load_reg(rn
, pass
);
6545 tmp2
= neon_load_reg(rm
, pass
);
6549 GEN_NEON_INTEGER_OP(hadd
);
6552 GEN_NEON_INTEGER_OP_ENV(qadd
);
6554 case NEON_3R_VRHADD
:
6555 GEN_NEON_INTEGER_OP(rhadd
);
6558 GEN_NEON_INTEGER_OP(hsub
);
6561 GEN_NEON_INTEGER_OP_ENV(qsub
);
6564 GEN_NEON_INTEGER_OP(shl
);
6567 GEN_NEON_INTEGER_OP_ENV(qshl
);
6570 GEN_NEON_INTEGER_OP(rshl
);
6572 case NEON_3R_VQRSHL
:
6573 GEN_NEON_INTEGER_OP_ENV(qrshl
);
6576 GEN_NEON_INTEGER_OP(max
);
6579 GEN_NEON_INTEGER_OP(min
);
6582 GEN_NEON_INTEGER_OP(abd
);
6585 GEN_NEON_INTEGER_OP(abd
);
6586 tcg_temp_free_i32(tmp2
);
6587 tmp2
= neon_load_reg(rd
, pass
);
6588 gen_neon_add(size
, tmp
, tmp2
);
6591 /* VMUL.P8; other cases already eliminated. */
6592 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
6595 GEN_NEON_INTEGER_OP(pmax
);
6598 GEN_NEON_INTEGER_OP(pmin
);
6600 case NEON_3R_VQDMULH_VQRDMULH
: /* Multiply high. */
6601 if (!u
) { /* VQDMULH */
6604 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6607 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6611 } else { /* VQRDMULH */
6614 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
6617 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
6623 case NEON_3R_VPADD_VQRDMLAH
:
6625 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
6626 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
6627 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
6631 case NEON_3R_FLOAT_ARITH
: /* Floating point arithmetic. */
6633 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6634 switch ((u
<< 2) | size
) {
6637 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
6640 gen_helper_vfp_subs(tmp
, tmp
, tmp2
, fpstatus
);
6643 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
, fpstatus
);
6648 tcg_temp_free_ptr(fpstatus
);
6651 case NEON_3R_FLOAT_MULTIPLY
:
6653 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6654 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
6656 tcg_temp_free_i32(tmp2
);
6657 tmp2
= neon_load_reg(rd
, pass
);
6659 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
6661 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
6664 tcg_temp_free_ptr(fpstatus
);
6667 case NEON_3R_FLOAT_CMP
:
6669 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6671 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
6674 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
6676 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
6679 tcg_temp_free_ptr(fpstatus
);
6682 case NEON_3R_FLOAT_ACMP
:
6684 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6686 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
, fpstatus
);
6688 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
6690 tcg_temp_free_ptr(fpstatus
);
6693 case NEON_3R_FLOAT_MINMAX
:
6695 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6697 gen_helper_vfp_maxs(tmp
, tmp
, tmp2
, fpstatus
);
6699 gen_helper_vfp_mins(tmp
, tmp
, tmp2
, fpstatus
);
6701 tcg_temp_free_ptr(fpstatus
);
6704 case NEON_3R_FLOAT_MISC
:
6707 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6709 gen_helper_vfp_maxnums(tmp
, tmp
, tmp2
, fpstatus
);
6711 gen_helper_vfp_minnums(tmp
, tmp
, tmp2
, fpstatus
);
6713 tcg_temp_free_ptr(fpstatus
);
6716 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
6718 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
6722 case NEON_3R_VFM_VQRDMLSH
:
6724 /* VFMA, VFMS: fused multiply-add */
6725 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
6726 TCGv_i32 tmp3
= neon_load_reg(rd
, pass
);
6729 gen_helper_vfp_negs(tmp
, tmp
);
6731 gen_helper_vfp_muladds(tmp
, tmp
, tmp2
, tmp3
, fpstatus
);
6732 tcg_temp_free_i32(tmp3
);
6733 tcg_temp_free_ptr(fpstatus
);
6739 tcg_temp_free_i32(tmp2
);
6741 /* Save the result. For elementwise operations we can put it
6742 straight into the destination register. For pairwise operations
6743 we have to be careful to avoid clobbering the source operands. */
6744 if (pairwise
&& rd
== rm
) {
6745 neon_store_scratch(pass
, tmp
);
6747 neon_store_reg(rd
, pass
, tmp
);
6751 if (pairwise
&& rd
== rm
) {
6752 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6753 tmp
= neon_load_scratch(pass
);
6754 neon_store_reg(rd
, pass
, tmp
);
6757 /* End of 3 register same size operations. */
6758 } else if (insn
& (1 << 4)) {
6759 if ((insn
& 0x00380080) != 0) {
6760 /* Two registers and shift. */
6761 op
= (insn
>> 8) & 0xf;
6762 if (insn
& (1 << 7)) {
6770 while ((insn
& (1 << (size
+ 19))) == 0)
6773 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
6775 /* Shift by immediate:
6776 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
6777 if (q
&& ((rd
| rm
) & 1)) {
6780 if (!u
&& (op
== 4 || op
== 6)) {
6783 /* Right shifts are encoded as N - shift, where N is the
6784 element size in bits. */
6786 shift
= shift
- (1 << (size
+ 3));
6791 /* Right shift comes here negative. */
6793 /* Shifts larger than the element size are architecturally
6794 * valid. Unsigned results in all zeros; signed results
6798 tcg_gen_gvec_sari(size
, rd_ofs
, rm_ofs
,
6799 MIN(shift
, (8 << size
) - 1),
6800 vec_size
, vec_size
);
6801 } else if (shift
>= 8 << size
) {
6802 tcg_gen_gvec_dup8i(rd_ofs
, vec_size
, vec_size
, 0);
6804 tcg_gen_gvec_shri(size
, rd_ofs
, rm_ofs
, shift
,
6805 vec_size
, vec_size
);
6810 /* Right shift comes here negative. */
6812 /* Shifts larger than the element size are architecturally
6813 * valid. Unsigned results in all zeros; signed results
6817 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
, vec_size
,
6818 MIN(shift
, (8 << size
) - 1),
6820 } else if (shift
>= 8 << size
) {
6823 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
, vec_size
,
6824 shift
, &usra_op
[size
]);
6832 /* Right shift comes here negative. */
6834 /* Shift out of range leaves destination unchanged. */
6835 if (shift
< 8 << size
) {
6836 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
, vec_size
,
6837 shift
, &sri_op
[size
]);
6841 case 5: /* VSHL, VSLI */
6843 /* Shift out of range leaves destination unchanged. */
6844 if (shift
< 8 << size
) {
6845 tcg_gen_gvec_2i(rd_ofs
, rm_ofs
, vec_size
,
6846 vec_size
, shift
, &sli_op
[size
]);
6849 /* Shifts larger than the element size are
6850 * architecturally valid and results in zero.
6852 if (shift
>= 8 << size
) {
6853 tcg_gen_gvec_dup8i(rd_ofs
, vec_size
, vec_size
, 0);
6855 tcg_gen_gvec_shli(size
, rd_ofs
, rm_ofs
, shift
,
6856 vec_size
, vec_size
);
6868 /* To avoid excessive duplication of ops we implement shift
6869 * by immediate using the variable shift operations.
6871 imm
= dup_const(size
, shift
);
6873 for (pass
= 0; pass
< count
; pass
++) {
6875 neon_load_reg64(cpu_V0
, rm
+ pass
);
6876 tcg_gen_movi_i64(cpu_V1
, imm
);
6881 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
6883 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
6885 case 6: /* VQSHLU */
6886 gen_helper_neon_qshlu_s64(cpu_V0
, cpu_env
,
6891 gen_helper_neon_qshl_u64(cpu_V0
, cpu_env
,
6894 gen_helper_neon_qshl_s64(cpu_V0
, cpu_env
,
6899 g_assert_not_reached();
6903 neon_load_reg64(cpu_V1
, rd
+ pass
);
6904 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
6906 neon_store_reg64(cpu_V0
, rd
+ pass
);
6907 } else { /* size < 3 */
6908 /* Operands in T0 and T1. */
6909 tmp
= neon_load_reg(rm
, pass
);
6910 tmp2
= tcg_temp_new_i32();
6911 tcg_gen_movi_i32(tmp2
, imm
);
6915 GEN_NEON_INTEGER_OP(rshl
);
6917 case 6: /* VQSHLU */
6920 gen_helper_neon_qshlu_s8(tmp
, cpu_env
,
6924 gen_helper_neon_qshlu_s16(tmp
, cpu_env
,
6928 gen_helper_neon_qshlu_s32(tmp
, cpu_env
,
6936 GEN_NEON_INTEGER_OP_ENV(qshl
);
6939 g_assert_not_reached();
6941 tcg_temp_free_i32(tmp2
);
6945 tmp2
= neon_load_reg(rd
, pass
);
6946 gen_neon_add(size
, tmp
, tmp2
);
6947 tcg_temp_free_i32(tmp2
);
6949 neon_store_reg(rd
, pass
, tmp
);
6952 } else if (op
< 10) {
6953 /* Shift by immediate and narrow:
6954 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
6955 int input_unsigned
= (op
== 8) ? !u
: u
;
6959 shift
= shift
- (1 << (size
+ 3));
6962 tmp64
= tcg_const_i64(shift
);
6963 neon_load_reg64(cpu_V0
, rm
);
6964 neon_load_reg64(cpu_V1
, rm
+ 1);
6965 for (pass
= 0; pass
< 2; pass
++) {
6973 if (input_unsigned
) {
6974 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
6976 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
6979 if (input_unsigned
) {
6980 gen_helper_neon_shl_u64(cpu_V0
, in
, tmp64
);
6982 gen_helper_neon_shl_s64(cpu_V0
, in
, tmp64
);
6985 tmp
= tcg_temp_new_i32();
6986 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
6987 neon_store_reg(rd
, pass
, tmp
);
6989 tcg_temp_free_i64(tmp64
);
6992 imm
= (uint16_t)shift
;
6996 imm
= (uint32_t)shift
;
6998 tmp2
= tcg_const_i32(imm
);
6999 tmp4
= neon_load_reg(rm
+ 1, 0);
7000 tmp5
= neon_load_reg(rm
+ 1, 1);
7001 for (pass
= 0; pass
< 2; pass
++) {
7003 tmp
= neon_load_reg(rm
, 0);
7007 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
7010 tmp3
= neon_load_reg(rm
, 1);
7014 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
7016 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
7017 tcg_temp_free_i32(tmp
);
7018 tcg_temp_free_i32(tmp3
);
7019 tmp
= tcg_temp_new_i32();
7020 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
7021 neon_store_reg(rd
, pass
, tmp
);
7023 tcg_temp_free_i32(tmp2
);
7025 } else if (op
== 10) {
7027 if (q
|| (rd
& 1)) {
7030 tmp
= neon_load_reg(rm
, 0);
7031 tmp2
= neon_load_reg(rm
, 1);
7032 for (pass
= 0; pass
< 2; pass
++) {
7036 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
7039 /* The shift is less than the width of the source
7040 type, so we can just shift the whole register. */
7041 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
7042 /* Widen the result of shift: we need to clear
7043 * the potential overflow bits resulting from
7044 * left bits of the narrow input appearing as
7045 * right bits of left the neighbour narrow
7047 if (size
< 2 || !u
) {
7050 imm
= (0xffu
>> (8 - shift
));
7052 } else if (size
== 1) {
7053 imm
= 0xffff >> (16 - shift
);
7056 imm
= 0xffffffff >> (32 - shift
);
7059 imm64
= imm
| (((uint64_t)imm
) << 32);
7063 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
7066 neon_store_reg64(cpu_V0
, rd
+ pass
);
7068 } else if (op
>= 14) {
7069 /* VCVT fixed-point. */
7070 if (!(insn
& (1 << 21)) || (q
&& ((rd
| rm
) & 1))) {
7073 /* We have already masked out the must-be-1 top bit of imm6,
7074 * hence this 32-shift where the ARM ARM has 64-imm6.
7077 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
7078 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, pass
));
7081 gen_vfp_ulto(0, shift
, 1);
7083 gen_vfp_slto(0, shift
, 1);
7086 gen_vfp_toul(0, shift
, 1);
7088 gen_vfp_tosl(0, shift
, 1);
7090 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, pass
));
7095 } else { /* (insn & 0x00380080) == 0 */
7096 int invert
, reg_ofs
, vec_size
;
7098 if (q
&& (rd
& 1)) {
7102 op
= (insn
>> 8) & 0xf;
7103 /* One register and immediate. */
7104 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
7105 invert
= (insn
& (1 << 5)) != 0;
7106 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
7107 * We choose to not special-case this and will behave as if a
7108 * valid constant encoding of 0 had been given.
7127 imm
= (imm
<< 8) | (imm
<< 24);
7130 imm
= (imm
<< 8) | 0xff;
7133 imm
= (imm
<< 16) | 0xffff;
7136 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
7145 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
7146 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
7153 reg_ofs
= neon_reg_offset(rd
, 0);
7154 vec_size
= q
? 16 : 8;
7156 if (op
& 1 && op
< 12) {
7158 /* The immediate value has already been inverted,
7159 * so BIC becomes AND.
7161 tcg_gen_gvec_andi(MO_32
, reg_ofs
, reg_ofs
, imm
,
7162 vec_size
, vec_size
);
7164 tcg_gen_gvec_ori(MO_32
, reg_ofs
, reg_ofs
, imm
,
7165 vec_size
, vec_size
);
7169 if (op
== 14 && invert
) {
7170 TCGv_i64 t64
= tcg_temp_new_i64();
7172 for (pass
= 0; pass
<= q
; ++pass
) {
7176 for (n
= 0; n
< 8; n
++) {
7177 if (imm
& (1 << (n
+ pass
* 8))) {
7178 val
|= 0xffull
<< (n
* 8);
7181 tcg_gen_movi_i64(t64
, val
);
7182 neon_store_reg64(t64
, rd
+ pass
);
7184 tcg_temp_free_i64(t64
);
7186 tcg_gen_gvec_dup32i(reg_ofs
, vec_size
, vec_size
, imm
);
7190 } else { /* (insn & 0x00800010 == 0x00800000) */
7192 op
= (insn
>> 8) & 0xf;
7193 if ((insn
& (1 << 6)) == 0) {
7194 /* Three registers of different lengths. */
7198 /* undefreq: bit 0 : UNDEF if size == 0
7199 * bit 1 : UNDEF if size == 1
7200 * bit 2 : UNDEF if size == 2
7201 * bit 3 : UNDEF if U == 1
7202 * Note that [2:0] set implies 'always UNDEF'
7205 /* prewiden, src1_wide, src2_wide, undefreq */
7206 static const int neon_3reg_wide
[16][4] = {
7207 {1, 0, 0, 0}, /* VADDL */
7208 {1, 1, 0, 0}, /* VADDW */
7209 {1, 0, 0, 0}, /* VSUBL */
7210 {1, 1, 0, 0}, /* VSUBW */
7211 {0, 1, 1, 0}, /* VADDHN */
7212 {0, 0, 0, 0}, /* VABAL */
7213 {0, 1, 1, 0}, /* VSUBHN */
7214 {0, 0, 0, 0}, /* VABDL */
7215 {0, 0, 0, 0}, /* VMLAL */
7216 {0, 0, 0, 9}, /* VQDMLAL */
7217 {0, 0, 0, 0}, /* VMLSL */
7218 {0, 0, 0, 9}, /* VQDMLSL */
7219 {0, 0, 0, 0}, /* Integer VMULL */
7220 {0, 0, 0, 1}, /* VQDMULL */
7221 {0, 0, 0, 0xa}, /* Polynomial VMULL */
7222 {0, 0, 0, 7}, /* Reserved: always UNDEF */
7225 prewiden
= neon_3reg_wide
[op
][0];
7226 src1_wide
= neon_3reg_wide
[op
][1];
7227 src2_wide
= neon_3reg_wide
[op
][2];
7228 undefreq
= neon_3reg_wide
[op
][3];
7230 if ((undefreq
& (1 << size
)) ||
7231 ((undefreq
& 8) && u
)) {
7234 if ((src1_wide
&& (rn
& 1)) ||
7235 (src2_wide
&& (rm
& 1)) ||
7236 (!src2_wide
&& (rd
& 1))) {
7240 /* Handle VMULL.P64 (Polynomial 64x64 to 128 bit multiply)
7241 * outside the loop below as it only performs a single pass.
7243 if (op
== 14 && size
== 2) {
7244 TCGv_i64 tcg_rn
, tcg_rm
, tcg_rd
;
7246 if (!dc_isar_feature(aa32_pmull
, s
)) {
7249 tcg_rn
= tcg_temp_new_i64();
7250 tcg_rm
= tcg_temp_new_i64();
7251 tcg_rd
= tcg_temp_new_i64();
7252 neon_load_reg64(tcg_rn
, rn
);
7253 neon_load_reg64(tcg_rm
, rm
);
7254 gen_helper_neon_pmull_64_lo(tcg_rd
, tcg_rn
, tcg_rm
);
7255 neon_store_reg64(tcg_rd
, rd
);
7256 gen_helper_neon_pmull_64_hi(tcg_rd
, tcg_rn
, tcg_rm
);
7257 neon_store_reg64(tcg_rd
, rd
+ 1);
7258 tcg_temp_free_i64(tcg_rn
);
7259 tcg_temp_free_i64(tcg_rm
);
7260 tcg_temp_free_i64(tcg_rd
);
7264 /* Avoid overlapping operands. Wide source operands are
7265 always aligned so will never overlap with wide
7266 destinations in problematic ways. */
7267 if (rd
== rm
&& !src2_wide
) {
7268 tmp
= neon_load_reg(rm
, 1);
7269 neon_store_scratch(2, tmp
);
7270 } else if (rd
== rn
&& !src1_wide
) {
7271 tmp
= neon_load_reg(rn
, 1);
7272 neon_store_scratch(2, tmp
);
7275 for (pass
= 0; pass
< 2; pass
++) {
7277 neon_load_reg64(cpu_V0
, rn
+ pass
);
7280 if (pass
== 1 && rd
== rn
) {
7281 tmp
= neon_load_scratch(2);
7283 tmp
= neon_load_reg(rn
, pass
);
7286 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
7290 neon_load_reg64(cpu_V1
, rm
+ pass
);
7293 if (pass
== 1 && rd
== rm
) {
7294 tmp2
= neon_load_scratch(2);
7296 tmp2
= neon_load_reg(rm
, pass
);
7299 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
7303 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
7304 gen_neon_addl(size
);
7306 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
7307 gen_neon_subl(size
);
7309 case 5: case 7: /* VABAL, VABDL */
7310 switch ((size
<< 1) | u
) {
7312 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
7315 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
7318 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
7321 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
7324 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
7327 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
7331 tcg_temp_free_i32(tmp2
);
7332 tcg_temp_free_i32(tmp
);
7334 case 8: case 9: case 10: case 11: case 12: case 13:
7335 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
7336 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
7338 case 14: /* Polynomial VMULL */
7339 gen_helper_neon_mull_p8(cpu_V0
, tmp
, tmp2
);
7340 tcg_temp_free_i32(tmp2
);
7341 tcg_temp_free_i32(tmp
);
7343 default: /* 15 is RESERVED: caught earlier */
7348 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
7349 neon_store_reg64(cpu_V0
, rd
+ pass
);
7350 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
7352 neon_load_reg64(cpu_V1
, rd
+ pass
);
7354 case 10: /* VMLSL */
7355 gen_neon_negl(cpu_V0
, size
);
7357 case 5: case 8: /* VABAL, VMLAL */
7358 gen_neon_addl(size
);
7360 case 9: case 11: /* VQDMLAL, VQDMLSL */
7361 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
7363 gen_neon_negl(cpu_V0
, size
);
7365 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
7370 neon_store_reg64(cpu_V0
, rd
+ pass
);
7371 } else if (op
== 4 || op
== 6) {
7372 /* Narrowing operation. */
7373 tmp
= tcg_temp_new_i32();
7377 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
7380 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
7383 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
7384 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
7391 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
7394 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
7397 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
7398 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
7399 tcg_gen_extrl_i64_i32(tmp
, cpu_V0
);
7407 neon_store_reg(rd
, 0, tmp3
);
7408 neon_store_reg(rd
, 1, tmp
);
7411 /* Write back the result. */
7412 neon_store_reg64(cpu_V0
, rd
+ pass
);
7416 /* Two registers and a scalar. NB that for ops of this form
7417 * the ARM ARM labels bit 24 as Q, but it is in our variable
7424 case 1: /* Float VMLA scalar */
7425 case 5: /* Floating point VMLS scalar */
7426 case 9: /* Floating point VMUL scalar */
7431 case 0: /* Integer VMLA scalar */
7432 case 4: /* Integer VMLS scalar */
7433 case 8: /* Integer VMUL scalar */
7434 case 12: /* VQDMULH scalar */
7435 case 13: /* VQRDMULH scalar */
7436 if (u
&& ((rd
| rn
) & 1)) {
7439 tmp
= neon_get_scalar(size
, rm
);
7440 neon_store_scratch(0, tmp
);
7441 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
7442 tmp
= neon_load_scratch(0);
7443 tmp2
= neon_load_reg(rn
, pass
);
7446 gen_helper_neon_qdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
7448 gen_helper_neon_qdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
7450 } else if (op
== 13) {
7452 gen_helper_neon_qrdmulh_s16(tmp
, cpu_env
, tmp
, tmp2
);
7454 gen_helper_neon_qrdmulh_s32(tmp
, cpu_env
, tmp
, tmp2
);
7456 } else if (op
& 1) {
7457 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7458 gen_helper_vfp_muls(tmp
, tmp
, tmp2
, fpstatus
);
7459 tcg_temp_free_ptr(fpstatus
);
7462 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
7463 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
7464 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
7468 tcg_temp_free_i32(tmp2
);
7471 tmp2
= neon_load_reg(rd
, pass
);
7474 gen_neon_add(size
, tmp
, tmp2
);
7478 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7479 gen_helper_vfp_adds(tmp
, tmp
, tmp2
, fpstatus
);
7480 tcg_temp_free_ptr(fpstatus
);
7484 gen_neon_rsb(size
, tmp
, tmp2
);
7488 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
7489 gen_helper_vfp_subs(tmp
, tmp2
, tmp
, fpstatus
);
7490 tcg_temp_free_ptr(fpstatus
);
7496 tcg_temp_free_i32(tmp2
);
7498 neon_store_reg(rd
, pass
, tmp
);
7501 case 3: /* VQDMLAL scalar */
7502 case 7: /* VQDMLSL scalar */
7503 case 11: /* VQDMULL scalar */
7508 case 2: /* VMLAL sclar */
7509 case 6: /* VMLSL scalar */
7510 case 10: /* VMULL scalar */
7514 tmp2
= neon_get_scalar(size
, rm
);
7515 /* We need a copy of tmp2 because gen_neon_mull
7516 * deletes it during pass 0. */
7517 tmp4
= tcg_temp_new_i32();
7518 tcg_gen_mov_i32(tmp4
, tmp2
);
7519 tmp3
= neon_load_reg(rn
, 1);
7521 for (pass
= 0; pass
< 2; pass
++) {
7523 tmp
= neon_load_reg(rn
, 0);
7528 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
7530 neon_load_reg64(cpu_V1
, rd
+ pass
);
7534 gen_neon_negl(cpu_V0
, size
);
7537 gen_neon_addl(size
);
7540 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
7542 gen_neon_negl(cpu_V0
, size
);
7544 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
7550 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
7555 neon_store_reg64(cpu_V0
, rd
+ pass
);
7558 case 14: /* VQRDMLAH scalar */
7559 case 15: /* VQRDMLSH scalar */
7561 NeonGenThreeOpEnvFn
*fn
;
7563 if (!dc_isar_feature(aa32_rdm
, s
)) {
7566 if (u
&& ((rd
| rn
) & 1)) {
7571 fn
= gen_helper_neon_qrdmlah_s16
;
7573 fn
= gen_helper_neon_qrdmlah_s32
;
7577 fn
= gen_helper_neon_qrdmlsh_s16
;
7579 fn
= gen_helper_neon_qrdmlsh_s32
;
7583 tmp2
= neon_get_scalar(size
, rm
);
7584 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
7585 tmp
= neon_load_reg(rn
, pass
);
7586 tmp3
= neon_load_reg(rd
, pass
);
7587 fn(tmp
, cpu_env
, tmp
, tmp2
, tmp3
);
7588 tcg_temp_free_i32(tmp3
);
7589 neon_store_reg(rd
, pass
, tmp
);
7591 tcg_temp_free_i32(tmp2
);
7595 g_assert_not_reached();
7598 } else { /* size == 3 */
7601 imm
= (insn
>> 8) & 0xf;
7606 if (q
&& ((rd
| rn
| rm
) & 1)) {
7611 neon_load_reg64(cpu_V0
, rn
);
7613 neon_load_reg64(cpu_V1
, rn
+ 1);
7615 } else if (imm
== 8) {
7616 neon_load_reg64(cpu_V0
, rn
+ 1);
7618 neon_load_reg64(cpu_V1
, rm
);
7621 tmp64
= tcg_temp_new_i64();
7623 neon_load_reg64(cpu_V0
, rn
);
7624 neon_load_reg64(tmp64
, rn
+ 1);
7626 neon_load_reg64(cpu_V0
, rn
+ 1);
7627 neon_load_reg64(tmp64
, rm
);
7629 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
7630 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
7631 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
7633 neon_load_reg64(cpu_V1
, rm
);
7635 neon_load_reg64(cpu_V1
, rm
+ 1);
7638 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
7639 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
7640 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
7641 tcg_temp_free_i64(tmp64
);
7644 neon_load_reg64(cpu_V0
, rn
);
7645 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
7646 neon_load_reg64(cpu_V1
, rm
);
7647 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
7648 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
7650 neon_store_reg64(cpu_V0
, rd
);
7652 neon_store_reg64(cpu_V1
, rd
+ 1);
7654 } else if ((insn
& (1 << 11)) == 0) {
7655 /* Two register misc. */
7656 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
7657 size
= (insn
>> 18) & 3;
7658 /* UNDEF for unknown op values and bad op-size combinations */
7659 if ((neon_2rm_sizes
[op
] & (1 << size
)) == 0) {
7662 if (neon_2rm_is_v8_op(op
) &&
7663 !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
7666 if ((op
!= NEON_2RM_VMOVN
&& op
!= NEON_2RM_VQMOVN
) &&
7667 q
&& ((rm
| rd
) & 1)) {
7671 case NEON_2RM_VREV64
:
7672 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
7673 tmp
= neon_load_reg(rm
, pass
* 2);
7674 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
7676 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
7677 case 1: gen_swap_half(tmp
); break;
7678 case 2: /* no-op */ break;
7681 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
7683 neon_store_reg(rd
, pass
* 2, tmp2
);
7686 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
7687 case 1: gen_swap_half(tmp2
); break;
7690 neon_store_reg(rd
, pass
* 2, tmp2
);
7694 case NEON_2RM_VPADDL
: case NEON_2RM_VPADDL_U
:
7695 case NEON_2RM_VPADAL
: case NEON_2RM_VPADAL_U
:
7696 for (pass
= 0; pass
< q
+ 1; pass
++) {
7697 tmp
= neon_load_reg(rm
, pass
* 2);
7698 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
7699 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
7700 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
7702 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
7703 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
7704 case 2: tcg_gen_add_i64(CPU_V001
); break;
7707 if (op
>= NEON_2RM_VPADAL
) {
7709 neon_load_reg64(cpu_V1
, rd
+ pass
);
7710 gen_neon_addl(size
);
7712 neon_store_reg64(cpu_V0
, rd
+ pass
);
7718 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
7719 tmp
= neon_load_reg(rm
, n
);
7720 tmp2
= neon_load_reg(rd
, n
+ 1);
7721 neon_store_reg(rm
, n
, tmp2
);
7722 neon_store_reg(rd
, n
+ 1, tmp
);
7729 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
7734 if (gen_neon_zip(rd
, rm
, size
, q
)) {
7738 case NEON_2RM_VMOVN
: case NEON_2RM_VQMOVN
:
7739 /* also VQMOVUN; op field and mnemonics don't line up */
7744 for (pass
= 0; pass
< 2; pass
++) {
7745 neon_load_reg64(cpu_V0
, rm
+ pass
);
7746 tmp
= tcg_temp_new_i32();
7747 gen_neon_narrow_op(op
== NEON_2RM_VMOVN
, q
, size
,
7752 neon_store_reg(rd
, 0, tmp2
);
7753 neon_store_reg(rd
, 1, tmp
);
7757 case NEON_2RM_VSHLL
:
7758 if (q
|| (rd
& 1)) {
7761 tmp
= neon_load_reg(rm
, 0);
7762 tmp2
= neon_load_reg(rm
, 1);
7763 for (pass
= 0; pass
< 2; pass
++) {
7766 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
7767 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
7768 neon_store_reg64(cpu_V0
, rd
+ pass
);
7771 case NEON_2RM_VCVT_F16_F32
:
7776 if (!arm_dc_feature(s
, ARM_FEATURE_VFP_FP16
) ||
7780 tmp
= tcg_temp_new_i32();
7781 tmp2
= tcg_temp_new_i32();
7782 fpst
= get_fpstatus_ptr(true);
7783 ahp
= get_ahp_flag();
7784 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 0));
7785 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, fpst
, ahp
);
7786 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 1));
7787 gen_helper_vfp_fcvt_f32_to_f16(tmp2
, cpu_F0s
, fpst
, ahp
);
7788 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
7789 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
7790 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 2));
7791 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, fpst
, ahp
);
7792 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 3));
7793 neon_store_reg(rd
, 0, tmp2
);
7794 tmp2
= tcg_temp_new_i32();
7795 gen_helper_vfp_fcvt_f32_to_f16(tmp2
, cpu_F0s
, fpst
, ahp
);
7796 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
7797 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
7798 neon_store_reg(rd
, 1, tmp2
);
7799 tcg_temp_free_i32(tmp
);
7800 tcg_temp_free_i32(ahp
);
7801 tcg_temp_free_ptr(fpst
);
7804 case NEON_2RM_VCVT_F32_F16
:
7808 if (!arm_dc_feature(s
, ARM_FEATURE_VFP_FP16
) ||
7812 fpst
= get_fpstatus_ptr(true);
7813 ahp
= get_ahp_flag();
7814 tmp3
= tcg_temp_new_i32();
7815 tmp
= neon_load_reg(rm
, 0);
7816 tmp2
= neon_load_reg(rm
, 1);
7817 tcg_gen_ext16u_i32(tmp3
, tmp
);
7818 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp3
, fpst
, ahp
);
7819 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 0));
7820 tcg_gen_shri_i32(tmp3
, tmp
, 16);
7821 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp3
, fpst
, ahp
);
7822 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 1));
7823 tcg_temp_free_i32(tmp
);
7824 tcg_gen_ext16u_i32(tmp3
, tmp2
);
7825 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp3
, fpst
, ahp
);
7826 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 2));
7827 tcg_gen_shri_i32(tmp3
, tmp2
, 16);
7828 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp3
, fpst
, ahp
);
7829 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 3));
7830 tcg_temp_free_i32(tmp2
);
7831 tcg_temp_free_i32(tmp3
);
7832 tcg_temp_free_i32(ahp
);
7833 tcg_temp_free_ptr(fpst
);
7836 case NEON_2RM_AESE
: case NEON_2RM_AESMC
:
7837 if (!dc_isar_feature(aa32_aes
, s
) || ((rm
| rd
) & 1)) {
7840 ptr1
= vfp_reg_ptr(true, rd
);
7841 ptr2
= vfp_reg_ptr(true, rm
);
7843 /* Bit 6 is the lowest opcode bit; it distinguishes between
7844 * encryption (AESE/AESMC) and decryption (AESD/AESIMC)
7846 tmp3
= tcg_const_i32(extract32(insn
, 6, 1));
7848 if (op
== NEON_2RM_AESE
) {
7849 gen_helper_crypto_aese(ptr1
, ptr2
, tmp3
);
7851 gen_helper_crypto_aesmc(ptr1
, ptr2
, tmp3
);
7853 tcg_temp_free_ptr(ptr1
);
7854 tcg_temp_free_ptr(ptr2
);
7855 tcg_temp_free_i32(tmp3
);
7857 case NEON_2RM_SHA1H
:
7858 if (!dc_isar_feature(aa32_sha1
, s
) || ((rm
| rd
) & 1)) {
7861 ptr1
= vfp_reg_ptr(true, rd
);
7862 ptr2
= vfp_reg_ptr(true, rm
);
7864 gen_helper_crypto_sha1h(ptr1
, ptr2
);
7866 tcg_temp_free_ptr(ptr1
);
7867 tcg_temp_free_ptr(ptr2
);
7869 case NEON_2RM_SHA1SU1
:
7870 if ((rm
| rd
) & 1) {
7873 /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */
7875 if (!dc_isar_feature(aa32_sha2
, s
)) {
7878 } else if (!dc_isar_feature(aa32_sha1
, s
)) {
7881 ptr1
= vfp_reg_ptr(true, rd
);
7882 ptr2
= vfp_reg_ptr(true, rm
);
7884 gen_helper_crypto_sha256su0(ptr1
, ptr2
);
7886 gen_helper_crypto_sha1su1(ptr1
, ptr2
);
7888 tcg_temp_free_ptr(ptr1
);
7889 tcg_temp_free_ptr(ptr2
);
7893 tcg_gen_gvec_not(0, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
7896 tcg_gen_gvec_neg(size
, rd_ofs
, rm_ofs
, vec_size
, vec_size
);
7901 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
7902 if (neon_2rm_is_float_op(op
)) {
7903 tcg_gen_ld_f32(cpu_F0s
, cpu_env
,
7904 neon_reg_offset(rm
, pass
));
7907 tmp
= neon_load_reg(rm
, pass
);
7910 case NEON_2RM_VREV32
:
7912 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
7913 case 1: gen_swap_half(tmp
); break;
7917 case NEON_2RM_VREV16
:
7922 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
7923 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
7924 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
7930 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
7931 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
7932 case 2: tcg_gen_clzi_i32(tmp
, tmp
, 32); break;
7937 gen_helper_neon_cnt_u8(tmp
, tmp
);
7939 case NEON_2RM_VQABS
:
7942 gen_helper_neon_qabs_s8(tmp
, cpu_env
, tmp
);
7945 gen_helper_neon_qabs_s16(tmp
, cpu_env
, tmp
);
7948 gen_helper_neon_qabs_s32(tmp
, cpu_env
, tmp
);
7953 case NEON_2RM_VQNEG
:
7956 gen_helper_neon_qneg_s8(tmp
, cpu_env
, tmp
);
7959 gen_helper_neon_qneg_s16(tmp
, cpu_env
, tmp
);
7962 gen_helper_neon_qneg_s32(tmp
, cpu_env
, tmp
);
7967 case NEON_2RM_VCGT0
: case NEON_2RM_VCLE0
:
7968 tmp2
= tcg_const_i32(0);
7970 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
7971 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
7972 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
7975 tcg_temp_free_i32(tmp2
);
7976 if (op
== NEON_2RM_VCLE0
) {
7977 tcg_gen_not_i32(tmp
, tmp
);
7980 case NEON_2RM_VCGE0
: case NEON_2RM_VCLT0
:
7981 tmp2
= tcg_const_i32(0);
7983 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
7984 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
7985 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
7988 tcg_temp_free_i32(tmp2
);
7989 if (op
== NEON_2RM_VCLT0
) {
7990 tcg_gen_not_i32(tmp
, tmp
);
7993 case NEON_2RM_VCEQ0
:
7994 tmp2
= tcg_const_i32(0);
7996 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
7997 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
7998 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
8001 tcg_temp_free_i32(tmp2
);
8005 case 0: gen_helper_neon_abs_s8(tmp
, tmp
); break;
8006 case 1: gen_helper_neon_abs_s16(tmp
, tmp
); break;
8007 case 2: tcg_gen_abs_i32(tmp
, tmp
); break;
8011 case NEON_2RM_VCGT0_F
:
8013 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8014 tmp2
= tcg_const_i32(0);
8015 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
, fpstatus
);
8016 tcg_temp_free_i32(tmp2
);
8017 tcg_temp_free_ptr(fpstatus
);
8020 case NEON_2RM_VCGE0_F
:
8022 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8023 tmp2
= tcg_const_i32(0);
8024 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
, fpstatus
);
8025 tcg_temp_free_i32(tmp2
);
8026 tcg_temp_free_ptr(fpstatus
);
8029 case NEON_2RM_VCEQ0_F
:
8031 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8032 tmp2
= tcg_const_i32(0);
8033 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
, fpstatus
);
8034 tcg_temp_free_i32(tmp2
);
8035 tcg_temp_free_ptr(fpstatus
);
8038 case NEON_2RM_VCLE0_F
:
8040 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8041 tmp2
= tcg_const_i32(0);
8042 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
, fpstatus
);
8043 tcg_temp_free_i32(tmp2
);
8044 tcg_temp_free_ptr(fpstatus
);
8047 case NEON_2RM_VCLT0_F
:
8049 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8050 tmp2
= tcg_const_i32(0);
8051 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
, fpstatus
);
8052 tcg_temp_free_i32(tmp2
);
8053 tcg_temp_free_ptr(fpstatus
);
8056 case NEON_2RM_VABS_F
:
8059 case NEON_2RM_VNEG_F
:
8063 tmp2
= neon_load_reg(rd
, pass
);
8064 neon_store_reg(rm
, pass
, tmp2
);
8067 tmp2
= neon_load_reg(rd
, pass
);
8069 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
8070 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
8073 neon_store_reg(rm
, pass
, tmp2
);
8075 case NEON_2RM_VRINTN
:
8076 case NEON_2RM_VRINTA
:
8077 case NEON_2RM_VRINTM
:
8078 case NEON_2RM_VRINTP
:
8079 case NEON_2RM_VRINTZ
:
8082 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8085 if (op
== NEON_2RM_VRINTZ
) {
8086 rmode
= FPROUNDING_ZERO
;
8088 rmode
= fp_decode_rm
[((op
& 0x6) >> 1) ^ 1];
8091 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8092 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
8094 gen_helper_rints(cpu_F0s
, cpu_F0s
, fpstatus
);
8095 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
8097 tcg_temp_free_ptr(fpstatus
);
8098 tcg_temp_free_i32(tcg_rmode
);
8101 case NEON_2RM_VRINTX
:
8103 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8104 gen_helper_rints_exact(cpu_F0s
, cpu_F0s
, fpstatus
);
8105 tcg_temp_free_ptr(fpstatus
);
8108 case NEON_2RM_VCVTAU
:
8109 case NEON_2RM_VCVTAS
:
8110 case NEON_2RM_VCVTNU
:
8111 case NEON_2RM_VCVTNS
:
8112 case NEON_2RM_VCVTPU
:
8113 case NEON_2RM_VCVTPS
:
8114 case NEON_2RM_VCVTMU
:
8115 case NEON_2RM_VCVTMS
:
8117 bool is_signed
= !extract32(insn
, 7, 1);
8118 TCGv_ptr fpst
= get_fpstatus_ptr(1);
8119 TCGv_i32 tcg_rmode
, tcg_shift
;
8120 int rmode
= fp_decode_rm
[extract32(insn
, 8, 2)];
8122 tcg_shift
= tcg_const_i32(0);
8123 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8124 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
8128 gen_helper_vfp_tosls(cpu_F0s
, cpu_F0s
,
8131 gen_helper_vfp_touls(cpu_F0s
, cpu_F0s
,
8135 gen_helper_set_neon_rmode(tcg_rmode
, tcg_rmode
,
8137 tcg_temp_free_i32(tcg_rmode
);
8138 tcg_temp_free_i32(tcg_shift
);
8139 tcg_temp_free_ptr(fpst
);
8142 case NEON_2RM_VRECPE
:
8144 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8145 gen_helper_recpe_u32(tmp
, tmp
, fpstatus
);
8146 tcg_temp_free_ptr(fpstatus
);
8149 case NEON_2RM_VRSQRTE
:
8151 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8152 gen_helper_rsqrte_u32(tmp
, tmp
, fpstatus
);
8153 tcg_temp_free_ptr(fpstatus
);
8156 case NEON_2RM_VRECPE_F
:
8158 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8159 gen_helper_recpe_f32(cpu_F0s
, cpu_F0s
, fpstatus
);
8160 tcg_temp_free_ptr(fpstatus
);
8163 case NEON_2RM_VRSQRTE_F
:
8165 TCGv_ptr fpstatus
= get_fpstatus_ptr(1);
8166 gen_helper_rsqrte_f32(cpu_F0s
, cpu_F0s
, fpstatus
);
8167 tcg_temp_free_ptr(fpstatus
);
8170 case NEON_2RM_VCVT_FS
: /* VCVT.F32.S32 */
8173 case NEON_2RM_VCVT_FU
: /* VCVT.F32.U32 */
8176 case NEON_2RM_VCVT_SF
: /* VCVT.S32.F32 */
8177 gen_vfp_tosiz(0, 1);
8179 case NEON_2RM_VCVT_UF
: /* VCVT.U32.F32 */
8180 gen_vfp_touiz(0, 1);
8183 /* Reserved op values were caught by the
8184 * neon_2rm_sizes[] check earlier.
8188 if (neon_2rm_is_float_op(op
)) {
8189 tcg_gen_st_f32(cpu_F0s
, cpu_env
,
8190 neon_reg_offset(rd
, pass
));
8192 neon_store_reg(rd
, pass
, tmp
);
8197 } else if ((insn
& (1 << 10)) == 0) {
8199 int n
= ((insn
>> 8) & 3) + 1;
8200 if ((rn
+ n
) > 32) {
8201 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
8202 * helper function running off the end of the register file.
8207 if (insn
& (1 << 6)) {
8208 tmp
= neon_load_reg(rd
, 0);
8210 tmp
= tcg_temp_new_i32();
8211 tcg_gen_movi_i32(tmp
, 0);
8213 tmp2
= neon_load_reg(rm
, 0);
8214 ptr1
= vfp_reg_ptr(true, rn
);
8215 tmp5
= tcg_const_i32(n
);
8216 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, ptr1
, tmp5
);
8217 tcg_temp_free_i32(tmp
);
8218 if (insn
& (1 << 6)) {
8219 tmp
= neon_load_reg(rd
, 1);
8221 tmp
= tcg_temp_new_i32();
8222 tcg_gen_movi_i32(tmp
, 0);
8224 tmp3
= neon_load_reg(rm
, 1);
8225 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, ptr1
, tmp5
);
8226 tcg_temp_free_i32(tmp5
);
8227 tcg_temp_free_ptr(ptr1
);
8228 neon_store_reg(rd
, 0, tmp2
);
8229 neon_store_reg(rd
, 1, tmp3
);
8230 tcg_temp_free_i32(tmp
);
8231 } else if ((insn
& 0x380) == 0) {
8236 if ((insn
& (7 << 16)) == 0 || (q
&& (rd
& 1))) {
8239 if (insn
& (1 << 16)) {
8241 element
= (insn
>> 17) & 7;
8242 } else if (insn
& (1 << 17)) {
8244 element
= (insn
>> 18) & 3;
8247 element
= (insn
>> 19) & 1;
8249 tcg_gen_gvec_dup_mem(size
, neon_reg_offset(rd
, 0),
8250 neon_element_offset(rm
, element
, size
),
8251 q
? 16 : 8, q
? 16 : 8);
8260 /* Advanced SIMD three registers of the same length extension.
8261 * 31 25 23 22 20 16 12 11 10 9 8 3 0
8262 * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
8263 * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
8264 * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
8266 static int disas_neon_insn_3same_ext(DisasContext
*s
, uint32_t insn
)
8268 gen_helper_gvec_3
*fn_gvec
= NULL
;
8269 gen_helper_gvec_3_ptr
*fn_gvec_ptr
= NULL
;
8270 int rd
, rn
, rm
, opr_sz
;
8274 q
= extract32(insn
, 6, 1);
8275 VFP_DREG_D(rd
, insn
);
8276 VFP_DREG_N(rn
, insn
);
8277 VFP_DREG_M(rm
, insn
);
8278 if ((rd
| rn
| rm
) & q
) {
8282 if ((insn
& 0xfe200f10) == 0xfc200800) {
8283 /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
8284 int size
= extract32(insn
, 20, 1);
8285 data
= extract32(insn
, 23, 2); /* rot */
8286 if (!dc_isar_feature(aa32_vcma
, s
)
8287 || (!size
&& !dc_isar_feature(aa32_fp16_arith
, s
))) {
8290 fn_gvec_ptr
= size
? gen_helper_gvec_fcmlas
: gen_helper_gvec_fcmlah
;
8291 } else if ((insn
& 0xfea00f10) == 0xfc800800) {
8292 /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
8293 int size
= extract32(insn
, 20, 1);
8294 data
= extract32(insn
, 24, 1); /* rot */
8295 if (!dc_isar_feature(aa32_vcma
, s
)
8296 || (!size
&& !dc_isar_feature(aa32_fp16_arith
, s
))) {
8299 fn_gvec_ptr
= size
? gen_helper_gvec_fcadds
: gen_helper_gvec_fcaddh
;
8300 } else if ((insn
& 0xfeb00f00) == 0xfc200d00) {
8301 /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
8302 bool u
= extract32(insn
, 4, 1);
8303 if (!dc_isar_feature(aa32_dp
, s
)) {
8306 fn_gvec
= u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
;
8311 if (s
->fp_excp_el
) {
8312 gen_exception_insn(s
, 4, EXCP_UDEF
,
8313 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
8316 if (!s
->vfp_enabled
) {
8320 opr_sz
= (1 + q
) * 8;
8322 TCGv_ptr fpst
= get_fpstatus_ptr(1);
8323 tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd
),
8324 vfp_reg_offset(1, rn
),
8325 vfp_reg_offset(1, rm
), fpst
,
8326 opr_sz
, opr_sz
, data
, fn_gvec_ptr
);
8327 tcg_temp_free_ptr(fpst
);
8329 tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd
),
8330 vfp_reg_offset(1, rn
),
8331 vfp_reg_offset(1, rm
),
8332 opr_sz
, opr_sz
, data
, fn_gvec
);
8337 /* Advanced SIMD two registers and a scalar extension.
8338 * 31 24 23 22 20 16 12 11 10 9 8 3 0
8339 * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
8340 * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
8341 * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
8345 static int disas_neon_insn_2reg_scalar_ext(DisasContext
*s
, uint32_t insn
)
8347 gen_helper_gvec_3
*fn_gvec
= NULL
;
8348 gen_helper_gvec_3_ptr
*fn_gvec_ptr
= NULL
;
8349 int rd
, rn
, rm
, opr_sz
, data
;
8352 q
= extract32(insn
, 6, 1);
8353 VFP_DREG_D(rd
, insn
);
8354 VFP_DREG_N(rn
, insn
);
8355 if ((rd
| rn
) & q
) {
8359 if ((insn
& 0xff000f10) == 0xfe000800) {
8360 /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
8361 int rot
= extract32(insn
, 20, 2);
8362 int size
= extract32(insn
, 23, 1);
8365 if (!dc_isar_feature(aa32_vcma
, s
)) {
8369 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
8372 /* For fp16, rm is just Vm, and index is M. */
8373 rm
= extract32(insn
, 0, 4);
8374 index
= extract32(insn
, 5, 1);
8376 /* For fp32, rm is the usual M:Vm, and index is 0. */
8377 VFP_DREG_M(rm
, insn
);
8380 data
= (index
<< 2) | rot
;
8381 fn_gvec_ptr
= (size
? gen_helper_gvec_fcmlas_idx
8382 : gen_helper_gvec_fcmlah_idx
);
8383 } else if ((insn
& 0xffb00f00) == 0xfe200d00) {
8384 /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
8385 int u
= extract32(insn
, 4, 1);
8386 if (!dc_isar_feature(aa32_dp
, s
)) {
8389 fn_gvec
= u
? gen_helper_gvec_udot_idx_b
: gen_helper_gvec_sdot_idx_b
;
8390 /* rm is just Vm, and index is M. */
8391 data
= extract32(insn
, 5, 1); /* index */
8392 rm
= extract32(insn
, 0, 4);
8397 if (s
->fp_excp_el
) {
8398 gen_exception_insn(s
, 4, EXCP_UDEF
,
8399 syn_simd_access_trap(1, 0xe, false), s
->fp_excp_el
);
8402 if (!s
->vfp_enabled
) {
8406 opr_sz
= (1 + q
) * 8;
8408 TCGv_ptr fpst
= get_fpstatus_ptr(1);
8409 tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd
),
8410 vfp_reg_offset(1, rn
),
8411 vfp_reg_offset(1, rm
), fpst
,
8412 opr_sz
, opr_sz
, data
, fn_gvec_ptr
);
8413 tcg_temp_free_ptr(fpst
);
8415 tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd
),
8416 vfp_reg_offset(1, rn
),
8417 vfp_reg_offset(1, rm
),
8418 opr_sz
, opr_sz
, data
, fn_gvec
);
8423 static int disas_coproc_insn(DisasContext
*s
, uint32_t insn
)
8425 int cpnum
, is64
, crn
, crm
, opc1
, opc2
, isread
, rt
, rt2
;
8426 const ARMCPRegInfo
*ri
;
8428 cpnum
= (insn
>> 8) & 0xf;
8430 /* First check for coprocessor space used for XScale/iwMMXt insns */
8431 if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && (cpnum
< 2)) {
8432 if (extract32(s
->c15_cpar
, cpnum
, 1) == 0) {
8435 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
8436 return disas_iwmmxt_insn(s
, insn
);
8437 } else if (arm_dc_feature(s
, ARM_FEATURE_XSCALE
)) {
8438 return disas_dsp_insn(s
, insn
);
8443 /* Otherwise treat as a generic register access */
8444 is64
= (insn
& (1 << 25)) == 0;
8445 if (!is64
&& ((insn
& (1 << 4)) == 0)) {
8453 opc1
= (insn
>> 4) & 0xf;
8455 rt2
= (insn
>> 16) & 0xf;
8457 crn
= (insn
>> 16) & 0xf;
8458 opc1
= (insn
>> 21) & 7;
8459 opc2
= (insn
>> 5) & 7;
8462 isread
= (insn
>> 20) & 1;
8463 rt
= (insn
>> 12) & 0xf;
8465 ri
= get_arm_cp_reginfo(s
->cp_regs
,
8466 ENCODE_CP_REG(cpnum
, is64
, s
->ns
, crn
, crm
, opc1
, opc2
));
8468 /* Check access permissions */
8469 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
8474 (arm_dc_feature(s
, ARM_FEATURE_XSCALE
) && cpnum
< 14)) {
8475 /* Emit code to perform further access permissions checks at
8476 * runtime; this may result in an exception.
8477 * Note that on XScale all cp0..c13 registers do an access check
8478 * call in order to handle c15_cpar.
8481 TCGv_i32 tcg_syn
, tcg_isread
;
8484 /* Note that since we are an implementation which takes an
8485 * exception on a trapped conditional instruction only if the
8486 * instruction passes its condition code check, we can take
8487 * advantage of the clause in the ARM ARM that allows us to set
8488 * the COND field in the instruction to 0xE in all cases.
8489 * We could fish the actual condition out of the insn (ARM)
8490 * or the condexec bits (Thumb) but it isn't necessary.
8495 syndrome
= syn_cp14_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
8498 syndrome
= syn_cp14_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
8504 syndrome
= syn_cp15_rrt_trap(1, 0xe, opc1
, crm
, rt
, rt2
,
8507 syndrome
= syn_cp15_rt_trap(1, 0xe, opc1
, opc2
, crn
, crm
,
8512 /* ARMv8 defines that only coprocessors 14 and 15 exist,
8513 * so this can only happen if this is an ARMv7 or earlier CPU,
8514 * in which case the syndrome information won't actually be
8517 assert(!arm_dc_feature(s
, ARM_FEATURE_V8
));
8518 syndrome
= syn_uncategorized();
8522 gen_set_condexec(s
);
8523 gen_set_pc_im(s
, s
->pc
- 4);
8524 tmpptr
= tcg_const_ptr(ri
);
8525 tcg_syn
= tcg_const_i32(syndrome
);
8526 tcg_isread
= tcg_const_i32(isread
);
8527 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
,
8529 tcg_temp_free_ptr(tmpptr
);
8530 tcg_temp_free_i32(tcg_syn
);
8531 tcg_temp_free_i32(tcg_isread
);
8534 /* Handle special cases first */
8535 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
8542 gen_set_pc_im(s
, s
->pc
);
8543 s
->base
.is_jmp
= DISAS_WFI
;
8549 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
8558 if (ri
->type
& ARM_CP_CONST
) {
8559 tmp64
= tcg_const_i64(ri
->resetvalue
);
8560 } else if (ri
->readfn
) {
8562 tmp64
= tcg_temp_new_i64();
8563 tmpptr
= tcg_const_ptr(ri
);
8564 gen_helper_get_cp_reg64(tmp64
, cpu_env
, tmpptr
);
8565 tcg_temp_free_ptr(tmpptr
);
8567 tmp64
= tcg_temp_new_i64();
8568 tcg_gen_ld_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
8570 tmp
= tcg_temp_new_i32();
8571 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
8572 store_reg(s
, rt
, tmp
);
8573 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
8574 tmp
= tcg_temp_new_i32();
8575 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
8576 tcg_temp_free_i64(tmp64
);
8577 store_reg(s
, rt2
, tmp
);
8580 if (ri
->type
& ARM_CP_CONST
) {
8581 tmp
= tcg_const_i32(ri
->resetvalue
);
8582 } else if (ri
->readfn
) {
8584 tmp
= tcg_temp_new_i32();
8585 tmpptr
= tcg_const_ptr(ri
);
8586 gen_helper_get_cp_reg(tmp
, cpu_env
, tmpptr
);
8587 tcg_temp_free_ptr(tmpptr
);
8589 tmp
= load_cpu_offset(ri
->fieldoffset
);
8592 /* Destination register of r15 for 32 bit loads sets
8593 * the condition codes from the high 4 bits of the value
8596 tcg_temp_free_i32(tmp
);
8598 store_reg(s
, rt
, tmp
);
8603 if (ri
->type
& ARM_CP_CONST
) {
8604 /* If not forbidden by access permissions, treat as WI */
8609 TCGv_i32 tmplo
, tmphi
;
8610 TCGv_i64 tmp64
= tcg_temp_new_i64();
8611 tmplo
= load_reg(s
, rt
);
8612 tmphi
= load_reg(s
, rt2
);
8613 tcg_gen_concat_i32_i64(tmp64
, tmplo
, tmphi
);
8614 tcg_temp_free_i32(tmplo
);
8615 tcg_temp_free_i32(tmphi
);
8617 TCGv_ptr tmpptr
= tcg_const_ptr(ri
);
8618 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tmp64
);
8619 tcg_temp_free_ptr(tmpptr
);
8621 tcg_gen_st_i64(tmp64
, cpu_env
, ri
->fieldoffset
);
8623 tcg_temp_free_i64(tmp64
);
8628 tmp
= load_reg(s
, rt
);
8629 tmpptr
= tcg_const_ptr(ri
);
8630 gen_helper_set_cp_reg(cpu_env
, tmpptr
, tmp
);
8631 tcg_temp_free_ptr(tmpptr
);
8632 tcg_temp_free_i32(tmp
);
8634 TCGv_i32 tmp
= load_reg(s
, rt
);
8635 store_cpu_offset(tmp
, ri
->fieldoffset
);
8640 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
8641 /* I/O operations must end the TB here (whether read or write) */
8644 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
8645 /* We default to ending the TB on a coprocessor register write,
8646 * but allow this to be suppressed by the register definition
8647 * (usually only necessary to work around guest bugs).
8655 /* Unknown register; this might be a guest error or a QEMU
8656 * unimplemented feature.
8659 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
8660 "64 bit system register cp:%d opc1: %d crm:%d "
8662 isread
? "read" : "write", cpnum
, opc1
, crm
,
8663 s
->ns
? "non-secure" : "secure");
8665 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch32 "
8666 "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d "
8668 isread
? "read" : "write", cpnum
, opc1
, crn
, crm
, opc2
,
8669 s
->ns
? "non-secure" : "secure");
8676 /* Store a 64-bit value to a register pair. Clobbers val. */
8677 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
8680 tmp
= tcg_temp_new_i32();
8681 tcg_gen_extrl_i64_i32(tmp
, val
);
8682 store_reg(s
, rlow
, tmp
);
8683 tmp
= tcg_temp_new_i32();
8684 tcg_gen_shri_i64(val
, val
, 32);
8685 tcg_gen_extrl_i64_i32(tmp
, val
);
8686 store_reg(s
, rhigh
, tmp
);
8689 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
8690 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
8695 /* Load value and extend to 64 bits. */
8696 tmp
= tcg_temp_new_i64();
8697 tmp2
= load_reg(s
, rlow
);
8698 tcg_gen_extu_i32_i64(tmp
, tmp2
);
8699 tcg_temp_free_i32(tmp2
);
8700 tcg_gen_add_i64(val
, val
, tmp
);
8701 tcg_temp_free_i64(tmp
);
8704 /* load and add a 64-bit value from a register pair. */
8705 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
8711 /* Load 64-bit value rd:rn. */
8712 tmpl
= load_reg(s
, rlow
);
8713 tmph
= load_reg(s
, rhigh
);
8714 tmp
= tcg_temp_new_i64();
8715 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
8716 tcg_temp_free_i32(tmpl
);
8717 tcg_temp_free_i32(tmph
);
8718 tcg_gen_add_i64(val
, val
, tmp
);
8719 tcg_temp_free_i64(tmp
);
8722 /* Set N and Z flags from hi|lo. */
8723 static void gen_logicq_cc(TCGv_i32 lo
, TCGv_i32 hi
)
8725 tcg_gen_mov_i32(cpu_NF
, hi
);
8726 tcg_gen_or_i32(cpu_ZF
, lo
, hi
);
8729 /* Load/Store exclusive instructions are implemented by remembering
8730 the value/address loaded, and seeing if these are the same
8731 when the store is performed. This should be sufficient to implement
8732 the architecturally mandated semantics, and avoids having to monitor
8733 regular stores. The compare vs the remembered value is done during
8734 the cmpxchg operation, but we must compare the addresses manually. */
8735 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
8736 TCGv_i32 addr
, int size
)
8738 TCGv_i32 tmp
= tcg_temp_new_i32();
8739 TCGMemOp opc
= size
| MO_ALIGN
| s
->be_data
;
8744 TCGv_i32 tmp2
= tcg_temp_new_i32();
8745 TCGv_i64 t64
= tcg_temp_new_i64();
8747 /* For AArch32, architecturally the 32-bit word at the lowest
8748 * address is always Rt and the one at addr+4 is Rt2, even if
8749 * the CPU is big-endian. That means we don't want to do a
8750 * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if
8751 * for an architecturally 64-bit access, but instead do a
8752 * 64-bit access using MO_BE if appropriate and then split
8754 * This only makes a difference for BE32 user-mode, where
8755 * frob64() must not flip the two halves of the 64-bit data
8756 * but this code must treat BE32 user-mode like BE32 system.
8758 TCGv taddr
= gen_aa32_addr(s
, addr
, opc
);
8760 tcg_gen_qemu_ld_i64(t64
, taddr
, get_mem_index(s
), opc
);
8761 tcg_temp_free(taddr
);
8762 tcg_gen_mov_i64(cpu_exclusive_val
, t64
);
8763 if (s
->be_data
== MO_BE
) {
8764 tcg_gen_extr_i64_i32(tmp2
, tmp
, t64
);
8766 tcg_gen_extr_i64_i32(tmp
, tmp2
, t64
);
8768 tcg_temp_free_i64(t64
);
8770 store_reg(s
, rt2
, tmp2
);
8772 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), opc
);
8773 tcg_gen_extu_i32_i64(cpu_exclusive_val
, tmp
);
8776 store_reg(s
, rt
, tmp
);
8777 tcg_gen_extu_i32_i64(cpu_exclusive_addr
, addr
);
8780 static void gen_clrex(DisasContext
*s
)
8782 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
8785 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
8786 TCGv_i32 addr
, int size
)
8788 TCGv_i32 t0
, t1
, t2
;
8791 TCGLabel
*done_label
;
8792 TCGLabel
*fail_label
;
8793 TCGMemOp opc
= size
| MO_ALIGN
| s
->be_data
;
8795 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
8801 fail_label
= gen_new_label();
8802 done_label
= gen_new_label();
8803 extaddr
= tcg_temp_new_i64();
8804 tcg_gen_extu_i32_i64(extaddr
, addr
);
8805 tcg_gen_brcond_i64(TCG_COND_NE
, extaddr
, cpu_exclusive_addr
, fail_label
);
8806 tcg_temp_free_i64(extaddr
);
8808 taddr
= gen_aa32_addr(s
, addr
, opc
);
8809 t0
= tcg_temp_new_i32();
8810 t1
= load_reg(s
, rt
);
8812 TCGv_i64 o64
= tcg_temp_new_i64();
8813 TCGv_i64 n64
= tcg_temp_new_i64();
8815 t2
= load_reg(s
, rt2
);
8816 /* For AArch32, architecturally the 32-bit word at the lowest
8817 * address is always Rt and the one at addr+4 is Rt2, even if
8818 * the CPU is big-endian. Since we're going to treat this as a
8819 * single 64-bit BE store, we need to put the two halves in the
8820 * opposite order for BE to LE, so that they end up in the right
8822 * We don't want gen_aa32_frob64() because that does the wrong
8823 * thing for BE32 usermode.
8825 if (s
->be_data
== MO_BE
) {
8826 tcg_gen_concat_i32_i64(n64
, t2
, t1
);
8828 tcg_gen_concat_i32_i64(n64
, t1
, t2
);
8830 tcg_temp_free_i32(t2
);
8832 tcg_gen_atomic_cmpxchg_i64(o64
, taddr
, cpu_exclusive_val
, n64
,
8833 get_mem_index(s
), opc
);
8834 tcg_temp_free_i64(n64
);
8836 tcg_gen_setcond_i64(TCG_COND_NE
, o64
, o64
, cpu_exclusive_val
);
8837 tcg_gen_extrl_i64_i32(t0
, o64
);
8839 tcg_temp_free_i64(o64
);
8841 t2
= tcg_temp_new_i32();
8842 tcg_gen_extrl_i64_i32(t2
, cpu_exclusive_val
);
8843 tcg_gen_atomic_cmpxchg_i32(t0
, taddr
, t2
, t1
, get_mem_index(s
), opc
);
8844 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t2
);
8845 tcg_temp_free_i32(t2
);
8847 tcg_temp_free_i32(t1
);
8848 tcg_temp_free(taddr
);
8849 tcg_gen_mov_i32(cpu_R
[rd
], t0
);
8850 tcg_temp_free_i32(t0
);
8851 tcg_gen_br(done_label
);
8853 gen_set_label(fail_label
);
8854 tcg_gen_movi_i32(cpu_R
[rd
], 1);
8855 gen_set_label(done_label
);
8856 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
8862 * @mode: mode field from insn (which stack to store to)
8863 * @amode: addressing mode (DA/IA/DB/IB), encoded as per P,U bits in ARM insn
8864 * @writeback: true if writeback bit set
8866 * Generate code for the SRS (Store Return State) insn.
8868 static void gen_srs(DisasContext
*s
,
8869 uint32_t mode
, uint32_t amode
, bool writeback
)
8876 * - trapped to EL3 if EL3 is AArch64 and we are at Secure EL1
8877 * and specified mode is monitor mode
8878 * - UNDEFINED in Hyp mode
8879 * - UNPREDICTABLE in User or System mode
8880 * - UNPREDICTABLE if the specified mode is:
8881 * -- not implemented
8882 * -- not a valid mode number
8883 * -- a mode that's at a higher exception level
8884 * -- Monitor, if we are Non-secure
8885 * For the UNPREDICTABLE cases we choose to UNDEF.
8887 if (s
->current_el
== 1 && !s
->ns
&& mode
== ARM_CPU_MODE_MON
) {
8888 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(), 3);
8892 if (s
->current_el
== 0 || s
->current_el
== 2) {
8897 case ARM_CPU_MODE_USR
:
8898 case ARM_CPU_MODE_FIQ
:
8899 case ARM_CPU_MODE_IRQ
:
8900 case ARM_CPU_MODE_SVC
:
8901 case ARM_CPU_MODE_ABT
:
8902 case ARM_CPU_MODE_UND
:
8903 case ARM_CPU_MODE_SYS
:
8905 case ARM_CPU_MODE_HYP
:
8906 if (s
->current_el
== 1 || !arm_dc_feature(s
, ARM_FEATURE_EL2
)) {
8910 case ARM_CPU_MODE_MON
:
8911 /* No need to check specifically for "are we non-secure" because
8912 * we've already made EL0 UNDEF and handled the trap for S-EL1;
8913 * so if this isn't EL3 then we must be non-secure.
8915 if (s
->current_el
!= 3) {
8924 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
8925 default_exception_el(s
));
8929 addr
= tcg_temp_new_i32();
8930 tmp
= tcg_const_i32(mode
);
8931 /* get_r13_banked() will raise an exception if called from System mode */
8932 gen_set_condexec(s
);
8933 gen_set_pc_im(s
, s
->pc
- 4);
8934 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
8935 tcg_temp_free_i32(tmp
);
8952 tcg_gen_addi_i32(addr
, addr
, offset
);
8953 tmp
= load_reg(s
, 14);
8954 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
8955 tcg_temp_free_i32(tmp
);
8956 tmp
= load_cpu_field(spsr
);
8957 tcg_gen_addi_i32(addr
, addr
, 4);
8958 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
8959 tcg_temp_free_i32(tmp
);
8977 tcg_gen_addi_i32(addr
, addr
, offset
);
8978 tmp
= tcg_const_i32(mode
);
8979 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
8980 tcg_temp_free_i32(tmp
);
8982 tcg_temp_free_i32(addr
);
8983 s
->base
.is_jmp
= DISAS_UPDATE
;
8986 /* Generate a label used for skipping this instruction */
8987 static void arm_gen_condlabel(DisasContext
*s
)
8990 s
->condlabel
= gen_new_label();
8995 /* Skip this instruction if the ARM condition is false */
8996 static void arm_skip_unless(DisasContext
*s
, uint32_t cond
)
8998 arm_gen_condlabel(s
);
8999 arm_gen_test_cc(cond
^ 1, s
->condlabel
);
9002 static void disas_arm_insn(DisasContext
*s
, unsigned int insn
)
9004 unsigned int cond
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
9011 /* M variants do not implement ARM mode; this must raise the INVSTATE
9012 * UsageFault exception.
9014 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
9015 gen_exception_insn(s
, 4, EXCP_INVSTATE
, syn_uncategorized(),
9016 default_exception_el(s
));
9021 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
9022 * choose to UNDEF. In ARMv5 and above the space is used
9023 * for miscellaneous unconditional instructions.
9027 /* Unconditional instructions. */
9028 if (((insn
>> 25) & 7) == 1) {
9029 /* NEON Data processing. */
9030 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
9034 if (disas_neon_data_insn(s
, insn
)) {
9039 if ((insn
& 0x0f100000) == 0x04000000) {
9040 /* NEON load/store. */
9041 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
9045 if (disas_neon_ls_insn(s
, insn
)) {
9050 if ((insn
& 0x0f000e10) == 0x0e000a00) {
9052 if (disas_vfp_insn(s
, insn
)) {
9057 if (((insn
& 0x0f30f000) == 0x0510f000) ||
9058 ((insn
& 0x0f30f010) == 0x0710f000)) {
9059 if ((insn
& (1 << 22)) == 0) {
9061 if (!arm_dc_feature(s
, ARM_FEATURE_V7MP
)) {
9065 /* Otherwise PLD; v5TE+ */
9069 if (((insn
& 0x0f70f000) == 0x0450f000) ||
9070 ((insn
& 0x0f70f010) == 0x0650f000)) {
9072 return; /* PLI; V7 */
9074 if (((insn
& 0x0f700000) == 0x04100000) ||
9075 ((insn
& 0x0f700010) == 0x06100000)) {
9076 if (!arm_dc_feature(s
, ARM_FEATURE_V7MP
)) {
9079 return; /* v7MP: Unallocated memory hint: must NOP */
9082 if ((insn
& 0x0ffffdff) == 0x01010000) {
9085 if (((insn
>> 9) & 1) != !!(s
->be_data
== MO_BE
)) {
9086 gen_helper_setend(cpu_env
);
9087 s
->base
.is_jmp
= DISAS_UPDATE
;
9090 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
9091 switch ((insn
>> 4) & 0xf) {
9099 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
9102 /* We need to break the TB after this insn to execute
9103 * self-modifying code correctly and also to take
9104 * any pending interrupts immediately.
9106 gen_goto_tb(s
, 0, s
->pc
& ~1);
9111 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
9114 gen_srs(s
, (insn
& 0x1f), (insn
>> 23) & 3, insn
& (1 << 21));
9116 } else if ((insn
& 0x0e50ffe0) == 0x08100a00) {
9122 rn
= (insn
>> 16) & 0xf;
9123 addr
= load_reg(s
, rn
);
9124 i
= (insn
>> 23) & 3;
9126 case 0: offset
= -4; break; /* DA */
9127 case 1: offset
= 0; break; /* IA */
9128 case 2: offset
= -8; break; /* DB */
9129 case 3: offset
= 4; break; /* IB */
9133 tcg_gen_addi_i32(addr
, addr
, offset
);
9134 /* Load PC into tmp and CPSR into tmp2. */
9135 tmp
= tcg_temp_new_i32();
9136 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9137 tcg_gen_addi_i32(addr
, addr
, 4);
9138 tmp2
= tcg_temp_new_i32();
9139 gen_aa32_ld32u(s
, tmp2
, addr
, get_mem_index(s
));
9140 if (insn
& (1 << 21)) {
9141 /* Base writeback. */
9143 case 0: offset
= -8; break;
9144 case 1: offset
= 4; break;
9145 case 2: offset
= -4; break;
9146 case 3: offset
= 0; break;
9150 tcg_gen_addi_i32(addr
, addr
, offset
);
9151 store_reg(s
, rn
, addr
);
9153 tcg_temp_free_i32(addr
);
9155 gen_rfe(s
, tmp
, tmp2
);
9157 } else if ((insn
& 0x0e000000) == 0x0a000000) {
9158 /* branch link and change to thumb (blx <offset>) */
9161 val
= (uint32_t)s
->pc
;
9162 tmp
= tcg_temp_new_i32();
9163 tcg_gen_movi_i32(tmp
, val
);
9164 store_reg(s
, 14, tmp
);
9165 /* Sign-extend the 24-bit offset */
9166 offset
= (((int32_t)insn
) << 8) >> 8;
9167 /* offset * 4 + bit24 * 2 + (thumb bit) */
9168 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
9169 /* pipeline offset */
9171 /* protected by ARCH(5); above, near the start of uncond block */
9174 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
9175 if (arm_dc_feature(s
, ARM_FEATURE_IWMMXT
)) {
9176 /* iWMMXt register transfer. */
9177 if (extract32(s
->c15_cpar
, 1, 1)) {
9178 if (!disas_iwmmxt_insn(s
, insn
)) {
9183 } else if ((insn
& 0x0e000a00) == 0x0c000800
9184 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
9185 if (disas_neon_insn_3same_ext(s
, insn
)) {
9189 } else if ((insn
& 0x0f000a00) == 0x0e000800
9190 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
9191 if (disas_neon_insn_2reg_scalar_ext(s
, insn
)) {
9195 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
9196 /* Coprocessor double register transfer. */
9198 } else if ((insn
& 0x0f000010) == 0x0e000010) {
9199 /* Additional coprocessor register transfer. */
9200 } else if ((insn
& 0x0ff10020) == 0x01000000) {
9203 /* cps (privileged) */
9207 if (insn
& (1 << 19)) {
9208 if (insn
& (1 << 8))
9210 if (insn
& (1 << 7))
9212 if (insn
& (1 << 6))
9214 if (insn
& (1 << 18))
9217 if (insn
& (1 << 17)) {
9219 val
|= (insn
& 0x1f);
9222 gen_set_psr_im(s
, mask
, 0, val
);
9229 /* if not always execute, we generate a conditional jump to
9231 arm_skip_unless(s
, cond
);
9233 if ((insn
& 0x0f900000) == 0x03000000) {
9234 if ((insn
& (1 << 21)) == 0) {
9236 rd
= (insn
>> 12) & 0xf;
9237 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
9238 if ((insn
& (1 << 22)) == 0) {
9240 tmp
= tcg_temp_new_i32();
9241 tcg_gen_movi_i32(tmp
, val
);
9244 tmp
= load_reg(s
, rd
);
9245 tcg_gen_ext16u_i32(tmp
, tmp
);
9246 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
9248 store_reg(s
, rd
, tmp
);
9250 if (((insn
>> 12) & 0xf) != 0xf)
9252 if (((insn
>> 16) & 0xf) == 0) {
9253 gen_nop_hint(s
, insn
& 0xff);
9255 /* CPSR = immediate */
9257 shift
= ((insn
>> 8) & 0xf) * 2;
9259 val
= (val
>> shift
) | (val
<< (32 - shift
));
9260 i
= ((insn
& (1 << 22)) != 0);
9261 if (gen_set_psr_im(s
, msr_mask(s
, (insn
>> 16) & 0xf, i
),
9267 } else if ((insn
& 0x0f900000) == 0x01000000
9268 && (insn
& 0x00000090) != 0x00000090) {
9269 /* miscellaneous instructions */
9270 op1
= (insn
>> 21) & 3;
9271 sh
= (insn
>> 4) & 0xf;
9274 case 0x0: /* MSR, MRS */
9275 if (insn
& (1 << 9)) {
9276 /* MSR (banked) and MRS (banked) */
9277 int sysm
= extract32(insn
, 16, 4) |
9278 (extract32(insn
, 8, 1) << 4);
9279 int r
= extract32(insn
, 22, 1);
9283 gen_msr_banked(s
, r
, sysm
, rm
);
9286 int rd
= extract32(insn
, 12, 4);
9288 gen_mrs_banked(s
, r
, sysm
, rd
);
9293 /* MSR, MRS (for PSRs) */
9296 tmp
= load_reg(s
, rm
);
9297 i
= ((op1
& 2) != 0);
9298 if (gen_set_psr(s
, msr_mask(s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
9302 rd
= (insn
>> 12) & 0xf;
9306 tmp
= load_cpu_field(spsr
);
9308 tmp
= tcg_temp_new_i32();
9309 gen_helper_cpsr_read(tmp
, cpu_env
);
9311 store_reg(s
, rd
, tmp
);
9316 /* branch/exchange thumb (bx). */
9318 tmp
= load_reg(s
, rm
);
9320 } else if (op1
== 3) {
9323 rd
= (insn
>> 12) & 0xf;
9324 tmp
= load_reg(s
, rm
);
9325 tcg_gen_clzi_i32(tmp
, tmp
, 32);
9326 store_reg(s
, rd
, tmp
);
9334 /* Trivial implementation equivalent to bx. */
9335 tmp
= load_reg(s
, rm
);
9346 /* branch link/exchange thumb (blx) */
9347 tmp
= load_reg(s
, rm
);
9348 tmp2
= tcg_temp_new_i32();
9349 tcg_gen_movi_i32(tmp2
, s
->pc
);
9350 store_reg(s
, 14, tmp2
);
9356 uint32_t c
= extract32(insn
, 8, 4);
9358 /* Check this CPU supports ARMv8 CRC instructions.
9359 * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED.
9360 * Bits 8, 10 and 11 should be zero.
9362 if (!dc_isar_feature(aa32_crc32
, s
) || op1
== 0x3 || (c
& 0xd) != 0) {
9366 rn
= extract32(insn
, 16, 4);
9367 rd
= extract32(insn
, 12, 4);
9369 tmp
= load_reg(s
, rn
);
9370 tmp2
= load_reg(s
, rm
);
9372 tcg_gen_andi_i32(tmp2
, tmp2
, 0xff);
9373 } else if (op1
== 1) {
9374 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff);
9376 tmp3
= tcg_const_i32(1 << op1
);
9378 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
9380 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
9382 tcg_temp_free_i32(tmp2
);
9383 tcg_temp_free_i32(tmp3
);
9384 store_reg(s
, rd
, tmp
);
9387 case 0x5: /* saturating add/subtract */
9389 rd
= (insn
>> 12) & 0xf;
9390 rn
= (insn
>> 16) & 0xf;
9391 tmp
= load_reg(s
, rm
);
9392 tmp2
= load_reg(s
, rn
);
9394 gen_helper_double_saturate(tmp2
, cpu_env
, tmp2
);
9396 gen_helper_sub_saturate(tmp
, cpu_env
, tmp
, tmp2
);
9398 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
9399 tcg_temp_free_i32(tmp2
);
9400 store_reg(s
, rd
, tmp
);
9402 case 0x6: /* ERET */
9406 if (!arm_dc_feature(s
, ARM_FEATURE_V7VE
)) {
9409 if ((insn
& 0x000fff0f) != 0x0000000e) {
9410 /* UNPREDICTABLE; we choose to UNDEF */
9414 if (s
->current_el
== 2) {
9415 tmp
= load_cpu_field(elr_el
[2]);
9417 tmp
= load_reg(s
, 14);
9419 gen_exception_return(s
, tmp
);
9423 int imm16
= extract32(insn
, 0, 4) | (extract32(insn
, 8, 12) << 4);
9432 gen_exception_bkpt_insn(s
, 4, syn_aa32_bkpt(imm16
, false));
9435 /* Hypervisor call (v7) */
9443 /* Secure monitor call (v6+) */
9451 g_assert_not_reached();
9455 case 0x8: /* signed multiply */
9460 rs
= (insn
>> 8) & 0xf;
9461 rn
= (insn
>> 12) & 0xf;
9462 rd
= (insn
>> 16) & 0xf;
9464 /* (32 * 16) >> 16 */
9465 tmp
= load_reg(s
, rm
);
9466 tmp2
= load_reg(s
, rs
);
9468 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
9471 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
9472 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
9473 tmp
= tcg_temp_new_i32();
9474 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
9475 tcg_temp_free_i64(tmp64
);
9476 if ((sh
& 2) == 0) {
9477 tmp2
= load_reg(s
, rn
);
9478 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9479 tcg_temp_free_i32(tmp2
);
9481 store_reg(s
, rd
, tmp
);
9484 tmp
= load_reg(s
, rm
);
9485 tmp2
= load_reg(s
, rs
);
9486 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
9487 tcg_temp_free_i32(tmp2
);
9489 tmp64
= tcg_temp_new_i64();
9490 tcg_gen_ext_i32_i64(tmp64
, tmp
);
9491 tcg_temp_free_i32(tmp
);
9492 gen_addq(s
, tmp64
, rn
, rd
);
9493 gen_storeq_reg(s
, rn
, rd
, tmp64
);
9494 tcg_temp_free_i64(tmp64
);
9497 tmp2
= load_reg(s
, rn
);
9498 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
9499 tcg_temp_free_i32(tmp2
);
9501 store_reg(s
, rd
, tmp
);
9508 } else if (((insn
& 0x0e000000) == 0 &&
9509 (insn
& 0x00000090) != 0x90) ||
9510 ((insn
& 0x0e000000) == (1 << 25))) {
9511 int set_cc
, logic_cc
, shiftop
;
9513 op1
= (insn
>> 21) & 0xf;
9514 set_cc
= (insn
>> 20) & 1;
9515 logic_cc
= table_logic_cc
[op1
] & set_cc
;
9517 /* data processing instruction */
9518 if (insn
& (1 << 25)) {
9519 /* immediate operand */
9521 shift
= ((insn
>> 8) & 0xf) * 2;
9523 val
= (val
>> shift
) | (val
<< (32 - shift
));
9525 tmp2
= tcg_temp_new_i32();
9526 tcg_gen_movi_i32(tmp2
, val
);
9527 if (logic_cc
&& shift
) {
9528 gen_set_CF_bit31(tmp2
);
9533 tmp2
= load_reg(s
, rm
);
9534 shiftop
= (insn
>> 5) & 3;
9535 if (!(insn
& (1 << 4))) {
9536 shift
= (insn
>> 7) & 0x1f;
9537 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
9539 rs
= (insn
>> 8) & 0xf;
9540 tmp
= load_reg(s
, rs
);
9541 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
9544 if (op1
!= 0x0f && op1
!= 0x0d) {
9545 rn
= (insn
>> 16) & 0xf;
9546 tmp
= load_reg(s
, rn
);
9550 rd
= (insn
>> 12) & 0xf;
9553 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
9557 store_reg_bx(s
, rd
, tmp
);
9560 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
9564 store_reg_bx(s
, rd
, tmp
);
9567 if (set_cc
&& rd
== 15) {
9568 /* SUBS r15, ... is used for exception return. */
9572 gen_sub_CC(tmp
, tmp
, tmp2
);
9573 gen_exception_return(s
, tmp
);
9576 gen_sub_CC(tmp
, tmp
, tmp2
);
9578 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
9580 store_reg_bx(s
, rd
, tmp
);
9585 gen_sub_CC(tmp
, tmp2
, tmp
);
9587 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
9589 store_reg_bx(s
, rd
, tmp
);
9593 gen_add_CC(tmp
, tmp
, tmp2
);
9595 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9597 store_reg_bx(s
, rd
, tmp
);
9601 gen_adc_CC(tmp
, tmp
, tmp2
);
9603 gen_add_carry(tmp
, tmp
, tmp2
);
9605 store_reg_bx(s
, rd
, tmp
);
9609 gen_sbc_CC(tmp
, tmp
, tmp2
);
9611 gen_sub_carry(tmp
, tmp
, tmp2
);
9613 store_reg_bx(s
, rd
, tmp
);
9617 gen_sbc_CC(tmp
, tmp2
, tmp
);
9619 gen_sub_carry(tmp
, tmp2
, tmp
);
9621 store_reg_bx(s
, rd
, tmp
);
9625 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
9628 tcg_temp_free_i32(tmp
);
9632 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
9635 tcg_temp_free_i32(tmp
);
9639 gen_sub_CC(tmp
, tmp
, tmp2
);
9641 tcg_temp_free_i32(tmp
);
9645 gen_add_CC(tmp
, tmp
, tmp2
);
9647 tcg_temp_free_i32(tmp
);
9650 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
9654 store_reg_bx(s
, rd
, tmp
);
9657 if (logic_cc
&& rd
== 15) {
9658 /* MOVS r15, ... is used for exception return. */
9662 gen_exception_return(s
, tmp2
);
9667 store_reg_bx(s
, rd
, tmp2
);
9671 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
9675 store_reg_bx(s
, rd
, tmp
);
9679 tcg_gen_not_i32(tmp2
, tmp2
);
9683 store_reg_bx(s
, rd
, tmp2
);
9686 if (op1
!= 0x0f && op1
!= 0x0d) {
9687 tcg_temp_free_i32(tmp2
);
9690 /* other instructions */
9691 op1
= (insn
>> 24) & 0xf;
9695 /* multiplies, extra load/stores */
9696 sh
= (insn
>> 5) & 3;
9699 rd
= (insn
>> 16) & 0xf;
9700 rn
= (insn
>> 12) & 0xf;
9701 rs
= (insn
>> 8) & 0xf;
9703 op1
= (insn
>> 20) & 0xf;
9705 case 0: case 1: case 2: case 3: case 6:
9707 tmp
= load_reg(s
, rs
);
9708 tmp2
= load_reg(s
, rm
);
9709 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
9710 tcg_temp_free_i32(tmp2
);
9711 if (insn
& (1 << 22)) {
9712 /* Subtract (mls) */
9714 tmp2
= load_reg(s
, rn
);
9715 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
9716 tcg_temp_free_i32(tmp2
);
9717 } else if (insn
& (1 << 21)) {
9719 tmp2
= load_reg(s
, rn
);
9720 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
9721 tcg_temp_free_i32(tmp2
);
9723 if (insn
& (1 << 20))
9725 store_reg(s
, rd
, tmp
);
9728 /* 64 bit mul double accumulate (UMAAL) */
9730 tmp
= load_reg(s
, rs
);
9731 tmp2
= load_reg(s
, rm
);
9732 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
9733 gen_addq_lo(s
, tmp64
, rn
);
9734 gen_addq_lo(s
, tmp64
, rd
);
9735 gen_storeq_reg(s
, rn
, rd
, tmp64
);
9736 tcg_temp_free_i64(tmp64
);
9738 case 8: case 9: case 10: case 11:
9739 case 12: case 13: case 14: case 15:
9740 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
9741 tmp
= load_reg(s
, rs
);
9742 tmp2
= load_reg(s
, rm
);
9743 if (insn
& (1 << 22)) {
9744 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
9746 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
9748 if (insn
& (1 << 21)) { /* mult accumulate */
9749 TCGv_i32 al
= load_reg(s
, rn
);
9750 TCGv_i32 ah
= load_reg(s
, rd
);
9751 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, al
, ah
);
9752 tcg_temp_free_i32(al
);
9753 tcg_temp_free_i32(ah
);
9755 if (insn
& (1 << 20)) {
9756 gen_logicq_cc(tmp
, tmp2
);
9758 store_reg(s
, rn
, tmp
);
9759 store_reg(s
, rd
, tmp2
);
9765 rn
= (insn
>> 16) & 0xf;
9766 rd
= (insn
>> 12) & 0xf;
9767 if (insn
& (1 << 23)) {
9768 /* load/store exclusive */
9769 int op2
= (insn
>> 8) & 3;
9770 op1
= (insn
>> 21) & 0x3;
9773 case 0: /* lda/stl */
9779 case 1: /* reserved */
9781 case 2: /* ldaex/stlex */
9784 case 3: /* ldrex/strex */
9793 addr
= tcg_temp_local_new_i32();
9794 load_reg_var(s
, addr
, rn
);
9796 /* Since the emulation does not have barriers,
9797 the acquire/release semantics need no special
9800 if (insn
& (1 << 20)) {
9801 tmp
= tcg_temp_new_i32();
9804 gen_aa32_ld32u_iss(s
, tmp
, addr
,
9809 gen_aa32_ld8u_iss(s
, tmp
, addr
,
9814 gen_aa32_ld16u_iss(s
, tmp
, addr
,
9821 store_reg(s
, rd
, tmp
);
9824 tmp
= load_reg(s
, rm
);
9827 gen_aa32_st32_iss(s
, tmp
, addr
,
9832 gen_aa32_st8_iss(s
, tmp
, addr
,
9837 gen_aa32_st16_iss(s
, tmp
, addr
,
9844 tcg_temp_free_i32(tmp
);
9846 } else if (insn
& (1 << 20)) {
9849 gen_load_exclusive(s
, rd
, 15, addr
, 2);
9851 case 1: /* ldrexd */
9852 gen_load_exclusive(s
, rd
, rd
+ 1, addr
, 3);
9854 case 2: /* ldrexb */
9855 gen_load_exclusive(s
, rd
, 15, addr
, 0);
9857 case 3: /* ldrexh */
9858 gen_load_exclusive(s
, rd
, 15, addr
, 1);
9867 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 2);
9869 case 1: /* strexd */
9870 gen_store_exclusive(s
, rd
, rm
, rm
+ 1, addr
, 3);
9872 case 2: /* strexb */
9873 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 0);
9875 case 3: /* strexh */
9876 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 1);
9882 tcg_temp_free_i32(addr
);
9883 } else if ((insn
& 0x00300f00) == 0) {
9884 /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
9889 TCGMemOp opc
= s
->be_data
;
9893 if (insn
& (1 << 22)) {
9896 opc
|= MO_UL
| MO_ALIGN
;
9899 addr
= load_reg(s
, rn
);
9900 taddr
= gen_aa32_addr(s
, addr
, opc
);
9901 tcg_temp_free_i32(addr
);
9903 tmp
= load_reg(s
, rm
);
9904 tcg_gen_atomic_xchg_i32(tmp
, taddr
, tmp
,
9905 get_mem_index(s
), opc
);
9906 tcg_temp_free(taddr
);
9907 store_reg(s
, rd
, tmp
);
9914 bool load
= insn
& (1 << 20);
9915 bool wbit
= insn
& (1 << 21);
9916 bool pbit
= insn
& (1 << 24);
9917 bool doubleword
= false;
9920 /* Misc load/store */
9921 rn
= (insn
>> 16) & 0xf;
9922 rd
= (insn
>> 12) & 0xf;
9924 /* ISS not valid if writeback */
9925 issinfo
= (pbit
& !wbit
) ? rd
: ISSInvalid
;
9927 if (!load
&& (sh
& 2)) {
9931 /* UNPREDICTABLE; we choose to UNDEF */
9934 load
= (sh
& 1) == 0;
9938 addr
= load_reg(s
, rn
);
9940 gen_add_datah_offset(s
, insn
, 0, addr
);
9947 tmp
= load_reg(s
, rd
);
9948 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9949 tcg_temp_free_i32(tmp
);
9950 tcg_gen_addi_i32(addr
, addr
, 4);
9951 tmp
= load_reg(s
, rd
+ 1);
9952 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
9953 tcg_temp_free_i32(tmp
);
9956 tmp
= tcg_temp_new_i32();
9957 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9958 store_reg(s
, rd
, tmp
);
9959 tcg_gen_addi_i32(addr
, addr
, 4);
9960 tmp
= tcg_temp_new_i32();
9961 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
9964 address_offset
= -4;
9967 tmp
= tcg_temp_new_i32();
9970 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
),
9974 gen_aa32_ld8s_iss(s
, tmp
, addr
, get_mem_index(s
),
9979 gen_aa32_ld16s_iss(s
, tmp
, addr
, get_mem_index(s
),
9985 tmp
= load_reg(s
, rd
);
9986 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), issinfo
);
9987 tcg_temp_free_i32(tmp
);
9989 /* Perform base writeback before the loaded value to
9990 ensure correct behavior with overlapping index registers.
9991 ldrd with base writeback is undefined if the
9992 destination and index registers overlap. */
9994 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
9995 store_reg(s
, rn
, addr
);
9998 tcg_gen_addi_i32(addr
, addr
, address_offset
);
9999 store_reg(s
, rn
, addr
);
10001 tcg_temp_free_i32(addr
);
10004 /* Complete the load. */
10005 store_reg(s
, rd
, tmp
);
10014 if (insn
& (1 << 4)) {
10016 /* Armv6 Media instructions. */
10018 rn
= (insn
>> 16) & 0xf;
10019 rd
= (insn
>> 12) & 0xf;
10020 rs
= (insn
>> 8) & 0xf;
10021 switch ((insn
>> 23) & 3) {
10022 case 0: /* Parallel add/subtract. */
10023 op1
= (insn
>> 20) & 7;
10024 tmp
= load_reg(s
, rn
);
10025 tmp2
= load_reg(s
, rm
);
10026 sh
= (insn
>> 5) & 7;
10027 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
10029 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
10030 tcg_temp_free_i32(tmp2
);
10031 store_reg(s
, rd
, tmp
);
10034 if ((insn
& 0x00700020) == 0) {
10035 /* Halfword pack. */
10036 tmp
= load_reg(s
, rn
);
10037 tmp2
= load_reg(s
, rm
);
10038 shift
= (insn
>> 7) & 0x1f;
10039 if (insn
& (1 << 6)) {
10043 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
10044 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
10045 tcg_gen_ext16u_i32(tmp2
, tmp2
);
10049 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
10050 tcg_gen_ext16u_i32(tmp
, tmp
);
10051 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
10053 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
10054 tcg_temp_free_i32(tmp2
);
10055 store_reg(s
, rd
, tmp
);
10056 } else if ((insn
& 0x00200020) == 0x00200000) {
10058 tmp
= load_reg(s
, rm
);
10059 shift
= (insn
>> 7) & 0x1f;
10060 if (insn
& (1 << 6)) {
10063 tcg_gen_sari_i32(tmp
, tmp
, shift
);
10065 tcg_gen_shli_i32(tmp
, tmp
, shift
);
10067 sh
= (insn
>> 16) & 0x1f;
10068 tmp2
= tcg_const_i32(sh
);
10069 if (insn
& (1 << 22))
10070 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
10072 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
10073 tcg_temp_free_i32(tmp2
);
10074 store_reg(s
, rd
, tmp
);
10075 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
10077 tmp
= load_reg(s
, rm
);
10078 sh
= (insn
>> 16) & 0x1f;
10079 tmp2
= tcg_const_i32(sh
);
10080 if (insn
& (1 << 22))
10081 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
10083 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
10084 tcg_temp_free_i32(tmp2
);
10085 store_reg(s
, rd
, tmp
);
10086 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
10087 /* Select bytes. */
10088 tmp
= load_reg(s
, rn
);
10089 tmp2
= load_reg(s
, rm
);
10090 tmp3
= tcg_temp_new_i32();
10091 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
10092 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
10093 tcg_temp_free_i32(tmp3
);
10094 tcg_temp_free_i32(tmp2
);
10095 store_reg(s
, rd
, tmp
);
10096 } else if ((insn
& 0x000003e0) == 0x00000060) {
10097 tmp
= load_reg(s
, rm
);
10098 shift
= (insn
>> 10) & 3;
10099 /* ??? In many cases it's not necessary to do a
10100 rotate, a shift is sufficient. */
10102 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
10103 op1
= (insn
>> 20) & 7;
10105 case 0: gen_sxtb16(tmp
); break;
10106 case 2: gen_sxtb(tmp
); break;
10107 case 3: gen_sxth(tmp
); break;
10108 case 4: gen_uxtb16(tmp
); break;
10109 case 6: gen_uxtb(tmp
); break;
10110 case 7: gen_uxth(tmp
); break;
10111 default: goto illegal_op
;
10114 tmp2
= load_reg(s
, rn
);
10115 if ((op1
& 3) == 0) {
10116 gen_add16(tmp
, tmp2
);
10118 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10119 tcg_temp_free_i32(tmp2
);
10122 store_reg(s
, rd
, tmp
);
10123 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
10125 tmp
= load_reg(s
, rm
);
10126 if (insn
& (1 << 22)) {
10127 if (insn
& (1 << 7)) {
10131 gen_helper_rbit(tmp
, tmp
);
10134 if (insn
& (1 << 7))
10137 tcg_gen_bswap32_i32(tmp
, tmp
);
10139 store_reg(s
, rd
, tmp
);
10144 case 2: /* Multiplies (Type 3). */
10145 switch ((insn
>> 20) & 0x7) {
10147 if (((insn
>> 6) ^ (insn
>> 7)) & 1) {
10148 /* op2 not 00x or 11x : UNDEF */
10151 /* Signed multiply most significant [accumulate].
10152 (SMMUL, SMMLA, SMMLS) */
10153 tmp
= load_reg(s
, rm
);
10154 tmp2
= load_reg(s
, rs
);
10155 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
10158 tmp
= load_reg(s
, rd
);
10159 if (insn
& (1 << 6)) {
10160 tmp64
= gen_subq_msw(tmp64
, tmp
);
10162 tmp64
= gen_addq_msw(tmp64
, tmp
);
10165 if (insn
& (1 << 5)) {
10166 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
10168 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
10169 tmp
= tcg_temp_new_i32();
10170 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
10171 tcg_temp_free_i64(tmp64
);
10172 store_reg(s
, rn
, tmp
);
10176 /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */
10177 if (insn
& (1 << 7)) {
10180 tmp
= load_reg(s
, rm
);
10181 tmp2
= load_reg(s
, rs
);
10182 if (insn
& (1 << 5))
10183 gen_swap_half(tmp2
);
10184 gen_smul_dual(tmp
, tmp2
);
10185 if (insn
& (1 << 22)) {
10186 /* smlald, smlsld */
10189 tmp64
= tcg_temp_new_i64();
10190 tmp64_2
= tcg_temp_new_i64();
10191 tcg_gen_ext_i32_i64(tmp64
, tmp
);
10192 tcg_gen_ext_i32_i64(tmp64_2
, tmp2
);
10193 tcg_temp_free_i32(tmp
);
10194 tcg_temp_free_i32(tmp2
);
10195 if (insn
& (1 << 6)) {
10196 tcg_gen_sub_i64(tmp64
, tmp64
, tmp64_2
);
10198 tcg_gen_add_i64(tmp64
, tmp64
, tmp64_2
);
10200 tcg_temp_free_i64(tmp64_2
);
10201 gen_addq(s
, tmp64
, rd
, rn
);
10202 gen_storeq_reg(s
, rd
, rn
, tmp64
);
10203 tcg_temp_free_i64(tmp64
);
10205 /* smuad, smusd, smlad, smlsd */
10206 if (insn
& (1 << 6)) {
10207 /* This subtraction cannot overflow. */
10208 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
10210 /* This addition cannot overflow 32 bits;
10211 * however it may overflow considered as a
10212 * signed operation, in which case we must set
10215 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10217 tcg_temp_free_i32(tmp2
);
10220 tmp2
= load_reg(s
, rd
);
10221 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
10222 tcg_temp_free_i32(tmp2
);
10224 store_reg(s
, rn
, tmp
);
10230 if (!dc_isar_feature(arm_div
, s
)) {
10233 if (((insn
>> 5) & 7) || (rd
!= 15)) {
10236 tmp
= load_reg(s
, rm
);
10237 tmp2
= load_reg(s
, rs
);
10238 if (insn
& (1 << 21)) {
10239 gen_helper_udiv(tmp
, tmp
, tmp2
);
10241 gen_helper_sdiv(tmp
, tmp
, tmp2
);
10243 tcg_temp_free_i32(tmp2
);
10244 store_reg(s
, rn
, tmp
);
10251 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
10253 case 0: /* Unsigned sum of absolute differences. */
10255 tmp
= load_reg(s
, rm
);
10256 tmp2
= load_reg(s
, rs
);
10257 gen_helper_usad8(tmp
, tmp
, tmp2
);
10258 tcg_temp_free_i32(tmp2
);
10260 tmp2
= load_reg(s
, rd
);
10261 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
10262 tcg_temp_free_i32(tmp2
);
10264 store_reg(s
, rn
, tmp
);
10266 case 0x20: case 0x24: case 0x28: case 0x2c:
10267 /* Bitfield insert/clear. */
10269 shift
= (insn
>> 7) & 0x1f;
10270 i
= (insn
>> 16) & 0x1f;
10272 /* UNPREDICTABLE; we choose to UNDEF */
10277 tmp
= tcg_temp_new_i32();
10278 tcg_gen_movi_i32(tmp
, 0);
10280 tmp
= load_reg(s
, rm
);
10283 tmp2
= load_reg(s
, rd
);
10284 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, i
);
10285 tcg_temp_free_i32(tmp2
);
10287 store_reg(s
, rd
, tmp
);
10289 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
10290 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
10292 tmp
= load_reg(s
, rm
);
10293 shift
= (insn
>> 7) & 0x1f;
10294 i
= ((insn
>> 16) & 0x1f) + 1;
10295 if (shift
+ i
> 32)
10299 tcg_gen_extract_i32(tmp
, tmp
, shift
, i
);
10301 tcg_gen_sextract_i32(tmp
, tmp
, shift
, i
);
10304 store_reg(s
, rd
, tmp
);
10314 /* Check for undefined extension instructions
10315 * per the ARM Bible IE:
10316 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
10318 sh
= (0xf << 20) | (0xf << 4);
10319 if (op1
== 0x7 && ((insn
& sh
) == sh
))
10323 /* load/store byte/word */
10324 rn
= (insn
>> 16) & 0xf;
10325 rd
= (insn
>> 12) & 0xf;
10326 tmp2
= load_reg(s
, rn
);
10327 if ((insn
& 0x01200000) == 0x00200000) {
10329 i
= get_a32_user_mem_index(s
);
10331 i
= get_mem_index(s
);
10333 if (insn
& (1 << 24))
10334 gen_add_data_offset(s
, insn
, tmp2
);
10335 if (insn
& (1 << 20)) {
10337 tmp
= tcg_temp_new_i32();
10338 if (insn
& (1 << 22)) {
10339 gen_aa32_ld8u_iss(s
, tmp
, tmp2
, i
, rd
);
10341 gen_aa32_ld32u_iss(s
, tmp
, tmp2
, i
, rd
);
10345 tmp
= load_reg(s
, rd
);
10346 if (insn
& (1 << 22)) {
10347 gen_aa32_st8_iss(s
, tmp
, tmp2
, i
, rd
);
10349 gen_aa32_st32_iss(s
, tmp
, tmp2
, i
, rd
);
10351 tcg_temp_free_i32(tmp
);
10353 if (!(insn
& (1 << 24))) {
10354 gen_add_data_offset(s
, insn
, tmp2
);
10355 store_reg(s
, rn
, tmp2
);
10356 } else if (insn
& (1 << 21)) {
10357 store_reg(s
, rn
, tmp2
);
10359 tcg_temp_free_i32(tmp2
);
10361 if (insn
& (1 << 20)) {
10362 /* Complete the load. */
10363 store_reg_from_load(s
, rd
, tmp
);
10369 int j
, n
, loaded_base
;
10370 bool exc_return
= false;
10371 bool is_load
= extract32(insn
, 20, 1);
10373 TCGv_i32 loaded_var
;
10374 /* load/store multiple words */
10375 /* XXX: store correct base if write back */
10376 if (insn
& (1 << 22)) {
10377 /* LDM (user), LDM (exception return) and STM (user) */
10379 goto illegal_op
; /* only usable in supervisor mode */
10381 if (is_load
&& extract32(insn
, 15, 1)) {
10387 rn
= (insn
>> 16) & 0xf;
10388 addr
= load_reg(s
, rn
);
10390 /* compute total size */
10394 for(i
=0;i
<16;i
++) {
10395 if (insn
& (1 << i
))
10398 /* XXX: test invalid n == 0 case ? */
10399 if (insn
& (1 << 23)) {
10400 if (insn
& (1 << 24)) {
10401 /* pre increment */
10402 tcg_gen_addi_i32(addr
, addr
, 4);
10404 /* post increment */
10407 if (insn
& (1 << 24)) {
10408 /* pre decrement */
10409 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
10411 /* post decrement */
10413 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
10417 for(i
=0;i
<16;i
++) {
10418 if (insn
& (1 << i
)) {
10421 tmp
= tcg_temp_new_i32();
10422 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
10424 tmp2
= tcg_const_i32(i
);
10425 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
10426 tcg_temp_free_i32(tmp2
);
10427 tcg_temp_free_i32(tmp
);
10428 } else if (i
== rn
) {
10431 } else if (rn
== 15 && exc_return
) {
10432 store_pc_exc_ret(s
, tmp
);
10434 store_reg_from_load(s
, i
, tmp
);
10439 /* special case: r15 = PC + 8 */
10440 val
= (long)s
->pc
+ 4;
10441 tmp
= tcg_temp_new_i32();
10442 tcg_gen_movi_i32(tmp
, val
);
10444 tmp
= tcg_temp_new_i32();
10445 tmp2
= tcg_const_i32(i
);
10446 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
10447 tcg_temp_free_i32(tmp2
);
10449 tmp
= load_reg(s
, i
);
10451 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
10452 tcg_temp_free_i32(tmp
);
10455 /* no need to add after the last transfer */
10457 tcg_gen_addi_i32(addr
, addr
, 4);
10460 if (insn
& (1 << 21)) {
10462 if (insn
& (1 << 23)) {
10463 if (insn
& (1 << 24)) {
10464 /* pre increment */
10466 /* post increment */
10467 tcg_gen_addi_i32(addr
, addr
, 4);
10470 if (insn
& (1 << 24)) {
10471 /* pre decrement */
10473 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
10475 /* post decrement */
10476 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
10479 store_reg(s
, rn
, addr
);
10481 tcg_temp_free_i32(addr
);
10484 store_reg(s
, rn
, loaded_var
);
10487 /* Restore CPSR from SPSR. */
10488 tmp
= load_cpu_field(spsr
);
10489 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
10492 gen_helper_cpsr_write_eret(cpu_env
, tmp
);
10493 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
10496 tcg_temp_free_i32(tmp
);
10497 /* Must exit loop to check un-masked IRQs */
10498 s
->base
.is_jmp
= DISAS_EXIT
;
10507 /* branch (and link) */
10508 val
= (int32_t)s
->pc
;
10509 if (insn
& (1 << 24)) {
10510 tmp
= tcg_temp_new_i32();
10511 tcg_gen_movi_i32(tmp
, val
);
10512 store_reg(s
, 14, tmp
);
10514 offset
= sextract32(insn
<< 2, 0, 26);
10522 if (((insn
>> 8) & 0xe) == 10) {
10524 if (disas_vfp_insn(s
, insn
)) {
10527 } else if (disas_coproc_insn(s
, insn
)) {
10534 gen_set_pc_im(s
, s
->pc
);
10535 s
->svc_imm
= extract32(insn
, 0, 24);
10536 s
->base
.is_jmp
= DISAS_SWI
;
10540 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
10541 default_exception_el(s
));
10547 static bool thumb_insn_is_16bit(DisasContext
*s
, uint32_t insn
)
10549 /* Return true if this is a 16 bit instruction. We must be precise
10550 * about this (matching the decode). We assume that s->pc still
10551 * points to the first 16 bits of the insn.
10553 if ((insn
>> 11) < 0x1d) {
10554 /* Definitely a 16-bit instruction */
10558 /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the
10559 * first half of a 32-bit Thumb insn. Thumb-1 cores might
10560 * end up actually treating this as two 16-bit insns, though,
10561 * if it's half of a bl/blx pair that might span a page boundary.
10563 if (arm_dc_feature(s
, ARM_FEATURE_THUMB2
) ||
10564 arm_dc_feature(s
, ARM_FEATURE_M
)) {
10565 /* Thumb2 cores (including all M profile ones) always treat
10566 * 32-bit insns as 32-bit.
10571 if ((insn
>> 11) == 0x1e && s
->pc
- s
->page_start
< TARGET_PAGE_SIZE
- 3) {
10572 /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
10573 * is not on the next page; we merge this into a 32-bit
10578 /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF);
10579 * 0b1111_1xxx_xxxx_xxxx : BL suffix;
10580 * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page
10581 * -- handle as single 16 bit insn
10586 /* Return true if this is a Thumb-2 logical op. */
10588 thumb2_logic_op(int op
)
10593 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
10594 then set condition code flags based on the result of the operation.
10595 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
10596 to the high bit of T1.
10597 Returns zero if the opcode is valid. */
10600 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
,
10601 TCGv_i32 t0
, TCGv_i32 t1
)
10608 tcg_gen_and_i32(t0
, t0
, t1
);
10612 tcg_gen_andc_i32(t0
, t0
, t1
);
10616 tcg_gen_or_i32(t0
, t0
, t1
);
10620 tcg_gen_orc_i32(t0
, t0
, t1
);
10624 tcg_gen_xor_i32(t0
, t0
, t1
);
10629 gen_add_CC(t0
, t0
, t1
);
10631 tcg_gen_add_i32(t0
, t0
, t1
);
10635 gen_adc_CC(t0
, t0
, t1
);
10641 gen_sbc_CC(t0
, t0
, t1
);
10643 gen_sub_carry(t0
, t0
, t1
);
10648 gen_sub_CC(t0
, t0
, t1
);
10650 tcg_gen_sub_i32(t0
, t0
, t1
);
10654 gen_sub_CC(t0
, t1
, t0
);
10656 tcg_gen_sub_i32(t0
, t1
, t0
);
10658 default: /* 5, 6, 7, 9, 12, 15. */
10664 gen_set_CF_bit31(t1
);
10669 /* Translate a 32-bit thumb instruction. */
10670 static void disas_thumb2_insn(DisasContext
*s
, uint32_t insn
)
10672 uint32_t imm
, shift
, offset
;
10673 uint32_t rd
, rn
, rm
, rs
;
10685 * ARMv6-M supports a limited subset of Thumb2 instructions.
10686 * Other Thumb1 architectures allow only 32-bit
10687 * combined BL/BLX prefix and suffix.
10689 if (arm_dc_feature(s
, ARM_FEATURE_M
) &&
10690 !arm_dc_feature(s
, ARM_FEATURE_V7
)) {
10692 bool found
= false;
10693 static const uint32_t armv6m_insn
[] = {0xf3808000 /* msr */,
10694 0xf3b08040 /* dsb */,
10695 0xf3b08050 /* dmb */,
10696 0xf3b08060 /* isb */,
10697 0xf3e08000 /* mrs */,
10698 0xf000d000 /* bl */};
10699 static const uint32_t armv6m_mask
[] = {0xffe0d000,
10706 for (i
= 0; i
< ARRAY_SIZE(armv6m_insn
); i
++) {
10707 if ((insn
& armv6m_mask
[i
]) == armv6m_insn
[i
]) {
10715 } else if ((insn
& 0xf800e800) != 0xf000e800) {
10719 rn
= (insn
>> 16) & 0xf;
10720 rs
= (insn
>> 12) & 0xf;
10721 rd
= (insn
>> 8) & 0xf;
10723 switch ((insn
>> 25) & 0xf) {
10724 case 0: case 1: case 2: case 3:
10725 /* 16-bit instructions. Should never happen. */
10728 if (insn
& (1 << 22)) {
10729 /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx
10730 * - load/store doubleword, load/store exclusive, ldacq/strel,
10731 * table branch, TT.
10733 if (insn
== 0xe97fe97f && arm_dc_feature(s
, ARM_FEATURE_M
) &&
10734 arm_dc_feature(s
, ARM_FEATURE_V8
)) {
10735 /* 0b1110_1001_0111_1111_1110_1001_0111_111
10737 * The bulk of the behaviour for this instruction is implemented
10738 * in v7m_handle_execute_nsc(), which deals with the insn when
10739 * it is executed by a CPU in non-secure state from memory
10740 * which is Secure & NonSecure-Callable.
10741 * Here we only need to handle the remaining cases:
10742 * * in NS memory (including the "security extension not
10743 * implemented" case) : NOP
10744 * * in S memory but CPU already secure (clear IT bits)
10745 * We know that the attribute for the memory this insn is
10746 * in must match the current CPU state, because otherwise
10747 * get_phys_addr_pmsav8 would have generated an exception.
10749 if (s
->v8m_secure
) {
10750 /* Like the IT insn, we don't need to generate any code */
10751 s
->condexec_cond
= 0;
10752 s
->condexec_mask
= 0;
10754 } else if (insn
& 0x01200000) {
10755 /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
10756 * - load/store dual (post-indexed)
10757 * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx
10758 * - load/store dual (literal and immediate)
10759 * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx
10760 * - load/store dual (pre-indexed)
10762 bool wback
= extract32(insn
, 21, 1);
10765 if (insn
& (1 << 21)) {
10766 /* UNPREDICTABLE */
10769 addr
= tcg_temp_new_i32();
10770 tcg_gen_movi_i32(addr
, s
->pc
& ~3);
10772 addr
= load_reg(s
, rn
);
10774 offset
= (insn
& 0xff) * 4;
10775 if ((insn
& (1 << 23)) == 0) {
10779 if (s
->v8m_stackcheck
&& rn
== 13 && wback
) {
10781 * Here 'addr' is the current SP; if offset is +ve we're
10782 * moving SP up, else down. It is UNKNOWN whether the limit
10783 * check triggers when SP starts below the limit and ends
10784 * up above it; check whichever of the current and final
10785 * SP is lower, so QEMU will trigger in that situation.
10787 if ((int32_t)offset
< 0) {
10788 TCGv_i32 newsp
= tcg_temp_new_i32();
10790 tcg_gen_addi_i32(newsp
, addr
, offset
);
10791 gen_helper_v8m_stackcheck(cpu_env
, newsp
);
10792 tcg_temp_free_i32(newsp
);
10794 gen_helper_v8m_stackcheck(cpu_env
, addr
);
10798 if (insn
& (1 << 24)) {
10799 tcg_gen_addi_i32(addr
, addr
, offset
);
10802 if (insn
& (1 << 20)) {
10804 tmp
= tcg_temp_new_i32();
10805 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
10806 store_reg(s
, rs
, tmp
);
10807 tcg_gen_addi_i32(addr
, addr
, 4);
10808 tmp
= tcg_temp_new_i32();
10809 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
10810 store_reg(s
, rd
, tmp
);
10813 tmp
= load_reg(s
, rs
);
10814 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
10815 tcg_temp_free_i32(tmp
);
10816 tcg_gen_addi_i32(addr
, addr
, 4);
10817 tmp
= load_reg(s
, rd
);
10818 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
10819 tcg_temp_free_i32(tmp
);
10822 /* Base writeback. */
10823 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
10824 store_reg(s
, rn
, addr
);
10826 tcg_temp_free_i32(addr
);
10828 } else if ((insn
& (1 << 23)) == 0) {
10829 /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx
10830 * - load/store exclusive word
10834 if (!(insn
& (1 << 20)) &&
10835 arm_dc_feature(s
, ARM_FEATURE_M
) &&
10836 arm_dc_feature(s
, ARM_FEATURE_V8
)) {
10837 /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx
10840 bool alt
= insn
& (1 << 7);
10841 TCGv_i32 addr
, op
, ttresp
;
10843 if ((insn
& 0x3f) || rd
== 13 || rd
== 15 || rn
== 15) {
10844 /* we UNDEF for these UNPREDICTABLE cases */
10848 if (alt
&& !s
->v8m_secure
) {
10852 addr
= load_reg(s
, rn
);
10853 op
= tcg_const_i32(extract32(insn
, 6, 2));
10854 ttresp
= tcg_temp_new_i32();
10855 gen_helper_v7m_tt(ttresp
, cpu_env
, addr
, op
);
10856 tcg_temp_free_i32(addr
);
10857 tcg_temp_free_i32(op
);
10858 store_reg(s
, rd
, ttresp
);
10863 addr
= tcg_temp_local_new_i32();
10864 load_reg_var(s
, addr
, rn
);
10865 tcg_gen_addi_i32(addr
, addr
, (insn
& 0xff) << 2);
10866 if (insn
& (1 << 20)) {
10867 gen_load_exclusive(s
, rs
, 15, addr
, 2);
10869 gen_store_exclusive(s
, rd
, rs
, 15, addr
, 2);
10871 tcg_temp_free_i32(addr
);
10872 } else if ((insn
& (7 << 5)) == 0) {
10873 /* Table Branch. */
10875 addr
= tcg_temp_new_i32();
10876 tcg_gen_movi_i32(addr
, s
->pc
);
10878 addr
= load_reg(s
, rn
);
10880 tmp
= load_reg(s
, rm
);
10881 tcg_gen_add_i32(addr
, addr
, tmp
);
10882 if (insn
& (1 << 4)) {
10884 tcg_gen_add_i32(addr
, addr
, tmp
);
10885 tcg_temp_free_i32(tmp
);
10886 tmp
= tcg_temp_new_i32();
10887 gen_aa32_ld16u(s
, tmp
, addr
, get_mem_index(s
));
10889 tcg_temp_free_i32(tmp
);
10890 tmp
= tcg_temp_new_i32();
10891 gen_aa32_ld8u(s
, tmp
, addr
, get_mem_index(s
));
10893 tcg_temp_free_i32(addr
);
10894 tcg_gen_shli_i32(tmp
, tmp
, 1);
10895 tcg_gen_addi_i32(tmp
, tmp
, s
->pc
);
10896 store_reg(s
, 15, tmp
);
10898 int op2
= (insn
>> 6) & 0x3;
10899 op
= (insn
>> 4) & 0x3;
10904 /* Load/store exclusive byte/halfword/doubleword */
10911 /* Load-acquire/store-release */
10917 /* Load-acquire/store-release exclusive */
10921 addr
= tcg_temp_local_new_i32();
10922 load_reg_var(s
, addr
, rn
);
10924 if (insn
& (1 << 20)) {
10925 tmp
= tcg_temp_new_i32();
10928 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
),
10932 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
),
10936 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
),
10942 store_reg(s
, rs
, tmp
);
10944 tmp
= load_reg(s
, rs
);
10947 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
),
10951 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
),
10955 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
),
10961 tcg_temp_free_i32(tmp
);
10963 } else if (insn
& (1 << 20)) {
10964 gen_load_exclusive(s
, rs
, rd
, addr
, op
);
10966 gen_store_exclusive(s
, rm
, rs
, rd
, addr
, op
);
10968 tcg_temp_free_i32(addr
);
10971 /* Load/store multiple, RFE, SRS. */
10972 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
10973 /* RFE, SRS: not available in user mode or on M profile */
10974 if (IS_USER(s
) || arm_dc_feature(s
, ARM_FEATURE_M
)) {
10977 if (insn
& (1 << 20)) {
10979 addr
= load_reg(s
, rn
);
10980 if ((insn
& (1 << 24)) == 0)
10981 tcg_gen_addi_i32(addr
, addr
, -8);
10982 /* Load PC into tmp and CPSR into tmp2. */
10983 tmp
= tcg_temp_new_i32();
10984 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
10985 tcg_gen_addi_i32(addr
, addr
, 4);
10986 tmp2
= tcg_temp_new_i32();
10987 gen_aa32_ld32u(s
, tmp2
, addr
, get_mem_index(s
));
10988 if (insn
& (1 << 21)) {
10989 /* Base writeback. */
10990 if (insn
& (1 << 24)) {
10991 tcg_gen_addi_i32(addr
, addr
, 4);
10993 tcg_gen_addi_i32(addr
, addr
, -4);
10995 store_reg(s
, rn
, addr
);
10997 tcg_temp_free_i32(addr
);
10999 gen_rfe(s
, tmp
, tmp2
);
11002 gen_srs(s
, (insn
& 0x1f), (insn
& (1 << 24)) ? 1 : 2,
11006 int i
, loaded_base
= 0;
11007 TCGv_i32 loaded_var
;
11008 bool wback
= extract32(insn
, 21, 1);
11009 /* Load/store multiple. */
11010 addr
= load_reg(s
, rn
);
11012 for (i
= 0; i
< 16; i
++) {
11013 if (insn
& (1 << i
))
11017 if (insn
& (1 << 24)) {
11018 tcg_gen_addi_i32(addr
, addr
, -offset
);
11021 if (s
->v8m_stackcheck
&& rn
== 13 && wback
) {
11023 * If the writeback is incrementing SP rather than
11024 * decrementing it, and the initial SP is below the
11025 * stack limit but the final written-back SP would
11026 * be above, then then we must not perform any memory
11027 * accesses, but it is IMPDEF whether we generate
11028 * an exception. We choose to do so in this case.
11029 * At this point 'addr' is the lowest address, so
11030 * either the original SP (if incrementing) or our
11031 * final SP (if decrementing), so that's what we check.
11033 gen_helper_v8m_stackcheck(cpu_env
, addr
);
11037 for (i
= 0; i
< 16; i
++) {
11038 if ((insn
& (1 << i
)) == 0)
11040 if (insn
& (1 << 20)) {
11042 tmp
= tcg_temp_new_i32();
11043 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
11045 gen_bx_excret(s
, tmp
);
11046 } else if (i
== rn
) {
11050 store_reg(s
, i
, tmp
);
11054 tmp
= load_reg(s
, i
);
11055 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
11056 tcg_temp_free_i32(tmp
);
11058 tcg_gen_addi_i32(addr
, addr
, 4);
11061 store_reg(s
, rn
, loaded_var
);
11064 /* Base register writeback. */
11065 if (insn
& (1 << 24)) {
11066 tcg_gen_addi_i32(addr
, addr
, -offset
);
11068 /* Fault if writeback register is in register list. */
11069 if (insn
& (1 << rn
))
11071 store_reg(s
, rn
, addr
);
11073 tcg_temp_free_i32(addr
);
11080 op
= (insn
>> 21) & 0xf;
11082 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11085 /* Halfword pack. */
11086 tmp
= load_reg(s
, rn
);
11087 tmp2
= load_reg(s
, rm
);
11088 shift
= ((insn
>> 10) & 0x1c) | ((insn
>> 6) & 0x3);
11089 if (insn
& (1 << 5)) {
11093 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
11094 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
11095 tcg_gen_ext16u_i32(tmp2
, tmp2
);
11099 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
11100 tcg_gen_ext16u_i32(tmp
, tmp
);
11101 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
11103 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
11104 tcg_temp_free_i32(tmp2
);
11105 store_reg(s
, rd
, tmp
);
11107 /* Data processing register constant shift. */
11109 tmp
= tcg_temp_new_i32();
11110 tcg_gen_movi_i32(tmp
, 0);
11112 tmp
= load_reg(s
, rn
);
11114 tmp2
= load_reg(s
, rm
);
11116 shiftop
= (insn
>> 4) & 3;
11117 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
11118 conds
= (insn
& (1 << 20)) != 0;
11119 logic_cc
= (conds
&& thumb2_logic_op(op
));
11120 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
11121 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
11123 tcg_temp_free_i32(tmp2
);
11125 ((op
== 2 && rn
== 15) ||
11126 (op
== 8 && rn
== 13) ||
11127 (op
== 13 && rn
== 13))) {
11128 /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */
11129 store_sp_checked(s
, tmp
);
11130 } else if (rd
!= 15) {
11131 store_reg(s
, rd
, tmp
);
11133 tcg_temp_free_i32(tmp
);
11137 case 13: /* Misc data processing. */
11138 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
11139 if (op
< 4 && (insn
& 0xf000) != 0xf000)
11142 case 0: /* Register controlled shift. */
11143 tmp
= load_reg(s
, rn
);
11144 tmp2
= load_reg(s
, rm
);
11145 if ((insn
& 0x70) != 0)
11148 * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx:
11149 * - MOV, MOVS (register-shifted register), flagsetting
11151 op
= (insn
>> 21) & 3;
11152 logic_cc
= (insn
& (1 << 20)) != 0;
11153 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
11156 store_reg(s
, rd
, tmp
);
11158 case 1: /* Sign/zero extend. */
11159 op
= (insn
>> 20) & 7;
11161 case 0: /* SXTAH, SXTH */
11162 case 1: /* UXTAH, UXTH */
11163 case 4: /* SXTAB, SXTB */
11164 case 5: /* UXTAB, UXTB */
11166 case 2: /* SXTAB16, SXTB16 */
11167 case 3: /* UXTAB16, UXTB16 */
11168 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11176 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11180 tmp
= load_reg(s
, rm
);
11181 shift
= (insn
>> 4) & 3;
11182 /* ??? In many cases it's not necessary to do a
11183 rotate, a shift is sufficient. */
11185 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
11186 op
= (insn
>> 20) & 7;
11188 case 0: gen_sxth(tmp
); break;
11189 case 1: gen_uxth(tmp
); break;
11190 case 2: gen_sxtb16(tmp
); break;
11191 case 3: gen_uxtb16(tmp
); break;
11192 case 4: gen_sxtb(tmp
); break;
11193 case 5: gen_uxtb(tmp
); break;
11195 g_assert_not_reached();
11198 tmp2
= load_reg(s
, rn
);
11199 if ((op
>> 1) == 1) {
11200 gen_add16(tmp
, tmp2
);
11202 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
11203 tcg_temp_free_i32(tmp2
);
11206 store_reg(s
, rd
, tmp
);
11208 case 2: /* SIMD add/subtract. */
11209 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11212 op
= (insn
>> 20) & 7;
11213 shift
= (insn
>> 4) & 7;
11214 if ((op
& 3) == 3 || (shift
& 3) == 3)
11216 tmp
= load_reg(s
, rn
);
11217 tmp2
= load_reg(s
, rm
);
11218 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
11219 tcg_temp_free_i32(tmp2
);
11220 store_reg(s
, rd
, tmp
);
11222 case 3: /* Other data processing. */
11223 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
11225 /* Saturating add/subtract. */
11226 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11229 tmp
= load_reg(s
, rn
);
11230 tmp2
= load_reg(s
, rm
);
11232 gen_helper_double_saturate(tmp
, cpu_env
, tmp
);
11234 gen_helper_sub_saturate(tmp
, cpu_env
, tmp2
, tmp
);
11236 gen_helper_add_saturate(tmp
, cpu_env
, tmp
, tmp2
);
11237 tcg_temp_free_i32(tmp2
);
11240 case 0x0a: /* rbit */
11241 case 0x08: /* rev */
11242 case 0x09: /* rev16 */
11243 case 0x0b: /* revsh */
11244 case 0x18: /* clz */
11246 case 0x10: /* sel */
11247 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11251 case 0x20: /* crc32/crc32c */
11257 if (!dc_isar_feature(aa32_crc32
, s
)) {
11264 tmp
= load_reg(s
, rn
);
11266 case 0x0a: /* rbit */
11267 gen_helper_rbit(tmp
, tmp
);
11269 case 0x08: /* rev */
11270 tcg_gen_bswap32_i32(tmp
, tmp
);
11272 case 0x09: /* rev16 */
11275 case 0x0b: /* revsh */
11278 case 0x10: /* sel */
11279 tmp2
= load_reg(s
, rm
);
11280 tmp3
= tcg_temp_new_i32();
11281 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUARMState
, GE
));
11282 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
11283 tcg_temp_free_i32(tmp3
);
11284 tcg_temp_free_i32(tmp2
);
11286 case 0x18: /* clz */
11287 tcg_gen_clzi_i32(tmp
, tmp
, 32);
11297 uint32_t sz
= op
& 0x3;
11298 uint32_t c
= op
& 0x8;
11300 tmp2
= load_reg(s
, rm
);
11302 tcg_gen_andi_i32(tmp2
, tmp2
, 0xff);
11303 } else if (sz
== 1) {
11304 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff);
11306 tmp3
= tcg_const_i32(1 << sz
);
11308 gen_helper_crc32c(tmp
, tmp
, tmp2
, tmp3
);
11310 gen_helper_crc32(tmp
, tmp
, tmp2
, tmp3
);
11312 tcg_temp_free_i32(tmp2
);
11313 tcg_temp_free_i32(tmp3
);
11317 g_assert_not_reached();
11320 store_reg(s
, rd
, tmp
);
11322 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
11323 switch ((insn
>> 20) & 7) {
11324 case 0: /* 32 x 32 -> 32 */
11325 case 7: /* Unsigned sum of absolute differences. */
11327 case 1: /* 16 x 16 -> 32 */
11328 case 2: /* Dual multiply add. */
11329 case 3: /* 32 * 16 -> 32msb */
11330 case 4: /* Dual multiply subtract. */
11331 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
11332 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11337 op
= (insn
>> 4) & 0xf;
11338 tmp
= load_reg(s
, rn
);
11339 tmp2
= load_reg(s
, rm
);
11340 switch ((insn
>> 20) & 7) {
11341 case 0: /* 32 x 32 -> 32 */
11342 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
11343 tcg_temp_free_i32(tmp2
);
11345 tmp2
= load_reg(s
, rs
);
11347 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
11349 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
11350 tcg_temp_free_i32(tmp2
);
11353 case 1: /* 16 x 16 -> 32 */
11354 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
11355 tcg_temp_free_i32(tmp2
);
11357 tmp2
= load_reg(s
, rs
);
11358 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
11359 tcg_temp_free_i32(tmp2
);
11362 case 2: /* Dual multiply add. */
11363 case 4: /* Dual multiply subtract. */
11365 gen_swap_half(tmp2
);
11366 gen_smul_dual(tmp
, tmp2
);
11367 if (insn
& (1 << 22)) {
11368 /* This subtraction cannot overflow. */
11369 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
11371 /* This addition cannot overflow 32 bits;
11372 * however it may overflow considered as a signed
11373 * operation, in which case we must set the Q flag.
11375 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
11377 tcg_temp_free_i32(tmp2
);
11380 tmp2
= load_reg(s
, rs
);
11381 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
11382 tcg_temp_free_i32(tmp2
);
11385 case 3: /* 32 * 16 -> 32msb */
11387 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
11390 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
11391 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
11392 tmp
= tcg_temp_new_i32();
11393 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
11394 tcg_temp_free_i64(tmp64
);
11397 tmp2
= load_reg(s
, rs
);
11398 gen_helper_add_setq(tmp
, cpu_env
, tmp
, tmp2
);
11399 tcg_temp_free_i32(tmp2
);
11402 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
11403 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
11405 tmp
= load_reg(s
, rs
);
11406 if (insn
& (1 << 20)) {
11407 tmp64
= gen_addq_msw(tmp64
, tmp
);
11409 tmp64
= gen_subq_msw(tmp64
, tmp
);
11412 if (insn
& (1 << 4)) {
11413 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
11415 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
11416 tmp
= tcg_temp_new_i32();
11417 tcg_gen_extrl_i64_i32(tmp
, tmp64
);
11418 tcg_temp_free_i64(tmp64
);
11420 case 7: /* Unsigned sum of absolute differences. */
11421 gen_helper_usad8(tmp
, tmp
, tmp2
);
11422 tcg_temp_free_i32(tmp2
);
11424 tmp2
= load_reg(s
, rs
);
11425 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
11426 tcg_temp_free_i32(tmp2
);
11430 store_reg(s
, rd
, tmp
);
11432 case 6: case 7: /* 64-bit multiply, Divide. */
11433 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
11434 tmp
= load_reg(s
, rn
);
11435 tmp2
= load_reg(s
, rm
);
11436 if ((op
& 0x50) == 0x10) {
11438 if (!dc_isar_feature(thumb_div
, s
)) {
11442 gen_helper_udiv(tmp
, tmp
, tmp2
);
11444 gen_helper_sdiv(tmp
, tmp
, tmp2
);
11445 tcg_temp_free_i32(tmp2
);
11446 store_reg(s
, rd
, tmp
);
11447 } else if ((op
& 0xe) == 0xc) {
11448 /* Dual multiply accumulate long. */
11449 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11450 tcg_temp_free_i32(tmp
);
11451 tcg_temp_free_i32(tmp2
);
11455 gen_swap_half(tmp2
);
11456 gen_smul_dual(tmp
, tmp2
);
11458 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
11460 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
11462 tcg_temp_free_i32(tmp2
);
11464 tmp64
= tcg_temp_new_i64();
11465 tcg_gen_ext_i32_i64(tmp64
, tmp
);
11466 tcg_temp_free_i32(tmp
);
11467 gen_addq(s
, tmp64
, rs
, rd
);
11468 gen_storeq_reg(s
, rs
, rd
, tmp64
);
11469 tcg_temp_free_i64(tmp64
);
11472 /* Unsigned 64-bit multiply */
11473 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
11477 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11478 tcg_temp_free_i32(tmp2
);
11479 tcg_temp_free_i32(tmp
);
11482 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
11483 tcg_temp_free_i32(tmp2
);
11484 tmp64
= tcg_temp_new_i64();
11485 tcg_gen_ext_i32_i64(tmp64
, tmp
);
11486 tcg_temp_free_i32(tmp
);
11488 /* Signed 64-bit multiply */
11489 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
11494 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11495 tcg_temp_free_i64(tmp64
);
11498 gen_addq_lo(s
, tmp64
, rs
);
11499 gen_addq_lo(s
, tmp64
, rd
);
11500 } else if (op
& 0x40) {
11501 /* 64-bit accumulate. */
11502 gen_addq(s
, tmp64
, rs
, rd
);
11504 gen_storeq_reg(s
, rs
, rd
, tmp64
);
11505 tcg_temp_free_i64(tmp64
);
11510 case 6: case 7: case 14: case 15:
11512 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11513 /* We don't currently implement M profile FP support,
11514 * so this entire space should give a NOCP fault, with
11515 * the exception of the v8M VLLDM and VLSTM insns, which
11516 * must be NOPs in Secure state and UNDEF in Nonsecure state.
11518 if (arm_dc_feature(s
, ARM_FEATURE_V8
) &&
11519 (insn
& 0xffa00f00) == 0xec200a00) {
11520 /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx
11522 * We choose to UNDEF if the RAZ bits are non-zero.
11524 if (!s
->v8m_secure
|| (insn
& 0x0040f0ff)) {
11527 /* Just NOP since FP support is not implemented */
11530 /* All other insns: NOCP */
11531 gen_exception_insn(s
, 4, EXCP_NOCP
, syn_uncategorized(),
11532 default_exception_el(s
));
11535 if ((insn
& 0xfe000a00) == 0xfc000800
11536 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
11537 /* The Thumb2 and ARM encodings are identical. */
11538 if (disas_neon_insn_3same_ext(s
, insn
)) {
11541 } else if ((insn
& 0xff000a00) == 0xfe000800
11542 && arm_dc_feature(s
, ARM_FEATURE_V8
)) {
11543 /* The Thumb2 and ARM encodings are identical. */
11544 if (disas_neon_insn_2reg_scalar_ext(s
, insn
)) {
11547 } else if (((insn
>> 24) & 3) == 3) {
11548 /* Translate into the equivalent ARM encoding. */
11549 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
11550 if (disas_neon_data_insn(s
, insn
)) {
11553 } else if (((insn
>> 8) & 0xe) == 10) {
11554 if (disas_vfp_insn(s
, insn
)) {
11558 if (insn
& (1 << 28))
11560 if (disas_coproc_insn(s
, insn
)) {
11565 case 8: case 9: case 10: case 11:
11566 if (insn
& (1 << 15)) {
11567 /* Branches, misc control. */
11568 if (insn
& 0x5000) {
11569 /* Unconditional branch. */
11570 /* signextend(hw1[10:0]) -> offset[:12]. */
11571 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
11572 /* hw1[10:0] -> offset[11:1]. */
11573 offset
|= (insn
& 0x7ff) << 1;
11574 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
11575 offset[24:22] already have the same value because of the
11576 sign extension above. */
11577 offset
^= ((~insn
) & (1 << 13)) << 10;
11578 offset
^= ((~insn
) & (1 << 11)) << 11;
11580 if (insn
& (1 << 14)) {
11581 /* Branch and link. */
11582 tcg_gen_movi_i32(cpu_R
[14], s
->pc
| 1);
11586 if (insn
& (1 << 12)) {
11588 gen_jmp(s
, offset
);
11591 offset
&= ~(uint32_t)2;
11592 /* thumb2 bx, no need to check */
11593 gen_bx_im(s
, offset
);
11595 } else if (((insn
>> 23) & 7) == 7) {
11597 if (insn
& (1 << 13))
11600 if (insn
& (1 << 26)) {
11601 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11604 if (!(insn
& (1 << 20))) {
11605 /* Hypervisor call (v7) */
11606 int imm16
= extract32(insn
, 16, 4) << 12
11607 | extract32(insn
, 0, 12);
11614 /* Secure monitor call (v6+) */
11622 op
= (insn
>> 20) & 7;
11624 case 0: /* msr cpsr. */
11625 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11626 tmp
= load_reg(s
, rn
);
11627 /* the constant is the mask and SYSm fields */
11628 addr
= tcg_const_i32(insn
& 0xfff);
11629 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
11630 tcg_temp_free_i32(addr
);
11631 tcg_temp_free_i32(tmp
);
11636 case 1: /* msr spsr. */
11637 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11641 if (extract32(insn
, 5, 1)) {
11643 int sysm
= extract32(insn
, 8, 4) |
11644 (extract32(insn
, 4, 1) << 4);
11647 gen_msr_banked(s
, r
, sysm
, rm
);
11651 /* MSR (for PSRs) */
11652 tmp
= load_reg(s
, rn
);
11654 msr_mask(s
, (insn
>> 8) & 0xf, op
== 1),
11658 case 2: /* cps, nop-hint. */
11659 if (((insn
>> 8) & 7) == 0) {
11660 gen_nop_hint(s
, insn
& 0xff);
11662 /* Implemented as NOP in user mode. */
11667 if (insn
& (1 << 10)) {
11668 if (insn
& (1 << 7))
11670 if (insn
& (1 << 6))
11672 if (insn
& (1 << 5))
11674 if (insn
& (1 << 9))
11675 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
11677 if (insn
& (1 << 8)) {
11679 imm
|= (insn
& 0x1f);
11682 gen_set_psr_im(s
, offset
, 0, imm
);
11685 case 3: /* Special control operations. */
11686 if (!arm_dc_feature(s
, ARM_FEATURE_V7
) &&
11687 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
11690 op
= (insn
>> 4) & 0xf;
11692 case 2: /* clrex */
11697 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
11700 /* We need to break the TB after this insn
11701 * to execute self-modifying code correctly
11702 * and also to take any pending interrupts
11705 gen_goto_tb(s
, 0, s
->pc
& ~1);
11712 /* Trivial implementation equivalent to bx.
11713 * This instruction doesn't exist at all for M-profile.
11715 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11718 tmp
= load_reg(s
, rn
);
11721 case 5: /* Exception return. */
11725 if (rn
!= 14 || rd
!= 15) {
11728 if (s
->current_el
== 2) {
11729 /* ERET from Hyp uses ELR_Hyp, not LR */
11733 tmp
= load_cpu_field(elr_el
[2]);
11735 tmp
= load_reg(s
, rn
);
11736 tcg_gen_subi_i32(tmp
, tmp
, insn
& 0xff);
11738 gen_exception_return(s
, tmp
);
11741 if (extract32(insn
, 5, 1) &&
11742 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
11744 int sysm
= extract32(insn
, 16, 4) |
11745 (extract32(insn
, 4, 1) << 4);
11747 gen_mrs_banked(s
, 0, sysm
, rd
);
11751 if (extract32(insn
, 16, 4) != 0xf) {
11754 if (!arm_dc_feature(s
, ARM_FEATURE_M
) &&
11755 extract32(insn
, 0, 8) != 0) {
11760 tmp
= tcg_temp_new_i32();
11761 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
11762 addr
= tcg_const_i32(insn
& 0xff);
11763 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
11764 tcg_temp_free_i32(addr
);
11766 gen_helper_cpsr_read(tmp
, cpu_env
);
11768 store_reg(s
, rd
, tmp
);
11771 if (extract32(insn
, 5, 1) &&
11772 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
11774 int sysm
= extract32(insn
, 16, 4) |
11775 (extract32(insn
, 4, 1) << 4);
11777 gen_mrs_banked(s
, 1, sysm
, rd
);
11782 /* Not accessible in user mode. */
11783 if (IS_USER(s
) || arm_dc_feature(s
, ARM_FEATURE_M
)) {
11787 if (extract32(insn
, 16, 4) != 0xf ||
11788 extract32(insn
, 0, 8) != 0) {
11792 tmp
= load_cpu_field(spsr
);
11793 store_reg(s
, rd
, tmp
);
11798 /* Conditional branch. */
11799 op
= (insn
>> 22) & 0xf;
11800 /* Generate a conditional jump to next instruction. */
11801 arm_skip_unless(s
, op
);
11803 /* offset[11:1] = insn[10:0] */
11804 offset
= (insn
& 0x7ff) << 1;
11805 /* offset[17:12] = insn[21:16]. */
11806 offset
|= (insn
& 0x003f0000) >> 4;
11807 /* offset[31:20] = insn[26]. */
11808 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
11809 /* offset[18] = insn[13]. */
11810 offset
|= (insn
& (1 << 13)) << 5;
11811 /* offset[19] = insn[11]. */
11812 offset
|= (insn
& (1 << 11)) << 8;
11814 /* jump to the offset */
11815 gen_jmp(s
, s
->pc
+ offset
);
11819 * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx
11820 * - Data-processing (modified immediate, plain binary immediate)
11822 if (insn
& (1 << 25)) {
11824 * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx
11825 * - Data-processing (plain binary immediate)
11827 if (insn
& (1 << 24)) {
11828 if (insn
& (1 << 20))
11830 /* Bitfield/Saturate. */
11831 op
= (insn
>> 21) & 7;
11833 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
11835 tmp
= tcg_temp_new_i32();
11836 tcg_gen_movi_i32(tmp
, 0);
11838 tmp
= load_reg(s
, rn
);
11841 case 2: /* Signed bitfield extract. */
11843 if (shift
+ imm
> 32)
11846 tcg_gen_sextract_i32(tmp
, tmp
, shift
, imm
);
11849 case 6: /* Unsigned bitfield extract. */
11851 if (shift
+ imm
> 32)
11854 tcg_gen_extract_i32(tmp
, tmp
, shift
, imm
);
11857 case 3: /* Bitfield insert/clear. */
11860 imm
= imm
+ 1 - shift
;
11862 tmp2
= load_reg(s
, rd
);
11863 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, shift
, imm
);
11864 tcg_temp_free_i32(tmp2
);
11869 default: /* Saturate. */
11872 tcg_gen_sari_i32(tmp
, tmp
, shift
);
11874 tcg_gen_shli_i32(tmp
, tmp
, shift
);
11876 tmp2
= tcg_const_i32(imm
);
11879 if ((op
& 1) && shift
== 0) {
11880 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11881 tcg_temp_free_i32(tmp
);
11882 tcg_temp_free_i32(tmp2
);
11885 gen_helper_usat16(tmp
, cpu_env
, tmp
, tmp2
);
11887 gen_helper_usat(tmp
, cpu_env
, tmp
, tmp2
);
11891 if ((op
& 1) && shift
== 0) {
11892 if (!arm_dc_feature(s
, ARM_FEATURE_THUMB_DSP
)) {
11893 tcg_temp_free_i32(tmp
);
11894 tcg_temp_free_i32(tmp2
);
11897 gen_helper_ssat16(tmp
, cpu_env
, tmp
, tmp2
);
11899 gen_helper_ssat(tmp
, cpu_env
, tmp
, tmp2
);
11902 tcg_temp_free_i32(tmp2
);
11905 store_reg(s
, rd
, tmp
);
11907 imm
= ((insn
& 0x04000000) >> 15)
11908 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
11909 if (insn
& (1 << 22)) {
11910 /* 16-bit immediate. */
11911 imm
|= (insn
>> 4) & 0xf000;
11912 if (insn
& (1 << 23)) {
11914 tmp
= load_reg(s
, rd
);
11915 tcg_gen_ext16u_i32(tmp
, tmp
);
11916 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
11919 tmp
= tcg_temp_new_i32();
11920 tcg_gen_movi_i32(tmp
, imm
);
11922 store_reg(s
, rd
, tmp
);
11924 /* Add/sub 12-bit immediate. */
11926 offset
= s
->pc
& ~(uint32_t)3;
11927 if (insn
& (1 << 23))
11931 tmp
= tcg_temp_new_i32();
11932 tcg_gen_movi_i32(tmp
, offset
);
11933 store_reg(s
, rd
, tmp
);
11935 tmp
= load_reg(s
, rn
);
11936 if (insn
& (1 << 23))
11937 tcg_gen_subi_i32(tmp
, tmp
, imm
);
11939 tcg_gen_addi_i32(tmp
, tmp
, imm
);
11940 if (rn
== 13 && rd
== 13) {
11941 /* ADD SP, SP, imm or SUB SP, SP, imm */
11942 store_sp_checked(s
, tmp
);
11944 store_reg(s
, rd
, tmp
);
11951 * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx
11952 * - Data-processing (modified immediate)
11954 int shifter_out
= 0;
11955 /* modified 12-bit immediate. */
11956 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
11957 imm
= (insn
& 0xff);
11960 /* Nothing to do. */
11962 case 1: /* 00XY00XY */
11965 case 2: /* XY00XY00 */
11969 case 3: /* XYXYXYXY */
11973 default: /* Rotated constant. */
11974 shift
= (shift
<< 1) | (imm
>> 7);
11976 imm
= imm
<< (32 - shift
);
11980 tmp2
= tcg_temp_new_i32();
11981 tcg_gen_movi_i32(tmp2
, imm
);
11982 rn
= (insn
>> 16) & 0xf;
11984 tmp
= tcg_temp_new_i32();
11985 tcg_gen_movi_i32(tmp
, 0);
11987 tmp
= load_reg(s
, rn
);
11989 op
= (insn
>> 21) & 0xf;
11990 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
11991 shifter_out
, tmp
, tmp2
))
11993 tcg_temp_free_i32(tmp2
);
11994 rd
= (insn
>> 8) & 0xf;
11995 if (rd
== 13 && rn
== 13
11996 && (op
== 8 || op
== 13)) {
11997 /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */
11998 store_sp_checked(s
, tmp
);
11999 } else if (rd
!= 15) {
12000 store_reg(s
, rd
, tmp
);
12002 tcg_temp_free_i32(tmp
);
12007 case 12: /* Load/store single data item. */
12014 if ((insn
& 0x01100000) == 0x01000000) {
12015 if (disas_neon_ls_insn(s
, insn
)) {
12020 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
12022 if (!(insn
& (1 << 20))) {
12026 /* Byte or halfword load space with dest == r15 : memory hints.
12027 * Catch them early so we don't emit pointless addressing code.
12028 * This space is a mix of:
12029 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
12030 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
12032 * unallocated hints, which must be treated as NOPs
12033 * UNPREDICTABLE space, which we NOP or UNDEF depending on
12034 * which is easiest for the decoding logic
12035 * Some space which must UNDEF
12037 int op1
= (insn
>> 23) & 3;
12038 int op2
= (insn
>> 6) & 0x3f;
12043 /* UNPREDICTABLE, unallocated hint or
12044 * PLD/PLDW/PLI (literal)
12049 return; /* PLD/PLDW/PLI or unallocated hint */
12051 if ((op2
== 0) || ((op2
& 0x3c) == 0x30)) {
12052 return; /* PLD/PLDW/PLI or unallocated hint */
12054 /* UNDEF space, or an UNPREDICTABLE */
12058 memidx
= get_mem_index(s
);
12060 addr
= tcg_temp_new_i32();
12062 /* s->pc has already been incremented by 4. */
12063 imm
= s
->pc
& 0xfffffffc;
12064 if (insn
& (1 << 23))
12065 imm
+= insn
& 0xfff;
12067 imm
-= insn
& 0xfff;
12068 tcg_gen_movi_i32(addr
, imm
);
12070 addr
= load_reg(s
, rn
);
12071 if (insn
& (1 << 23)) {
12072 /* Positive offset. */
12073 imm
= insn
& 0xfff;
12074 tcg_gen_addi_i32(addr
, addr
, imm
);
12077 switch ((insn
>> 8) & 0xf) {
12078 case 0x0: /* Shifted Register. */
12079 shift
= (insn
>> 4) & 0xf;
12081 tcg_temp_free_i32(addr
);
12084 tmp
= load_reg(s
, rm
);
12086 tcg_gen_shli_i32(tmp
, tmp
, shift
);
12087 tcg_gen_add_i32(addr
, addr
, tmp
);
12088 tcg_temp_free_i32(tmp
);
12090 case 0xc: /* Negative offset. */
12091 tcg_gen_addi_i32(addr
, addr
, -imm
);
12093 case 0xe: /* User privilege. */
12094 tcg_gen_addi_i32(addr
, addr
, imm
);
12095 memidx
= get_a32_user_mem_index(s
);
12097 case 0x9: /* Post-decrement. */
12099 /* Fall through. */
12100 case 0xb: /* Post-increment. */
12104 case 0xd: /* Pre-decrement. */
12106 /* Fall through. */
12107 case 0xf: /* Pre-increment. */
12111 tcg_temp_free_i32(addr
);
12117 issinfo
= writeback
? ISSInvalid
: rs
;
12119 if (s
->v8m_stackcheck
&& rn
== 13 && writeback
) {
12121 * Stackcheck. Here we know 'addr' is the current SP;
12122 * if imm is +ve we're moving SP up, else down. It is
12123 * UNKNOWN whether the limit check triggers when SP starts
12124 * below the limit and ends up above it; we chose to do so.
12126 if ((int32_t)imm
< 0) {
12127 TCGv_i32 newsp
= tcg_temp_new_i32();
12129 tcg_gen_addi_i32(newsp
, addr
, imm
);
12130 gen_helper_v8m_stackcheck(cpu_env
, newsp
);
12131 tcg_temp_free_i32(newsp
);
12133 gen_helper_v8m_stackcheck(cpu_env
, addr
);
12137 if (writeback
&& !postinc
) {
12138 tcg_gen_addi_i32(addr
, addr
, imm
);
12141 if (insn
& (1 << 20)) {
12143 tmp
= tcg_temp_new_i32();
12146 gen_aa32_ld8u_iss(s
, tmp
, addr
, memidx
, issinfo
);
12149 gen_aa32_ld8s_iss(s
, tmp
, addr
, memidx
, issinfo
);
12152 gen_aa32_ld16u_iss(s
, tmp
, addr
, memidx
, issinfo
);
12155 gen_aa32_ld16s_iss(s
, tmp
, addr
, memidx
, issinfo
);
12158 gen_aa32_ld32u_iss(s
, tmp
, addr
, memidx
, issinfo
);
12161 tcg_temp_free_i32(tmp
);
12162 tcg_temp_free_i32(addr
);
12166 gen_bx_excret(s
, tmp
);
12168 store_reg(s
, rs
, tmp
);
12172 tmp
= load_reg(s
, rs
);
12175 gen_aa32_st8_iss(s
, tmp
, addr
, memidx
, issinfo
);
12178 gen_aa32_st16_iss(s
, tmp
, addr
, memidx
, issinfo
);
12181 gen_aa32_st32_iss(s
, tmp
, addr
, memidx
, issinfo
);
12184 tcg_temp_free_i32(tmp
);
12185 tcg_temp_free_i32(addr
);
12188 tcg_temp_free_i32(tmp
);
12191 tcg_gen_addi_i32(addr
, addr
, imm
);
12193 store_reg(s
, rn
, addr
);
12195 tcg_temp_free_i32(addr
);
12204 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
12205 default_exception_el(s
));
12208 static void disas_thumb_insn(DisasContext
*s
, uint32_t insn
)
12210 uint32_t val
, op
, rm
, rn
, rd
, shift
, cond
;
12217 switch (insn
>> 12) {
12221 op
= (insn
>> 11) & 3;
12224 * 0b0001_1xxx_xxxx_xxxx
12225 * - Add, subtract (three low registers)
12226 * - Add, subtract (two low registers and immediate)
12228 rn
= (insn
>> 3) & 7;
12229 tmp
= load_reg(s
, rn
);
12230 if (insn
& (1 << 10)) {
12232 tmp2
= tcg_temp_new_i32();
12233 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
12236 rm
= (insn
>> 6) & 7;
12237 tmp2
= load_reg(s
, rm
);
12239 if (insn
& (1 << 9)) {
12240 if (s
->condexec_mask
)
12241 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
12243 gen_sub_CC(tmp
, tmp
, tmp2
);
12245 if (s
->condexec_mask
)
12246 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
12248 gen_add_CC(tmp
, tmp
, tmp2
);
12250 tcg_temp_free_i32(tmp2
);
12251 store_reg(s
, rd
, tmp
);
12253 /* shift immediate */
12254 rm
= (insn
>> 3) & 7;
12255 shift
= (insn
>> 6) & 0x1f;
12256 tmp
= load_reg(s
, rm
);
12257 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
12258 if (!s
->condexec_mask
)
12260 store_reg(s
, rd
, tmp
);
12265 * 0b001x_xxxx_xxxx_xxxx
12266 * - Add, subtract, compare, move (one low register and immediate)
12268 op
= (insn
>> 11) & 3;
12269 rd
= (insn
>> 8) & 0x7;
12270 if (op
== 0) { /* mov */
12271 tmp
= tcg_temp_new_i32();
12272 tcg_gen_movi_i32(tmp
, insn
& 0xff);
12273 if (!s
->condexec_mask
)
12275 store_reg(s
, rd
, tmp
);
12277 tmp
= load_reg(s
, rd
);
12278 tmp2
= tcg_temp_new_i32();
12279 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
12282 gen_sub_CC(tmp
, tmp
, tmp2
);
12283 tcg_temp_free_i32(tmp
);
12284 tcg_temp_free_i32(tmp2
);
12287 if (s
->condexec_mask
)
12288 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
12290 gen_add_CC(tmp
, tmp
, tmp2
);
12291 tcg_temp_free_i32(tmp2
);
12292 store_reg(s
, rd
, tmp
);
12295 if (s
->condexec_mask
)
12296 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
12298 gen_sub_CC(tmp
, tmp
, tmp2
);
12299 tcg_temp_free_i32(tmp2
);
12300 store_reg(s
, rd
, tmp
);
12306 if (insn
& (1 << 11)) {
12307 rd
= (insn
>> 8) & 7;
12308 /* load pc-relative. Bit 1 of PC is ignored. */
12309 val
= s
->pc
+ 2 + ((insn
& 0xff) * 4);
12310 val
&= ~(uint32_t)2;
12311 addr
= tcg_temp_new_i32();
12312 tcg_gen_movi_i32(addr
, val
);
12313 tmp
= tcg_temp_new_i32();
12314 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
),
12316 tcg_temp_free_i32(addr
);
12317 store_reg(s
, rd
, tmp
);
12320 if (insn
& (1 << 10)) {
12321 /* 0b0100_01xx_xxxx_xxxx
12322 * - data processing extended, branch and exchange
12324 rd
= (insn
& 7) | ((insn
>> 4) & 8);
12325 rm
= (insn
>> 3) & 0xf;
12326 op
= (insn
>> 8) & 3;
12329 tmp
= load_reg(s
, rd
);
12330 tmp2
= load_reg(s
, rm
);
12331 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
12332 tcg_temp_free_i32(tmp2
);
12334 /* ADD SP, SP, reg */
12335 store_sp_checked(s
, tmp
);
12337 store_reg(s
, rd
, tmp
);
12341 tmp
= load_reg(s
, rd
);
12342 tmp2
= load_reg(s
, rm
);
12343 gen_sub_CC(tmp
, tmp
, tmp2
);
12344 tcg_temp_free_i32(tmp2
);
12345 tcg_temp_free_i32(tmp
);
12347 case 2: /* mov/cpy */
12348 tmp
= load_reg(s
, rm
);
12351 store_sp_checked(s
, tmp
);
12353 store_reg(s
, rd
, tmp
);
12358 /* 0b0100_0111_xxxx_xxxx
12359 * - branch [and link] exchange thumb register
12361 bool link
= insn
& (1 << 7);
12370 /* BXNS/BLXNS: only exists for v8M with the
12371 * security extensions, and always UNDEF if NonSecure.
12372 * We don't implement these in the user-only mode
12373 * either (in theory you can use them from Secure User
12374 * mode but they are too tied in to system emulation.)
12376 if (!s
->v8m_secure
|| IS_USER_ONLY
) {
12387 tmp
= load_reg(s
, rm
);
12389 val
= (uint32_t)s
->pc
| 1;
12390 tmp2
= tcg_temp_new_i32();
12391 tcg_gen_movi_i32(tmp2
, val
);
12392 store_reg(s
, 14, tmp2
);
12395 /* Only BX works as exception-return, not BLX */
12396 gen_bx_excret(s
, tmp
);
12405 * 0b0100_00xx_xxxx_xxxx
12406 * - Data-processing (two low registers)
12409 rm
= (insn
>> 3) & 7;
12410 op
= (insn
>> 6) & 0xf;
12411 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
12412 /* the shift/rotate ops want the operands backwards */
12421 if (op
== 9) { /* neg */
12422 tmp
= tcg_temp_new_i32();
12423 tcg_gen_movi_i32(tmp
, 0);
12424 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
12425 tmp
= load_reg(s
, rd
);
12430 tmp2
= load_reg(s
, rm
);
12432 case 0x0: /* and */
12433 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
12434 if (!s
->condexec_mask
)
12437 case 0x1: /* eor */
12438 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
12439 if (!s
->condexec_mask
)
12442 case 0x2: /* lsl */
12443 if (s
->condexec_mask
) {
12444 gen_shl(tmp2
, tmp2
, tmp
);
12446 gen_helper_shl_cc(tmp2
, cpu_env
, tmp2
, tmp
);
12447 gen_logic_CC(tmp2
);
12450 case 0x3: /* lsr */
12451 if (s
->condexec_mask
) {
12452 gen_shr(tmp2
, tmp2
, tmp
);
12454 gen_helper_shr_cc(tmp2
, cpu_env
, tmp2
, tmp
);
12455 gen_logic_CC(tmp2
);
12458 case 0x4: /* asr */
12459 if (s
->condexec_mask
) {
12460 gen_sar(tmp2
, tmp2
, tmp
);
12462 gen_helper_sar_cc(tmp2
, cpu_env
, tmp2
, tmp
);
12463 gen_logic_CC(tmp2
);
12466 case 0x5: /* adc */
12467 if (s
->condexec_mask
) {
12468 gen_adc(tmp
, tmp2
);
12470 gen_adc_CC(tmp
, tmp
, tmp2
);
12473 case 0x6: /* sbc */
12474 if (s
->condexec_mask
) {
12475 gen_sub_carry(tmp
, tmp
, tmp2
);
12477 gen_sbc_CC(tmp
, tmp
, tmp2
);
12480 case 0x7: /* ror */
12481 if (s
->condexec_mask
) {
12482 tcg_gen_andi_i32(tmp
, tmp
, 0x1f);
12483 tcg_gen_rotr_i32(tmp2
, tmp2
, tmp
);
12485 gen_helper_ror_cc(tmp2
, cpu_env
, tmp2
, tmp
);
12486 gen_logic_CC(tmp2
);
12489 case 0x8: /* tst */
12490 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
12494 case 0x9: /* neg */
12495 if (s
->condexec_mask
)
12496 tcg_gen_neg_i32(tmp
, tmp2
);
12498 gen_sub_CC(tmp
, tmp
, tmp2
);
12500 case 0xa: /* cmp */
12501 gen_sub_CC(tmp
, tmp
, tmp2
);
12504 case 0xb: /* cmn */
12505 gen_add_CC(tmp
, tmp
, tmp2
);
12508 case 0xc: /* orr */
12509 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
12510 if (!s
->condexec_mask
)
12513 case 0xd: /* mul */
12514 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
12515 if (!s
->condexec_mask
)
12518 case 0xe: /* bic */
12519 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
12520 if (!s
->condexec_mask
)
12523 case 0xf: /* mvn */
12524 tcg_gen_not_i32(tmp2
, tmp2
);
12525 if (!s
->condexec_mask
)
12526 gen_logic_CC(tmp2
);
12533 store_reg(s
, rm
, tmp2
);
12535 tcg_temp_free_i32(tmp
);
12537 store_reg(s
, rd
, tmp
);
12538 tcg_temp_free_i32(tmp2
);
12541 tcg_temp_free_i32(tmp
);
12542 tcg_temp_free_i32(tmp2
);
12547 /* load/store register offset. */
12549 rn
= (insn
>> 3) & 7;
12550 rm
= (insn
>> 6) & 7;
12551 op
= (insn
>> 9) & 7;
12552 addr
= load_reg(s
, rn
);
12553 tmp
= load_reg(s
, rm
);
12554 tcg_gen_add_i32(addr
, addr
, tmp
);
12555 tcg_temp_free_i32(tmp
);
12557 if (op
< 3) { /* store */
12558 tmp
= load_reg(s
, rd
);
12560 tmp
= tcg_temp_new_i32();
12565 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12568 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12571 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12573 case 3: /* ldrsb */
12574 gen_aa32_ld8s_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12577 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12580 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12583 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12585 case 7: /* ldrsh */
12586 gen_aa32_ld16s_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12589 if (op
>= 3) { /* load */
12590 store_reg(s
, rd
, tmp
);
12592 tcg_temp_free_i32(tmp
);
12594 tcg_temp_free_i32(addr
);
12598 /* load/store word immediate offset */
12600 rn
= (insn
>> 3) & 7;
12601 addr
= load_reg(s
, rn
);
12602 val
= (insn
>> 4) & 0x7c;
12603 tcg_gen_addi_i32(addr
, addr
, val
);
12605 if (insn
& (1 << 11)) {
12607 tmp
= tcg_temp_new_i32();
12608 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
12609 store_reg(s
, rd
, tmp
);
12612 tmp
= load_reg(s
, rd
);
12613 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
12614 tcg_temp_free_i32(tmp
);
12616 tcg_temp_free_i32(addr
);
12620 /* load/store byte immediate offset */
12622 rn
= (insn
>> 3) & 7;
12623 addr
= load_reg(s
, rn
);
12624 val
= (insn
>> 6) & 0x1f;
12625 tcg_gen_addi_i32(addr
, addr
, val
);
12627 if (insn
& (1 << 11)) {
12629 tmp
= tcg_temp_new_i32();
12630 gen_aa32_ld8u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12631 store_reg(s
, rd
, tmp
);
12634 tmp
= load_reg(s
, rd
);
12635 gen_aa32_st8_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12636 tcg_temp_free_i32(tmp
);
12638 tcg_temp_free_i32(addr
);
12642 /* load/store halfword immediate offset */
12644 rn
= (insn
>> 3) & 7;
12645 addr
= load_reg(s
, rn
);
12646 val
= (insn
>> 5) & 0x3e;
12647 tcg_gen_addi_i32(addr
, addr
, val
);
12649 if (insn
& (1 << 11)) {
12651 tmp
= tcg_temp_new_i32();
12652 gen_aa32_ld16u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12653 store_reg(s
, rd
, tmp
);
12656 tmp
= load_reg(s
, rd
);
12657 gen_aa32_st16_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12658 tcg_temp_free_i32(tmp
);
12660 tcg_temp_free_i32(addr
);
12664 /* load/store from stack */
12665 rd
= (insn
>> 8) & 7;
12666 addr
= load_reg(s
, 13);
12667 val
= (insn
& 0xff) * 4;
12668 tcg_gen_addi_i32(addr
, addr
, val
);
12670 if (insn
& (1 << 11)) {
12672 tmp
= tcg_temp_new_i32();
12673 gen_aa32_ld32u_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12674 store_reg(s
, rd
, tmp
);
12677 tmp
= load_reg(s
, rd
);
12678 gen_aa32_st32_iss(s
, tmp
, addr
, get_mem_index(s
), rd
| ISSIs16Bit
);
12679 tcg_temp_free_i32(tmp
);
12681 tcg_temp_free_i32(addr
);
12686 * 0b1010_xxxx_xxxx_xxxx
12687 * - Add PC/SP (immediate)
12689 rd
= (insn
>> 8) & 7;
12690 if (insn
& (1 << 11)) {
12692 tmp
= load_reg(s
, 13);
12694 /* PC. bit 1 is ignored. */
12695 tmp
= tcg_temp_new_i32();
12696 tcg_gen_movi_i32(tmp
, (s
->pc
+ 2) & ~(uint32_t)2);
12698 val
= (insn
& 0xff) * 4;
12699 tcg_gen_addi_i32(tmp
, tmp
, val
);
12700 store_reg(s
, rd
, tmp
);
12705 op
= (insn
>> 8) & 0xf;
12709 * 0b1011_0000_xxxx_xxxx
12710 * - ADD (SP plus immediate)
12711 * - SUB (SP minus immediate)
12713 tmp
= load_reg(s
, 13);
12714 val
= (insn
& 0x7f) * 4;
12715 if (insn
& (1 << 7))
12716 val
= -(int32_t)val
;
12717 tcg_gen_addi_i32(tmp
, tmp
, val
);
12718 store_sp_checked(s
, tmp
);
12721 case 2: /* sign/zero extend. */
12724 rm
= (insn
>> 3) & 7;
12725 tmp
= load_reg(s
, rm
);
12726 switch ((insn
>> 6) & 3) {
12727 case 0: gen_sxth(tmp
); break;
12728 case 1: gen_sxtb(tmp
); break;
12729 case 2: gen_uxth(tmp
); break;
12730 case 3: gen_uxtb(tmp
); break;
12732 store_reg(s
, rd
, tmp
);
12734 case 4: case 5: case 0xc: case 0xd:
12736 * 0b1011_x10x_xxxx_xxxx
12739 addr
= load_reg(s
, 13);
12740 if (insn
& (1 << 8))
12744 for (i
= 0; i
< 8; i
++) {
12745 if (insn
& (1 << i
))
12748 if ((insn
& (1 << 11)) == 0) {
12749 tcg_gen_addi_i32(addr
, addr
, -offset
);
12752 if (s
->v8m_stackcheck
) {
12754 * Here 'addr' is the lower of "old SP" and "new SP";
12755 * if this is a pop that starts below the limit and ends
12756 * above it, it is UNKNOWN whether the limit check triggers;
12757 * we choose to trigger.
12759 gen_helper_v8m_stackcheck(cpu_env
, addr
);
12762 for (i
= 0; i
< 8; i
++) {
12763 if (insn
& (1 << i
)) {
12764 if (insn
& (1 << 11)) {
12766 tmp
= tcg_temp_new_i32();
12767 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
12768 store_reg(s
, i
, tmp
);
12771 tmp
= load_reg(s
, i
);
12772 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
12773 tcg_temp_free_i32(tmp
);
12775 /* advance to the next address. */
12776 tcg_gen_addi_i32(addr
, addr
, 4);
12780 if (insn
& (1 << 8)) {
12781 if (insn
& (1 << 11)) {
12783 tmp
= tcg_temp_new_i32();
12784 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
12785 /* don't set the pc until the rest of the instruction
12789 tmp
= load_reg(s
, 14);
12790 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
12791 tcg_temp_free_i32(tmp
);
12793 tcg_gen_addi_i32(addr
, addr
, 4);
12795 if ((insn
& (1 << 11)) == 0) {
12796 tcg_gen_addi_i32(addr
, addr
, -offset
);
12798 /* write back the new stack pointer */
12799 store_reg(s
, 13, addr
);
12800 /* set the new PC value */
12801 if ((insn
& 0x0900) == 0x0900) {
12802 store_reg_from_load(s
, 15, tmp
);
12806 case 1: case 3: case 9: case 11: /* czb */
12808 tmp
= load_reg(s
, rm
);
12809 arm_gen_condlabel(s
);
12810 if (insn
& (1 << 11))
12811 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
12813 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
12814 tcg_temp_free_i32(tmp
);
12815 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
12816 val
= (uint32_t)s
->pc
+ 2;
12821 case 15: /* IT, nop-hint. */
12822 if ((insn
& 0xf) == 0) {
12823 gen_nop_hint(s
, (insn
>> 4) & 0xf);
12827 s
->condexec_cond
= (insn
>> 4) & 0xe;
12828 s
->condexec_mask
= insn
& 0x1f;
12829 /* No actual code generated for this insn, just setup state. */
12832 case 0xe: /* bkpt */
12834 int imm8
= extract32(insn
, 0, 8);
12836 gen_exception_bkpt_insn(s
, 2, syn_aa32_bkpt(imm8
, true));
12840 case 0xa: /* rev, and hlt */
12842 int op1
= extract32(insn
, 6, 2);
12846 int imm6
= extract32(insn
, 0, 6);
12852 /* Otherwise this is rev */
12854 rn
= (insn
>> 3) & 0x7;
12856 tmp
= load_reg(s
, rn
);
12858 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
12859 case 1: gen_rev16(tmp
); break;
12860 case 3: gen_revsh(tmp
); break;
12862 g_assert_not_reached();
12864 store_reg(s
, rd
, tmp
);
12869 switch ((insn
>> 5) & 7) {
12873 if (((insn
>> 3) & 1) != !!(s
->be_data
== MO_BE
)) {
12874 gen_helper_setend(cpu_env
);
12875 s
->base
.is_jmp
= DISAS_UPDATE
;
12884 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
12885 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
12888 addr
= tcg_const_i32(19);
12889 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
12890 tcg_temp_free_i32(addr
);
12894 addr
= tcg_const_i32(16);
12895 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
12896 tcg_temp_free_i32(addr
);
12898 tcg_temp_free_i32(tmp
);
12901 if (insn
& (1 << 4)) {
12902 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
12906 gen_set_psr_im(s
, ((insn
& 7) << 6), 0, shift
);
12921 /* load/store multiple */
12922 TCGv_i32 loaded_var
= NULL
;
12923 rn
= (insn
>> 8) & 0x7;
12924 addr
= load_reg(s
, rn
);
12925 for (i
= 0; i
< 8; i
++) {
12926 if (insn
& (1 << i
)) {
12927 if (insn
& (1 << 11)) {
12929 tmp
= tcg_temp_new_i32();
12930 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
12934 store_reg(s
, i
, tmp
);
12938 tmp
= load_reg(s
, i
);
12939 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
12940 tcg_temp_free_i32(tmp
);
12942 /* advance to the next address */
12943 tcg_gen_addi_i32(addr
, addr
, 4);
12946 if ((insn
& (1 << rn
)) == 0) {
12947 /* base reg not in list: base register writeback */
12948 store_reg(s
, rn
, addr
);
12950 /* base reg in list: if load, complete it now */
12951 if (insn
& (1 << 11)) {
12952 store_reg(s
, rn
, loaded_var
);
12954 tcg_temp_free_i32(addr
);
12959 /* conditional branch or swi */
12960 cond
= (insn
>> 8) & 0xf;
12966 gen_set_pc_im(s
, s
->pc
);
12967 s
->svc_imm
= extract32(insn
, 0, 8);
12968 s
->base
.is_jmp
= DISAS_SWI
;
12971 /* generate a conditional jump to next instruction */
12972 arm_skip_unless(s
, cond
);
12974 /* jump to the offset */
12975 val
= (uint32_t)s
->pc
+ 2;
12976 offset
= ((int32_t)insn
<< 24) >> 24;
12977 val
+= offset
<< 1;
12982 if (insn
& (1 << 11)) {
12983 /* thumb_insn_is_16bit() ensures we can't get here for
12984 * a Thumb2 CPU, so this must be a thumb1 split BL/BLX:
12985 * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF)
12987 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
12989 offset
= ((insn
& 0x7ff) << 1);
12990 tmp
= load_reg(s
, 14);
12991 tcg_gen_addi_i32(tmp
, tmp
, offset
);
12992 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
12994 tmp2
= tcg_temp_new_i32();
12995 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
12996 store_reg(s
, 14, tmp2
);
13000 /* unconditional branch */
13001 val
= (uint32_t)s
->pc
;
13002 offset
= ((int32_t)insn
<< 21) >> 21;
13003 val
+= (offset
<< 1) + 2;
13008 /* thumb_insn_is_16bit() ensures we can't get here for
13009 * a Thumb2 CPU, so this must be a thumb1 split BL/BLX.
13011 assert(!arm_dc_feature(s
, ARM_FEATURE_THUMB2
));
13013 if (insn
& (1 << 11)) {
13014 /* 0b1111_1xxx_xxxx_xxxx : BL suffix */
13015 offset
= ((insn
& 0x7ff) << 1) | 1;
13016 tmp
= load_reg(s
, 14);
13017 tcg_gen_addi_i32(tmp
, tmp
, offset
);
13019 tmp2
= tcg_temp_new_i32();
13020 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
13021 store_reg(s
, 14, tmp2
);
13024 /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
13025 uint32_t uoffset
= ((int32_t)insn
<< 21) >> 9;
13027 tcg_gen_movi_i32(cpu_R
[14], s
->pc
+ 2 + uoffset
);
13034 gen_exception_insn(s
, 2, EXCP_UDEF
, syn_uncategorized(),
13035 default_exception_el(s
));
13038 static bool insn_crosses_page(CPUARMState
*env
, DisasContext
*s
)
13040 /* Return true if the insn at dc->pc might cross a page boundary.
13041 * (False positives are OK, false negatives are not.)
13042 * We know this is a Thumb insn, and our caller ensures we are
13043 * only called if dc->pc is less than 4 bytes from the page
13044 * boundary, so we cross the page if the first 16 bits indicate
13045 * that this is a 32 bit insn.
13047 uint16_t insn
= arm_lduw_code(env
, s
->pc
, s
->sctlr_b
);
13049 return !thumb_insn_is_16bit(s
, insn
);
13052 static void arm_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
13054 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13055 CPUARMState
*env
= cs
->env_ptr
;
13056 ARMCPU
*cpu
= arm_env_get_cpu(env
);
13058 dc
->isar
= &cpu
->isar
;
13059 dc
->pc
= dc
->base
.pc_first
;
13063 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13064 * there is no secure EL1, so we route exceptions to EL3.
13066 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
13067 !arm_el_is_aa64(env
, 3);
13068 dc
->thumb
= ARM_TBFLAG_THUMB(dc
->base
.tb
->flags
);
13069 dc
->sctlr_b
= ARM_TBFLAG_SCTLR_B(dc
->base
.tb
->flags
);
13070 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
13071 dc
->condexec_mask
= (ARM_TBFLAG_CONDEXEC(dc
->base
.tb
->flags
) & 0xf) << 1;
13072 dc
->condexec_cond
= ARM_TBFLAG_CONDEXEC(dc
->base
.tb
->flags
) >> 4;
13073 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
13074 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
13075 #if !defined(CONFIG_USER_ONLY)
13076 dc
->user
= (dc
->current_el
== 0);
13078 dc
->ns
= ARM_TBFLAG_NS(dc
->base
.tb
->flags
);
13079 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
13080 dc
->vfp_enabled
= ARM_TBFLAG_VFPEN(dc
->base
.tb
->flags
);
13081 dc
->vec_len
= ARM_TBFLAG_VECLEN(dc
->base
.tb
->flags
);
13082 dc
->vec_stride
= ARM_TBFLAG_VECSTRIDE(dc
->base
.tb
->flags
);
13083 dc
->c15_cpar
= ARM_TBFLAG_XSCALE_CPAR(dc
->base
.tb
->flags
);
13084 dc
->v7m_handler_mode
= ARM_TBFLAG_HANDLER(dc
->base
.tb
->flags
);
13085 dc
->v8m_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
13086 regime_is_secure(env
, dc
->mmu_idx
);
13087 dc
->v8m_stackcheck
= ARM_TBFLAG_STACKCHECK(dc
->base
.tb
->flags
);
13088 dc
->cp_regs
= cpu
->cp_regs
;
13089 dc
->features
= env
->features
;
13091 /* Single step state. The code-generation logic here is:
13093 * generate code with no special handling for single-stepping (except
13094 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13095 * this happens anyway because those changes are all system register or
13097 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13098 * emit code for one insn
13099 * emit code to clear PSTATE.SS
13100 * emit code to generate software step exception for completed step
13101 * end TB (as usual for having generated an exception)
13102 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13103 * emit code to generate a software step exception
13106 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
13107 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
13108 dc
->is_ldex
= false;
13109 dc
->ss_same_el
= false; /* Can't be true since EL_d must be AArch64 */
13111 dc
->page_start
= dc
->base
.pc_first
& TARGET_PAGE_MASK
;
13113 /* If architectural single step active, limit to 1. */
13114 if (is_singlestepping(dc
)) {
13115 dc
->base
.max_insns
= 1;
13118 /* ARM is a fixed-length ISA. Bound the number of insns to execute
13119 to those left on the page. */
13121 int bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
13122 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
13125 cpu_F0s
= tcg_temp_new_i32();
13126 cpu_F1s
= tcg_temp_new_i32();
13127 cpu_F0d
= tcg_temp_new_i64();
13128 cpu_F1d
= tcg_temp_new_i64();
13131 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
13132 cpu_M0
= tcg_temp_new_i64();
13135 static void arm_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13137 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13139 /* A note on handling of the condexec (IT) bits:
13141 * We want to avoid the overhead of having to write the updated condexec
13142 * bits back to the CPUARMState for every instruction in an IT block. So:
13143 * (1) if the condexec bits are not already zero then we write
13144 * zero back into the CPUARMState now. This avoids complications trying
13145 * to do it at the end of the block. (For example if we don't do this
13146 * it's hard to identify whether we can safely skip writing condexec
13147 * at the end of the TB, which we definitely want to do for the case
13148 * where a TB doesn't do anything with the IT state at all.)
13149 * (2) if we are going to leave the TB then we call gen_set_condexec()
13150 * which will write the correct value into CPUARMState if zero is wrong.
13151 * This is done both for leaving the TB at the end, and for leaving
13152 * it because of an exception we know will happen, which is done in
13153 * gen_exception_insn(). The latter is necessary because we need to
13154 * leave the TB with the PC/IT state just prior to execution of the
13155 * instruction which caused the exception.
13156 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
13157 * then the CPUARMState will be wrong and we need to reset it.
13158 * This is handled in the same way as restoration of the
13159 * PC in these situations; we save the value of the condexec bits
13160 * for each PC via tcg_gen_insn_start(), and restore_state_to_opc()
13161 * then uses this to restore them after an exception.
13163 * Note that there are no instructions which can read the condexec
13164 * bits, and none which can write non-static values to them, so
13165 * we don't need to care about whether CPUARMState is correct in the
13169 /* Reset the conditional execution bits immediately. This avoids
13170 complications trying to do it at the end of the block. */
13171 if (dc
->condexec_mask
|| dc
->condexec_cond
) {
13172 TCGv_i32 tmp
= tcg_temp_new_i32();
13173 tcg_gen_movi_i32(tmp
, 0);
13174 store_cpu_field(tmp
, condexec_bits
);
13178 static void arm_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13180 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13182 tcg_gen_insn_start(dc
->pc
,
13183 (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1),
13185 dc
->insn_start
= tcg_last_op();
13188 static bool arm_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
13189 const CPUBreakpoint
*bp
)
13191 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13193 if (bp
->flags
& BP_CPU
) {
13194 gen_set_condexec(dc
);
13195 gen_set_pc_im(dc
, dc
->pc
);
13196 gen_helper_check_breakpoints(cpu_env
);
13197 /* End the TB early; it's likely not going to be executed */
13198 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13200 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
13201 /* The address covered by the breakpoint must be
13202 included in [tb->pc, tb->pc + tb->size) in order
13203 to for it to be properly cleared -- thus we
13204 increment the PC here so that the logic setting
13205 tb->size below does the right thing. */
13206 /* TODO: Advance PC by correct instruction length to
13207 * avoid disassembler error messages */
13209 dc
->base
.is_jmp
= DISAS_NORETURN
;
13215 static bool arm_pre_translate_insn(DisasContext
*dc
)
13217 #ifdef CONFIG_USER_ONLY
13218 /* Intercept jump to the magic kernel page. */
13219 if (dc
->pc
>= 0xffff0000) {
13220 /* We always get here via a jump, so know we are not in a
13221 conditional execution block. */
13222 gen_exception_internal(EXCP_KERNEL_TRAP
);
13223 dc
->base
.is_jmp
= DISAS_NORETURN
;
13228 if (dc
->ss_active
&& !dc
->pstate_ss
) {
13229 /* Singlestep state is Active-pending.
13230 * If we're in this state at the start of a TB then either
13231 * a) we just took an exception to an EL which is being debugged
13232 * and this is the first insn in the exception handler
13233 * b) debug exceptions were masked and we just unmasked them
13234 * without changing EL (eg by clearing PSTATE.D)
13235 * In either case we're going to take a swstep exception in the
13236 * "did not step an insn" case, and so the syndrome ISV and EX
13237 * bits should be zero.
13239 assert(dc
->base
.num_insns
== 1);
13240 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
13241 default_exception_el(dc
));
13242 dc
->base
.is_jmp
= DISAS_NORETURN
;
13249 static void arm_post_translate_insn(DisasContext
*dc
)
13251 if (dc
->condjmp
&& !dc
->base
.is_jmp
) {
13252 gen_set_label(dc
->condlabel
);
13255 dc
->base
.pc_next
= dc
->pc
;
13256 translator_loop_temp_check(&dc
->base
);
13259 static void arm_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13261 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13262 CPUARMState
*env
= cpu
->env_ptr
;
13265 if (arm_pre_translate_insn(dc
)) {
13269 insn
= arm_ldl_code(env
, dc
->pc
, dc
->sctlr_b
);
13272 disas_arm_insn(dc
, insn
);
13274 arm_post_translate_insn(dc
);
13276 /* ARM is a fixed-length ISA. We performed the cross-page check
13277 in init_disas_context by adjusting max_insns. */
13280 static bool thumb_insn_is_unconditional(DisasContext
*s
, uint32_t insn
)
13282 /* Return true if this Thumb insn is always unconditional,
13283 * even inside an IT block. This is true of only a very few
13284 * instructions: BKPT, HLT, and SG.
13286 * A larger class of instructions are UNPREDICTABLE if used
13287 * inside an IT block; we do not need to detect those here, because
13288 * what we do by default (perform the cc check and update the IT
13289 * bits state machine) is a permitted CONSTRAINED UNPREDICTABLE
13290 * choice for those situations.
13292 * insn is either a 16-bit or a 32-bit instruction; the two are
13293 * distinguishable because for the 16-bit case the top 16 bits
13294 * are zeroes, and that isn't a valid 32-bit encoding.
13296 if ((insn
& 0xffffff00) == 0xbe00) {
13301 if ((insn
& 0xffffffc0) == 0xba80 && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
13302 !arm_dc_feature(s
, ARM_FEATURE_M
)) {
13303 /* HLT: v8A only. This is unconditional even when it is going to
13304 * UNDEF; see the v8A ARM ARM DDI0487B.a H3.3.
13305 * For v7 cores this was a plain old undefined encoding and so
13306 * honours its cc check. (We might be using the encoding as
13307 * a semihosting trap, but we don't change the cc check behaviour
13308 * on that account, because a debugger connected to a real v7A
13309 * core and emulating semihosting traps by catching the UNDEF
13310 * exception would also only see cases where the cc check passed.
13311 * No guest code should be trying to do a HLT semihosting trap
13312 * in an IT block anyway.
13317 if (insn
== 0xe97fe97f && arm_dc_feature(s
, ARM_FEATURE_V8
) &&
13318 arm_dc_feature(s
, ARM_FEATURE_M
)) {
13326 static void thumb_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13328 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13329 CPUARMState
*env
= cpu
->env_ptr
;
13333 if (arm_pre_translate_insn(dc
)) {
13337 insn
= arm_lduw_code(env
, dc
->pc
, dc
->sctlr_b
);
13338 is_16bit
= thumb_insn_is_16bit(dc
, insn
);
13341 uint32_t insn2
= arm_lduw_code(env
, dc
->pc
, dc
->sctlr_b
);
13343 insn
= insn
<< 16 | insn2
;
13348 if (dc
->condexec_mask
&& !thumb_insn_is_unconditional(dc
, insn
)) {
13349 uint32_t cond
= dc
->condexec_cond
;
13351 if (cond
!= 0x0e) { /* Skip conditional when condition is AL. */
13352 arm_skip_unless(dc
, cond
);
13357 disas_thumb_insn(dc
, insn
);
13359 disas_thumb2_insn(dc
, insn
);
13362 /* Advance the Thumb condexec condition. */
13363 if (dc
->condexec_mask
) {
13364 dc
->condexec_cond
= ((dc
->condexec_cond
& 0xe) |
13365 ((dc
->condexec_mask
>> 4) & 1));
13366 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
13367 if (dc
->condexec_mask
== 0) {
13368 dc
->condexec_cond
= 0;
13372 arm_post_translate_insn(dc
);
13374 /* Thumb is a variable-length ISA. Stop translation when the next insn
13375 * will touch a new page. This ensures that prefetch aborts occur at
13378 * We want to stop the TB if the next insn starts in a new page,
13379 * or if it spans between this page and the next. This means that
13380 * if we're looking at the last halfword in the page we need to
13381 * see if it's a 16-bit Thumb insn (which will fit in this TB)
13382 * or a 32-bit Thumb insn (which won't).
13383 * This is to avoid generating a silly TB with a single 16-bit insn
13384 * in it at the end of this page (which would execute correctly
13385 * but isn't very efficient).
13387 if (dc
->base
.is_jmp
== DISAS_NEXT
13388 && (dc
->pc
- dc
->page_start
>= TARGET_PAGE_SIZE
13389 || (dc
->pc
- dc
->page_start
>= TARGET_PAGE_SIZE
- 3
13390 && insn_crosses_page(env
, dc
)))) {
13391 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13395 static void arm_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
13397 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13399 if (tb_cflags(dc
->base
.tb
) & CF_LAST_IO
&& dc
->condjmp
) {
13400 /* FIXME: This can theoretically happen with self-modifying code. */
13401 cpu_abort(cpu
, "IO on conditional branch instruction");
13404 /* At this stage dc->condjmp will only be set when the skipped
13405 instruction was a conditional branch or trap, and the PC has
13406 already been written. */
13407 gen_set_condexec(dc
);
13408 if (dc
->base
.is_jmp
== DISAS_BX_EXCRET
) {
13409 /* Exception return branches need some special case code at the
13410 * end of the TB, which is complex enough that it has to
13411 * handle the single-step vs not and the condition-failed
13412 * insn codepath itself.
13414 gen_bx_excret_final_code(dc
);
13415 } else if (unlikely(is_singlestepping(dc
))) {
13416 /* Unconditional and "condition passed" instruction codepath. */
13417 switch (dc
->base
.is_jmp
) {
13419 gen_ss_advance(dc
);
13420 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
13421 default_exception_el(dc
));
13424 gen_ss_advance(dc
);
13425 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
13428 gen_ss_advance(dc
);
13429 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
13432 case DISAS_TOO_MANY
:
13434 gen_set_pc_im(dc
, dc
->pc
);
13437 /* FIXME: Single stepping a WFI insn will not halt the CPU. */
13438 gen_singlestep_exception(dc
);
13440 case DISAS_NORETURN
:
13444 /* While branches must always occur at the end of an IT block,
13445 there are a few other things that can cause us to terminate
13446 the TB in the middle of an IT block:
13447 - Exception generating instructions (bkpt, swi, undefined).
13449 - Hardware watchpoints.
13450 Hardware breakpoints have already been handled and skip this code.
13452 switch(dc
->base
.is_jmp
) {
13454 case DISAS_TOO_MANY
:
13455 gen_goto_tb(dc
, 1, dc
->pc
);
13461 gen_set_pc_im(dc
, dc
->pc
);
13464 /* indicate that the hash table must be used to find the next TB */
13465 tcg_gen_exit_tb(NULL
, 0);
13467 case DISAS_NORETURN
:
13468 /* nothing more to generate */
13472 TCGv_i32 tmp
= tcg_const_i32((dc
->thumb
&&
13473 !(dc
->insn
& (1U << 31))) ? 2 : 4);
13475 gen_helper_wfi(cpu_env
, tmp
);
13476 tcg_temp_free_i32(tmp
);
13477 /* The helper doesn't necessarily throw an exception, but we
13478 * must go back to the main loop to check for interrupts anyway.
13480 tcg_gen_exit_tb(NULL
, 0);
13484 gen_helper_wfe(cpu_env
);
13487 gen_helper_yield(cpu_env
);
13490 gen_exception(EXCP_SWI
, syn_aa32_svc(dc
->svc_imm
, dc
->thumb
),
13491 default_exception_el(dc
));
13494 gen_exception(EXCP_HVC
, syn_aa32_hvc(dc
->svc_imm
), 2);
13497 gen_exception(EXCP_SMC
, syn_aa32_smc(), 3);
13503 /* "Condition failed" instruction codepath for the branch/trap insn */
13504 gen_set_label(dc
->condlabel
);
13505 gen_set_condexec(dc
);
13506 if (unlikely(is_singlestepping(dc
))) {
13507 gen_set_pc_im(dc
, dc
->pc
);
13508 gen_singlestep_exception(dc
);
13510 gen_goto_tb(dc
, 1, dc
->pc
);
13514 /* Functions above can change dc->pc, so re-align db->pc_next */
13515 dc
->base
.pc_next
= dc
->pc
;
13518 static void arm_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
13520 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13522 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
13523 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
13526 static const TranslatorOps arm_translator_ops
= {
13527 .init_disas_context
= arm_tr_init_disas_context
,
13528 .tb_start
= arm_tr_tb_start
,
13529 .insn_start
= arm_tr_insn_start
,
13530 .breakpoint_check
= arm_tr_breakpoint_check
,
13531 .translate_insn
= arm_tr_translate_insn
,
13532 .tb_stop
= arm_tr_tb_stop
,
13533 .disas_log
= arm_tr_disas_log
,
13536 static const TranslatorOps thumb_translator_ops
= {
13537 .init_disas_context
= arm_tr_init_disas_context
,
13538 .tb_start
= arm_tr_tb_start
,
13539 .insn_start
= arm_tr_insn_start
,
13540 .breakpoint_check
= arm_tr_breakpoint_check
,
13541 .translate_insn
= thumb_tr_translate_insn
,
13542 .tb_stop
= arm_tr_tb_stop
,
13543 .disas_log
= arm_tr_disas_log
,
13546 /* generate intermediate code for basic block 'tb'. */
13547 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
)
13550 const TranslatorOps
*ops
= &arm_translator_ops
;
13552 if (ARM_TBFLAG_THUMB(tb
->flags
)) {
13553 ops
= &thumb_translator_ops
;
13555 #ifdef TARGET_AARCH64
13556 if (ARM_TBFLAG_AARCH64_STATE(tb
->flags
)) {
13557 ops
= &aarch64_translator_ops
;
13561 translator_loop(ops
, &dc
.base
, cpu
, tb
);
13564 void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
13567 ARMCPU
*cpu
= ARM_CPU(cs
);
13568 CPUARMState
*env
= &cpu
->env
;
13572 aarch64_cpu_dump_state(cs
, f
, cpu_fprintf
, flags
);
13576 for(i
=0;i
<16;i
++) {
13577 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
13579 cpu_fprintf(f
, "\n");
13581 cpu_fprintf(f
, " ");
13584 if (arm_feature(env
, ARM_FEATURE_M
)) {
13585 uint32_t xpsr
= xpsr_read(env
);
13587 const char *ns_status
= "";
13589 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
13590 ns_status
= env
->v7m
.secure
? "S " : "NS ";
13593 if (xpsr
& XPSR_EXCP
) {
13596 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
13597 mode
= "unpriv-thread";
13599 mode
= "priv-thread";
13603 cpu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
13605 xpsr
& XPSR_N
? 'N' : '-',
13606 xpsr
& XPSR_Z
? 'Z' : '-',
13607 xpsr
& XPSR_C
? 'C' : '-',
13608 xpsr
& XPSR_V
? 'V' : '-',
13609 xpsr
& XPSR_T
? 'T' : 'A',
13613 uint32_t psr
= cpsr_read(env
);
13614 const char *ns_status
= "";
13616 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
13617 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
13618 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
13621 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
13623 psr
& CPSR_N
? 'N' : '-',
13624 psr
& CPSR_Z
? 'Z' : '-',
13625 psr
& CPSR_C
? 'C' : '-',
13626 psr
& CPSR_V
? 'V' : '-',
13627 psr
& CPSR_T
? 'T' : 'A',
13629 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
13632 if (flags
& CPU_DUMP_FPU
) {
13633 int numvfpregs
= 0;
13634 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
13637 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
13640 for (i
= 0; i
< numvfpregs
; i
++) {
13641 uint64_t v
= *aa32_vfp_dreg(env
, i
);
13642 cpu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
13643 i
* 2, (uint32_t)v
,
13644 i
* 2 + 1, (uint32_t)(v
>> 32),
13647 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->vfp
.xregs
[ARM_VFP_FPSCR
]);
13651 void restore_state_to_opc(CPUARMState
*env
, TranslationBlock
*tb
,
13652 target_ulong
*data
)
13656 env
->condexec_bits
= 0;
13657 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
13659 env
->regs
[15] = data
[0];
13660 env
->condexec_bits
= data
[1];
13661 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;