2 * HPPA emulation cpu translation for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "disas/disas.h"
23 #include "qemu/host-utils.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/cpu_ldst.h"
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
32 /* Since we have a distinction between register size and address size,
33 we need to redefine all of these. */
37 #undef tcg_global_mem_new
39 #if TARGET_LONG_BITS == 64
40 #define TCGv_tl TCGv_i64
41 #define tcg_temp_new_tl tcg_temp_new_i64
42 #if TARGET_REGISTER_BITS == 64
43 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64
45 #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
48 #define TCGv_tl TCGv_i32
49 #define tcg_temp_new_tl tcg_temp_new_i32
50 #define tcg_gen_extu_reg_tl tcg_gen_mov_i32
53 #if TARGET_REGISTER_BITS == 64
54 #define TCGv_reg TCGv_i64
56 #define tcg_temp_new tcg_temp_new_i64
57 #define tcg_global_mem_new tcg_global_mem_new_i64
59 #define tcg_gen_movi_reg tcg_gen_movi_i64
60 #define tcg_gen_mov_reg tcg_gen_mov_i64
61 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
62 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
63 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
64 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
65 #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
66 #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
67 #define tcg_gen_ld_reg tcg_gen_ld_i64
68 #define tcg_gen_st8_reg tcg_gen_st8_i64
69 #define tcg_gen_st16_reg tcg_gen_st16_i64
70 #define tcg_gen_st32_reg tcg_gen_st32_i64
71 #define tcg_gen_st_reg tcg_gen_st_i64
72 #define tcg_gen_add_reg tcg_gen_add_i64
73 #define tcg_gen_addi_reg tcg_gen_addi_i64
74 #define tcg_gen_sub_reg tcg_gen_sub_i64
75 #define tcg_gen_neg_reg tcg_gen_neg_i64
76 #define tcg_gen_subfi_reg tcg_gen_subfi_i64
77 #define tcg_gen_subi_reg tcg_gen_subi_i64
78 #define tcg_gen_and_reg tcg_gen_and_i64
79 #define tcg_gen_andi_reg tcg_gen_andi_i64
80 #define tcg_gen_or_reg tcg_gen_or_i64
81 #define tcg_gen_ori_reg tcg_gen_ori_i64
82 #define tcg_gen_xor_reg tcg_gen_xor_i64
83 #define tcg_gen_xori_reg tcg_gen_xori_i64
84 #define tcg_gen_not_reg tcg_gen_not_i64
85 #define tcg_gen_shl_reg tcg_gen_shl_i64
86 #define tcg_gen_shli_reg tcg_gen_shli_i64
87 #define tcg_gen_shr_reg tcg_gen_shr_i64
88 #define tcg_gen_shri_reg tcg_gen_shri_i64
89 #define tcg_gen_sar_reg tcg_gen_sar_i64
90 #define tcg_gen_sari_reg tcg_gen_sari_i64
91 #define tcg_gen_brcond_reg tcg_gen_brcond_i64
92 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
93 #define tcg_gen_setcond_reg tcg_gen_setcond_i64
94 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
95 #define tcg_gen_mul_reg tcg_gen_mul_i64
96 #define tcg_gen_muli_reg tcg_gen_muli_i64
97 #define tcg_gen_div_reg tcg_gen_div_i64
98 #define tcg_gen_rem_reg tcg_gen_rem_i64
99 #define tcg_gen_divu_reg tcg_gen_divu_i64
100 #define tcg_gen_remu_reg tcg_gen_remu_i64
101 #define tcg_gen_discard_reg tcg_gen_discard_i64
102 #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
103 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
104 #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
105 #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
106 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
107 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
108 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
109 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
110 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
111 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
112 #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
113 #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
114 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
115 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
116 #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
117 #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
118 #define tcg_gen_andc_reg tcg_gen_andc_i64
119 #define tcg_gen_eqv_reg tcg_gen_eqv_i64
120 #define tcg_gen_nand_reg tcg_gen_nand_i64
121 #define tcg_gen_nor_reg tcg_gen_nor_i64
122 #define tcg_gen_orc_reg tcg_gen_orc_i64
123 #define tcg_gen_clz_reg tcg_gen_clz_i64
124 #define tcg_gen_ctz_reg tcg_gen_ctz_i64
125 #define tcg_gen_clzi_reg tcg_gen_clzi_i64
126 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
127 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
128 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
129 #define tcg_gen_rotl_reg tcg_gen_rotl_i64
130 #define tcg_gen_rotli_reg tcg_gen_rotli_i64
131 #define tcg_gen_rotr_reg tcg_gen_rotr_i64
132 #define tcg_gen_rotri_reg tcg_gen_rotri_i64
133 #define tcg_gen_deposit_reg tcg_gen_deposit_i64
134 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
135 #define tcg_gen_extract_reg tcg_gen_extract_i64
136 #define tcg_gen_sextract_reg tcg_gen_sextract_i64
137 #define tcg_gen_extract2_reg tcg_gen_extract2_i64
138 #define tcg_constant_reg tcg_constant_i64
139 #define tcg_gen_movcond_reg tcg_gen_movcond_i64
140 #define tcg_gen_add2_reg tcg_gen_add2_i64
141 #define tcg_gen_sub2_reg tcg_gen_sub2_i64
142 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
143 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
144 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
145 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
147 #define TCGv_reg TCGv_i32
148 #define tcg_temp_new tcg_temp_new_i32
149 #define tcg_global_mem_new tcg_global_mem_new_i32
151 #define tcg_gen_movi_reg tcg_gen_movi_i32
152 #define tcg_gen_mov_reg tcg_gen_mov_i32
153 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
154 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
155 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
156 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
157 #define tcg_gen_ld32u_reg tcg_gen_ld_i32
158 #define tcg_gen_ld32s_reg tcg_gen_ld_i32
159 #define tcg_gen_ld_reg tcg_gen_ld_i32
160 #define tcg_gen_st8_reg tcg_gen_st8_i32
161 #define tcg_gen_st16_reg tcg_gen_st16_i32
162 #define tcg_gen_st32_reg tcg_gen_st32_i32
163 #define tcg_gen_st_reg tcg_gen_st_i32
164 #define tcg_gen_add_reg tcg_gen_add_i32
165 #define tcg_gen_addi_reg tcg_gen_addi_i32
166 #define tcg_gen_sub_reg tcg_gen_sub_i32
167 #define tcg_gen_neg_reg tcg_gen_neg_i32
168 #define tcg_gen_subfi_reg tcg_gen_subfi_i32
169 #define tcg_gen_subi_reg tcg_gen_subi_i32
170 #define tcg_gen_and_reg tcg_gen_and_i32
171 #define tcg_gen_andi_reg tcg_gen_andi_i32
172 #define tcg_gen_or_reg tcg_gen_or_i32
173 #define tcg_gen_ori_reg tcg_gen_ori_i32
174 #define tcg_gen_xor_reg tcg_gen_xor_i32
175 #define tcg_gen_xori_reg tcg_gen_xori_i32
176 #define tcg_gen_not_reg tcg_gen_not_i32
177 #define tcg_gen_shl_reg tcg_gen_shl_i32
178 #define tcg_gen_shli_reg tcg_gen_shli_i32
179 #define tcg_gen_shr_reg tcg_gen_shr_i32
180 #define tcg_gen_shri_reg tcg_gen_shri_i32
181 #define tcg_gen_sar_reg tcg_gen_sar_i32
182 #define tcg_gen_sari_reg tcg_gen_sari_i32
183 #define tcg_gen_brcond_reg tcg_gen_brcond_i32
184 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
185 #define tcg_gen_setcond_reg tcg_gen_setcond_i32
186 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
187 #define tcg_gen_mul_reg tcg_gen_mul_i32
188 #define tcg_gen_muli_reg tcg_gen_muli_i32
189 #define tcg_gen_div_reg tcg_gen_div_i32
190 #define tcg_gen_rem_reg tcg_gen_rem_i32
191 #define tcg_gen_divu_reg tcg_gen_divu_i32
192 #define tcg_gen_remu_reg tcg_gen_remu_i32
193 #define tcg_gen_discard_reg tcg_gen_discard_i32
194 #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
195 #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
196 #define tcg_gen_extu_i32_reg tcg_gen_mov_i32
197 #define tcg_gen_ext_i32_reg tcg_gen_mov_i32
198 #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
199 #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
200 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
201 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
202 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
203 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
204 #define tcg_gen_ext32u_reg tcg_gen_mov_i32
205 #define tcg_gen_ext32s_reg tcg_gen_mov_i32
206 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
207 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
208 #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
209 #define tcg_gen_andc_reg tcg_gen_andc_i32
210 #define tcg_gen_eqv_reg tcg_gen_eqv_i32
211 #define tcg_gen_nand_reg tcg_gen_nand_i32
212 #define tcg_gen_nor_reg tcg_gen_nor_i32
213 #define tcg_gen_orc_reg tcg_gen_orc_i32
214 #define tcg_gen_clz_reg tcg_gen_clz_i32
215 #define tcg_gen_ctz_reg tcg_gen_ctz_i32
216 #define tcg_gen_clzi_reg tcg_gen_clzi_i32
217 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
218 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
219 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
220 #define tcg_gen_rotl_reg tcg_gen_rotl_i32
221 #define tcg_gen_rotli_reg tcg_gen_rotli_i32
222 #define tcg_gen_rotr_reg tcg_gen_rotr_i32
223 #define tcg_gen_rotri_reg tcg_gen_rotri_i32
224 #define tcg_gen_deposit_reg tcg_gen_deposit_i32
225 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
226 #define tcg_gen_extract_reg tcg_gen_extract_i32
227 #define tcg_gen_sextract_reg tcg_gen_sextract_i32
228 #define tcg_gen_extract2_reg tcg_gen_extract2_i32
229 #define tcg_constant_reg tcg_constant_i32
230 #define tcg_gen_movcond_reg tcg_gen_movcond_i32
231 #define tcg_gen_add2_reg tcg_gen_add2_i32
232 #define tcg_gen_sub2_reg tcg_gen_sub2_i32
233 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
234 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
235 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
236 #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
237 #endif /* TARGET_REGISTER_BITS */
239 typedef struct DisasCond
{
244 typedef struct DisasContext
{
245 DisasContextBase base
;
266 #ifdef CONFIG_USER_ONLY
271 #ifdef CONFIG_USER_ONLY
272 #define UNALIGN(C) (C)->unalign
274 #define UNALIGN(C) MO_ALIGN
277 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
278 static int expand_sm_imm(DisasContext
*ctx
, int val
)
280 if (val
& PSW_SM_E
) {
281 val
= (val
& ~PSW_SM_E
) | PSW_E
;
283 if (val
& PSW_SM_W
) {
284 val
= (val
& ~PSW_SM_W
) | PSW_W
;
289 /* Inverted space register indicates 0 means sr0 not inferred from base. */
290 static int expand_sr3x(DisasContext
*ctx
, int val
)
295 /* Convert the M:A bits within a memory insn to the tri-state value
296 we use for the final M. */
297 static int ma_to_m(DisasContext
*ctx
, int val
)
299 return val
& 2 ? (val
& 1 ? -1 : 1) : 0;
302 /* Convert the sign of the displacement to a pre or post-modify. */
303 static int pos_to_m(DisasContext
*ctx
, int val
)
308 static int neg_to_m(DisasContext
*ctx
, int val
)
313 /* Used for branch targets and fp memory ops. */
314 static int expand_shl2(DisasContext
*ctx
, int val
)
319 /* Used for fp memory ops. */
320 static int expand_shl3(DisasContext
*ctx
, int val
)
325 /* Used for assemble_21. */
326 static int expand_shl11(DisasContext
*ctx
, int val
)
332 /* Include the auto-generated decoder. */
333 #include "decode-insns.c.inc"
335 /* We are not using a goto_tb (for whatever reason), but have updated
336 the iaq (for whatever reason), so don't do it again on exit. */
337 #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0
339 /* We are exiting the TB, but have neither emitted a goto_tb, nor
340 updated the iaq for the next instruction to be executed. */
341 #define DISAS_IAQ_N_STALE DISAS_TARGET_1
343 /* Similarly, but we want to return to the main loop immediately
344 to recognize unmasked interrupts. */
345 #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2
346 #define DISAS_EXIT DISAS_TARGET_3
348 /* global register indexes */
349 static TCGv_reg cpu_gr
[32];
350 static TCGv_i64 cpu_sr
[4];
351 static TCGv_i64 cpu_srH
;
352 static TCGv_reg cpu_iaoq_f
;
353 static TCGv_reg cpu_iaoq_b
;
354 static TCGv_i64 cpu_iasq_f
;
355 static TCGv_i64 cpu_iasq_b
;
356 static TCGv_reg cpu_sar
;
357 static TCGv_reg cpu_psw_n
;
358 static TCGv_reg cpu_psw_v
;
359 static TCGv_reg cpu_psw_cb
;
360 static TCGv_reg cpu_psw_cb_msb
;
362 #include "exec/gen-icount.h"
364 void hppa_translate_init(void)
366 #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
368 typedef struct { TCGv_reg
*var
; const char *name
; int ofs
; } GlobalVar
;
369 static const GlobalVar vars
[] = {
370 { &cpu_sar
, "sar", offsetof(CPUHPPAState
, cr
[CR_SAR
]) },
381 /* Use the symbolic register names that match the disassembler. */
382 static const char gr_names
[32][4] = {
383 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
384 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
385 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
386 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
388 /* SR[4-7] are not global registers so that we can index them. */
389 static const char sr_names
[5][4] = {
390 "sr0", "sr1", "sr2", "sr3", "srH"
396 for (i
= 1; i
< 32; i
++) {
397 cpu_gr
[i
] = tcg_global_mem_new(cpu_env
,
398 offsetof(CPUHPPAState
, gr
[i
]),
401 for (i
= 0; i
< 4; i
++) {
402 cpu_sr
[i
] = tcg_global_mem_new_i64(cpu_env
,
403 offsetof(CPUHPPAState
, sr
[i
]),
406 cpu_srH
= tcg_global_mem_new_i64(cpu_env
,
407 offsetof(CPUHPPAState
, sr
[4]),
410 for (i
= 0; i
< ARRAY_SIZE(vars
); ++i
) {
411 const GlobalVar
*v
= &vars
[i
];
412 *v
->var
= tcg_global_mem_new(cpu_env
, v
->ofs
, v
->name
);
415 cpu_iasq_f
= tcg_global_mem_new_i64(cpu_env
,
416 offsetof(CPUHPPAState
, iasq_f
),
418 cpu_iasq_b
= tcg_global_mem_new_i64(cpu_env
,
419 offsetof(CPUHPPAState
, iasq_b
),
423 static DisasCond
cond_make_f(void)
432 static DisasCond
cond_make_t(void)
435 .c
= TCG_COND_ALWAYS
,
441 static DisasCond
cond_make_n(void)
446 .a1
= tcg_constant_reg(0)
450 static DisasCond
cond_make_0_tmp(TCGCond c
, TCGv_reg a0
)
452 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
454 .c
= c
, .a0
= a0
, .a1
= tcg_constant_reg(0)
458 static DisasCond
cond_make_0(TCGCond c
, TCGv_reg a0
)
460 TCGv_reg tmp
= tcg_temp_new();
461 tcg_gen_mov_reg(tmp
, a0
);
462 return cond_make_0_tmp(c
, tmp
);
465 static DisasCond
cond_make(TCGCond c
, TCGv_reg a0
, TCGv_reg a1
)
467 DisasCond r
= { .c
= c
};
469 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
470 r
.a0
= tcg_temp_new();
471 tcg_gen_mov_reg(r
.a0
, a0
);
472 r
.a1
= tcg_temp_new();
473 tcg_gen_mov_reg(r
.a1
, a1
);
478 static void cond_free(DisasCond
*cond
)
485 case TCG_COND_ALWAYS
:
486 cond
->c
= TCG_COND_NEVER
;
493 static TCGv_reg
get_temp(DisasContext
*ctx
)
495 unsigned i
= ctx
->ntempr
++;
496 g_assert(i
< ARRAY_SIZE(ctx
->tempr
));
497 return ctx
->tempr
[i
] = tcg_temp_new();
500 #ifndef CONFIG_USER_ONLY
501 static TCGv_tl
get_temp_tl(DisasContext
*ctx
)
503 unsigned i
= ctx
->ntempl
++;
504 g_assert(i
< ARRAY_SIZE(ctx
->templ
));
505 return ctx
->templ
[i
] = tcg_temp_new_tl();
509 static TCGv_reg
load_const(DisasContext
*ctx
, target_sreg v
)
511 TCGv_reg t
= get_temp(ctx
);
512 tcg_gen_movi_reg(t
, v
);
516 static TCGv_reg
load_gpr(DisasContext
*ctx
, unsigned reg
)
519 TCGv_reg t
= get_temp(ctx
);
520 tcg_gen_movi_reg(t
, 0);
527 static TCGv_reg
dest_gpr(DisasContext
*ctx
, unsigned reg
)
529 if (reg
== 0 || ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
530 return get_temp(ctx
);
536 static void save_or_nullify(DisasContext
*ctx
, TCGv_reg dest
, TCGv_reg t
)
538 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
539 tcg_gen_movcond_reg(ctx
->null_cond
.c
, dest
, ctx
->null_cond
.a0
,
540 ctx
->null_cond
.a1
, dest
, t
);
542 tcg_gen_mov_reg(dest
, t
);
546 static void save_gpr(DisasContext
*ctx
, unsigned reg
, TCGv_reg t
)
549 save_or_nullify(ctx
, cpu_gr
[reg
], t
);
561 static TCGv_i32
load_frw_i32(unsigned rt
)
563 TCGv_i32 ret
= tcg_temp_new_i32();
564 tcg_gen_ld_i32(ret
, cpu_env
,
565 offsetof(CPUHPPAState
, fr
[rt
& 31])
566 + (rt
& 32 ? LO_OFS
: HI_OFS
));
570 static TCGv_i32
load_frw0_i32(unsigned rt
)
573 TCGv_i32 ret
= tcg_temp_new_i32();
574 tcg_gen_movi_i32(ret
, 0);
577 return load_frw_i32(rt
);
581 static TCGv_i64
load_frw0_i64(unsigned rt
)
583 TCGv_i64 ret
= tcg_temp_new_i64();
585 tcg_gen_movi_i64(ret
, 0);
587 tcg_gen_ld32u_i64(ret
, cpu_env
,
588 offsetof(CPUHPPAState
, fr
[rt
& 31])
589 + (rt
& 32 ? LO_OFS
: HI_OFS
));
594 static void save_frw_i32(unsigned rt
, TCGv_i32 val
)
596 tcg_gen_st_i32(val
, cpu_env
,
597 offsetof(CPUHPPAState
, fr
[rt
& 31])
598 + (rt
& 32 ? LO_OFS
: HI_OFS
));
604 static TCGv_i64
load_frd(unsigned rt
)
606 TCGv_i64 ret
= tcg_temp_new_i64();
607 tcg_gen_ld_i64(ret
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
611 static TCGv_i64
load_frd0(unsigned rt
)
614 TCGv_i64 ret
= tcg_temp_new_i64();
615 tcg_gen_movi_i64(ret
, 0);
622 static void save_frd(unsigned rt
, TCGv_i64 val
)
624 tcg_gen_st_i64(val
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
627 static void load_spr(DisasContext
*ctx
, TCGv_i64 dest
, unsigned reg
)
629 #ifdef CONFIG_USER_ONLY
630 tcg_gen_movi_i64(dest
, 0);
633 tcg_gen_mov_i64(dest
, cpu_sr
[reg
]);
634 } else if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
635 tcg_gen_mov_i64(dest
, cpu_srH
);
637 tcg_gen_ld_i64(dest
, cpu_env
, offsetof(CPUHPPAState
, sr
[reg
]));
642 /* Skip over the implementation of an insn that has been nullified.
643 Use this when the insn is too complex for a conditional move. */
644 static void nullify_over(DisasContext
*ctx
)
646 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
647 /* The always condition should have been handled in the main loop. */
648 assert(ctx
->null_cond
.c
!= TCG_COND_ALWAYS
);
650 ctx
->null_lab
= gen_new_label();
652 /* If we're using PSW[N], copy it to a temp because... */
653 if (ctx
->null_cond
.a0
== cpu_psw_n
) {
654 ctx
->null_cond
.a0
= tcg_temp_new();
655 tcg_gen_mov_reg(ctx
->null_cond
.a0
, cpu_psw_n
);
657 /* ... we clear it before branching over the implementation,
658 so that (1) it's clear after nullifying this insn and
659 (2) if this insn nullifies the next, PSW[N] is valid. */
660 if (ctx
->psw_n_nonzero
) {
661 ctx
->psw_n_nonzero
= false;
662 tcg_gen_movi_reg(cpu_psw_n
, 0);
665 tcg_gen_brcond_reg(ctx
->null_cond
.c
, ctx
->null_cond
.a0
,
666 ctx
->null_cond
.a1
, ctx
->null_lab
);
667 cond_free(&ctx
->null_cond
);
671 /* Save the current nullification state to PSW[N]. */
672 static void nullify_save(DisasContext
*ctx
)
674 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
675 if (ctx
->psw_n_nonzero
) {
676 tcg_gen_movi_reg(cpu_psw_n
, 0);
680 if (ctx
->null_cond
.a0
!= cpu_psw_n
) {
681 tcg_gen_setcond_reg(ctx
->null_cond
.c
, cpu_psw_n
,
682 ctx
->null_cond
.a0
, ctx
->null_cond
.a1
);
683 ctx
->psw_n_nonzero
= true;
685 cond_free(&ctx
->null_cond
);
688 /* Set a PSW[N] to X. The intention is that this is used immediately
689 before a goto_tb/exit_tb, so that there is no fallthru path to other
690 code within the TB. Therefore we do not update psw_n_nonzero. */
691 static void nullify_set(DisasContext
*ctx
, bool x
)
693 if (ctx
->psw_n_nonzero
|| x
) {
694 tcg_gen_movi_reg(cpu_psw_n
, x
);
698 /* Mark the end of an instruction that may have been nullified.
699 This is the pair to nullify_over. Always returns true so that
700 it may be tail-called from a translate function. */
701 static bool nullify_end(DisasContext
*ctx
)
703 TCGLabel
*null_lab
= ctx
->null_lab
;
704 DisasJumpType status
= ctx
->base
.is_jmp
;
706 /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
707 For UPDATED, we cannot update on the nullified path. */
708 assert(status
!= DISAS_IAQ_N_UPDATED
);
710 if (likely(null_lab
== NULL
)) {
711 /* The current insn wasn't conditional or handled the condition
712 applied to it without a branch, so the (new) setting of
713 NULL_COND can be applied directly to the next insn. */
716 ctx
->null_lab
= NULL
;
718 if (likely(ctx
->null_cond
.c
== TCG_COND_NEVER
)) {
719 /* The next instruction will be unconditional,
720 and NULL_COND already reflects that. */
721 gen_set_label(null_lab
);
723 /* The insn that we just executed is itself nullifying the next
724 instruction. Store the condition in the PSW[N] global.
725 We asserted PSW[N] = 0 in nullify_over, so that after the
726 label we have the proper value in place. */
728 gen_set_label(null_lab
);
729 ctx
->null_cond
= cond_make_n();
731 if (status
== DISAS_NORETURN
) {
732 ctx
->base
.is_jmp
= DISAS_NEXT
;
737 static void copy_iaoq_entry(TCGv_reg dest
, target_ureg ival
, TCGv_reg vval
)
739 if (unlikely(ival
== -1)) {
740 tcg_gen_mov_reg(dest
, vval
);
742 tcg_gen_movi_reg(dest
, ival
);
746 static inline target_ureg
iaoq_dest(DisasContext
*ctx
, target_sreg disp
)
748 return ctx
->iaoq_f
+ disp
+ 8;
751 static void gen_excp_1(int exception
)
753 gen_helper_excp(cpu_env
, tcg_constant_i32(exception
));
756 static void gen_excp(DisasContext
*ctx
, int exception
)
758 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
759 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
761 gen_excp_1(exception
);
762 ctx
->base
.is_jmp
= DISAS_NORETURN
;
765 static bool gen_excp_iir(DisasContext
*ctx
, int exc
)
768 tcg_gen_st_reg(tcg_constant_reg(ctx
->insn
),
769 cpu_env
, offsetof(CPUHPPAState
, cr
[CR_IIR
]));
771 return nullify_end(ctx
);
774 static bool gen_illegal(DisasContext
*ctx
)
776 return gen_excp_iir(ctx
, EXCP_ILL
);
779 #ifdef CONFIG_USER_ONLY
780 #define CHECK_MOST_PRIVILEGED(EXCP) \
781 return gen_excp_iir(ctx, EXCP)
783 #define CHECK_MOST_PRIVILEGED(EXCP) \
785 if (ctx->privilege != 0) { \
786 return gen_excp_iir(ctx, EXCP); \
791 static bool use_goto_tb(DisasContext
*ctx
, target_ureg dest
)
793 return translator_use_goto_tb(&ctx
->base
, dest
);
796 /* If the next insn is to be nullified, and it's on the same page,
797 and we're not attempting to set a breakpoint on it, then we can
798 totally skip the nullified insn. This avoids creating and
799 executing a TB that merely branches to the next TB. */
800 static bool use_nullify_skip(DisasContext
*ctx
)
802 return (((ctx
->iaoq_b
^ ctx
->iaoq_f
) & TARGET_PAGE_MASK
) == 0
803 && !cpu_breakpoint_test(ctx
->cs
, ctx
->iaoq_b
, BP_ANY
));
806 static void gen_goto_tb(DisasContext
*ctx
, int which
,
807 target_ureg f
, target_ureg b
)
809 if (f
!= -1 && b
!= -1 && use_goto_tb(ctx
, f
)) {
810 tcg_gen_goto_tb(which
);
811 tcg_gen_movi_reg(cpu_iaoq_f
, f
);
812 tcg_gen_movi_reg(cpu_iaoq_b
, b
);
813 tcg_gen_exit_tb(ctx
->base
.tb
, which
);
815 copy_iaoq_entry(cpu_iaoq_f
, f
, cpu_iaoq_b
);
816 copy_iaoq_entry(cpu_iaoq_b
, b
, ctx
->iaoq_n_var
);
817 tcg_gen_lookup_and_goto_ptr();
821 static bool cond_need_sv(int c
)
823 return c
== 2 || c
== 3 || c
== 6;
826 static bool cond_need_cb(int c
)
828 return c
== 4 || c
== 5;
832 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
833 * the Parisc 1.1 Architecture Reference Manual for details.
836 static DisasCond
do_cond(unsigned cf
, TCGv_reg res
,
837 TCGv_reg cb_msb
, TCGv_reg sv
)
843 case 0: /* Never / TR (0 / 1) */
844 cond
= cond_make_f();
846 case 1: /* = / <> (Z / !Z) */
847 cond
= cond_make_0(TCG_COND_EQ
, res
);
849 case 2: /* < / >= (N ^ V / !(N ^ V) */
850 tmp
= tcg_temp_new();
851 tcg_gen_xor_reg(tmp
, res
, sv
);
852 cond
= cond_make_0_tmp(TCG_COND_LT
, tmp
);
854 case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
858 * ((res < 0) ^ (sv < 0)) | !res
859 * ((res ^ sv) < 0) | !res
860 * (~(res ^ sv) >= 0) | !res
861 * !(~(res ^ sv) >> 31) | !res
862 * !(~(res ^ sv) >> 31 & res)
864 tmp
= tcg_temp_new();
865 tcg_gen_eqv_reg(tmp
, res
, sv
);
866 tcg_gen_sari_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
867 tcg_gen_and_reg(tmp
, tmp
, res
);
868 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
870 case 4: /* NUV / UV (!C / C) */
871 cond
= cond_make_0(TCG_COND_EQ
, cb_msb
);
873 case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
874 tmp
= tcg_temp_new();
875 tcg_gen_neg_reg(tmp
, cb_msb
);
876 tcg_gen_and_reg(tmp
, tmp
, res
);
877 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
879 case 6: /* SV / NSV (V / !V) */
880 cond
= cond_make_0(TCG_COND_LT
, sv
);
882 case 7: /* OD / EV */
883 tmp
= tcg_temp_new();
884 tcg_gen_andi_reg(tmp
, res
, 1);
885 cond
= cond_make_0_tmp(TCG_COND_NE
, tmp
);
888 g_assert_not_reached();
891 cond
.c
= tcg_invert_cond(cond
.c
);
897 /* Similar, but for the special case of subtraction without borrow, we
898 can use the inputs directly. This can allow other computation to be
899 deleted as unused. */
901 static DisasCond
do_sub_cond(unsigned cf
, TCGv_reg res
,
902 TCGv_reg in1
, TCGv_reg in2
, TCGv_reg sv
)
908 cond
= cond_make(TCG_COND_EQ
, in1
, in2
);
911 cond
= cond_make(TCG_COND_LT
, in1
, in2
);
914 cond
= cond_make(TCG_COND_LE
, in1
, in2
);
916 case 4: /* << / >>= */
917 cond
= cond_make(TCG_COND_LTU
, in1
, in2
);
919 case 5: /* <<= / >> */
920 cond
= cond_make(TCG_COND_LEU
, in1
, in2
);
923 return do_cond(cf
, res
, NULL
, sv
);
926 cond
.c
= tcg_invert_cond(cond
.c
);
933 * Similar, but for logicals, where the carry and overflow bits are not
934 * computed, and use of them is undefined.
936 * Undefined or not, hardware does not trap. It seems reasonable to
937 * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
938 * how cases c={2,3} are treated.
941 static DisasCond
do_log_cond(unsigned cf
, TCGv_reg res
)
945 case 9: /* undef, C */
946 case 11: /* undef, C & !Z */
947 case 12: /* undef, V */
948 return cond_make_f();
951 case 8: /* undef, !C */
952 case 10: /* undef, !C | Z */
953 case 13: /* undef, !V */
954 return cond_make_t();
957 return cond_make_0(TCG_COND_EQ
, res
);
959 return cond_make_0(TCG_COND_NE
, res
);
961 return cond_make_0(TCG_COND_LT
, res
);
963 return cond_make_0(TCG_COND_GE
, res
);
965 return cond_make_0(TCG_COND_LE
, res
);
967 return cond_make_0(TCG_COND_GT
, res
);
971 return do_cond(cf
, res
, NULL
, NULL
);
974 g_assert_not_reached();
978 /* Similar, but for shift/extract/deposit conditions. */
980 static DisasCond
do_sed_cond(unsigned orig
, TCGv_reg res
)
984 /* Convert the compressed condition codes to standard.
985 0-2 are the same as logicals (nv,<,<=), while 3 is OD.
986 4-7 are the reverse of 0-3. */
993 return do_log_cond(c
* 2 + f
, res
);
996 /* Similar, but for unit conditions. */
998 static DisasCond
do_unit_cond(unsigned cf
, TCGv_reg res
,
999 TCGv_reg in1
, TCGv_reg in2
)
1002 TCGv_reg tmp
, cb
= NULL
;
1005 /* Since we want to test lots of carry-out bits all at once, do not
1006 * do our normal thing and compute carry-in of bit B+1 since that
1007 * leaves us with carry bits spread across two words.
1009 cb
= tcg_temp_new();
1010 tmp
= tcg_temp_new();
1011 tcg_gen_or_reg(cb
, in1
, in2
);
1012 tcg_gen_and_reg(tmp
, in1
, in2
);
1013 tcg_gen_andc_reg(cb
, cb
, res
);
1014 tcg_gen_or_reg(cb
, cb
, tmp
);
1018 case 0: /* never / TR */
1019 case 1: /* undefined */
1020 case 5: /* undefined */
1021 cond
= cond_make_f();
1024 case 2: /* SBZ / NBZ */
1025 /* See hasless(v,1) from
1026 * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
1028 tmp
= tcg_temp_new();
1029 tcg_gen_subi_reg(tmp
, res
, 0x01010101u
);
1030 tcg_gen_andc_reg(tmp
, tmp
, res
);
1031 tcg_gen_andi_reg(tmp
, tmp
, 0x80808080u
);
1032 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1035 case 3: /* SHZ / NHZ */
1036 tmp
= tcg_temp_new();
1037 tcg_gen_subi_reg(tmp
, res
, 0x00010001u
);
1038 tcg_gen_andc_reg(tmp
, tmp
, res
);
1039 tcg_gen_andi_reg(tmp
, tmp
, 0x80008000u
);
1040 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1043 case 4: /* SDC / NDC */
1044 tcg_gen_andi_reg(cb
, cb
, 0x88888888u
);
1045 cond
= cond_make_0(TCG_COND_NE
, cb
);
1048 case 6: /* SBC / NBC */
1049 tcg_gen_andi_reg(cb
, cb
, 0x80808080u
);
1050 cond
= cond_make_0(TCG_COND_NE
, cb
);
1053 case 7: /* SHC / NHC */
1054 tcg_gen_andi_reg(cb
, cb
, 0x80008000u
);
1055 cond
= cond_make_0(TCG_COND_NE
, cb
);
1059 g_assert_not_reached();
1062 cond
.c
= tcg_invert_cond(cond
.c
);
1068 /* Compute signed overflow for addition. */
1069 static TCGv_reg
do_add_sv(DisasContext
*ctx
, TCGv_reg res
,
1070 TCGv_reg in1
, TCGv_reg in2
)
1072 TCGv_reg sv
= get_temp(ctx
);
1073 TCGv_reg tmp
= tcg_temp_new();
1075 tcg_gen_xor_reg(sv
, res
, in1
);
1076 tcg_gen_xor_reg(tmp
, in1
, in2
);
1077 tcg_gen_andc_reg(sv
, sv
, tmp
);
1082 /* Compute signed overflow for subtraction. */
1083 static TCGv_reg
do_sub_sv(DisasContext
*ctx
, TCGv_reg res
,
1084 TCGv_reg in1
, TCGv_reg in2
)
1086 TCGv_reg sv
= get_temp(ctx
);
1087 TCGv_reg tmp
= tcg_temp_new();
1089 tcg_gen_xor_reg(sv
, res
, in1
);
1090 tcg_gen_xor_reg(tmp
, in1
, in2
);
1091 tcg_gen_and_reg(sv
, sv
, tmp
);
1096 static void do_add(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1097 TCGv_reg in2
, unsigned shift
, bool is_l
,
1098 bool is_tsv
, bool is_tc
, bool is_c
, unsigned cf
)
1100 TCGv_reg dest
, cb
, cb_msb
, sv
, tmp
;
1101 unsigned c
= cf
>> 1;
1104 dest
= tcg_temp_new();
1109 tmp
= get_temp(ctx
);
1110 tcg_gen_shli_reg(tmp
, in1
, shift
);
1114 if (!is_l
|| cond_need_cb(c
)) {
1115 TCGv_reg zero
= tcg_constant_reg(0);
1116 cb_msb
= get_temp(ctx
);
1117 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, in2
, zero
);
1119 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cpu_psw_cb_msb
, zero
);
1123 tcg_gen_xor_reg(cb
, in1
, in2
);
1124 tcg_gen_xor_reg(cb
, cb
, dest
);
1127 tcg_gen_add_reg(dest
, in1
, in2
);
1129 tcg_gen_add_reg(dest
, dest
, cpu_psw_cb_msb
);
1133 /* Compute signed overflow if required. */
1135 if (is_tsv
|| cond_need_sv(c
)) {
1136 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
1138 /* ??? Need to include overflow from shift. */
1139 gen_helper_tsv(cpu_env
, sv
);
1143 /* Emit any conditional trap before any writeback. */
1144 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1146 tmp
= tcg_temp_new();
1147 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1148 gen_helper_tcond(cpu_env
, tmp
);
1151 /* Write back the result. */
1153 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1154 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1156 save_gpr(ctx
, rt
, dest
);
1158 /* Install the new nullification. */
1159 cond_free(&ctx
->null_cond
);
1160 ctx
->null_cond
= cond
;
1163 static bool do_add_reg(DisasContext
*ctx
, arg_rrr_cf_sh
*a
,
1164 bool is_l
, bool is_tsv
, bool is_tc
, bool is_c
)
1166 TCGv_reg tcg_r1
, tcg_r2
;
1171 tcg_r1
= load_gpr(ctx
, a
->r1
);
1172 tcg_r2
= load_gpr(ctx
, a
->r2
);
1173 do_add(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->sh
, is_l
, is_tsv
, is_tc
, is_c
, a
->cf
);
1174 return nullify_end(ctx
);
1177 static bool do_add_imm(DisasContext
*ctx
, arg_rri_cf
*a
,
1178 bool is_tsv
, bool is_tc
)
1180 TCGv_reg tcg_im
, tcg_r2
;
1185 tcg_im
= load_const(ctx
, a
->i
);
1186 tcg_r2
= load_gpr(ctx
, a
->r
);
1187 do_add(ctx
, a
->t
, tcg_im
, tcg_r2
, 0, 0, is_tsv
, is_tc
, 0, a
->cf
);
1188 return nullify_end(ctx
);
1191 static void do_sub(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1192 TCGv_reg in2
, bool is_tsv
, bool is_b
,
1193 bool is_tc
, unsigned cf
)
1195 TCGv_reg dest
, sv
, cb
, cb_msb
, zero
, tmp
;
1196 unsigned c
= cf
>> 1;
1199 dest
= tcg_temp_new();
1200 cb
= tcg_temp_new();
1201 cb_msb
= tcg_temp_new();
1203 zero
= tcg_constant_reg(0);
1205 /* DEST,C = IN1 + ~IN2 + C. */
1206 tcg_gen_not_reg(cb
, in2
);
1207 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, cpu_psw_cb_msb
, zero
);
1208 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cb
, zero
);
1209 tcg_gen_xor_reg(cb
, cb
, in1
);
1210 tcg_gen_xor_reg(cb
, cb
, dest
);
1212 /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
1213 operations by seeding the high word with 1 and subtracting. */
1214 tcg_gen_movi_reg(cb_msb
, 1);
1215 tcg_gen_sub2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, zero
);
1216 tcg_gen_eqv_reg(cb
, in1
, in2
);
1217 tcg_gen_xor_reg(cb
, cb
, dest
);
1220 /* Compute signed overflow if required. */
1222 if (is_tsv
|| cond_need_sv(c
)) {
1223 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1225 gen_helper_tsv(cpu_env
, sv
);
1229 /* Compute the condition. We cannot use the special case for borrow. */
1231 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1233 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1236 /* Emit any conditional trap before any writeback. */
1238 tmp
= tcg_temp_new();
1239 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1240 gen_helper_tcond(cpu_env
, tmp
);
1243 /* Write back the result. */
1244 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1245 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1246 save_gpr(ctx
, rt
, dest
);
1248 /* Install the new nullification. */
1249 cond_free(&ctx
->null_cond
);
1250 ctx
->null_cond
= cond
;
1253 static bool do_sub_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1254 bool is_tsv
, bool is_b
, bool is_tc
)
1256 TCGv_reg tcg_r1
, tcg_r2
;
1261 tcg_r1
= load_gpr(ctx
, a
->r1
);
1262 tcg_r2
= load_gpr(ctx
, a
->r2
);
1263 do_sub(ctx
, a
->t
, tcg_r1
, tcg_r2
, is_tsv
, is_b
, is_tc
, a
->cf
);
1264 return nullify_end(ctx
);
1267 static bool do_sub_imm(DisasContext
*ctx
, arg_rri_cf
*a
, bool is_tsv
)
1269 TCGv_reg tcg_im
, tcg_r2
;
1274 tcg_im
= load_const(ctx
, a
->i
);
1275 tcg_r2
= load_gpr(ctx
, a
->r
);
1276 do_sub(ctx
, a
->t
, tcg_im
, tcg_r2
, is_tsv
, 0, 0, a
->cf
);
1277 return nullify_end(ctx
);
1280 static void do_cmpclr(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1281 TCGv_reg in2
, unsigned cf
)
1286 dest
= tcg_temp_new();
1287 tcg_gen_sub_reg(dest
, in1
, in2
);
1289 /* Compute signed overflow if required. */
1291 if (cond_need_sv(cf
>> 1)) {
1292 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1295 /* Form the condition for the compare. */
1296 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1299 tcg_gen_movi_reg(dest
, 0);
1300 save_gpr(ctx
, rt
, dest
);
1302 /* Install the new nullification. */
1303 cond_free(&ctx
->null_cond
);
1304 ctx
->null_cond
= cond
;
1307 static void do_log(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1308 TCGv_reg in2
, unsigned cf
,
1309 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1311 TCGv_reg dest
= dest_gpr(ctx
, rt
);
1313 /* Perform the operation, and writeback. */
1315 save_gpr(ctx
, rt
, dest
);
1317 /* Install the new nullification. */
1318 cond_free(&ctx
->null_cond
);
1320 ctx
->null_cond
= do_log_cond(cf
, dest
);
1324 static bool do_log_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1325 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1327 TCGv_reg tcg_r1
, tcg_r2
;
1332 tcg_r1
= load_gpr(ctx
, a
->r1
);
1333 tcg_r2
= load_gpr(ctx
, a
->r2
);
1334 do_log(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, fn
);
1335 return nullify_end(ctx
);
1338 static void do_unit(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1339 TCGv_reg in2
, unsigned cf
, bool is_tc
,
1340 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1346 dest
= dest_gpr(ctx
, rt
);
1348 save_gpr(ctx
, rt
, dest
);
1349 cond_free(&ctx
->null_cond
);
1351 dest
= tcg_temp_new();
1354 cond
= do_unit_cond(cf
, dest
, in1
, in2
);
1357 TCGv_reg tmp
= tcg_temp_new();
1358 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1359 gen_helper_tcond(cpu_env
, tmp
);
1361 save_gpr(ctx
, rt
, dest
);
1363 cond_free(&ctx
->null_cond
);
1364 ctx
->null_cond
= cond
;
1368 #ifndef CONFIG_USER_ONLY
1369 /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
1370 from the top 2 bits of the base register. There are a few system
1371 instructions that have a 3-bit space specifier, for which SR0 is
1372 not special. To handle this, pass ~SP. */
1373 static TCGv_i64
space_select(DisasContext
*ctx
, int sp
, TCGv_reg base
)
1383 spc
= get_temp_tl(ctx
);
1384 load_spr(ctx
, spc
, sp
);
1387 if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
1391 ptr
= tcg_temp_new_ptr();
1392 tmp
= tcg_temp_new();
1393 spc
= get_temp_tl(ctx
);
1395 tcg_gen_shri_reg(tmp
, base
, TARGET_REGISTER_BITS
- 5);
1396 tcg_gen_andi_reg(tmp
, tmp
, 030);
1397 tcg_gen_trunc_reg_ptr(ptr
, tmp
);
1399 tcg_gen_add_ptr(ptr
, ptr
, cpu_env
);
1400 tcg_gen_ld_i64(spc
, ptr
, offsetof(CPUHPPAState
, sr
[4]));
1406 static void form_gva(DisasContext
*ctx
, TCGv_tl
*pgva
, TCGv_reg
*pofs
,
1407 unsigned rb
, unsigned rx
, int scale
, target_sreg disp
,
1408 unsigned sp
, int modify
, bool is_phys
)
1410 TCGv_reg base
= load_gpr(ctx
, rb
);
1413 /* Note that RX is mutually exclusive with DISP. */
1415 ofs
= get_temp(ctx
);
1416 tcg_gen_shli_reg(ofs
, cpu_gr
[rx
], scale
);
1417 tcg_gen_add_reg(ofs
, ofs
, base
);
1418 } else if (disp
|| modify
) {
1419 ofs
= get_temp(ctx
);
1420 tcg_gen_addi_reg(ofs
, base
, disp
);
1426 #ifdef CONFIG_USER_ONLY
1427 *pgva
= (modify
<= 0 ? ofs
: base
);
1429 TCGv_tl addr
= get_temp_tl(ctx
);
1430 tcg_gen_extu_reg_tl(addr
, modify
<= 0 ? ofs
: base
);
1431 if (ctx
->tb_flags
& PSW_W
) {
1432 tcg_gen_andi_tl(addr
, addr
, 0x3fffffffffffffffull
);
1435 tcg_gen_or_tl(addr
, addr
, space_select(ctx
, sp
, base
));
1441 /* Emit a memory load. The modify parameter should be
1442 * < 0 for pre-modify,
1443 * > 0 for post-modify,
1444 * = 0 for no base register update.
1446 static void do_load_32(DisasContext
*ctx
, TCGv_i32 dest
, unsigned rb
,
1447 unsigned rx
, int scale
, target_sreg disp
,
1448 unsigned sp
, int modify
, MemOp mop
)
1453 /* Caller uses nullify_over/nullify_end. */
1454 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1456 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1457 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1458 tcg_gen_qemu_ld_reg(dest
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1460 save_gpr(ctx
, rb
, ofs
);
1464 static void do_load_64(DisasContext
*ctx
, TCGv_i64 dest
, unsigned rb
,
1465 unsigned rx
, int scale
, target_sreg disp
,
1466 unsigned sp
, int modify
, MemOp mop
)
1471 /* Caller uses nullify_over/nullify_end. */
1472 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1474 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1475 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1476 tcg_gen_qemu_ld_i64(dest
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1478 save_gpr(ctx
, rb
, ofs
);
1482 static void do_store_32(DisasContext
*ctx
, TCGv_i32 src
, unsigned rb
,
1483 unsigned rx
, int scale
, target_sreg disp
,
1484 unsigned sp
, int modify
, MemOp mop
)
1489 /* Caller uses nullify_over/nullify_end. */
1490 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1492 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1493 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1494 tcg_gen_qemu_st_i32(src
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1496 save_gpr(ctx
, rb
, ofs
);
1500 static void do_store_64(DisasContext
*ctx
, TCGv_i64 src
, unsigned rb
,
1501 unsigned rx
, int scale
, target_sreg disp
,
1502 unsigned sp
, int modify
, MemOp mop
)
1507 /* Caller uses nullify_over/nullify_end. */
1508 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1510 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1511 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1512 tcg_gen_qemu_st_i64(src
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1514 save_gpr(ctx
, rb
, ofs
);
1518 #if TARGET_REGISTER_BITS == 64
1519 #define do_load_reg do_load_64
1520 #define do_store_reg do_store_64
1522 #define do_load_reg do_load_32
1523 #define do_store_reg do_store_32
1526 static bool do_load(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1527 unsigned rx
, int scale
, target_sreg disp
,
1528 unsigned sp
, int modify
, MemOp mop
)
1535 /* No base register update. */
1536 dest
= dest_gpr(ctx
, rt
);
1538 /* Make sure if RT == RB, we see the result of the load. */
1539 dest
= get_temp(ctx
);
1541 do_load_reg(ctx
, dest
, rb
, rx
, scale
, disp
, sp
, modify
, mop
);
1542 save_gpr(ctx
, rt
, dest
);
1544 return nullify_end(ctx
);
1547 static bool do_floadw(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1548 unsigned rx
, int scale
, target_sreg disp
,
1549 unsigned sp
, int modify
)
1555 tmp
= tcg_temp_new_i32();
1556 do_load_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1557 save_frw_i32(rt
, tmp
);
1560 gen_helper_loaded_fr0(cpu_env
);
1563 return nullify_end(ctx
);
1566 static bool trans_fldw(DisasContext
*ctx
, arg_ldst
*a
)
1568 return do_floadw(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1569 a
->disp
, a
->sp
, a
->m
);
1572 static bool do_floadd(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1573 unsigned rx
, int scale
, target_sreg disp
,
1574 unsigned sp
, int modify
)
1580 tmp
= tcg_temp_new_i64();
1581 do_load_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUQ
);
1585 gen_helper_loaded_fr0(cpu_env
);
1588 return nullify_end(ctx
);
1591 static bool trans_fldd(DisasContext
*ctx
, arg_ldst
*a
)
1593 return do_floadd(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1594 a
->disp
, a
->sp
, a
->m
);
1597 static bool do_store(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1598 target_sreg disp
, unsigned sp
,
1599 int modify
, MemOp mop
)
1602 do_store_reg(ctx
, load_gpr(ctx
, rt
), rb
, 0, 0, disp
, sp
, modify
, mop
);
1603 return nullify_end(ctx
);
1606 static bool do_fstorew(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1607 unsigned rx
, int scale
, target_sreg disp
,
1608 unsigned sp
, int modify
)
1614 tmp
= load_frw_i32(rt
);
1615 do_store_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1617 return nullify_end(ctx
);
1620 static bool trans_fstw(DisasContext
*ctx
, arg_ldst
*a
)
1622 return do_fstorew(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1623 a
->disp
, a
->sp
, a
->m
);
1626 static bool do_fstored(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1627 unsigned rx
, int scale
, target_sreg disp
,
1628 unsigned sp
, int modify
)
1635 do_store_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUQ
);
1637 return nullify_end(ctx
);
1640 static bool trans_fstd(DisasContext
*ctx
, arg_ldst
*a
)
1642 return do_fstored(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1643 a
->disp
, a
->sp
, a
->m
);
1646 static bool do_fop_wew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1647 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
))
1652 tmp
= load_frw0_i32(ra
);
1654 func(tmp
, cpu_env
, tmp
);
1656 save_frw_i32(rt
, tmp
);
1657 return nullify_end(ctx
);
1660 static bool do_fop_wed(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1661 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i64
))
1668 dst
= tcg_temp_new_i32();
1670 func(dst
, cpu_env
, src
);
1672 save_frw_i32(rt
, dst
);
1673 return nullify_end(ctx
);
1676 static bool do_fop_ded(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1677 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
1682 tmp
= load_frd0(ra
);
1684 func(tmp
, cpu_env
, tmp
);
1687 return nullify_end(ctx
);
1690 static bool do_fop_dew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1691 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i32
))
1697 src
= load_frw0_i32(ra
);
1698 dst
= tcg_temp_new_i64();
1700 func(dst
, cpu_env
, src
);
1703 return nullify_end(ctx
);
1706 static bool do_fop_weww(DisasContext
*ctx
, unsigned rt
,
1707 unsigned ra
, unsigned rb
,
1708 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
1713 a
= load_frw0_i32(ra
);
1714 b
= load_frw0_i32(rb
);
1716 func(a
, cpu_env
, a
, b
);
1718 save_frw_i32(rt
, a
);
1719 return nullify_end(ctx
);
1722 static bool do_fop_dedd(DisasContext
*ctx
, unsigned rt
,
1723 unsigned ra
, unsigned rb
,
1724 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
1732 func(a
, cpu_env
, a
, b
);
1735 return nullify_end(ctx
);
1738 /* Emit an unconditional branch to a direct target, which may or may not
1739 have already had nullification handled. */
1740 static bool do_dbranch(DisasContext
*ctx
, target_ureg dest
,
1741 unsigned link
, bool is_n
)
1743 if (ctx
->null_cond
.c
== TCG_COND_NEVER
&& ctx
->null_lab
== NULL
) {
1745 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1749 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1755 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1758 if (is_n
&& use_nullify_skip(ctx
)) {
1759 nullify_set(ctx
, 0);
1760 gen_goto_tb(ctx
, 0, dest
, dest
+ 4);
1762 nullify_set(ctx
, is_n
);
1763 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, dest
);
1768 nullify_set(ctx
, 0);
1769 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, ctx
->iaoq_n
);
1770 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1775 /* Emit a conditional branch to a direct target. If the branch itself
1776 is nullified, we should have already used nullify_over. */
1777 static bool do_cbranch(DisasContext
*ctx
, target_sreg disp
, bool is_n
,
1780 target_ureg dest
= iaoq_dest(ctx
, disp
);
1781 TCGLabel
*taken
= NULL
;
1782 TCGCond c
= cond
->c
;
1785 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1787 /* Handle TRUE and NEVER as direct branches. */
1788 if (c
== TCG_COND_ALWAYS
) {
1789 return do_dbranch(ctx
, dest
, 0, is_n
&& disp
>= 0);
1791 if (c
== TCG_COND_NEVER
) {
1792 return do_dbranch(ctx
, ctx
->iaoq_n
, 0, is_n
&& disp
< 0);
1795 taken
= gen_new_label();
1796 tcg_gen_brcond_reg(c
, cond
->a0
, cond
->a1
, taken
);
1799 /* Not taken: Condition not satisfied; nullify on backward branches. */
1800 n
= is_n
&& disp
< 0;
1801 if (n
&& use_nullify_skip(ctx
)) {
1802 nullify_set(ctx
, 0);
1803 gen_goto_tb(ctx
, 0, ctx
->iaoq_n
, ctx
->iaoq_n
+ 4);
1805 if (!n
&& ctx
->null_lab
) {
1806 gen_set_label(ctx
->null_lab
);
1807 ctx
->null_lab
= NULL
;
1809 nullify_set(ctx
, n
);
1810 if (ctx
->iaoq_n
== -1) {
1811 /* The temporary iaoq_n_var died at the branch above.
1812 Regenerate it here instead of saving it. */
1813 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
1815 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
1818 gen_set_label(taken
);
1820 /* Taken: Condition satisfied; nullify on forward branches. */
1821 n
= is_n
&& disp
>= 0;
1822 if (n
&& use_nullify_skip(ctx
)) {
1823 nullify_set(ctx
, 0);
1824 gen_goto_tb(ctx
, 1, dest
, dest
+ 4);
1826 nullify_set(ctx
, n
);
1827 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, dest
);
1830 /* Not taken: the branch itself was nullified. */
1831 if (ctx
->null_lab
) {
1832 gen_set_label(ctx
->null_lab
);
1833 ctx
->null_lab
= NULL
;
1834 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
1836 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1841 /* Emit an unconditional branch to an indirect target. This handles
1842 nullification of the branch itself. */
1843 static bool do_ibranch(DisasContext
*ctx
, TCGv_reg dest
,
1844 unsigned link
, bool is_n
)
1846 TCGv_reg a0
, a1
, next
, tmp
;
1849 assert(ctx
->null_lab
== NULL
);
1851 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
1853 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1855 next
= get_temp(ctx
);
1856 tcg_gen_mov_reg(next
, dest
);
1858 if (use_nullify_skip(ctx
)) {
1859 tcg_gen_mov_reg(cpu_iaoq_f
, next
);
1860 tcg_gen_addi_reg(cpu_iaoq_b
, next
, 4);
1861 nullify_set(ctx
, 0);
1862 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
1865 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1868 ctx
->iaoq_n_var
= next
;
1869 } else if (is_n
&& use_nullify_skip(ctx
)) {
1870 /* The (conditional) branch, B, nullifies the next insn, N,
1871 and we're allowed to skip execution N (no single-step or
1872 tracepoint in effect). Since the goto_ptr that we must use
1873 for the indirect branch consumes no special resources, we
1874 can (conditionally) skip B and continue execution. */
1875 /* The use_nullify_skip test implies we have a known control path. */
1876 tcg_debug_assert(ctx
->iaoq_b
!= -1);
1877 tcg_debug_assert(ctx
->iaoq_n
!= -1);
1879 /* We do have to handle the non-local temporary, DEST, before
1880 branching. Since IOAQ_F is not really live at this point, we
1881 can simply store DEST optimistically. Similarly with IAOQ_B. */
1882 tcg_gen_mov_reg(cpu_iaoq_f
, dest
);
1883 tcg_gen_addi_reg(cpu_iaoq_b
, dest
, 4);
1887 tcg_gen_movi_reg(cpu_gr
[link
], ctx
->iaoq_n
);
1889 tcg_gen_lookup_and_goto_ptr();
1890 return nullify_end(ctx
);
1892 c
= ctx
->null_cond
.c
;
1893 a0
= ctx
->null_cond
.a0
;
1894 a1
= ctx
->null_cond
.a1
;
1896 tmp
= tcg_temp_new();
1897 next
= get_temp(ctx
);
1899 copy_iaoq_entry(tmp
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1900 tcg_gen_movcond_reg(c
, next
, a0
, a1
, tmp
, dest
);
1902 ctx
->iaoq_n_var
= next
;
1905 tcg_gen_movcond_reg(c
, cpu_gr
[link
], a0
, a1
, cpu_gr
[link
], tmp
);
1909 /* The branch nullifies the next insn, which means the state of N
1910 after the branch is the inverse of the state of N that applied
1912 tcg_gen_setcond_reg(tcg_invert_cond(c
), cpu_psw_n
, a0
, a1
);
1913 cond_free(&ctx
->null_cond
);
1914 ctx
->null_cond
= cond_make_n();
1915 ctx
->psw_n_nonzero
= true;
1917 cond_free(&ctx
->null_cond
);
1924 * if (IAOQ_Front{30..31} < GR[b]{30..31})
1925 * IAOQ_Next{30..31} ← GR[b]{30..31};
1927 * IAOQ_Next{30..31} ← IAOQ_Front{30..31};
1928 * which keeps the privilege level from being increased.
1930 static TCGv_reg
do_ibranch_priv(DisasContext
*ctx
, TCGv_reg offset
)
1933 switch (ctx
->privilege
) {
1935 /* Privilege 0 is maximum and is allowed to decrease. */
1938 /* Privilege 3 is minimum and is never allowed to increase. */
1939 dest
= get_temp(ctx
);
1940 tcg_gen_ori_reg(dest
, offset
, 3);
1943 dest
= get_temp(ctx
);
1944 tcg_gen_andi_reg(dest
, offset
, -4);
1945 tcg_gen_ori_reg(dest
, dest
, ctx
->privilege
);
1946 tcg_gen_movcond_reg(TCG_COND_GTU
, dest
, dest
, offset
, dest
, offset
);
1952 #ifdef CONFIG_USER_ONLY
1953 /* On Linux, page zero is normally marked execute only + gateway.
1954 Therefore normal read or write is supposed to fail, but specific
1955 offsets have kernel code mapped to raise permissions to implement
1956 system calls. Handling this via an explicit check here, rather
1957 in than the "be disp(sr2,r0)" instruction that probably sent us
1958 here, is the easiest way to handle the branch delay slot on the
1959 aforementioned BE. */
1960 static void do_page_zero(DisasContext
*ctx
)
1962 /* If by some means we get here with PSW[N]=1, that implies that
1963 the B,GATE instruction would be skipped, and we'd fault on the
1964 next insn within the privilaged page. */
1965 switch (ctx
->null_cond
.c
) {
1966 case TCG_COND_NEVER
:
1968 case TCG_COND_ALWAYS
:
1969 tcg_gen_movi_reg(cpu_psw_n
, 0);
1972 /* Since this is always the first (and only) insn within the
1973 TB, we should know the state of PSW[N] from TB->FLAGS. */
1974 g_assert_not_reached();
1977 /* Check that we didn't arrive here via some means that allowed
1978 non-sequential instruction execution. Normally the PSW[B] bit
1979 detects this by disallowing the B,GATE instruction to execute
1980 under such conditions. */
1981 if (ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
1985 switch (ctx
->iaoq_f
& -4) {
1986 case 0x00: /* Null pointer call */
1987 gen_excp_1(EXCP_IMP
);
1988 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1991 case 0xb0: /* LWS */
1992 gen_excp_1(EXCP_SYSCALL_LWS
);
1993 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1996 case 0xe0: /* SET_THREAD_POINTER */
1997 tcg_gen_st_reg(cpu_gr
[26], cpu_env
, offsetof(CPUHPPAState
, cr
[27]));
1998 tcg_gen_ori_reg(cpu_iaoq_f
, cpu_gr
[31], 3);
1999 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
2000 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
2003 case 0x100: /* SYSCALL */
2004 gen_excp_1(EXCP_SYSCALL
);
2005 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2010 gen_excp_1(EXCP_ILL
);
2011 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2017 static bool trans_nop(DisasContext
*ctx
, arg_nop
*a
)
2019 cond_free(&ctx
->null_cond
);
2023 static bool trans_break(DisasContext
*ctx
, arg_break
*a
)
2025 return gen_excp_iir(ctx
, EXCP_BREAK
);
2028 static bool trans_sync(DisasContext
*ctx
, arg_sync
*a
)
2030 /* No point in nullifying the memory barrier. */
2031 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
2033 cond_free(&ctx
->null_cond
);
2037 static bool trans_mfia(DisasContext
*ctx
, arg_mfia
*a
)
2040 TCGv_reg tmp
= dest_gpr(ctx
, rt
);
2041 tcg_gen_movi_reg(tmp
, ctx
->iaoq_f
);
2042 save_gpr(ctx
, rt
, tmp
);
2044 cond_free(&ctx
->null_cond
);
2048 static bool trans_mfsp(DisasContext
*ctx
, arg_mfsp
*a
)
2051 unsigned rs
= a
->sp
;
2052 TCGv_i64 t0
= tcg_temp_new_i64();
2053 TCGv_reg t1
= tcg_temp_new();
2055 load_spr(ctx
, t0
, rs
);
2056 tcg_gen_shri_i64(t0
, t0
, 32);
2057 tcg_gen_trunc_i64_reg(t1
, t0
);
2059 save_gpr(ctx
, rt
, t1
);
2061 cond_free(&ctx
->null_cond
);
2065 static bool trans_mfctl(DisasContext
*ctx
, arg_mfctl
*a
)
2068 unsigned ctl
= a
->r
;
2073 #ifdef TARGET_HPPA64
2075 /* MFSAR without ,W masks low 5 bits. */
2076 tmp
= dest_gpr(ctx
, rt
);
2077 tcg_gen_andi_reg(tmp
, cpu_sar
, 31);
2078 save_gpr(ctx
, rt
, tmp
);
2082 save_gpr(ctx
, rt
, cpu_sar
);
2084 case CR_IT
: /* Interval Timer */
2085 /* FIXME: Respect PSW_S bit. */
2087 tmp
= dest_gpr(ctx
, rt
);
2088 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
2090 gen_helper_read_interval_timer(tmp
);
2091 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2093 gen_helper_read_interval_timer(tmp
);
2095 save_gpr(ctx
, rt
, tmp
);
2096 return nullify_end(ctx
);
2101 /* All other control registers are privileged. */
2102 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2106 tmp
= get_temp(ctx
);
2107 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2108 save_gpr(ctx
, rt
, tmp
);
2111 cond_free(&ctx
->null_cond
);
2115 static bool trans_mtsp(DisasContext
*ctx
, arg_mtsp
*a
)
2118 unsigned rs
= a
->sp
;
2122 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2126 t64
= tcg_temp_new_i64();
2127 tcg_gen_extu_reg_i64(t64
, load_gpr(ctx
, rr
));
2128 tcg_gen_shli_i64(t64
, t64
, 32);
2131 tcg_gen_st_i64(t64
, cpu_env
, offsetof(CPUHPPAState
, sr
[rs
]));
2132 ctx
->tb_flags
&= ~TB_FLAG_SR_SAME
;
2134 tcg_gen_mov_i64(cpu_sr
[rs
], t64
);
2137 return nullify_end(ctx
);
2140 static bool trans_mtctl(DisasContext
*ctx
, arg_mtctl
*a
)
2142 unsigned ctl
= a
->t
;
2146 if (ctl
== CR_SAR
) {
2147 reg
= load_gpr(ctx
, a
->r
);
2148 tmp
= tcg_temp_new();
2149 tcg_gen_andi_reg(tmp
, reg
, TARGET_REGISTER_BITS
- 1);
2150 save_or_nullify(ctx
, cpu_sar
, tmp
);
2152 cond_free(&ctx
->null_cond
);
2156 /* All other control registers are privileged or read-only. */
2157 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2159 #ifndef CONFIG_USER_ONLY
2161 reg
= load_gpr(ctx
, a
->r
);
2165 gen_helper_write_interval_timer(cpu_env
, reg
);
2168 gen_helper_write_eirr(cpu_env
, reg
);
2171 gen_helper_write_eiem(cpu_env
, reg
);
2172 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2177 /* FIXME: Respect PSW_Q bit */
2178 /* The write advances the queue and stores to the back element. */
2179 tmp
= get_temp(ctx
);
2180 tcg_gen_ld_reg(tmp
, cpu_env
,
2181 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2182 tcg_gen_st_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2183 tcg_gen_st_reg(reg
, cpu_env
,
2184 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2191 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2192 #ifndef CONFIG_USER_ONLY
2193 gen_helper_change_prot_id(cpu_env
);
2198 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2201 return nullify_end(ctx
);
2205 static bool trans_mtsarcm(DisasContext
*ctx
, arg_mtsarcm
*a
)
2207 TCGv_reg tmp
= tcg_temp_new();
2209 tcg_gen_not_reg(tmp
, load_gpr(ctx
, a
->r
));
2210 tcg_gen_andi_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
2211 save_or_nullify(ctx
, cpu_sar
, tmp
);
2213 cond_free(&ctx
->null_cond
);
2217 static bool trans_ldsid(DisasContext
*ctx
, arg_ldsid
*a
)
2219 TCGv_reg dest
= dest_gpr(ctx
, a
->t
);
2221 #ifdef CONFIG_USER_ONLY
2222 /* We don't implement space registers in user mode. */
2223 tcg_gen_movi_reg(dest
, 0);
2225 TCGv_i64 t0
= tcg_temp_new_i64();
2227 tcg_gen_mov_i64(t0
, space_select(ctx
, a
->sp
, load_gpr(ctx
, a
->b
)));
2228 tcg_gen_shri_i64(t0
, t0
, 32);
2229 tcg_gen_trunc_i64_reg(dest
, t0
);
2231 save_gpr(ctx
, a
->t
, dest
);
2233 cond_free(&ctx
->null_cond
);
2237 static bool trans_rsm(DisasContext
*ctx
, arg_rsm
*a
)
2239 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2240 #ifndef CONFIG_USER_ONLY
2245 tmp
= get_temp(ctx
);
2246 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2247 tcg_gen_andi_reg(tmp
, tmp
, ~a
->i
);
2248 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2249 save_gpr(ctx
, a
->t
, tmp
);
2251 /* Exit the TB to recognize new interrupts, e.g. PSW_M. */
2252 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2253 return nullify_end(ctx
);
2257 static bool trans_ssm(DisasContext
*ctx
, arg_ssm
*a
)
2259 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2260 #ifndef CONFIG_USER_ONLY
2265 tmp
= get_temp(ctx
);
2266 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2267 tcg_gen_ori_reg(tmp
, tmp
, a
->i
);
2268 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2269 save_gpr(ctx
, a
->t
, tmp
);
2271 /* Exit the TB to recognize new interrupts, e.g. PSW_I. */
2272 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2273 return nullify_end(ctx
);
2277 static bool trans_mtsm(DisasContext
*ctx
, arg_mtsm
*a
)
2279 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2280 #ifndef CONFIG_USER_ONLY
2284 reg
= load_gpr(ctx
, a
->r
);
2285 tmp
= get_temp(ctx
);
2286 gen_helper_swap_system_mask(tmp
, cpu_env
, reg
);
2288 /* Exit the TB to recognize new interrupts. */
2289 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2290 return nullify_end(ctx
);
2294 static bool do_rfi(DisasContext
*ctx
, bool rfi_r
)
2296 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2297 #ifndef CONFIG_USER_ONLY
2301 gen_helper_rfi_r(cpu_env
);
2303 gen_helper_rfi(cpu_env
);
2305 /* Exit the TB to recognize new interrupts. */
2306 tcg_gen_exit_tb(NULL
, 0);
2307 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2309 return nullify_end(ctx
);
2313 static bool trans_rfi(DisasContext
*ctx
, arg_rfi
*a
)
2315 return do_rfi(ctx
, false);
2318 static bool trans_rfi_r(DisasContext
*ctx
, arg_rfi_r
*a
)
2320 return do_rfi(ctx
, true);
2323 static bool trans_halt(DisasContext
*ctx
, arg_halt
*a
)
2325 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2326 #ifndef CONFIG_USER_ONLY
2328 gen_helper_halt(cpu_env
);
2329 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2330 return nullify_end(ctx
);
2334 static bool trans_reset(DisasContext
*ctx
, arg_reset
*a
)
2336 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2337 #ifndef CONFIG_USER_ONLY
2339 gen_helper_reset(cpu_env
);
2340 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2341 return nullify_end(ctx
);
2345 static bool trans_getshadowregs(DisasContext
*ctx
, arg_getshadowregs
*a
)
2347 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2348 #ifndef CONFIG_USER_ONLY
2350 gen_helper_getshadowregs(cpu_env
);
2351 return nullify_end(ctx
);
2355 static bool trans_nop_addrx(DisasContext
*ctx
, arg_ldst
*a
)
2358 TCGv_reg dest
= dest_gpr(ctx
, a
->b
);
2359 TCGv_reg src1
= load_gpr(ctx
, a
->b
);
2360 TCGv_reg src2
= load_gpr(ctx
, a
->x
);
2362 /* The only thing we need to do is the base register modification. */
2363 tcg_gen_add_reg(dest
, src1
, src2
);
2364 save_gpr(ctx
, a
->b
, dest
);
2366 cond_free(&ctx
->null_cond
);
2370 static bool trans_probe(DisasContext
*ctx
, arg_probe
*a
)
2373 TCGv_i32 level
, want
;
2378 dest
= dest_gpr(ctx
, a
->t
);
2379 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2382 level
= tcg_constant_i32(a
->ri
);
2384 level
= tcg_temp_new_i32();
2385 tcg_gen_trunc_reg_i32(level
, load_gpr(ctx
, a
->ri
));
2386 tcg_gen_andi_i32(level
, level
, 3);
2388 want
= tcg_constant_i32(a
->write
? PAGE_WRITE
: PAGE_READ
);
2390 gen_helper_probe(dest
, cpu_env
, addr
, level
, want
);
2392 save_gpr(ctx
, a
->t
, dest
);
2393 return nullify_end(ctx
);
2396 static bool trans_ixtlbx(DisasContext
*ctx
, arg_ixtlbx
*a
)
2398 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2399 #ifndef CONFIG_USER_ONLY
2405 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2406 reg
= load_gpr(ctx
, a
->r
);
2408 gen_helper_itlba(cpu_env
, addr
, reg
);
2410 gen_helper_itlbp(cpu_env
, addr
, reg
);
2413 /* Exit TB for TLB change if mmu is enabled. */
2414 if (ctx
->tb_flags
& PSW_C
) {
2415 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2417 return nullify_end(ctx
);
2421 static bool trans_pxtlbx(DisasContext
*ctx
, arg_pxtlbx
*a
)
2423 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2424 #ifndef CONFIG_USER_ONLY
2430 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2432 save_gpr(ctx
, a
->b
, ofs
);
2435 gen_helper_ptlbe(cpu_env
);
2437 gen_helper_ptlb(cpu_env
, addr
);
2440 /* Exit TB for TLB change if mmu is enabled. */
2441 if (ctx
->tb_flags
& PSW_C
) {
2442 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2444 return nullify_end(ctx
);
2449 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2451 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2452 * page 13-9 (195/206)
2454 static bool trans_ixtlbxf(DisasContext
*ctx
, arg_ixtlbxf
*a
)
2456 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2457 #ifndef CONFIG_USER_ONLY
2458 TCGv_tl addr
, atl
, stl
;
2465 * if (not (pcxl or pcxl2))
2466 * return gen_illegal(ctx);
2468 * Note for future: these are 32-bit systems; no hppa64.
2471 atl
= tcg_temp_new_tl();
2472 stl
= tcg_temp_new_tl();
2473 addr
= tcg_temp_new_tl();
2475 tcg_gen_ld32u_i64(stl
, cpu_env
,
2476 a
->data
? offsetof(CPUHPPAState
, cr
[CR_ISR
])
2477 : offsetof(CPUHPPAState
, cr
[CR_IIASQ
]));
2478 tcg_gen_ld32u_i64(atl
, cpu_env
,
2479 a
->data
? offsetof(CPUHPPAState
, cr
[CR_IOR
])
2480 : offsetof(CPUHPPAState
, cr
[CR_IIAOQ
]));
2481 tcg_gen_shli_i64(stl
, stl
, 32);
2482 tcg_gen_or_tl(addr
, atl
, stl
);
2484 reg
= load_gpr(ctx
, a
->r
);
2486 gen_helper_itlba(cpu_env
, addr
, reg
);
2488 gen_helper_itlbp(cpu_env
, addr
, reg
);
2491 /* Exit TB for TLB change if mmu is enabled. */
2492 if (ctx
->tb_flags
& PSW_C
) {
2493 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2495 return nullify_end(ctx
);
2499 static bool trans_lpa(DisasContext
*ctx
, arg_ldst
*a
)
2501 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2502 #ifndef CONFIG_USER_ONLY
2504 TCGv_reg ofs
, paddr
;
2508 form_gva(ctx
, &vaddr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2510 paddr
= tcg_temp_new();
2511 gen_helper_lpa(paddr
, cpu_env
, vaddr
);
2513 /* Note that physical address result overrides base modification. */
2515 save_gpr(ctx
, a
->b
, ofs
);
2517 save_gpr(ctx
, a
->t
, paddr
);
2519 return nullify_end(ctx
);
2523 static bool trans_lci(DisasContext
*ctx
, arg_lci
*a
)
2525 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2527 /* The Coherence Index is an implementation-defined function of the
2528 physical address. Two addresses with the same CI have a coherent
2529 view of the cache. Our implementation is to return 0 for all,
2530 since the entire address space is coherent. */
2531 save_gpr(ctx
, a
->t
, tcg_constant_reg(0));
2533 cond_free(&ctx
->null_cond
);
2537 static bool trans_add(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2539 return do_add_reg(ctx
, a
, false, false, false, false);
2542 static bool trans_add_l(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2544 return do_add_reg(ctx
, a
, true, false, false, false);
2547 static bool trans_add_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2549 return do_add_reg(ctx
, a
, false, true, false, false);
2552 static bool trans_add_c(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2554 return do_add_reg(ctx
, a
, false, false, false, true);
2557 static bool trans_add_c_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2559 return do_add_reg(ctx
, a
, false, true, false, true);
2562 static bool trans_sub(DisasContext
*ctx
, arg_rrr_cf
*a
)
2564 return do_sub_reg(ctx
, a
, false, false, false);
2567 static bool trans_sub_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2569 return do_sub_reg(ctx
, a
, true, false, false);
2572 static bool trans_sub_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2574 return do_sub_reg(ctx
, a
, false, false, true);
2577 static bool trans_sub_tsv_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2579 return do_sub_reg(ctx
, a
, true, false, true);
2582 static bool trans_sub_b(DisasContext
*ctx
, arg_rrr_cf
*a
)
2584 return do_sub_reg(ctx
, a
, false, true, false);
2587 static bool trans_sub_b_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2589 return do_sub_reg(ctx
, a
, true, true, false);
2592 static bool trans_andcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2594 return do_log_reg(ctx
, a
, tcg_gen_andc_reg
);
2597 static bool trans_and(DisasContext
*ctx
, arg_rrr_cf
*a
)
2599 return do_log_reg(ctx
, a
, tcg_gen_and_reg
);
2602 static bool trans_or(DisasContext
*ctx
, arg_rrr_cf
*a
)
2605 unsigned r2
= a
->r2
;
2606 unsigned r1
= a
->r1
;
2609 if (rt
== 0) { /* NOP */
2610 cond_free(&ctx
->null_cond
);
2613 if (r2
== 0) { /* COPY */
2615 TCGv_reg dest
= dest_gpr(ctx
, rt
);
2616 tcg_gen_movi_reg(dest
, 0);
2617 save_gpr(ctx
, rt
, dest
);
2619 save_gpr(ctx
, rt
, cpu_gr
[r1
]);
2621 cond_free(&ctx
->null_cond
);
2624 #ifndef CONFIG_USER_ONLY
2625 /* These are QEMU extensions and are nops in the real architecture:
2627 * or %r10,%r10,%r10 -- idle loop; wait for interrupt
2628 * or %r31,%r31,%r31 -- death loop; offline cpu
2629 * currently implemented as idle.
2631 if ((rt
== 10 || rt
== 31) && r1
== rt
&& r2
== rt
) { /* PAUSE */
2632 /* No need to check for supervisor, as userland can only pause
2633 until the next timer interrupt. */
2636 /* Advance the instruction queue. */
2637 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
2638 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
2639 nullify_set(ctx
, 0);
2641 /* Tell the qemu main loop to halt until this cpu has work. */
2642 tcg_gen_st_i32(tcg_constant_i32(1), cpu_env
,
2643 offsetof(CPUState
, halted
) - offsetof(HPPACPU
, env
));
2644 gen_excp_1(EXCP_HALTED
);
2645 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2647 return nullify_end(ctx
);
2651 return do_log_reg(ctx
, a
, tcg_gen_or_reg
);
2654 static bool trans_xor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2656 return do_log_reg(ctx
, a
, tcg_gen_xor_reg
);
2659 static bool trans_cmpclr(DisasContext
*ctx
, arg_rrr_cf
*a
)
2661 TCGv_reg tcg_r1
, tcg_r2
;
2666 tcg_r1
= load_gpr(ctx
, a
->r1
);
2667 tcg_r2
= load_gpr(ctx
, a
->r2
);
2668 do_cmpclr(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
);
2669 return nullify_end(ctx
);
2672 static bool trans_uxor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2674 TCGv_reg tcg_r1
, tcg_r2
;
2679 tcg_r1
= load_gpr(ctx
, a
->r1
);
2680 tcg_r2
= load_gpr(ctx
, a
->r2
);
2681 do_unit(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, false, tcg_gen_xor_reg
);
2682 return nullify_end(ctx
);
2685 static bool do_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
, bool is_tc
)
2687 TCGv_reg tcg_r1
, tcg_r2
, tmp
;
2692 tcg_r1
= load_gpr(ctx
, a
->r1
);
2693 tcg_r2
= load_gpr(ctx
, a
->r2
);
2694 tmp
= get_temp(ctx
);
2695 tcg_gen_not_reg(tmp
, tcg_r2
);
2696 do_unit(ctx
, a
->t
, tcg_r1
, tmp
, a
->cf
, is_tc
, tcg_gen_add_reg
);
2697 return nullify_end(ctx
);
2700 static bool trans_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2702 return do_uaddcm(ctx
, a
, false);
2705 static bool trans_uaddcm_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2707 return do_uaddcm(ctx
, a
, true);
2710 static bool do_dcor(DisasContext
*ctx
, arg_rr_cf
*a
, bool is_i
)
2716 tmp
= get_temp(ctx
);
2717 tcg_gen_shri_reg(tmp
, cpu_psw_cb
, 3);
2719 tcg_gen_not_reg(tmp
, tmp
);
2721 tcg_gen_andi_reg(tmp
, tmp
, 0x11111111);
2722 tcg_gen_muli_reg(tmp
, tmp
, 6);
2723 do_unit(ctx
, a
->t
, load_gpr(ctx
, a
->r
), tmp
, a
->cf
, false,
2724 is_i
? tcg_gen_add_reg
: tcg_gen_sub_reg
);
2725 return nullify_end(ctx
);
2728 static bool trans_dcor(DisasContext
*ctx
, arg_rr_cf
*a
)
2730 return do_dcor(ctx
, a
, false);
2733 static bool trans_dcor_i(DisasContext
*ctx
, arg_rr_cf
*a
)
2735 return do_dcor(ctx
, a
, true);
2738 static bool trans_ds(DisasContext
*ctx
, arg_rrr_cf
*a
)
2740 TCGv_reg dest
, add1
, add2
, addc
, zero
, in1
, in2
;
2744 in1
= load_gpr(ctx
, a
->r1
);
2745 in2
= load_gpr(ctx
, a
->r2
);
2747 add1
= tcg_temp_new();
2748 add2
= tcg_temp_new();
2749 addc
= tcg_temp_new();
2750 dest
= tcg_temp_new();
2751 zero
= tcg_constant_reg(0);
2753 /* Form R1 << 1 | PSW[CB]{8}. */
2754 tcg_gen_add_reg(add1
, in1
, in1
);
2755 tcg_gen_add_reg(add1
, add1
, cpu_psw_cb_msb
);
2757 /* Add or subtract R2, depending on PSW[V]. Proper computation of
2758 carry{8} requires that we subtract via + ~R2 + 1, as described in
2759 the manual. By extracting and masking V, we can produce the
2760 proper inputs to the addition without movcond. */
2761 tcg_gen_sari_reg(addc
, cpu_psw_v
, TARGET_REGISTER_BITS
- 1);
2762 tcg_gen_xor_reg(add2
, in2
, addc
);
2763 tcg_gen_andi_reg(addc
, addc
, 1);
2764 /* ??? This is only correct for 32-bit. */
2765 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, add1
, zero
, add2
, zero
);
2766 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, dest
, cpu_psw_cb_msb
, addc
, zero
);
2768 /* Write back the result register. */
2769 save_gpr(ctx
, a
->t
, dest
);
2771 /* Write back PSW[CB]. */
2772 tcg_gen_xor_reg(cpu_psw_cb
, add1
, add2
);
2773 tcg_gen_xor_reg(cpu_psw_cb
, cpu_psw_cb
, dest
);
2775 /* Write back PSW[V] for the division step. */
2776 tcg_gen_neg_reg(cpu_psw_v
, cpu_psw_cb_msb
);
2777 tcg_gen_xor_reg(cpu_psw_v
, cpu_psw_v
, in2
);
2779 /* Install the new nullification. */
2782 if (cond_need_sv(a
->cf
>> 1)) {
2783 /* ??? The lshift is supposed to contribute to overflow. */
2784 sv
= do_add_sv(ctx
, dest
, add1
, add2
);
2786 ctx
->null_cond
= do_cond(a
->cf
, dest
, cpu_psw_cb_msb
, sv
);
2789 return nullify_end(ctx
);
2792 static bool trans_addi(DisasContext
*ctx
, arg_rri_cf
*a
)
2794 return do_add_imm(ctx
, a
, false, false);
2797 static bool trans_addi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2799 return do_add_imm(ctx
, a
, true, false);
2802 static bool trans_addi_tc(DisasContext
*ctx
, arg_rri_cf
*a
)
2804 return do_add_imm(ctx
, a
, false, true);
2807 static bool trans_addi_tc_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2809 return do_add_imm(ctx
, a
, true, true);
2812 static bool trans_subi(DisasContext
*ctx
, arg_rri_cf
*a
)
2814 return do_sub_imm(ctx
, a
, false);
2817 static bool trans_subi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2819 return do_sub_imm(ctx
, a
, true);
2822 static bool trans_cmpiclr(DisasContext
*ctx
, arg_rri_cf
*a
)
2824 TCGv_reg tcg_im
, tcg_r2
;
2830 tcg_im
= load_const(ctx
, a
->i
);
2831 tcg_r2
= load_gpr(ctx
, a
->r
);
2832 do_cmpclr(ctx
, a
->t
, tcg_im
, tcg_r2
, a
->cf
);
2834 return nullify_end(ctx
);
2837 static bool trans_ld(DisasContext
*ctx
, arg_ldst
*a
)
2839 if (unlikely(TARGET_REGISTER_BITS
== 32 && a
->size
> MO_32
)) {
2840 return gen_illegal(ctx
);
2842 return do_load(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2843 a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2847 static bool trans_st(DisasContext
*ctx
, arg_ldst
*a
)
2849 assert(a
->x
== 0 && a
->scale
== 0);
2850 if (unlikely(TARGET_REGISTER_BITS
== 32 && a
->size
> MO_32
)) {
2851 return gen_illegal(ctx
);
2853 return do_store(ctx
, a
->t
, a
->b
, a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2857 static bool trans_ldc(DisasContext
*ctx
, arg_ldst
*a
)
2859 MemOp mop
= MO_TE
| MO_ALIGN
| a
->size
;
2860 TCGv_reg zero
, dest
, ofs
;
2866 /* Base register modification. Make sure if RT == RB,
2867 we see the result of the load. */
2868 dest
= get_temp(ctx
);
2870 dest
= dest_gpr(ctx
, a
->t
);
2873 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2874 a
->disp
, a
->sp
, a
->m
, ctx
->mmu_idx
== MMU_PHYS_IDX
);
2877 * For hppa1.1, LDCW is undefined unless aligned mod 16.
2878 * However actual hardware succeeds with aligned mod 4.
2879 * Detect this case and log a GUEST_ERROR.
2881 * TODO: HPPA64 relaxes the over-alignment requirement
2882 * with the ,co completer.
2884 gen_helper_ldc_check(addr
);
2886 zero
= tcg_constant_reg(0);
2887 tcg_gen_atomic_xchg_reg(dest
, addr
, zero
, ctx
->mmu_idx
, mop
);
2890 save_gpr(ctx
, a
->b
, ofs
);
2892 save_gpr(ctx
, a
->t
, dest
);
2894 return nullify_end(ctx
);
2897 static bool trans_stby(DisasContext
*ctx
, arg_stby
*a
)
2904 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, a
->disp
, a
->sp
, a
->m
,
2905 ctx
->mmu_idx
== MMU_PHYS_IDX
);
2906 val
= load_gpr(ctx
, a
->r
);
2908 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2909 gen_helper_stby_e_parallel(cpu_env
, addr
, val
);
2911 gen_helper_stby_e(cpu_env
, addr
, val
);
2914 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2915 gen_helper_stby_b_parallel(cpu_env
, addr
, val
);
2917 gen_helper_stby_b(cpu_env
, addr
, val
);
2921 tcg_gen_andi_reg(ofs
, ofs
, ~3);
2922 save_gpr(ctx
, a
->b
, ofs
);
2925 return nullify_end(ctx
);
2928 static bool trans_lda(DisasContext
*ctx
, arg_ldst
*a
)
2930 int hold_mmu_idx
= ctx
->mmu_idx
;
2932 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2933 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2935 ctx
->mmu_idx
= hold_mmu_idx
;
2939 static bool trans_sta(DisasContext
*ctx
, arg_ldst
*a
)
2941 int hold_mmu_idx
= ctx
->mmu_idx
;
2943 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2944 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2946 ctx
->mmu_idx
= hold_mmu_idx
;
2950 static bool trans_ldil(DisasContext
*ctx
, arg_ldil
*a
)
2952 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
2954 tcg_gen_movi_reg(tcg_rt
, a
->i
);
2955 save_gpr(ctx
, a
->t
, tcg_rt
);
2956 cond_free(&ctx
->null_cond
);
2960 static bool trans_addil(DisasContext
*ctx
, arg_addil
*a
)
2962 TCGv_reg tcg_rt
= load_gpr(ctx
, a
->r
);
2963 TCGv_reg tcg_r1
= dest_gpr(ctx
, 1);
2965 tcg_gen_addi_reg(tcg_r1
, tcg_rt
, a
->i
);
2966 save_gpr(ctx
, 1, tcg_r1
);
2967 cond_free(&ctx
->null_cond
);
2971 static bool trans_ldo(DisasContext
*ctx
, arg_ldo
*a
)
2973 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
2975 /* Special case rb == 0, for the LDI pseudo-op.
2976 The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
2978 tcg_gen_movi_reg(tcg_rt
, a
->i
);
2980 tcg_gen_addi_reg(tcg_rt
, cpu_gr
[a
->b
], a
->i
);
2982 save_gpr(ctx
, a
->t
, tcg_rt
);
2983 cond_free(&ctx
->null_cond
);
2987 static bool do_cmpb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
2988 unsigned c
, unsigned f
, unsigned n
, int disp
)
2990 TCGv_reg dest
, in2
, sv
;
2993 in2
= load_gpr(ctx
, r
);
2994 dest
= get_temp(ctx
);
2996 tcg_gen_sub_reg(dest
, in1
, in2
);
2999 if (cond_need_sv(c
)) {
3000 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
3003 cond
= do_sub_cond(c
* 2 + f
, dest
, in1
, in2
, sv
);
3004 return do_cbranch(ctx
, disp
, n
, &cond
);
3007 static bool trans_cmpb(DisasContext
*ctx
, arg_cmpb
*a
)
3010 return do_cmpb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3013 static bool trans_cmpbi(DisasContext
*ctx
, arg_cmpbi
*a
)
3016 return do_cmpb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3019 static bool do_addb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3020 unsigned c
, unsigned f
, unsigned n
, int disp
)
3022 TCGv_reg dest
, in2
, sv
, cb_msb
;
3025 in2
= load_gpr(ctx
, r
);
3026 dest
= tcg_temp_new();
3030 if (cond_need_cb(c
)) {
3031 cb_msb
= get_temp(ctx
);
3032 tcg_gen_movi_reg(cb_msb
, 0);
3033 tcg_gen_add2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, cb_msb
);
3035 tcg_gen_add_reg(dest
, in1
, in2
);
3037 if (cond_need_sv(c
)) {
3038 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
3041 cond
= do_cond(c
* 2 + f
, dest
, cb_msb
, sv
);
3042 save_gpr(ctx
, r
, dest
);
3043 return do_cbranch(ctx
, disp
, n
, &cond
);
3046 static bool trans_addb(DisasContext
*ctx
, arg_addb
*a
)
3049 return do_addb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3052 static bool trans_addbi(DisasContext
*ctx
, arg_addbi
*a
)
3055 return do_addb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3058 static bool trans_bb_sar(DisasContext
*ctx
, arg_bb_sar
*a
)
3060 TCGv_reg tmp
, tcg_r
;
3065 tmp
= tcg_temp_new();
3066 tcg_r
= load_gpr(ctx
, a
->r
);
3067 tcg_gen_shl_reg(tmp
, tcg_r
, cpu_sar
);
3069 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3070 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3073 static bool trans_bb_imm(DisasContext
*ctx
, arg_bb_imm
*a
)
3075 TCGv_reg tmp
, tcg_r
;
3080 tmp
= tcg_temp_new();
3081 tcg_r
= load_gpr(ctx
, a
->r
);
3082 tcg_gen_shli_reg(tmp
, tcg_r
, a
->p
);
3084 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3085 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3088 static bool trans_movb(DisasContext
*ctx
, arg_movb
*a
)
3095 dest
= dest_gpr(ctx
, a
->r2
);
3097 tcg_gen_movi_reg(dest
, 0);
3099 tcg_gen_mov_reg(dest
, cpu_gr
[a
->r1
]);
3102 cond
= do_sed_cond(a
->c
, dest
);
3103 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3106 static bool trans_movbi(DisasContext
*ctx
, arg_movbi
*a
)
3113 dest
= dest_gpr(ctx
, a
->r
);
3114 tcg_gen_movi_reg(dest
, a
->i
);
3116 cond
= do_sed_cond(a
->c
, dest
);
3117 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3120 static bool trans_shrpw_sar(DisasContext
*ctx
, arg_shrpw_sar
*a
)
3128 dest
= dest_gpr(ctx
, a
->t
);
3130 tcg_gen_ext32u_reg(dest
, load_gpr(ctx
, a
->r2
));
3131 tcg_gen_shr_reg(dest
, dest
, cpu_sar
);
3132 } else if (a
->r1
== a
->r2
) {
3133 TCGv_i32 t32
= tcg_temp_new_i32();
3134 tcg_gen_trunc_reg_i32(t32
, load_gpr(ctx
, a
->r2
));
3135 tcg_gen_rotr_i32(t32
, t32
, cpu_sar
);
3136 tcg_gen_extu_i32_reg(dest
, t32
);
3138 TCGv_i64 t
= tcg_temp_new_i64();
3139 TCGv_i64 s
= tcg_temp_new_i64();
3141 tcg_gen_concat_reg_i64(t
, load_gpr(ctx
, a
->r2
), load_gpr(ctx
, a
->r1
));
3142 tcg_gen_extu_reg_i64(s
, cpu_sar
);
3143 tcg_gen_shr_i64(t
, t
, s
);
3144 tcg_gen_trunc_i64_reg(dest
, t
);
3146 save_gpr(ctx
, a
->t
, dest
);
3148 /* Install the new nullification. */
3149 cond_free(&ctx
->null_cond
);
3151 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3153 return nullify_end(ctx
);
3156 static bool trans_shrpw_imm(DisasContext
*ctx
, arg_shrpw_imm
*a
)
3158 unsigned sa
= 31 - a
->cpos
;
3165 dest
= dest_gpr(ctx
, a
->t
);
3166 t2
= load_gpr(ctx
, a
->r2
);
3168 tcg_gen_extract_reg(dest
, t2
, sa
, 32 - sa
);
3169 } else if (TARGET_REGISTER_BITS
== 32) {
3170 tcg_gen_extract2_reg(dest
, t2
, cpu_gr
[a
->r1
], sa
);
3171 } else if (a
->r1
== a
->r2
) {
3172 TCGv_i32 t32
= tcg_temp_new_i32();
3173 tcg_gen_trunc_reg_i32(t32
, t2
);
3174 tcg_gen_rotri_i32(t32
, t32
, sa
);
3175 tcg_gen_extu_i32_reg(dest
, t32
);
3177 TCGv_i64 t64
= tcg_temp_new_i64();
3178 tcg_gen_concat_reg_i64(t64
, t2
, cpu_gr
[a
->r1
]);
3179 tcg_gen_shri_i64(t64
, t64
, sa
);
3180 tcg_gen_trunc_i64_reg(dest
, t64
);
3182 save_gpr(ctx
, a
->t
, dest
);
3184 /* Install the new nullification. */
3185 cond_free(&ctx
->null_cond
);
3187 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3189 return nullify_end(ctx
);
3192 static bool trans_extrw_sar(DisasContext
*ctx
, arg_extrw_sar
*a
)
3194 unsigned len
= 32 - a
->clen
;
3195 TCGv_reg dest
, src
, tmp
;
3201 dest
= dest_gpr(ctx
, a
->t
);
3202 src
= load_gpr(ctx
, a
->r
);
3203 tmp
= tcg_temp_new();
3205 /* Recall that SAR is using big-endian bit numbering. */
3206 tcg_gen_xori_reg(tmp
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3208 tcg_gen_sar_reg(dest
, src
, tmp
);
3209 tcg_gen_sextract_reg(dest
, dest
, 0, len
);
3211 tcg_gen_shr_reg(dest
, src
, tmp
);
3212 tcg_gen_extract_reg(dest
, dest
, 0, len
);
3214 save_gpr(ctx
, a
->t
, dest
);
3216 /* Install the new nullification. */
3217 cond_free(&ctx
->null_cond
);
3219 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3221 return nullify_end(ctx
);
3224 static bool trans_extrw_imm(DisasContext
*ctx
, arg_extrw_imm
*a
)
3226 unsigned len
= 32 - a
->clen
;
3227 unsigned cpos
= 31 - a
->pos
;
3234 dest
= dest_gpr(ctx
, a
->t
);
3235 src
= load_gpr(ctx
, a
->r
);
3237 tcg_gen_sextract_reg(dest
, src
, cpos
, len
);
3239 tcg_gen_extract_reg(dest
, src
, cpos
, len
);
3241 save_gpr(ctx
, a
->t
, dest
);
3243 /* Install the new nullification. */
3244 cond_free(&ctx
->null_cond
);
3246 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3248 return nullify_end(ctx
);
3251 static bool trans_depwi_imm(DisasContext
*ctx
, arg_depwi_imm
*a
)
3253 unsigned len
= 32 - a
->clen
;
3254 target_sreg mask0
, mask1
;
3260 if (a
->cpos
+ len
> 32) {
3264 dest
= dest_gpr(ctx
, a
->t
);
3265 mask0
= deposit64(0, a
->cpos
, len
, a
->i
);
3266 mask1
= deposit64(-1, a
->cpos
, len
, a
->i
);
3269 TCGv_reg src
= load_gpr(ctx
, a
->t
);
3271 tcg_gen_andi_reg(dest
, src
, mask1
);
3274 tcg_gen_ori_reg(dest
, src
, mask0
);
3276 tcg_gen_movi_reg(dest
, mask0
);
3278 save_gpr(ctx
, a
->t
, dest
);
3280 /* Install the new nullification. */
3281 cond_free(&ctx
->null_cond
);
3283 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3285 return nullify_end(ctx
);
3288 static bool trans_depw_imm(DisasContext
*ctx
, arg_depw_imm
*a
)
3290 unsigned rs
= a
->nz
? a
->t
: 0;
3291 unsigned len
= 32 - a
->clen
;
3297 if (a
->cpos
+ len
> 32) {
3301 dest
= dest_gpr(ctx
, a
->t
);
3302 val
= load_gpr(ctx
, a
->r
);
3304 tcg_gen_deposit_z_reg(dest
, val
, a
->cpos
, len
);
3306 tcg_gen_deposit_reg(dest
, cpu_gr
[rs
], val
, a
->cpos
, len
);
3308 save_gpr(ctx
, a
->t
, dest
);
3310 /* Install the new nullification. */
3311 cond_free(&ctx
->null_cond
);
3313 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3315 return nullify_end(ctx
);
3318 static bool do_depw_sar(DisasContext
*ctx
, unsigned rt
, unsigned c
,
3319 unsigned nz
, unsigned clen
, TCGv_reg val
)
3321 unsigned rs
= nz
? rt
: 0;
3322 unsigned len
= 32 - clen
;
3323 TCGv_reg mask
, tmp
, shift
, dest
;
3324 unsigned msb
= 1U << (len
- 1);
3326 dest
= dest_gpr(ctx
, rt
);
3327 shift
= tcg_temp_new();
3328 tmp
= tcg_temp_new();
3330 /* Convert big-endian bit numbering in SAR to left-shift. */
3331 tcg_gen_xori_reg(shift
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3333 mask
= tcg_temp_new();
3334 tcg_gen_movi_reg(mask
, msb
+ (msb
- 1));
3335 tcg_gen_and_reg(tmp
, val
, mask
);
3337 tcg_gen_shl_reg(mask
, mask
, shift
);
3338 tcg_gen_shl_reg(tmp
, tmp
, shift
);
3339 tcg_gen_andc_reg(dest
, cpu_gr
[rs
], mask
);
3340 tcg_gen_or_reg(dest
, dest
, tmp
);
3342 tcg_gen_shl_reg(dest
, tmp
, shift
);
3344 save_gpr(ctx
, rt
, dest
);
3346 /* Install the new nullification. */
3347 cond_free(&ctx
->null_cond
);
3349 ctx
->null_cond
= do_sed_cond(c
, dest
);
3351 return nullify_end(ctx
);
3354 static bool trans_depw_sar(DisasContext
*ctx
, arg_depw_sar
*a
)
3359 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_gpr(ctx
, a
->r
));
3362 static bool trans_depwi_sar(DisasContext
*ctx
, arg_depwi_sar
*a
)
3367 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_const(ctx
, a
->i
));
3370 static bool trans_be(DisasContext
*ctx
, arg_be
*a
)
3374 #ifdef CONFIG_USER_ONLY
3375 /* ??? It seems like there should be a good way of using
3376 "be disp(sr2, r0)", the canonical gateway entry mechanism
3377 to our advantage. But that appears to be inconvenient to
3378 manage along side branch delay slots. Therefore we handle
3379 entry into the gateway page via absolute address. */
3380 /* Since we don't implement spaces, just branch. Do notice the special
3381 case of "be disp(*,r0)" using a direct branch to disp, so that we can
3382 goto_tb to the TB containing the syscall. */
3384 return do_dbranch(ctx
, a
->disp
, a
->l
, a
->n
);
3390 tmp
= get_temp(ctx
);
3391 tcg_gen_addi_reg(tmp
, load_gpr(ctx
, a
->b
), a
->disp
);
3392 tmp
= do_ibranch_priv(ctx
, tmp
);
3394 #ifdef CONFIG_USER_ONLY
3395 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3397 TCGv_i64 new_spc
= tcg_temp_new_i64();
3399 load_spr(ctx
, new_spc
, a
->sp
);
3401 copy_iaoq_entry(cpu_gr
[31], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3402 tcg_gen_mov_i64(cpu_sr
[0], cpu_iasq_f
);
3404 if (a
->n
&& use_nullify_skip(ctx
)) {
3405 tcg_gen_mov_reg(cpu_iaoq_f
, tmp
);
3406 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
3407 tcg_gen_mov_i64(cpu_iasq_f
, new_spc
);
3408 tcg_gen_mov_i64(cpu_iasq_b
, cpu_iasq_f
);
3410 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3411 if (ctx
->iaoq_b
== -1) {
3412 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3414 tcg_gen_mov_reg(cpu_iaoq_b
, tmp
);
3415 tcg_gen_mov_i64(cpu_iasq_b
, new_spc
);
3416 nullify_set(ctx
, a
->n
);
3418 tcg_gen_lookup_and_goto_ptr();
3419 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3420 return nullify_end(ctx
);
3424 static bool trans_bl(DisasContext
*ctx
, arg_bl
*a
)
3426 return do_dbranch(ctx
, iaoq_dest(ctx
, a
->disp
), a
->l
, a
->n
);
3429 static bool trans_b_gate(DisasContext
*ctx
, arg_b_gate
*a
)
3431 target_ureg dest
= iaoq_dest(ctx
, a
->disp
);
3435 /* Make sure the caller hasn't done something weird with the queue.
3436 * ??? This is not quite the same as the PSW[B] bit, which would be
3437 * expensive to track. Real hardware will trap for
3439 * b gateway+4 (in delay slot of first branch)
3440 * However, checking for a non-sequential instruction queue *will*
3441 * diagnose the security hole
3444 * in which instructions at evil would run with increased privs.
3446 if (ctx
->iaoq_b
== -1 || ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
3447 return gen_illegal(ctx
);
3450 #ifndef CONFIG_USER_ONLY
3451 if (ctx
->tb_flags
& PSW_C
) {
3452 CPUHPPAState
*env
= ctx
->cs
->env_ptr
;
3453 int type
= hppa_artype_for_page(env
, ctx
->base
.pc_next
);
3454 /* If we could not find a TLB entry, then we need to generate an
3455 ITLB miss exception so the kernel will provide it.
3456 The resulting TLB fill operation will invalidate this TB and
3457 we will re-translate, at which point we *will* be able to find
3458 the TLB entry and determine if this is in fact a gateway page. */
3460 gen_excp(ctx
, EXCP_ITLB_MISS
);
3463 /* No change for non-gateway pages or for priv decrease. */
3464 if (type
>= 4 && type
- 4 < ctx
->privilege
) {
3465 dest
= deposit32(dest
, 0, 2, type
- 4);
3468 dest
&= -4; /* priv = 0 */
3473 TCGv_reg tmp
= dest_gpr(ctx
, a
->l
);
3474 if (ctx
->privilege
< 3) {
3475 tcg_gen_andi_reg(tmp
, tmp
, -4);
3477 tcg_gen_ori_reg(tmp
, tmp
, ctx
->privilege
);
3478 save_gpr(ctx
, a
->l
, tmp
);
3481 return do_dbranch(ctx
, dest
, 0, a
->n
);
3484 static bool trans_blr(DisasContext
*ctx
, arg_blr
*a
)
3487 TCGv_reg tmp
= get_temp(ctx
);
3488 tcg_gen_shli_reg(tmp
, load_gpr(ctx
, a
->x
), 3);
3489 tcg_gen_addi_reg(tmp
, tmp
, ctx
->iaoq_f
+ 8);
3490 /* The computation here never changes privilege level. */
3491 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3493 /* BLR R0,RX is a good way to load PC+8 into RX. */
3494 return do_dbranch(ctx
, ctx
->iaoq_f
+ 8, a
->l
, a
->n
);
3498 static bool trans_bv(DisasContext
*ctx
, arg_bv
*a
)
3503 dest
= load_gpr(ctx
, a
->b
);
3505 dest
= get_temp(ctx
);
3506 tcg_gen_shli_reg(dest
, load_gpr(ctx
, a
->x
), 3);
3507 tcg_gen_add_reg(dest
, dest
, load_gpr(ctx
, a
->b
));
3509 dest
= do_ibranch_priv(ctx
, dest
);
3510 return do_ibranch(ctx
, dest
, 0, a
->n
);
3513 static bool trans_bve(DisasContext
*ctx
, arg_bve
*a
)
3517 #ifdef CONFIG_USER_ONLY
3518 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3519 return do_ibranch(ctx
, dest
, a
->l
, a
->n
);
3522 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3524 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3525 if (ctx
->iaoq_b
== -1) {
3526 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3528 copy_iaoq_entry(cpu_iaoq_b
, -1, dest
);
3529 tcg_gen_mov_i64(cpu_iasq_b
, space_select(ctx
, 0, dest
));
3531 copy_iaoq_entry(cpu_gr
[a
->l
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3533 nullify_set(ctx
, a
->n
);
3534 tcg_gen_lookup_and_goto_ptr();
3535 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3536 return nullify_end(ctx
);
3544 static void gen_fcpy_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3546 tcg_gen_mov_i32(dst
, src
);
3549 static bool trans_fid_f(DisasContext
*ctx
, arg_fid_f
*a
)
3553 if (TARGET_REGISTER_BITS
== 64) {
3554 ret
= 0x13080000000000ULL
; /* PA8700 (PCX-W2) */
3556 ret
= 0x0f080000000000ULL
; /* PA7300LC (PCX-L2) */
3560 save_frd(0, tcg_constant_i64(ret
));
3561 return nullify_end(ctx
);
3564 static bool trans_fcpy_f(DisasContext
*ctx
, arg_fclass01
*a
)
3566 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fcpy_f
);
3569 static void gen_fcpy_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3571 tcg_gen_mov_i64(dst
, src
);
3574 static bool trans_fcpy_d(DisasContext
*ctx
, arg_fclass01
*a
)
3576 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fcpy_d
);
3579 static void gen_fabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3581 tcg_gen_andi_i32(dst
, src
, INT32_MAX
);
3584 static bool trans_fabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3586 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fabs_f
);
3589 static void gen_fabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3591 tcg_gen_andi_i64(dst
, src
, INT64_MAX
);
3594 static bool trans_fabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3596 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fabs_d
);
3599 static bool trans_fsqrt_f(DisasContext
*ctx
, arg_fclass01
*a
)
3601 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_s
);
3604 static bool trans_fsqrt_d(DisasContext
*ctx
, arg_fclass01
*a
)
3606 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_d
);
3609 static bool trans_frnd_f(DisasContext
*ctx
, arg_fclass01
*a
)
3611 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_frnd_s
);
3614 static bool trans_frnd_d(DisasContext
*ctx
, arg_fclass01
*a
)
3616 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_frnd_d
);
3619 static void gen_fneg_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3621 tcg_gen_xori_i32(dst
, src
, INT32_MIN
);
3624 static bool trans_fneg_f(DisasContext
*ctx
, arg_fclass01
*a
)
3626 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fneg_f
);
3629 static void gen_fneg_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3631 tcg_gen_xori_i64(dst
, src
, INT64_MIN
);
3634 static bool trans_fneg_d(DisasContext
*ctx
, arg_fclass01
*a
)
3636 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fneg_d
);
3639 static void gen_fnegabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3641 tcg_gen_ori_i32(dst
, src
, INT32_MIN
);
3644 static bool trans_fnegabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3646 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fnegabs_f
);
3649 static void gen_fnegabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3651 tcg_gen_ori_i64(dst
, src
, INT64_MIN
);
3654 static bool trans_fnegabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3656 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fnegabs_d
);
3663 static bool trans_fcnv_d_f(DisasContext
*ctx
, arg_fclass01
*a
)
3665 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_s
);
3668 static bool trans_fcnv_f_d(DisasContext
*ctx
, arg_fclass01
*a
)
3670 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_d
);
3673 static bool trans_fcnv_w_f(DisasContext
*ctx
, arg_fclass01
*a
)
3675 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_s
);
3678 static bool trans_fcnv_q_f(DisasContext
*ctx
, arg_fclass01
*a
)
3680 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_s
);
3683 static bool trans_fcnv_w_d(DisasContext
*ctx
, arg_fclass01
*a
)
3685 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_d
);
3688 static bool trans_fcnv_q_d(DisasContext
*ctx
, arg_fclass01
*a
)
3690 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_d
);
3693 static bool trans_fcnv_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3695 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_w
);
3698 static bool trans_fcnv_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3700 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_w
);
3703 static bool trans_fcnv_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3705 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_dw
);
3708 static bool trans_fcnv_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3710 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_dw
);
3713 static bool trans_fcnv_t_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3715 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_w
);
3718 static bool trans_fcnv_t_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3720 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_w
);
3723 static bool trans_fcnv_t_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3725 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_dw
);
3728 static bool trans_fcnv_t_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3730 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_dw
);
3733 static bool trans_fcnv_uw_f(DisasContext
*ctx
, arg_fclass01
*a
)
3735 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_s
);
3738 static bool trans_fcnv_uq_f(DisasContext
*ctx
, arg_fclass01
*a
)
3740 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_s
);
3743 static bool trans_fcnv_uw_d(DisasContext
*ctx
, arg_fclass01
*a
)
3745 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_d
);
3748 static bool trans_fcnv_uq_d(DisasContext
*ctx
, arg_fclass01
*a
)
3750 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_d
);
3753 static bool trans_fcnv_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3755 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_uw
);
3758 static bool trans_fcnv_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3760 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_uw
);
3763 static bool trans_fcnv_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3765 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_udw
);
3768 static bool trans_fcnv_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3770 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_udw
);
3773 static bool trans_fcnv_t_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3775 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_uw
);
3778 static bool trans_fcnv_t_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3780 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_uw
);
3783 static bool trans_fcnv_t_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3785 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_udw
);
3788 static bool trans_fcnv_t_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3790 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_udw
);
3797 static bool trans_fcmp_f(DisasContext
*ctx
, arg_fclass2
*a
)
3799 TCGv_i32 ta
, tb
, tc
, ty
;
3803 ta
= load_frw0_i32(a
->r1
);
3804 tb
= load_frw0_i32(a
->r2
);
3805 ty
= tcg_constant_i32(a
->y
);
3806 tc
= tcg_constant_i32(a
->c
);
3808 gen_helper_fcmp_s(cpu_env
, ta
, tb
, ty
, tc
);
3810 return nullify_end(ctx
);
3813 static bool trans_fcmp_d(DisasContext
*ctx
, arg_fclass2
*a
)
3820 ta
= load_frd0(a
->r1
);
3821 tb
= load_frd0(a
->r2
);
3822 ty
= tcg_constant_i32(a
->y
);
3823 tc
= tcg_constant_i32(a
->c
);
3825 gen_helper_fcmp_d(cpu_env
, ta
, tb
, ty
, tc
);
3827 return nullify_end(ctx
);
3830 static bool trans_ftest(DisasContext
*ctx
, arg_ftest
*a
)
3837 tcg_gen_ld32u_reg(t
, cpu_env
, offsetof(CPUHPPAState
, fr0_shadow
));
3844 case 0: /* simple */
3845 tcg_gen_andi_reg(t
, t
, 0x4000000);
3846 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3874 TCGv_reg c
= load_const(ctx
, mask
);
3875 tcg_gen_or_reg(t
, t
, c
);
3876 ctx
->null_cond
= cond_make(TCG_COND_EQ
, t
, c
);
3878 tcg_gen_andi_reg(t
, t
, mask
);
3879 ctx
->null_cond
= cond_make_0(TCG_COND_EQ
, t
);
3882 unsigned cbit
= (a
->y
^ 1) - 1;
3884 tcg_gen_extract_reg(t
, t
, 21 - cbit
, 1);
3885 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3889 return nullify_end(ctx
);
3896 static bool trans_fadd_f(DisasContext
*ctx
, arg_fclass3
*a
)
3898 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_s
);
3901 static bool trans_fadd_d(DisasContext
*ctx
, arg_fclass3
*a
)
3903 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_d
);
3906 static bool trans_fsub_f(DisasContext
*ctx
, arg_fclass3
*a
)
3908 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_s
);
3911 static bool trans_fsub_d(DisasContext
*ctx
, arg_fclass3
*a
)
3913 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_d
);
3916 static bool trans_fmpy_f(DisasContext
*ctx
, arg_fclass3
*a
)
3918 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_s
);
3921 static bool trans_fmpy_d(DisasContext
*ctx
, arg_fclass3
*a
)
3923 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_d
);
3926 static bool trans_fdiv_f(DisasContext
*ctx
, arg_fclass3
*a
)
3928 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_s
);
3931 static bool trans_fdiv_d(DisasContext
*ctx
, arg_fclass3
*a
)
3933 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_d
);
3936 static bool trans_xmpyu(DisasContext
*ctx
, arg_xmpyu
*a
)
3942 x
= load_frw0_i64(a
->r1
);
3943 y
= load_frw0_i64(a
->r2
);
3944 tcg_gen_mul_i64(x
, x
, y
);
3947 return nullify_end(ctx
);
3950 /* Convert the fmpyadd single-precision register encodings to standard. */
3951 static inline int fmpyadd_s_reg(unsigned r
)
3953 return (r
& 16) * 2 + 16 + (r
& 15);
3956 static bool do_fmpyadd_s(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
3958 int tm
= fmpyadd_s_reg(a
->tm
);
3959 int ra
= fmpyadd_s_reg(a
->ra
);
3960 int ta
= fmpyadd_s_reg(a
->ta
);
3961 int rm2
= fmpyadd_s_reg(a
->rm2
);
3962 int rm1
= fmpyadd_s_reg(a
->rm1
);
3966 do_fop_weww(ctx
, tm
, rm1
, rm2
, gen_helper_fmpy_s
);
3967 do_fop_weww(ctx
, ta
, ta
, ra
,
3968 is_sub
? gen_helper_fsub_s
: gen_helper_fadd_s
);
3970 return nullify_end(ctx
);
3973 static bool trans_fmpyadd_f(DisasContext
*ctx
, arg_mpyadd
*a
)
3975 return do_fmpyadd_s(ctx
, a
, false);
3978 static bool trans_fmpysub_f(DisasContext
*ctx
, arg_mpyadd
*a
)
3980 return do_fmpyadd_s(ctx
, a
, true);
3983 static bool do_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
3987 do_fop_dedd(ctx
, a
->tm
, a
->rm1
, a
->rm2
, gen_helper_fmpy_d
);
3988 do_fop_dedd(ctx
, a
->ta
, a
->ta
, a
->ra
,
3989 is_sub
? gen_helper_fsub_d
: gen_helper_fadd_d
);
3991 return nullify_end(ctx
);
3994 static bool trans_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
)
3996 return do_fmpyadd_d(ctx
, a
, false);
3999 static bool trans_fmpysub_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4001 return do_fmpyadd_d(ctx
, a
, true);
4004 static bool trans_fmpyfadd_f(DisasContext
*ctx
, arg_fmpyfadd_f
*a
)
4009 x
= load_frw0_i32(a
->rm1
);
4010 y
= load_frw0_i32(a
->rm2
);
4011 z
= load_frw0_i32(a
->ra3
);
4014 gen_helper_fmpynfadd_s(x
, cpu_env
, x
, y
, z
);
4016 gen_helper_fmpyfadd_s(x
, cpu_env
, x
, y
, z
);
4019 save_frw_i32(a
->t
, x
);
4020 return nullify_end(ctx
);
4023 static bool trans_fmpyfadd_d(DisasContext
*ctx
, arg_fmpyfadd_d
*a
)
4028 x
= load_frd0(a
->rm1
);
4029 y
= load_frd0(a
->rm2
);
4030 z
= load_frd0(a
->ra3
);
4033 gen_helper_fmpynfadd_d(x
, cpu_env
, x
, y
, z
);
4035 gen_helper_fmpyfadd_d(x
, cpu_env
, x
, y
, z
);
4039 return nullify_end(ctx
);
4042 static bool trans_diag(DisasContext
*ctx
, arg_diag
*a
)
4044 qemu_log_mask(LOG_UNIMP
, "DIAG opcode ignored\n");
4045 cond_free(&ctx
->null_cond
);
4049 static void hppa_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
4051 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4055 ctx
->tb_flags
= ctx
->base
.tb
->flags
;
4057 #ifdef CONFIG_USER_ONLY
4058 ctx
->privilege
= MMU_USER_IDX
;
4059 ctx
->mmu_idx
= MMU_USER_IDX
;
4060 ctx
->iaoq_f
= ctx
->base
.pc_first
| MMU_USER_IDX
;
4061 ctx
->iaoq_b
= ctx
->base
.tb
->cs_base
| MMU_USER_IDX
;
4062 ctx
->unalign
= (ctx
->tb_flags
& TB_FLAG_UNALIGN
? MO_UNALN
: MO_ALIGN
);
4064 ctx
->privilege
= (ctx
->tb_flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
4065 ctx
->mmu_idx
= (ctx
->tb_flags
& PSW_D
? ctx
->privilege
: MMU_PHYS_IDX
);
4067 /* Recover the IAOQ values from the GVA + PRIV. */
4068 uint64_t cs_base
= ctx
->base
.tb
->cs_base
;
4069 uint64_t iasq_f
= cs_base
& ~0xffffffffull
;
4070 int32_t diff
= cs_base
;
4072 ctx
->iaoq_f
= (ctx
->base
.pc_first
& ~iasq_f
) + ctx
->privilege
;
4073 ctx
->iaoq_b
= (diff
? ctx
->iaoq_f
+ diff
: -1);
4076 ctx
->iaoq_n_var
= NULL
;
4078 /* Bound the number of instructions by those left on the page. */
4079 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
4080 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
4084 memset(ctx
->tempr
, 0, sizeof(ctx
->tempr
));
4085 memset(ctx
->templ
, 0, sizeof(ctx
->templ
));
4088 static void hppa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4090 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4092 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */
4093 ctx
->null_cond
= cond_make_f();
4094 ctx
->psw_n_nonzero
= false;
4095 if (ctx
->tb_flags
& PSW_N
) {
4096 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
4097 ctx
->psw_n_nonzero
= true;
4099 ctx
->null_lab
= NULL
;
4102 static void hppa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4104 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4106 tcg_gen_insn_start(ctx
->iaoq_f
, ctx
->iaoq_b
);
4109 static void hppa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
4111 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4112 CPUHPPAState
*env
= cs
->env_ptr
;
4116 /* Execute one insn. */
4117 #ifdef CONFIG_USER_ONLY
4118 if (ctx
->base
.pc_next
< TARGET_PAGE_SIZE
) {
4120 ret
= ctx
->base
.is_jmp
;
4121 assert(ret
!= DISAS_NEXT
);
4125 /* Always fetch the insn, even if nullified, so that we check
4126 the page permissions for execute. */
4127 uint32_t insn
= translator_ldl(env
, &ctx
->base
, ctx
->base
.pc_next
);
4129 /* Set up the IA queue for the next insn.
4130 This will be overwritten by a branch. */
4131 if (ctx
->iaoq_b
== -1) {
4133 ctx
->iaoq_n_var
= get_temp(ctx
);
4134 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
4136 ctx
->iaoq_n
= ctx
->iaoq_b
+ 4;
4137 ctx
->iaoq_n_var
= NULL
;
4140 if (unlikely(ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4141 ctx
->null_cond
.c
= TCG_COND_NEVER
;
4145 if (!decode(ctx
, insn
)) {
4148 ret
= ctx
->base
.is_jmp
;
4149 assert(ctx
->null_lab
== NULL
);
4153 /* Forget any temporaries allocated. */
4154 for (i
= 0, n
= ctx
->ntempr
; i
< n
; ++i
) {
4155 ctx
->tempr
[i
] = NULL
;
4157 for (i
= 0, n
= ctx
->ntempl
; i
< n
; ++i
) {
4158 ctx
->templ
[i
] = NULL
;
4163 /* Advance the insn queue. Note that this check also detects
4164 a priority change within the instruction queue. */
4165 if (ret
== DISAS_NEXT
&& ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
4166 if (ctx
->iaoq_b
!= -1 && ctx
->iaoq_n
!= -1
4167 && use_goto_tb(ctx
, ctx
->iaoq_b
)
4168 && (ctx
->null_cond
.c
== TCG_COND_NEVER
4169 || ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4170 nullify_set(ctx
, ctx
->null_cond
.c
== TCG_COND_ALWAYS
);
4171 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
4172 ctx
->base
.is_jmp
= ret
= DISAS_NORETURN
;
4174 ctx
->base
.is_jmp
= ret
= DISAS_IAQ_N_STALE
;
4177 ctx
->iaoq_f
= ctx
->iaoq_b
;
4178 ctx
->iaoq_b
= ctx
->iaoq_n
;
4179 ctx
->base
.pc_next
+= 4;
4182 case DISAS_NORETURN
:
4183 case DISAS_IAQ_N_UPDATED
:
4187 case DISAS_IAQ_N_STALE
:
4188 case DISAS_IAQ_N_STALE_EXIT
:
4189 if (ctx
->iaoq_f
== -1) {
4190 tcg_gen_mov_reg(cpu_iaoq_f
, cpu_iaoq_b
);
4191 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
4192 #ifndef CONFIG_USER_ONLY
4193 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
4196 ctx
->base
.is_jmp
= (ret
== DISAS_IAQ_N_STALE_EXIT
4198 : DISAS_IAQ_N_UPDATED
);
4199 } else if (ctx
->iaoq_b
== -1) {
4200 tcg_gen_mov_reg(cpu_iaoq_b
, ctx
->iaoq_n_var
);
4205 g_assert_not_reached();
4209 static void hppa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
4211 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4212 DisasJumpType is_jmp
= ctx
->base
.is_jmp
;
4215 case DISAS_NORETURN
:
4217 case DISAS_TOO_MANY
:
4218 case DISAS_IAQ_N_STALE
:
4219 case DISAS_IAQ_N_STALE_EXIT
:
4220 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
4221 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
4224 case DISAS_IAQ_N_UPDATED
:
4225 if (is_jmp
!= DISAS_IAQ_N_STALE_EXIT
) {
4226 tcg_gen_lookup_and_goto_ptr();
4231 tcg_gen_exit_tb(NULL
, 0);
4234 g_assert_not_reached();
4238 static void hppa_tr_disas_log(const DisasContextBase
*dcbase
,
4239 CPUState
*cs
, FILE *logfile
)
4241 target_ulong pc
= dcbase
->pc_first
;
4243 #ifdef CONFIG_USER_ONLY
4246 fprintf(logfile
, "IN:\n0x00000000: (null)\n");
4249 fprintf(logfile
, "IN:\n0x000000b0: light-weight-syscall\n");
4252 fprintf(logfile
, "IN:\n0x000000e0: set-thread-pointer-syscall\n");
4255 fprintf(logfile
, "IN:\n0x00000100: syscall\n");
4260 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc
));
4261 target_disas(logfile
, cs
, pc
, dcbase
->tb
->size
);
4264 static const TranslatorOps hppa_tr_ops
= {
4265 .init_disas_context
= hppa_tr_init_disas_context
,
4266 .tb_start
= hppa_tr_tb_start
,
4267 .insn_start
= hppa_tr_insn_start
,
4268 .translate_insn
= hppa_tr_translate_insn
,
4269 .tb_stop
= hppa_tr_tb_stop
,
4270 .disas_log
= hppa_tr_disas_log
,
4273 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
4274 target_ulong pc
, void *host_pc
)
4277 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &hppa_tr_ops
, &ctx
.base
);