2 * HPPA emulation cpu translation for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "disas/disas.h"
23 #include "qemu/host-utils.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/cpu_ldst.h"
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
32 /* Since we have a distinction between register size and address size,
33 we need to redefine all of these. */
37 #undef tcg_global_reg_new
38 #undef tcg_global_mem_new
39 #undef tcg_temp_local_new
42 #if TARGET_LONG_BITS == 64
43 #define TCGv_tl TCGv_i64
44 #define tcg_temp_new_tl tcg_temp_new_i64
45 #define tcg_temp_free_tl tcg_temp_free_i64
46 #if TARGET_REGISTER_BITS == 64
47 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64
49 #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
52 #define TCGv_tl TCGv_i32
53 #define tcg_temp_new_tl tcg_temp_new_i32
54 #define tcg_temp_free_tl tcg_temp_free_i32
55 #define tcg_gen_extu_reg_tl tcg_gen_mov_i32
58 #if TARGET_REGISTER_BITS == 64
59 #define TCGv_reg TCGv_i64
61 #define tcg_temp_new tcg_temp_new_i64
62 #define tcg_global_reg_new tcg_global_reg_new_i64
63 #define tcg_global_mem_new tcg_global_mem_new_i64
64 #define tcg_temp_local_new tcg_temp_local_new_i64
65 #define tcg_temp_free tcg_temp_free_i64
67 #define tcg_gen_movi_reg tcg_gen_movi_i64
68 #define tcg_gen_mov_reg tcg_gen_mov_i64
69 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
70 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
71 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
72 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
73 #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
74 #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
75 #define tcg_gen_ld_reg tcg_gen_ld_i64
76 #define tcg_gen_st8_reg tcg_gen_st8_i64
77 #define tcg_gen_st16_reg tcg_gen_st16_i64
78 #define tcg_gen_st32_reg tcg_gen_st32_i64
79 #define tcg_gen_st_reg tcg_gen_st_i64
80 #define tcg_gen_add_reg tcg_gen_add_i64
81 #define tcg_gen_addi_reg tcg_gen_addi_i64
82 #define tcg_gen_sub_reg tcg_gen_sub_i64
83 #define tcg_gen_neg_reg tcg_gen_neg_i64
84 #define tcg_gen_subfi_reg tcg_gen_subfi_i64
85 #define tcg_gen_subi_reg tcg_gen_subi_i64
86 #define tcg_gen_and_reg tcg_gen_and_i64
87 #define tcg_gen_andi_reg tcg_gen_andi_i64
88 #define tcg_gen_or_reg tcg_gen_or_i64
89 #define tcg_gen_ori_reg tcg_gen_ori_i64
90 #define tcg_gen_xor_reg tcg_gen_xor_i64
91 #define tcg_gen_xori_reg tcg_gen_xori_i64
92 #define tcg_gen_not_reg tcg_gen_not_i64
93 #define tcg_gen_shl_reg tcg_gen_shl_i64
94 #define tcg_gen_shli_reg tcg_gen_shli_i64
95 #define tcg_gen_shr_reg tcg_gen_shr_i64
96 #define tcg_gen_shri_reg tcg_gen_shri_i64
97 #define tcg_gen_sar_reg tcg_gen_sar_i64
98 #define tcg_gen_sari_reg tcg_gen_sari_i64
99 #define tcg_gen_brcond_reg tcg_gen_brcond_i64
100 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
101 #define tcg_gen_setcond_reg tcg_gen_setcond_i64
102 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
103 #define tcg_gen_mul_reg tcg_gen_mul_i64
104 #define tcg_gen_muli_reg tcg_gen_muli_i64
105 #define tcg_gen_div_reg tcg_gen_div_i64
106 #define tcg_gen_rem_reg tcg_gen_rem_i64
107 #define tcg_gen_divu_reg tcg_gen_divu_i64
108 #define tcg_gen_remu_reg tcg_gen_remu_i64
109 #define tcg_gen_discard_reg tcg_gen_discard_i64
110 #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
111 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
112 #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
113 #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
114 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
115 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
116 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
117 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
118 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
119 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
120 #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
121 #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
122 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
123 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
124 #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
125 #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
126 #define tcg_gen_andc_reg tcg_gen_andc_i64
127 #define tcg_gen_eqv_reg tcg_gen_eqv_i64
128 #define tcg_gen_nand_reg tcg_gen_nand_i64
129 #define tcg_gen_nor_reg tcg_gen_nor_i64
130 #define tcg_gen_orc_reg tcg_gen_orc_i64
131 #define tcg_gen_clz_reg tcg_gen_clz_i64
132 #define tcg_gen_ctz_reg tcg_gen_ctz_i64
133 #define tcg_gen_clzi_reg tcg_gen_clzi_i64
134 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
135 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
136 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
137 #define tcg_gen_rotl_reg tcg_gen_rotl_i64
138 #define tcg_gen_rotli_reg tcg_gen_rotli_i64
139 #define tcg_gen_rotr_reg tcg_gen_rotr_i64
140 #define tcg_gen_rotri_reg tcg_gen_rotri_i64
141 #define tcg_gen_deposit_reg tcg_gen_deposit_i64
142 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
143 #define tcg_gen_extract_reg tcg_gen_extract_i64
144 #define tcg_gen_sextract_reg tcg_gen_sextract_i64
145 #define tcg_const_reg tcg_const_i64
146 #define tcg_const_local_reg tcg_const_local_i64
147 #define tcg_gen_movcond_reg tcg_gen_movcond_i64
148 #define tcg_gen_add2_reg tcg_gen_add2_i64
149 #define tcg_gen_sub2_reg tcg_gen_sub2_i64
150 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
151 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
152 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
153 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
155 #define TCGv_reg TCGv_i32
156 #define tcg_temp_new tcg_temp_new_i32
157 #define tcg_global_reg_new tcg_global_reg_new_i32
158 #define tcg_global_mem_new tcg_global_mem_new_i32
159 #define tcg_temp_local_new tcg_temp_local_new_i32
160 #define tcg_temp_free tcg_temp_free_i32
162 #define tcg_gen_movi_reg tcg_gen_movi_i32
163 #define tcg_gen_mov_reg tcg_gen_mov_i32
164 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
165 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
166 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
167 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
168 #define tcg_gen_ld32u_reg tcg_gen_ld_i32
169 #define tcg_gen_ld32s_reg tcg_gen_ld_i32
170 #define tcg_gen_ld_reg tcg_gen_ld_i32
171 #define tcg_gen_st8_reg tcg_gen_st8_i32
172 #define tcg_gen_st16_reg tcg_gen_st16_i32
173 #define tcg_gen_st32_reg tcg_gen_st32_i32
174 #define tcg_gen_st_reg tcg_gen_st_i32
175 #define tcg_gen_add_reg tcg_gen_add_i32
176 #define tcg_gen_addi_reg tcg_gen_addi_i32
177 #define tcg_gen_sub_reg tcg_gen_sub_i32
178 #define tcg_gen_neg_reg tcg_gen_neg_i32
179 #define tcg_gen_subfi_reg tcg_gen_subfi_i32
180 #define tcg_gen_subi_reg tcg_gen_subi_i32
181 #define tcg_gen_and_reg tcg_gen_and_i32
182 #define tcg_gen_andi_reg tcg_gen_andi_i32
183 #define tcg_gen_or_reg tcg_gen_or_i32
184 #define tcg_gen_ori_reg tcg_gen_ori_i32
185 #define tcg_gen_xor_reg tcg_gen_xor_i32
186 #define tcg_gen_xori_reg tcg_gen_xori_i32
187 #define tcg_gen_not_reg tcg_gen_not_i32
188 #define tcg_gen_shl_reg tcg_gen_shl_i32
189 #define tcg_gen_shli_reg tcg_gen_shli_i32
190 #define tcg_gen_shr_reg tcg_gen_shr_i32
191 #define tcg_gen_shri_reg tcg_gen_shri_i32
192 #define tcg_gen_sar_reg tcg_gen_sar_i32
193 #define tcg_gen_sari_reg tcg_gen_sari_i32
194 #define tcg_gen_brcond_reg tcg_gen_brcond_i32
195 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
196 #define tcg_gen_setcond_reg tcg_gen_setcond_i32
197 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
198 #define tcg_gen_mul_reg tcg_gen_mul_i32
199 #define tcg_gen_muli_reg tcg_gen_muli_i32
200 #define tcg_gen_div_reg tcg_gen_div_i32
201 #define tcg_gen_rem_reg tcg_gen_rem_i32
202 #define tcg_gen_divu_reg tcg_gen_divu_i32
203 #define tcg_gen_remu_reg tcg_gen_remu_i32
204 #define tcg_gen_discard_reg tcg_gen_discard_i32
205 #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
206 #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
207 #define tcg_gen_extu_i32_reg tcg_gen_mov_i32
208 #define tcg_gen_ext_i32_reg tcg_gen_mov_i32
209 #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
210 #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
211 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
212 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
213 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
214 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
215 #define tcg_gen_ext32u_reg tcg_gen_mov_i32
216 #define tcg_gen_ext32s_reg tcg_gen_mov_i32
217 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
218 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
219 #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
220 #define tcg_gen_andc_reg tcg_gen_andc_i32
221 #define tcg_gen_eqv_reg tcg_gen_eqv_i32
222 #define tcg_gen_nand_reg tcg_gen_nand_i32
223 #define tcg_gen_nor_reg tcg_gen_nor_i32
224 #define tcg_gen_orc_reg tcg_gen_orc_i32
225 #define tcg_gen_clz_reg tcg_gen_clz_i32
226 #define tcg_gen_ctz_reg tcg_gen_ctz_i32
227 #define tcg_gen_clzi_reg tcg_gen_clzi_i32
228 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
229 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
230 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
231 #define tcg_gen_rotl_reg tcg_gen_rotl_i32
232 #define tcg_gen_rotli_reg tcg_gen_rotli_i32
233 #define tcg_gen_rotr_reg tcg_gen_rotr_i32
234 #define tcg_gen_rotri_reg tcg_gen_rotri_i32
235 #define tcg_gen_deposit_reg tcg_gen_deposit_i32
236 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
237 #define tcg_gen_extract_reg tcg_gen_extract_i32
238 #define tcg_gen_sextract_reg tcg_gen_sextract_i32
239 #define tcg_const_reg tcg_const_i32
240 #define tcg_const_local_reg tcg_const_local_i32
241 #define tcg_gen_movcond_reg tcg_gen_movcond_i32
242 #define tcg_gen_add2_reg tcg_gen_add2_i32
243 #define tcg_gen_sub2_reg tcg_gen_sub2_i32
244 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
245 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
246 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
247 #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
248 #endif /* TARGET_REGISTER_BITS */
250 typedef struct DisasCond
{
257 typedef struct DisasContext
{
258 DisasContextBase base
;
280 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
281 static int expand_sm_imm(DisasContext
*ctx
, int val
)
283 if (val
& PSW_SM_E
) {
284 val
= (val
& ~PSW_SM_E
) | PSW_E
;
286 if (val
& PSW_SM_W
) {
287 val
= (val
& ~PSW_SM_W
) | PSW_W
;
292 /* Inverted space register indicates 0 means sr0 not inferred from base. */
293 static int expand_sr3x(DisasContext
*ctx
, int val
)
298 /* Convert the M:A bits within a memory insn to the tri-state value
299 we use for the final M. */
300 static int ma_to_m(DisasContext
*ctx
, int val
)
302 return val
& 2 ? (val
& 1 ? -1 : 1) : 0;
305 /* Convert the sign of the displacement to a pre or post-modify. */
306 static int pos_to_m(DisasContext
*ctx
, int val
)
311 static int neg_to_m(DisasContext
*ctx
, int val
)
316 /* Used for branch targets and fp memory ops. */
317 static int expand_shl2(DisasContext
*ctx
, int val
)
322 /* Used for fp memory ops. */
323 static int expand_shl3(DisasContext
*ctx
, int val
)
328 /* Used for assemble_21. */
329 static int expand_shl11(DisasContext
*ctx
, int val
)
335 /* Include the auto-generated decoder. */
336 #include "decode-insns.c.inc"
338 /* We are not using a goto_tb (for whatever reason), but have updated
339 the iaq (for whatever reason), so don't do it again on exit. */
340 #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0
342 /* We are exiting the TB, but have neither emitted a goto_tb, nor
343 updated the iaq for the next instruction to be executed. */
344 #define DISAS_IAQ_N_STALE DISAS_TARGET_1
346 /* Similarly, but we want to return to the main loop immediately
347 to recognize unmasked interrupts. */
348 #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2
349 #define DISAS_EXIT DISAS_TARGET_3
351 /* global register indexes */
352 static TCGv_reg cpu_gr
[32];
353 static TCGv_i64 cpu_sr
[4];
354 static TCGv_i64 cpu_srH
;
355 static TCGv_reg cpu_iaoq_f
;
356 static TCGv_reg cpu_iaoq_b
;
357 static TCGv_i64 cpu_iasq_f
;
358 static TCGv_i64 cpu_iasq_b
;
359 static TCGv_reg cpu_sar
;
360 static TCGv_reg cpu_psw_n
;
361 static TCGv_reg cpu_psw_v
;
362 static TCGv_reg cpu_psw_cb
;
363 static TCGv_reg cpu_psw_cb_msb
;
365 #include "exec/gen-icount.h"
367 void hppa_translate_init(void)
369 #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
371 typedef struct { TCGv_reg
*var
; const char *name
; int ofs
; } GlobalVar
;
372 static const GlobalVar vars
[] = {
373 { &cpu_sar
, "sar", offsetof(CPUHPPAState
, cr
[CR_SAR
]) },
384 /* Use the symbolic register names that match the disassembler. */
385 static const char gr_names
[32][4] = {
386 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
387 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
388 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
389 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
391 /* SR[4-7] are not global registers so that we can index them. */
392 static const char sr_names
[5][4] = {
393 "sr0", "sr1", "sr2", "sr3", "srH"
399 for (i
= 1; i
< 32; i
++) {
400 cpu_gr
[i
] = tcg_global_mem_new(cpu_env
,
401 offsetof(CPUHPPAState
, gr
[i
]),
404 for (i
= 0; i
< 4; i
++) {
405 cpu_sr
[i
] = tcg_global_mem_new_i64(cpu_env
,
406 offsetof(CPUHPPAState
, sr
[i
]),
409 cpu_srH
= tcg_global_mem_new_i64(cpu_env
,
410 offsetof(CPUHPPAState
, sr
[4]),
413 for (i
= 0; i
< ARRAY_SIZE(vars
); ++i
) {
414 const GlobalVar
*v
= &vars
[i
];
415 *v
->var
= tcg_global_mem_new(cpu_env
, v
->ofs
, v
->name
);
418 cpu_iasq_f
= tcg_global_mem_new_i64(cpu_env
,
419 offsetof(CPUHPPAState
, iasq_f
),
421 cpu_iasq_b
= tcg_global_mem_new_i64(cpu_env
,
422 offsetof(CPUHPPAState
, iasq_b
),
426 static DisasCond
cond_make_f(void)
435 static DisasCond
cond_make_t(void)
438 .c
= TCG_COND_ALWAYS
,
444 static DisasCond
cond_make_n(void)
455 static DisasCond
cond_make_0_tmp(TCGCond c
, TCGv_reg a0
)
457 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
459 .c
= c
, .a0
= a0
, .a1_is_0
= true
463 static DisasCond
cond_make_0(TCGCond c
, TCGv_reg a0
)
465 TCGv_reg tmp
= tcg_temp_new();
466 tcg_gen_mov_reg(tmp
, a0
);
467 return cond_make_0_tmp(c
, tmp
);
470 static DisasCond
cond_make(TCGCond c
, TCGv_reg a0
, TCGv_reg a1
)
472 DisasCond r
= { .c
= c
};
474 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
475 r
.a0
= tcg_temp_new();
476 tcg_gen_mov_reg(r
.a0
, a0
);
477 r
.a1
= tcg_temp_new();
478 tcg_gen_mov_reg(r
.a1
, a1
);
483 static void cond_prep(DisasCond
*cond
)
486 cond
->a1_is_0
= false;
487 cond
->a1
= tcg_const_reg(0);
491 static void cond_free(DisasCond
*cond
)
495 if (!cond
->a0_is_n
) {
496 tcg_temp_free(cond
->a0
);
498 if (!cond
->a1_is_0
) {
499 tcg_temp_free(cond
->a1
);
501 cond
->a0_is_n
= false;
502 cond
->a1_is_0
= false;
506 case TCG_COND_ALWAYS
:
507 cond
->c
= TCG_COND_NEVER
;
514 static TCGv_reg
get_temp(DisasContext
*ctx
)
516 unsigned i
= ctx
->ntempr
++;
517 g_assert(i
< ARRAY_SIZE(ctx
->tempr
));
518 return ctx
->tempr
[i
] = tcg_temp_new();
521 #ifndef CONFIG_USER_ONLY
522 static TCGv_tl
get_temp_tl(DisasContext
*ctx
)
524 unsigned i
= ctx
->ntempl
++;
525 g_assert(i
< ARRAY_SIZE(ctx
->templ
));
526 return ctx
->templ
[i
] = tcg_temp_new_tl();
530 static TCGv_reg
load_const(DisasContext
*ctx
, target_sreg v
)
532 TCGv_reg t
= get_temp(ctx
);
533 tcg_gen_movi_reg(t
, v
);
537 static TCGv_reg
load_gpr(DisasContext
*ctx
, unsigned reg
)
540 TCGv_reg t
= get_temp(ctx
);
541 tcg_gen_movi_reg(t
, 0);
548 static TCGv_reg
dest_gpr(DisasContext
*ctx
, unsigned reg
)
550 if (reg
== 0 || ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
551 return get_temp(ctx
);
557 static void save_or_nullify(DisasContext
*ctx
, TCGv_reg dest
, TCGv_reg t
)
559 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
560 cond_prep(&ctx
->null_cond
);
561 tcg_gen_movcond_reg(ctx
->null_cond
.c
, dest
, ctx
->null_cond
.a0
,
562 ctx
->null_cond
.a1
, dest
, t
);
564 tcg_gen_mov_reg(dest
, t
);
568 static void save_gpr(DisasContext
*ctx
, unsigned reg
, TCGv_reg t
)
571 save_or_nullify(ctx
, cpu_gr
[reg
], t
);
575 #ifdef HOST_WORDS_BIGENDIAN
583 static TCGv_i32
load_frw_i32(unsigned rt
)
585 TCGv_i32 ret
= tcg_temp_new_i32();
586 tcg_gen_ld_i32(ret
, cpu_env
,
587 offsetof(CPUHPPAState
, fr
[rt
& 31])
588 + (rt
& 32 ? LO_OFS
: HI_OFS
));
592 static TCGv_i32
load_frw0_i32(unsigned rt
)
595 return tcg_const_i32(0);
597 return load_frw_i32(rt
);
601 static TCGv_i64
load_frw0_i64(unsigned rt
)
604 return tcg_const_i64(0);
606 TCGv_i64 ret
= tcg_temp_new_i64();
607 tcg_gen_ld32u_i64(ret
, cpu_env
,
608 offsetof(CPUHPPAState
, fr
[rt
& 31])
609 + (rt
& 32 ? LO_OFS
: HI_OFS
));
614 static void save_frw_i32(unsigned rt
, TCGv_i32 val
)
616 tcg_gen_st_i32(val
, cpu_env
,
617 offsetof(CPUHPPAState
, fr
[rt
& 31])
618 + (rt
& 32 ? LO_OFS
: HI_OFS
));
624 static TCGv_i64
load_frd(unsigned rt
)
626 TCGv_i64 ret
= tcg_temp_new_i64();
627 tcg_gen_ld_i64(ret
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
631 static TCGv_i64
load_frd0(unsigned rt
)
634 return tcg_const_i64(0);
640 static void save_frd(unsigned rt
, TCGv_i64 val
)
642 tcg_gen_st_i64(val
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
645 static void load_spr(DisasContext
*ctx
, TCGv_i64 dest
, unsigned reg
)
647 #ifdef CONFIG_USER_ONLY
648 tcg_gen_movi_i64(dest
, 0);
651 tcg_gen_mov_i64(dest
, cpu_sr
[reg
]);
652 } else if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
653 tcg_gen_mov_i64(dest
, cpu_srH
);
655 tcg_gen_ld_i64(dest
, cpu_env
, offsetof(CPUHPPAState
, sr
[reg
]));
660 /* Skip over the implementation of an insn that has been nullified.
661 Use this when the insn is too complex for a conditional move. */
662 static void nullify_over(DisasContext
*ctx
)
664 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
665 /* The always condition should have been handled in the main loop. */
666 assert(ctx
->null_cond
.c
!= TCG_COND_ALWAYS
);
668 ctx
->null_lab
= gen_new_label();
669 cond_prep(&ctx
->null_cond
);
671 /* If we're using PSW[N], copy it to a temp because... */
672 if (ctx
->null_cond
.a0_is_n
) {
673 ctx
->null_cond
.a0_is_n
= false;
674 ctx
->null_cond
.a0
= tcg_temp_new();
675 tcg_gen_mov_reg(ctx
->null_cond
.a0
, cpu_psw_n
);
677 /* ... we clear it before branching over the implementation,
678 so that (1) it's clear after nullifying this insn and
679 (2) if this insn nullifies the next, PSW[N] is valid. */
680 if (ctx
->psw_n_nonzero
) {
681 ctx
->psw_n_nonzero
= false;
682 tcg_gen_movi_reg(cpu_psw_n
, 0);
685 tcg_gen_brcond_reg(ctx
->null_cond
.c
, ctx
->null_cond
.a0
,
686 ctx
->null_cond
.a1
, ctx
->null_lab
);
687 cond_free(&ctx
->null_cond
);
691 /* Save the current nullification state to PSW[N]. */
692 static void nullify_save(DisasContext
*ctx
)
694 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
695 if (ctx
->psw_n_nonzero
) {
696 tcg_gen_movi_reg(cpu_psw_n
, 0);
700 if (!ctx
->null_cond
.a0_is_n
) {
701 cond_prep(&ctx
->null_cond
);
702 tcg_gen_setcond_reg(ctx
->null_cond
.c
, cpu_psw_n
,
703 ctx
->null_cond
.a0
, ctx
->null_cond
.a1
);
704 ctx
->psw_n_nonzero
= true;
706 cond_free(&ctx
->null_cond
);
709 /* Set a PSW[N] to X. The intention is that this is used immediately
710 before a goto_tb/exit_tb, so that there is no fallthru path to other
711 code within the TB. Therefore we do not update psw_n_nonzero. */
712 static void nullify_set(DisasContext
*ctx
, bool x
)
714 if (ctx
->psw_n_nonzero
|| x
) {
715 tcg_gen_movi_reg(cpu_psw_n
, x
);
719 /* Mark the end of an instruction that may have been nullified.
720 This is the pair to nullify_over. Always returns true so that
721 it may be tail-called from a translate function. */
722 static bool nullify_end(DisasContext
*ctx
)
724 TCGLabel
*null_lab
= ctx
->null_lab
;
725 DisasJumpType status
= ctx
->base
.is_jmp
;
727 /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
728 For UPDATED, we cannot update on the nullified path. */
729 assert(status
!= DISAS_IAQ_N_UPDATED
);
731 if (likely(null_lab
== NULL
)) {
732 /* The current insn wasn't conditional or handled the condition
733 applied to it without a branch, so the (new) setting of
734 NULL_COND can be applied directly to the next insn. */
737 ctx
->null_lab
= NULL
;
739 if (likely(ctx
->null_cond
.c
== TCG_COND_NEVER
)) {
740 /* The next instruction will be unconditional,
741 and NULL_COND already reflects that. */
742 gen_set_label(null_lab
);
744 /* The insn that we just executed is itself nullifying the next
745 instruction. Store the condition in the PSW[N] global.
746 We asserted PSW[N] = 0 in nullify_over, so that after the
747 label we have the proper value in place. */
749 gen_set_label(null_lab
);
750 ctx
->null_cond
= cond_make_n();
752 if (status
== DISAS_NORETURN
) {
753 ctx
->base
.is_jmp
= DISAS_NEXT
;
758 static void copy_iaoq_entry(TCGv_reg dest
, target_ureg ival
, TCGv_reg vval
)
760 if (unlikely(ival
== -1)) {
761 tcg_gen_mov_reg(dest
, vval
);
763 tcg_gen_movi_reg(dest
, ival
);
767 static inline target_ureg
iaoq_dest(DisasContext
*ctx
, target_sreg disp
)
769 return ctx
->iaoq_f
+ disp
+ 8;
772 static void gen_excp_1(int exception
)
774 TCGv_i32 t
= tcg_const_i32(exception
);
775 gen_helper_excp(cpu_env
, t
);
776 tcg_temp_free_i32(t
);
779 static void gen_excp(DisasContext
*ctx
, int exception
)
781 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
782 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
784 gen_excp_1(exception
);
785 ctx
->base
.is_jmp
= DISAS_NORETURN
;
788 static bool gen_excp_iir(DisasContext
*ctx
, int exc
)
793 tmp
= tcg_const_reg(ctx
->insn
);
794 tcg_gen_st_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[CR_IIR
]));
797 return nullify_end(ctx
);
800 static bool gen_illegal(DisasContext
*ctx
)
802 return gen_excp_iir(ctx
, EXCP_ILL
);
805 #ifdef CONFIG_USER_ONLY
806 #define CHECK_MOST_PRIVILEGED(EXCP) \
807 return gen_excp_iir(ctx, EXCP)
809 #define CHECK_MOST_PRIVILEGED(EXCP) \
811 if (ctx->privilege != 0) { \
812 return gen_excp_iir(ctx, EXCP); \
817 static bool use_goto_tb(DisasContext
*ctx
, target_ureg dest
)
819 return translator_use_goto_tb(&ctx
->base
, dest
);
822 /* If the next insn is to be nullified, and it's on the same page,
823 and we're not attempting to set a breakpoint on it, then we can
824 totally skip the nullified insn. This avoids creating and
825 executing a TB that merely branches to the next TB. */
826 static bool use_nullify_skip(DisasContext
*ctx
)
828 return (((ctx
->iaoq_b
^ ctx
->iaoq_f
) & TARGET_PAGE_MASK
) == 0
829 && !cpu_breakpoint_test(ctx
->cs
, ctx
->iaoq_b
, BP_ANY
));
832 static void gen_goto_tb(DisasContext
*ctx
, int which
,
833 target_ureg f
, target_ureg b
)
835 if (f
!= -1 && b
!= -1 && use_goto_tb(ctx
, f
)) {
836 tcg_gen_goto_tb(which
);
837 tcg_gen_movi_reg(cpu_iaoq_f
, f
);
838 tcg_gen_movi_reg(cpu_iaoq_b
, b
);
839 tcg_gen_exit_tb(ctx
->base
.tb
, which
);
841 copy_iaoq_entry(cpu_iaoq_f
, f
, cpu_iaoq_b
);
842 copy_iaoq_entry(cpu_iaoq_b
, b
, ctx
->iaoq_n_var
);
843 if (ctx
->base
.singlestep_enabled
) {
844 gen_excp_1(EXCP_DEBUG
);
846 tcg_gen_lookup_and_goto_ptr();
851 static bool cond_need_sv(int c
)
853 return c
== 2 || c
== 3 || c
== 6;
856 static bool cond_need_cb(int c
)
858 return c
== 4 || c
== 5;
862 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
863 * the Parisc 1.1 Architecture Reference Manual for details.
866 static DisasCond
do_cond(unsigned cf
, TCGv_reg res
,
867 TCGv_reg cb_msb
, TCGv_reg sv
)
873 case 0: /* Never / TR (0 / 1) */
874 cond
= cond_make_f();
876 case 1: /* = / <> (Z / !Z) */
877 cond
= cond_make_0(TCG_COND_EQ
, res
);
879 case 2: /* < / >= (N ^ V / !(N ^ V) */
880 tmp
= tcg_temp_new();
881 tcg_gen_xor_reg(tmp
, res
, sv
);
882 cond
= cond_make_0_tmp(TCG_COND_LT
, tmp
);
884 case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
888 * ((res < 0) ^ (sv < 0)) | !res
889 * ((res ^ sv) < 0) | !res
890 * (~(res ^ sv) >= 0) | !res
891 * !(~(res ^ sv) >> 31) | !res
892 * !(~(res ^ sv) >> 31 & res)
894 tmp
= tcg_temp_new();
895 tcg_gen_eqv_reg(tmp
, res
, sv
);
896 tcg_gen_sari_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
897 tcg_gen_and_reg(tmp
, tmp
, res
);
898 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
900 case 4: /* NUV / UV (!C / C) */
901 cond
= cond_make_0(TCG_COND_EQ
, cb_msb
);
903 case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
904 tmp
= tcg_temp_new();
905 tcg_gen_neg_reg(tmp
, cb_msb
);
906 tcg_gen_and_reg(tmp
, tmp
, res
);
907 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
909 case 6: /* SV / NSV (V / !V) */
910 cond
= cond_make_0(TCG_COND_LT
, sv
);
912 case 7: /* OD / EV */
913 tmp
= tcg_temp_new();
914 tcg_gen_andi_reg(tmp
, res
, 1);
915 cond
= cond_make_0_tmp(TCG_COND_NE
, tmp
);
918 g_assert_not_reached();
921 cond
.c
= tcg_invert_cond(cond
.c
);
927 /* Similar, but for the special case of subtraction without borrow, we
928 can use the inputs directly. This can allow other computation to be
929 deleted as unused. */
931 static DisasCond
do_sub_cond(unsigned cf
, TCGv_reg res
,
932 TCGv_reg in1
, TCGv_reg in2
, TCGv_reg sv
)
938 cond
= cond_make(TCG_COND_EQ
, in1
, in2
);
941 cond
= cond_make(TCG_COND_LT
, in1
, in2
);
944 cond
= cond_make(TCG_COND_LE
, in1
, in2
);
946 case 4: /* << / >>= */
947 cond
= cond_make(TCG_COND_LTU
, in1
, in2
);
949 case 5: /* <<= / >> */
950 cond
= cond_make(TCG_COND_LEU
, in1
, in2
);
953 return do_cond(cf
, res
, NULL
, sv
);
956 cond
.c
= tcg_invert_cond(cond
.c
);
963 * Similar, but for logicals, where the carry and overflow bits are not
964 * computed, and use of them is undefined.
966 * Undefined or not, hardware does not trap. It seems reasonable to
967 * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
968 * how cases c={2,3} are treated.
971 static DisasCond
do_log_cond(unsigned cf
, TCGv_reg res
)
975 case 9: /* undef, C */
976 case 11: /* undef, C & !Z */
977 case 12: /* undef, V */
978 return cond_make_f();
981 case 8: /* undef, !C */
982 case 10: /* undef, !C | Z */
983 case 13: /* undef, !V */
984 return cond_make_t();
987 return cond_make_0(TCG_COND_EQ
, res
);
989 return cond_make_0(TCG_COND_NE
, res
);
991 return cond_make_0(TCG_COND_LT
, res
);
993 return cond_make_0(TCG_COND_GE
, res
);
995 return cond_make_0(TCG_COND_LE
, res
);
997 return cond_make_0(TCG_COND_GT
, res
);
1001 return do_cond(cf
, res
, NULL
, NULL
);
1004 g_assert_not_reached();
1008 /* Similar, but for shift/extract/deposit conditions. */
1010 static DisasCond
do_sed_cond(unsigned orig
, TCGv_reg res
)
1014 /* Convert the compressed condition codes to standard.
1015 0-2 are the same as logicals (nv,<,<=), while 3 is OD.
1016 4-7 are the reverse of 0-3. */
1023 return do_log_cond(c
* 2 + f
, res
);
1026 /* Similar, but for unit conditions. */
1028 static DisasCond
do_unit_cond(unsigned cf
, TCGv_reg res
,
1029 TCGv_reg in1
, TCGv_reg in2
)
1032 TCGv_reg tmp
, cb
= NULL
;
1035 /* Since we want to test lots of carry-out bits all at once, do not
1036 * do our normal thing and compute carry-in of bit B+1 since that
1037 * leaves us with carry bits spread across two words.
1039 cb
= tcg_temp_new();
1040 tmp
= tcg_temp_new();
1041 tcg_gen_or_reg(cb
, in1
, in2
);
1042 tcg_gen_and_reg(tmp
, in1
, in2
);
1043 tcg_gen_andc_reg(cb
, cb
, res
);
1044 tcg_gen_or_reg(cb
, cb
, tmp
);
1049 case 0: /* never / TR */
1050 case 1: /* undefined */
1051 case 5: /* undefined */
1052 cond
= cond_make_f();
1055 case 2: /* SBZ / NBZ */
1056 /* See hasless(v,1) from
1057 * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
1059 tmp
= tcg_temp_new();
1060 tcg_gen_subi_reg(tmp
, res
, 0x01010101u
);
1061 tcg_gen_andc_reg(tmp
, tmp
, res
);
1062 tcg_gen_andi_reg(tmp
, tmp
, 0x80808080u
);
1063 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1067 case 3: /* SHZ / NHZ */
1068 tmp
= tcg_temp_new();
1069 tcg_gen_subi_reg(tmp
, res
, 0x00010001u
);
1070 tcg_gen_andc_reg(tmp
, tmp
, res
);
1071 tcg_gen_andi_reg(tmp
, tmp
, 0x80008000u
);
1072 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1076 case 4: /* SDC / NDC */
1077 tcg_gen_andi_reg(cb
, cb
, 0x88888888u
);
1078 cond
= cond_make_0(TCG_COND_NE
, cb
);
1081 case 6: /* SBC / NBC */
1082 tcg_gen_andi_reg(cb
, cb
, 0x80808080u
);
1083 cond
= cond_make_0(TCG_COND_NE
, cb
);
1086 case 7: /* SHC / NHC */
1087 tcg_gen_andi_reg(cb
, cb
, 0x80008000u
);
1088 cond
= cond_make_0(TCG_COND_NE
, cb
);
1092 g_assert_not_reached();
1098 cond
.c
= tcg_invert_cond(cond
.c
);
1104 /* Compute signed overflow for addition. */
1105 static TCGv_reg
do_add_sv(DisasContext
*ctx
, TCGv_reg res
,
1106 TCGv_reg in1
, TCGv_reg in2
)
1108 TCGv_reg sv
= get_temp(ctx
);
1109 TCGv_reg tmp
= tcg_temp_new();
1111 tcg_gen_xor_reg(sv
, res
, in1
);
1112 tcg_gen_xor_reg(tmp
, in1
, in2
);
1113 tcg_gen_andc_reg(sv
, sv
, tmp
);
1119 /* Compute signed overflow for subtraction. */
1120 static TCGv_reg
do_sub_sv(DisasContext
*ctx
, TCGv_reg res
,
1121 TCGv_reg in1
, TCGv_reg in2
)
1123 TCGv_reg sv
= get_temp(ctx
);
1124 TCGv_reg tmp
= tcg_temp_new();
1126 tcg_gen_xor_reg(sv
, res
, in1
);
1127 tcg_gen_xor_reg(tmp
, in1
, in2
);
1128 tcg_gen_and_reg(sv
, sv
, tmp
);
1134 static void do_add(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1135 TCGv_reg in2
, unsigned shift
, bool is_l
,
1136 bool is_tsv
, bool is_tc
, bool is_c
, unsigned cf
)
1138 TCGv_reg dest
, cb
, cb_msb
, sv
, tmp
;
1139 unsigned c
= cf
>> 1;
1142 dest
= tcg_temp_new();
1147 tmp
= get_temp(ctx
);
1148 tcg_gen_shli_reg(tmp
, in1
, shift
);
1152 if (!is_l
|| cond_need_cb(c
)) {
1153 TCGv_reg zero
= tcg_const_reg(0);
1154 cb_msb
= get_temp(ctx
);
1155 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, in2
, zero
);
1157 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cpu_psw_cb_msb
, zero
);
1159 tcg_temp_free(zero
);
1162 tcg_gen_xor_reg(cb
, in1
, in2
);
1163 tcg_gen_xor_reg(cb
, cb
, dest
);
1166 tcg_gen_add_reg(dest
, in1
, in2
);
1168 tcg_gen_add_reg(dest
, dest
, cpu_psw_cb_msb
);
1172 /* Compute signed overflow if required. */
1174 if (is_tsv
|| cond_need_sv(c
)) {
1175 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
1177 /* ??? Need to include overflow from shift. */
1178 gen_helper_tsv(cpu_env
, sv
);
1182 /* Emit any conditional trap before any writeback. */
1183 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1186 tmp
= tcg_temp_new();
1187 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1188 gen_helper_tcond(cpu_env
, tmp
);
1192 /* Write back the result. */
1194 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1195 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1197 save_gpr(ctx
, rt
, dest
);
1198 tcg_temp_free(dest
);
1200 /* Install the new nullification. */
1201 cond_free(&ctx
->null_cond
);
1202 ctx
->null_cond
= cond
;
1205 static bool do_add_reg(DisasContext
*ctx
, arg_rrr_cf_sh
*a
,
1206 bool is_l
, bool is_tsv
, bool is_tc
, bool is_c
)
1208 TCGv_reg tcg_r1
, tcg_r2
;
1213 tcg_r1
= load_gpr(ctx
, a
->r1
);
1214 tcg_r2
= load_gpr(ctx
, a
->r2
);
1215 do_add(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->sh
, is_l
, is_tsv
, is_tc
, is_c
, a
->cf
);
1216 return nullify_end(ctx
);
1219 static bool do_add_imm(DisasContext
*ctx
, arg_rri_cf
*a
,
1220 bool is_tsv
, bool is_tc
)
1222 TCGv_reg tcg_im
, tcg_r2
;
1227 tcg_im
= load_const(ctx
, a
->i
);
1228 tcg_r2
= load_gpr(ctx
, a
->r
);
1229 do_add(ctx
, a
->t
, tcg_im
, tcg_r2
, 0, 0, is_tsv
, is_tc
, 0, a
->cf
);
1230 return nullify_end(ctx
);
1233 static void do_sub(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1234 TCGv_reg in2
, bool is_tsv
, bool is_b
,
1235 bool is_tc
, unsigned cf
)
1237 TCGv_reg dest
, sv
, cb
, cb_msb
, zero
, tmp
;
1238 unsigned c
= cf
>> 1;
1241 dest
= tcg_temp_new();
1242 cb
= tcg_temp_new();
1243 cb_msb
= tcg_temp_new();
1245 zero
= tcg_const_reg(0);
1247 /* DEST,C = IN1 + ~IN2 + C. */
1248 tcg_gen_not_reg(cb
, in2
);
1249 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, cpu_psw_cb_msb
, zero
);
1250 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cb
, zero
);
1251 tcg_gen_xor_reg(cb
, cb
, in1
);
1252 tcg_gen_xor_reg(cb
, cb
, dest
);
1254 /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
1255 operations by seeding the high word with 1 and subtracting. */
1256 tcg_gen_movi_reg(cb_msb
, 1);
1257 tcg_gen_sub2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, zero
);
1258 tcg_gen_eqv_reg(cb
, in1
, in2
);
1259 tcg_gen_xor_reg(cb
, cb
, dest
);
1261 tcg_temp_free(zero
);
1263 /* Compute signed overflow if required. */
1265 if (is_tsv
|| cond_need_sv(c
)) {
1266 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1268 gen_helper_tsv(cpu_env
, sv
);
1272 /* Compute the condition. We cannot use the special case for borrow. */
1274 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1276 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1279 /* Emit any conditional trap before any writeback. */
1282 tmp
= tcg_temp_new();
1283 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1284 gen_helper_tcond(cpu_env
, tmp
);
1288 /* Write back the result. */
1289 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1290 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1291 save_gpr(ctx
, rt
, dest
);
1292 tcg_temp_free(dest
);
1294 tcg_temp_free(cb_msb
);
1296 /* Install the new nullification. */
1297 cond_free(&ctx
->null_cond
);
1298 ctx
->null_cond
= cond
;
1301 static bool do_sub_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1302 bool is_tsv
, bool is_b
, bool is_tc
)
1304 TCGv_reg tcg_r1
, tcg_r2
;
1309 tcg_r1
= load_gpr(ctx
, a
->r1
);
1310 tcg_r2
= load_gpr(ctx
, a
->r2
);
1311 do_sub(ctx
, a
->t
, tcg_r1
, tcg_r2
, is_tsv
, is_b
, is_tc
, a
->cf
);
1312 return nullify_end(ctx
);
1315 static bool do_sub_imm(DisasContext
*ctx
, arg_rri_cf
*a
, bool is_tsv
)
1317 TCGv_reg tcg_im
, tcg_r2
;
1322 tcg_im
= load_const(ctx
, a
->i
);
1323 tcg_r2
= load_gpr(ctx
, a
->r
);
1324 do_sub(ctx
, a
->t
, tcg_im
, tcg_r2
, is_tsv
, 0, 0, a
->cf
);
1325 return nullify_end(ctx
);
1328 static void do_cmpclr(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1329 TCGv_reg in2
, unsigned cf
)
1334 dest
= tcg_temp_new();
1335 tcg_gen_sub_reg(dest
, in1
, in2
);
1337 /* Compute signed overflow if required. */
1339 if (cond_need_sv(cf
>> 1)) {
1340 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1343 /* Form the condition for the compare. */
1344 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1347 tcg_gen_movi_reg(dest
, 0);
1348 save_gpr(ctx
, rt
, dest
);
1349 tcg_temp_free(dest
);
1351 /* Install the new nullification. */
1352 cond_free(&ctx
->null_cond
);
1353 ctx
->null_cond
= cond
;
1356 static void do_log(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1357 TCGv_reg in2
, unsigned cf
,
1358 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1360 TCGv_reg dest
= dest_gpr(ctx
, rt
);
1362 /* Perform the operation, and writeback. */
1364 save_gpr(ctx
, rt
, dest
);
1366 /* Install the new nullification. */
1367 cond_free(&ctx
->null_cond
);
1369 ctx
->null_cond
= do_log_cond(cf
, dest
);
1373 static bool do_log_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1374 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1376 TCGv_reg tcg_r1
, tcg_r2
;
1381 tcg_r1
= load_gpr(ctx
, a
->r1
);
1382 tcg_r2
= load_gpr(ctx
, a
->r2
);
1383 do_log(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, fn
);
1384 return nullify_end(ctx
);
1387 static void do_unit(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1388 TCGv_reg in2
, unsigned cf
, bool is_tc
,
1389 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1395 dest
= dest_gpr(ctx
, rt
);
1397 save_gpr(ctx
, rt
, dest
);
1398 cond_free(&ctx
->null_cond
);
1400 dest
= tcg_temp_new();
1403 cond
= do_unit_cond(cf
, dest
, in1
, in2
);
1406 TCGv_reg tmp
= tcg_temp_new();
1408 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1409 gen_helper_tcond(cpu_env
, tmp
);
1412 save_gpr(ctx
, rt
, dest
);
1414 cond_free(&ctx
->null_cond
);
1415 ctx
->null_cond
= cond
;
1419 #ifndef CONFIG_USER_ONLY
1420 /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
1421 from the top 2 bits of the base register. There are a few system
1422 instructions that have a 3-bit space specifier, for which SR0 is
1423 not special. To handle this, pass ~SP. */
1424 static TCGv_i64
space_select(DisasContext
*ctx
, int sp
, TCGv_reg base
)
1434 spc
= get_temp_tl(ctx
);
1435 load_spr(ctx
, spc
, sp
);
1438 if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
1442 ptr
= tcg_temp_new_ptr();
1443 tmp
= tcg_temp_new();
1444 spc
= get_temp_tl(ctx
);
1446 tcg_gen_shri_reg(tmp
, base
, TARGET_REGISTER_BITS
- 5);
1447 tcg_gen_andi_reg(tmp
, tmp
, 030);
1448 tcg_gen_trunc_reg_ptr(ptr
, tmp
);
1451 tcg_gen_add_ptr(ptr
, ptr
, cpu_env
);
1452 tcg_gen_ld_i64(spc
, ptr
, offsetof(CPUHPPAState
, sr
[4]));
1453 tcg_temp_free_ptr(ptr
);
1459 static void form_gva(DisasContext
*ctx
, TCGv_tl
*pgva
, TCGv_reg
*pofs
,
1460 unsigned rb
, unsigned rx
, int scale
, target_sreg disp
,
1461 unsigned sp
, int modify
, bool is_phys
)
1463 TCGv_reg base
= load_gpr(ctx
, rb
);
1466 /* Note that RX is mutually exclusive with DISP. */
1468 ofs
= get_temp(ctx
);
1469 tcg_gen_shli_reg(ofs
, cpu_gr
[rx
], scale
);
1470 tcg_gen_add_reg(ofs
, ofs
, base
);
1471 } else if (disp
|| modify
) {
1472 ofs
= get_temp(ctx
);
1473 tcg_gen_addi_reg(ofs
, base
, disp
);
1479 #ifdef CONFIG_USER_ONLY
1480 *pgva
= (modify
<= 0 ? ofs
: base
);
1482 TCGv_tl addr
= get_temp_tl(ctx
);
1483 tcg_gen_extu_reg_tl(addr
, modify
<= 0 ? ofs
: base
);
1484 if (ctx
->tb_flags
& PSW_W
) {
1485 tcg_gen_andi_tl(addr
, addr
, 0x3fffffffffffffffull
);
1488 tcg_gen_or_tl(addr
, addr
, space_select(ctx
, sp
, base
));
1494 /* Emit a memory load. The modify parameter should be
1495 * < 0 for pre-modify,
1496 * > 0 for post-modify,
1497 * = 0 for no base register update.
1499 static void do_load_32(DisasContext
*ctx
, TCGv_i32 dest
, unsigned rb
,
1500 unsigned rx
, int scale
, target_sreg disp
,
1501 unsigned sp
, int modify
, MemOp mop
)
1506 /* Caller uses nullify_over/nullify_end. */
1507 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1509 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1510 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1511 tcg_gen_qemu_ld_reg(dest
, addr
, ctx
->mmu_idx
, mop
);
1513 save_gpr(ctx
, rb
, ofs
);
1517 static void do_load_64(DisasContext
*ctx
, TCGv_i64 dest
, unsigned rb
,
1518 unsigned rx
, int scale
, target_sreg disp
,
1519 unsigned sp
, int modify
, MemOp mop
)
1524 /* Caller uses nullify_over/nullify_end. */
1525 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1527 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1528 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1529 tcg_gen_qemu_ld_i64(dest
, addr
, ctx
->mmu_idx
, mop
);
1531 save_gpr(ctx
, rb
, ofs
);
1535 static void do_store_32(DisasContext
*ctx
, TCGv_i32 src
, unsigned rb
,
1536 unsigned rx
, int scale
, target_sreg disp
,
1537 unsigned sp
, int modify
, MemOp mop
)
1542 /* Caller uses nullify_over/nullify_end. */
1543 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1545 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1546 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1547 tcg_gen_qemu_st_i32(src
, addr
, ctx
->mmu_idx
, mop
);
1549 save_gpr(ctx
, rb
, ofs
);
1553 static void do_store_64(DisasContext
*ctx
, TCGv_i64 src
, unsigned rb
,
1554 unsigned rx
, int scale
, target_sreg disp
,
1555 unsigned sp
, int modify
, MemOp mop
)
1560 /* Caller uses nullify_over/nullify_end. */
1561 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1563 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1564 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1565 tcg_gen_qemu_st_i64(src
, addr
, ctx
->mmu_idx
, mop
);
1567 save_gpr(ctx
, rb
, ofs
);
1571 #if TARGET_REGISTER_BITS == 64
1572 #define do_load_reg do_load_64
1573 #define do_store_reg do_store_64
1575 #define do_load_reg do_load_32
1576 #define do_store_reg do_store_32
1579 static bool do_load(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1580 unsigned rx
, int scale
, target_sreg disp
,
1581 unsigned sp
, int modify
, MemOp mop
)
1588 /* No base register update. */
1589 dest
= dest_gpr(ctx
, rt
);
1591 /* Make sure if RT == RB, we see the result of the load. */
1592 dest
= get_temp(ctx
);
1594 do_load_reg(ctx
, dest
, rb
, rx
, scale
, disp
, sp
, modify
, mop
);
1595 save_gpr(ctx
, rt
, dest
);
1597 return nullify_end(ctx
);
1600 static bool do_floadw(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1601 unsigned rx
, int scale
, target_sreg disp
,
1602 unsigned sp
, int modify
)
1608 tmp
= tcg_temp_new_i32();
1609 do_load_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1610 save_frw_i32(rt
, tmp
);
1611 tcg_temp_free_i32(tmp
);
1614 gen_helper_loaded_fr0(cpu_env
);
1617 return nullify_end(ctx
);
1620 static bool trans_fldw(DisasContext
*ctx
, arg_ldst
*a
)
1622 return do_floadw(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1623 a
->disp
, a
->sp
, a
->m
);
1626 static bool do_floadd(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1627 unsigned rx
, int scale
, target_sreg disp
,
1628 unsigned sp
, int modify
)
1634 tmp
= tcg_temp_new_i64();
1635 do_load_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEQ
);
1637 tcg_temp_free_i64(tmp
);
1640 gen_helper_loaded_fr0(cpu_env
);
1643 return nullify_end(ctx
);
1646 static bool trans_fldd(DisasContext
*ctx
, arg_ldst
*a
)
1648 return do_floadd(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1649 a
->disp
, a
->sp
, a
->m
);
1652 static bool do_store(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1653 target_sreg disp
, unsigned sp
,
1654 int modify
, MemOp mop
)
1657 do_store_reg(ctx
, load_gpr(ctx
, rt
), rb
, 0, 0, disp
, sp
, modify
, mop
);
1658 return nullify_end(ctx
);
1661 static bool do_fstorew(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1662 unsigned rx
, int scale
, target_sreg disp
,
1663 unsigned sp
, int modify
)
1669 tmp
= load_frw_i32(rt
);
1670 do_store_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1671 tcg_temp_free_i32(tmp
);
1673 return nullify_end(ctx
);
1676 static bool trans_fstw(DisasContext
*ctx
, arg_ldst
*a
)
1678 return do_fstorew(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1679 a
->disp
, a
->sp
, a
->m
);
1682 static bool do_fstored(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1683 unsigned rx
, int scale
, target_sreg disp
,
1684 unsigned sp
, int modify
)
1691 do_store_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEQ
);
1692 tcg_temp_free_i64(tmp
);
1694 return nullify_end(ctx
);
1697 static bool trans_fstd(DisasContext
*ctx
, arg_ldst
*a
)
1699 return do_fstored(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1700 a
->disp
, a
->sp
, a
->m
);
1703 static bool do_fop_wew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1704 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
))
1709 tmp
= load_frw0_i32(ra
);
1711 func(tmp
, cpu_env
, tmp
);
1713 save_frw_i32(rt
, tmp
);
1714 tcg_temp_free_i32(tmp
);
1715 return nullify_end(ctx
);
1718 static bool do_fop_wed(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1719 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i64
))
1726 dst
= tcg_temp_new_i32();
1728 func(dst
, cpu_env
, src
);
1730 tcg_temp_free_i64(src
);
1731 save_frw_i32(rt
, dst
);
1732 tcg_temp_free_i32(dst
);
1733 return nullify_end(ctx
);
1736 static bool do_fop_ded(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1737 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
1742 tmp
= load_frd0(ra
);
1744 func(tmp
, cpu_env
, tmp
);
1747 tcg_temp_free_i64(tmp
);
1748 return nullify_end(ctx
);
1751 static bool do_fop_dew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1752 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i32
))
1758 src
= load_frw0_i32(ra
);
1759 dst
= tcg_temp_new_i64();
1761 func(dst
, cpu_env
, src
);
1763 tcg_temp_free_i32(src
);
1765 tcg_temp_free_i64(dst
);
1766 return nullify_end(ctx
);
1769 static bool do_fop_weww(DisasContext
*ctx
, unsigned rt
,
1770 unsigned ra
, unsigned rb
,
1771 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
1776 a
= load_frw0_i32(ra
);
1777 b
= load_frw0_i32(rb
);
1779 func(a
, cpu_env
, a
, b
);
1781 tcg_temp_free_i32(b
);
1782 save_frw_i32(rt
, a
);
1783 tcg_temp_free_i32(a
);
1784 return nullify_end(ctx
);
1787 static bool do_fop_dedd(DisasContext
*ctx
, unsigned rt
,
1788 unsigned ra
, unsigned rb
,
1789 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
1797 func(a
, cpu_env
, a
, b
);
1799 tcg_temp_free_i64(b
);
1801 tcg_temp_free_i64(a
);
1802 return nullify_end(ctx
);
1805 /* Emit an unconditional branch to a direct target, which may or may not
1806 have already had nullification handled. */
1807 static bool do_dbranch(DisasContext
*ctx
, target_ureg dest
,
1808 unsigned link
, bool is_n
)
1810 if (ctx
->null_cond
.c
== TCG_COND_NEVER
&& ctx
->null_lab
== NULL
) {
1812 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1816 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1822 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1825 if (is_n
&& use_nullify_skip(ctx
)) {
1826 nullify_set(ctx
, 0);
1827 gen_goto_tb(ctx
, 0, dest
, dest
+ 4);
1829 nullify_set(ctx
, is_n
);
1830 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, dest
);
1835 nullify_set(ctx
, 0);
1836 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, ctx
->iaoq_n
);
1837 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1842 /* Emit a conditional branch to a direct target. If the branch itself
1843 is nullified, we should have already used nullify_over. */
1844 static bool do_cbranch(DisasContext
*ctx
, target_sreg disp
, bool is_n
,
1847 target_ureg dest
= iaoq_dest(ctx
, disp
);
1848 TCGLabel
*taken
= NULL
;
1849 TCGCond c
= cond
->c
;
1852 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1854 /* Handle TRUE and NEVER as direct branches. */
1855 if (c
== TCG_COND_ALWAYS
) {
1856 return do_dbranch(ctx
, dest
, 0, is_n
&& disp
>= 0);
1858 if (c
== TCG_COND_NEVER
) {
1859 return do_dbranch(ctx
, ctx
->iaoq_n
, 0, is_n
&& disp
< 0);
1862 taken
= gen_new_label();
1864 tcg_gen_brcond_reg(c
, cond
->a0
, cond
->a1
, taken
);
1867 /* Not taken: Condition not satisfied; nullify on backward branches. */
1868 n
= is_n
&& disp
< 0;
1869 if (n
&& use_nullify_skip(ctx
)) {
1870 nullify_set(ctx
, 0);
1871 gen_goto_tb(ctx
, 0, ctx
->iaoq_n
, ctx
->iaoq_n
+ 4);
1873 if (!n
&& ctx
->null_lab
) {
1874 gen_set_label(ctx
->null_lab
);
1875 ctx
->null_lab
= NULL
;
1877 nullify_set(ctx
, n
);
1878 if (ctx
->iaoq_n
== -1) {
1879 /* The temporary iaoq_n_var died at the branch above.
1880 Regenerate it here instead of saving it. */
1881 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
1883 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
1886 gen_set_label(taken
);
1888 /* Taken: Condition satisfied; nullify on forward branches. */
1889 n
= is_n
&& disp
>= 0;
1890 if (n
&& use_nullify_skip(ctx
)) {
1891 nullify_set(ctx
, 0);
1892 gen_goto_tb(ctx
, 1, dest
, dest
+ 4);
1894 nullify_set(ctx
, n
);
1895 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, dest
);
1898 /* Not taken: the branch itself was nullified. */
1899 if (ctx
->null_lab
) {
1900 gen_set_label(ctx
->null_lab
);
1901 ctx
->null_lab
= NULL
;
1902 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
1904 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1909 /* Emit an unconditional branch to an indirect target. This handles
1910 nullification of the branch itself. */
1911 static bool do_ibranch(DisasContext
*ctx
, TCGv_reg dest
,
1912 unsigned link
, bool is_n
)
1914 TCGv_reg a0
, a1
, next
, tmp
;
1917 assert(ctx
->null_lab
== NULL
);
1919 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
1921 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1923 next
= get_temp(ctx
);
1924 tcg_gen_mov_reg(next
, dest
);
1926 if (use_nullify_skip(ctx
)) {
1927 tcg_gen_mov_reg(cpu_iaoq_f
, next
);
1928 tcg_gen_addi_reg(cpu_iaoq_b
, next
, 4);
1929 nullify_set(ctx
, 0);
1930 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
1933 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1936 ctx
->iaoq_n_var
= next
;
1937 } else if (is_n
&& use_nullify_skip(ctx
)) {
1938 /* The (conditional) branch, B, nullifies the next insn, N,
1939 and we're allowed to skip execution N (no single-step or
1940 tracepoint in effect). Since the goto_ptr that we must use
1941 for the indirect branch consumes no special resources, we
1942 can (conditionally) skip B and continue execution. */
1943 /* The use_nullify_skip test implies we have a known control path. */
1944 tcg_debug_assert(ctx
->iaoq_b
!= -1);
1945 tcg_debug_assert(ctx
->iaoq_n
!= -1);
1947 /* We do have to handle the non-local temporary, DEST, before
1948 branching. Since IOAQ_F is not really live at this point, we
1949 can simply store DEST optimistically. Similarly with IAOQ_B. */
1950 tcg_gen_mov_reg(cpu_iaoq_f
, dest
);
1951 tcg_gen_addi_reg(cpu_iaoq_b
, dest
, 4);
1955 tcg_gen_movi_reg(cpu_gr
[link
], ctx
->iaoq_n
);
1957 tcg_gen_lookup_and_goto_ptr();
1958 return nullify_end(ctx
);
1960 cond_prep(&ctx
->null_cond
);
1961 c
= ctx
->null_cond
.c
;
1962 a0
= ctx
->null_cond
.a0
;
1963 a1
= ctx
->null_cond
.a1
;
1965 tmp
= tcg_temp_new();
1966 next
= get_temp(ctx
);
1968 copy_iaoq_entry(tmp
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1969 tcg_gen_movcond_reg(c
, next
, a0
, a1
, tmp
, dest
);
1971 ctx
->iaoq_n_var
= next
;
1974 tcg_gen_movcond_reg(c
, cpu_gr
[link
], a0
, a1
, cpu_gr
[link
], tmp
);
1978 /* The branch nullifies the next insn, which means the state of N
1979 after the branch is the inverse of the state of N that applied
1981 tcg_gen_setcond_reg(tcg_invert_cond(c
), cpu_psw_n
, a0
, a1
);
1982 cond_free(&ctx
->null_cond
);
1983 ctx
->null_cond
= cond_make_n();
1984 ctx
->psw_n_nonzero
= true;
1986 cond_free(&ctx
->null_cond
);
1993 * if (IAOQ_Front{30..31} < GR[b]{30..31})
1994 * IAOQ_Next{30..31} ← GR[b]{30..31};
1996 * IAOQ_Next{30..31} ← IAOQ_Front{30..31};
1997 * which keeps the privilege level from being increased.
1999 static TCGv_reg
do_ibranch_priv(DisasContext
*ctx
, TCGv_reg offset
)
2002 switch (ctx
->privilege
) {
2004 /* Privilege 0 is maximum and is allowed to decrease. */
2007 /* Privilege 3 is minimum and is never allowed to increase. */
2008 dest
= get_temp(ctx
);
2009 tcg_gen_ori_reg(dest
, offset
, 3);
2012 dest
= get_temp(ctx
);
2013 tcg_gen_andi_reg(dest
, offset
, -4);
2014 tcg_gen_ori_reg(dest
, dest
, ctx
->privilege
);
2015 tcg_gen_movcond_reg(TCG_COND_GTU
, dest
, dest
, offset
, dest
, offset
);
2021 #ifdef CONFIG_USER_ONLY
2022 /* On Linux, page zero is normally marked execute only + gateway.
2023 Therefore normal read or write is supposed to fail, but specific
2024 offsets have kernel code mapped to raise permissions to implement
2025 system calls. Handling this via an explicit check here, rather
2026 in than the "be disp(sr2,r0)" instruction that probably sent us
2027 here, is the easiest way to handle the branch delay slot on the
2028 aforementioned BE. */
2029 static void do_page_zero(DisasContext
*ctx
)
2031 /* If by some means we get here with PSW[N]=1, that implies that
2032 the B,GATE instruction would be skipped, and we'd fault on the
2033 next insn within the privilaged page. */
2034 switch (ctx
->null_cond
.c
) {
2035 case TCG_COND_NEVER
:
2037 case TCG_COND_ALWAYS
:
2038 tcg_gen_movi_reg(cpu_psw_n
, 0);
2041 /* Since this is always the first (and only) insn within the
2042 TB, we should know the state of PSW[N] from TB->FLAGS. */
2043 g_assert_not_reached();
2046 /* Check that we didn't arrive here via some means that allowed
2047 non-sequential instruction execution. Normally the PSW[B] bit
2048 detects this by disallowing the B,GATE instruction to execute
2049 under such conditions. */
2050 if (ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
2054 switch (ctx
->iaoq_f
& -4) {
2055 case 0x00: /* Null pointer call */
2056 gen_excp_1(EXCP_IMP
);
2057 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2060 case 0xb0: /* LWS */
2061 gen_excp_1(EXCP_SYSCALL_LWS
);
2062 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2065 case 0xe0: /* SET_THREAD_POINTER */
2066 tcg_gen_st_reg(cpu_gr
[26], cpu_env
, offsetof(CPUHPPAState
, cr
[27]));
2067 tcg_gen_ori_reg(cpu_iaoq_f
, cpu_gr
[31], 3);
2068 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
2069 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
2072 case 0x100: /* SYSCALL */
2073 gen_excp_1(EXCP_SYSCALL
);
2074 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2079 gen_excp_1(EXCP_ILL
);
2080 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2086 static bool trans_nop(DisasContext
*ctx
, arg_nop
*a
)
2088 cond_free(&ctx
->null_cond
);
2092 static bool trans_break(DisasContext
*ctx
, arg_break
*a
)
2094 return gen_excp_iir(ctx
, EXCP_BREAK
);
2097 static bool trans_sync(DisasContext
*ctx
, arg_sync
*a
)
2099 /* No point in nullifying the memory barrier. */
2100 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
2102 cond_free(&ctx
->null_cond
);
2106 static bool trans_mfia(DisasContext
*ctx
, arg_mfia
*a
)
2109 TCGv_reg tmp
= dest_gpr(ctx
, rt
);
2110 tcg_gen_movi_reg(tmp
, ctx
->iaoq_f
);
2111 save_gpr(ctx
, rt
, tmp
);
2113 cond_free(&ctx
->null_cond
);
2117 static bool trans_mfsp(DisasContext
*ctx
, arg_mfsp
*a
)
2120 unsigned rs
= a
->sp
;
2121 TCGv_i64 t0
= tcg_temp_new_i64();
2122 TCGv_reg t1
= tcg_temp_new();
2124 load_spr(ctx
, t0
, rs
);
2125 tcg_gen_shri_i64(t0
, t0
, 32);
2126 tcg_gen_trunc_i64_reg(t1
, t0
);
2128 save_gpr(ctx
, rt
, t1
);
2130 tcg_temp_free_i64(t0
);
2132 cond_free(&ctx
->null_cond
);
2136 static bool trans_mfctl(DisasContext
*ctx
, arg_mfctl
*a
)
2139 unsigned ctl
= a
->r
;
2144 #ifdef TARGET_HPPA64
2146 /* MFSAR without ,W masks low 5 bits. */
2147 tmp
= dest_gpr(ctx
, rt
);
2148 tcg_gen_andi_reg(tmp
, cpu_sar
, 31);
2149 save_gpr(ctx
, rt
, tmp
);
2153 save_gpr(ctx
, rt
, cpu_sar
);
2155 case CR_IT
: /* Interval Timer */
2156 /* FIXME: Respect PSW_S bit. */
2158 tmp
= dest_gpr(ctx
, rt
);
2159 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
2161 gen_helper_read_interval_timer(tmp
);
2162 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2164 gen_helper_read_interval_timer(tmp
);
2166 save_gpr(ctx
, rt
, tmp
);
2167 return nullify_end(ctx
);
2172 /* All other control registers are privileged. */
2173 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2177 tmp
= get_temp(ctx
);
2178 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2179 save_gpr(ctx
, rt
, tmp
);
2182 cond_free(&ctx
->null_cond
);
2186 static bool trans_mtsp(DisasContext
*ctx
, arg_mtsp
*a
)
2189 unsigned rs
= a
->sp
;
2193 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2197 t64
= tcg_temp_new_i64();
2198 tcg_gen_extu_reg_i64(t64
, load_gpr(ctx
, rr
));
2199 tcg_gen_shli_i64(t64
, t64
, 32);
2202 tcg_gen_st_i64(t64
, cpu_env
, offsetof(CPUHPPAState
, sr
[rs
]));
2203 ctx
->tb_flags
&= ~TB_FLAG_SR_SAME
;
2205 tcg_gen_mov_i64(cpu_sr
[rs
], t64
);
2207 tcg_temp_free_i64(t64
);
2209 return nullify_end(ctx
);
2212 static bool trans_mtctl(DisasContext
*ctx
, arg_mtctl
*a
)
2214 unsigned ctl
= a
->t
;
2218 if (ctl
== CR_SAR
) {
2219 reg
= load_gpr(ctx
, a
->r
);
2220 tmp
= tcg_temp_new();
2221 tcg_gen_andi_reg(tmp
, reg
, TARGET_REGISTER_BITS
- 1);
2222 save_or_nullify(ctx
, cpu_sar
, tmp
);
2225 cond_free(&ctx
->null_cond
);
2229 /* All other control registers are privileged or read-only. */
2230 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2232 #ifndef CONFIG_USER_ONLY
2234 reg
= load_gpr(ctx
, a
->r
);
2238 gen_helper_write_interval_timer(cpu_env
, reg
);
2241 gen_helper_write_eirr(cpu_env
, reg
);
2244 gen_helper_write_eiem(cpu_env
, reg
);
2245 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2250 /* FIXME: Respect PSW_Q bit */
2251 /* The write advances the queue and stores to the back element. */
2252 tmp
= get_temp(ctx
);
2253 tcg_gen_ld_reg(tmp
, cpu_env
,
2254 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2255 tcg_gen_st_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2256 tcg_gen_st_reg(reg
, cpu_env
,
2257 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2264 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2265 #ifndef CONFIG_USER_ONLY
2266 gen_helper_change_prot_id(cpu_env
);
2271 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2274 return nullify_end(ctx
);
2278 static bool trans_mtsarcm(DisasContext
*ctx
, arg_mtsarcm
*a
)
2280 TCGv_reg tmp
= tcg_temp_new();
2282 tcg_gen_not_reg(tmp
, load_gpr(ctx
, a
->r
));
2283 tcg_gen_andi_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
2284 save_or_nullify(ctx
, cpu_sar
, tmp
);
2287 cond_free(&ctx
->null_cond
);
2291 static bool trans_ldsid(DisasContext
*ctx
, arg_ldsid
*a
)
2293 TCGv_reg dest
= dest_gpr(ctx
, a
->t
);
2295 #ifdef CONFIG_USER_ONLY
2296 /* We don't implement space registers in user mode. */
2297 tcg_gen_movi_reg(dest
, 0);
2299 TCGv_i64 t0
= tcg_temp_new_i64();
2301 tcg_gen_mov_i64(t0
, space_select(ctx
, a
->sp
, load_gpr(ctx
, a
->b
)));
2302 tcg_gen_shri_i64(t0
, t0
, 32);
2303 tcg_gen_trunc_i64_reg(dest
, t0
);
2305 tcg_temp_free_i64(t0
);
2307 save_gpr(ctx
, a
->t
, dest
);
2309 cond_free(&ctx
->null_cond
);
2313 static bool trans_rsm(DisasContext
*ctx
, arg_rsm
*a
)
2315 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2316 #ifndef CONFIG_USER_ONLY
2321 tmp
= get_temp(ctx
);
2322 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2323 tcg_gen_andi_reg(tmp
, tmp
, ~a
->i
);
2324 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2325 save_gpr(ctx
, a
->t
, tmp
);
2327 /* Exit the TB to recognize new interrupts, e.g. PSW_M. */
2328 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2329 return nullify_end(ctx
);
2333 static bool trans_ssm(DisasContext
*ctx
, arg_ssm
*a
)
2335 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2336 #ifndef CONFIG_USER_ONLY
2341 tmp
= get_temp(ctx
);
2342 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2343 tcg_gen_ori_reg(tmp
, tmp
, a
->i
);
2344 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2345 save_gpr(ctx
, a
->t
, tmp
);
2347 /* Exit the TB to recognize new interrupts, e.g. PSW_I. */
2348 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2349 return nullify_end(ctx
);
2353 static bool trans_mtsm(DisasContext
*ctx
, arg_mtsm
*a
)
2355 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2356 #ifndef CONFIG_USER_ONLY
2360 reg
= load_gpr(ctx
, a
->r
);
2361 tmp
= get_temp(ctx
);
2362 gen_helper_swap_system_mask(tmp
, cpu_env
, reg
);
2364 /* Exit the TB to recognize new interrupts. */
2365 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2366 return nullify_end(ctx
);
2370 static bool do_rfi(DisasContext
*ctx
, bool rfi_r
)
2372 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2373 #ifndef CONFIG_USER_ONLY
2377 gen_helper_rfi_r(cpu_env
);
2379 gen_helper_rfi(cpu_env
);
2381 /* Exit the TB to recognize new interrupts. */
2382 if (ctx
->base
.singlestep_enabled
) {
2383 gen_excp_1(EXCP_DEBUG
);
2385 tcg_gen_exit_tb(NULL
, 0);
2387 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2389 return nullify_end(ctx
);
2393 static bool trans_rfi(DisasContext
*ctx
, arg_rfi
*a
)
2395 return do_rfi(ctx
, false);
2398 static bool trans_rfi_r(DisasContext
*ctx
, arg_rfi_r
*a
)
2400 return do_rfi(ctx
, true);
2403 static bool trans_halt(DisasContext
*ctx
, arg_halt
*a
)
2405 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2406 #ifndef CONFIG_USER_ONLY
2408 gen_helper_halt(cpu_env
);
2409 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2410 return nullify_end(ctx
);
2414 static bool trans_reset(DisasContext
*ctx
, arg_reset
*a
)
2416 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2417 #ifndef CONFIG_USER_ONLY
2419 gen_helper_reset(cpu_env
);
2420 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2421 return nullify_end(ctx
);
2425 static bool trans_nop_addrx(DisasContext
*ctx
, arg_ldst
*a
)
2428 TCGv_reg dest
= dest_gpr(ctx
, a
->b
);
2429 TCGv_reg src1
= load_gpr(ctx
, a
->b
);
2430 TCGv_reg src2
= load_gpr(ctx
, a
->x
);
2432 /* The only thing we need to do is the base register modification. */
2433 tcg_gen_add_reg(dest
, src1
, src2
);
2434 save_gpr(ctx
, a
->b
, dest
);
2436 cond_free(&ctx
->null_cond
);
2440 static bool trans_probe(DisasContext
*ctx
, arg_probe
*a
)
2443 TCGv_i32 level
, want
;
2448 dest
= dest_gpr(ctx
, a
->t
);
2449 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2452 level
= tcg_const_i32(a
->ri
);
2454 level
= tcg_temp_new_i32();
2455 tcg_gen_trunc_reg_i32(level
, load_gpr(ctx
, a
->ri
));
2456 tcg_gen_andi_i32(level
, level
, 3);
2458 want
= tcg_const_i32(a
->write
? PAGE_WRITE
: PAGE_READ
);
2460 gen_helper_probe(dest
, cpu_env
, addr
, level
, want
);
2462 tcg_temp_free_i32(want
);
2463 tcg_temp_free_i32(level
);
2465 save_gpr(ctx
, a
->t
, dest
);
2466 return nullify_end(ctx
);
2469 static bool trans_ixtlbx(DisasContext
*ctx
, arg_ixtlbx
*a
)
2471 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2472 #ifndef CONFIG_USER_ONLY
2478 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2479 reg
= load_gpr(ctx
, a
->r
);
2481 gen_helper_itlba(cpu_env
, addr
, reg
);
2483 gen_helper_itlbp(cpu_env
, addr
, reg
);
2486 /* Exit TB for TLB change if mmu is enabled. */
2487 if (ctx
->tb_flags
& PSW_C
) {
2488 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2490 return nullify_end(ctx
);
2494 static bool trans_pxtlbx(DisasContext
*ctx
, arg_pxtlbx
*a
)
2496 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2497 #ifndef CONFIG_USER_ONLY
2503 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2505 save_gpr(ctx
, a
->b
, ofs
);
2508 gen_helper_ptlbe(cpu_env
);
2510 gen_helper_ptlb(cpu_env
, addr
);
2513 /* Exit TB for TLB change if mmu is enabled. */
2514 if (ctx
->tb_flags
& PSW_C
) {
2515 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2517 return nullify_end(ctx
);
2522 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2524 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2525 * page 13-9 (195/206)
2527 static bool trans_ixtlbxf(DisasContext
*ctx
, arg_ixtlbxf
*a
)
2529 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2530 #ifndef CONFIG_USER_ONLY
2531 TCGv_tl addr
, atl
, stl
;
2538 * if (not (pcxl or pcxl2))
2539 * return gen_illegal(ctx);
2541 * Note for future: these are 32-bit systems; no hppa64.
2544 atl
= tcg_temp_new_tl();
2545 stl
= tcg_temp_new_tl();
2546 addr
= tcg_temp_new_tl();
2548 tcg_gen_ld32u_i64(stl
, cpu_env
,
2549 a
->data
? offsetof(CPUHPPAState
, cr
[CR_ISR
])
2550 : offsetof(CPUHPPAState
, cr
[CR_IIASQ
]));
2551 tcg_gen_ld32u_i64(atl
, cpu_env
,
2552 a
->data
? offsetof(CPUHPPAState
, cr
[CR_IOR
])
2553 : offsetof(CPUHPPAState
, cr
[CR_IIAOQ
]));
2554 tcg_gen_shli_i64(stl
, stl
, 32);
2555 tcg_gen_or_tl(addr
, atl
, stl
);
2556 tcg_temp_free_tl(atl
);
2557 tcg_temp_free_tl(stl
);
2559 reg
= load_gpr(ctx
, a
->r
);
2561 gen_helper_itlba(cpu_env
, addr
, reg
);
2563 gen_helper_itlbp(cpu_env
, addr
, reg
);
2565 tcg_temp_free_tl(addr
);
2567 /* Exit TB for TLB change if mmu is enabled. */
2568 if (ctx
->tb_flags
& PSW_C
) {
2569 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2571 return nullify_end(ctx
);
2575 static bool trans_lpa(DisasContext
*ctx
, arg_ldst
*a
)
2577 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2578 #ifndef CONFIG_USER_ONLY
2580 TCGv_reg ofs
, paddr
;
2584 form_gva(ctx
, &vaddr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2586 paddr
= tcg_temp_new();
2587 gen_helper_lpa(paddr
, cpu_env
, vaddr
);
2589 /* Note that physical address result overrides base modification. */
2591 save_gpr(ctx
, a
->b
, ofs
);
2593 save_gpr(ctx
, a
->t
, paddr
);
2594 tcg_temp_free(paddr
);
2596 return nullify_end(ctx
);
2600 static bool trans_lci(DisasContext
*ctx
, arg_lci
*a
)
2604 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2606 /* The Coherence Index is an implementation-defined function of the
2607 physical address. Two addresses with the same CI have a coherent
2608 view of the cache. Our implementation is to return 0 for all,
2609 since the entire address space is coherent. */
2610 ci
= tcg_const_reg(0);
2611 save_gpr(ctx
, a
->t
, ci
);
2614 cond_free(&ctx
->null_cond
);
2618 static bool trans_add(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2620 return do_add_reg(ctx
, a
, false, false, false, false);
2623 static bool trans_add_l(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2625 return do_add_reg(ctx
, a
, true, false, false, false);
2628 static bool trans_add_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2630 return do_add_reg(ctx
, a
, false, true, false, false);
2633 static bool trans_add_c(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2635 return do_add_reg(ctx
, a
, false, false, false, true);
2638 static bool trans_add_c_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2640 return do_add_reg(ctx
, a
, false, true, false, true);
2643 static bool trans_sub(DisasContext
*ctx
, arg_rrr_cf
*a
)
2645 return do_sub_reg(ctx
, a
, false, false, false);
2648 static bool trans_sub_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2650 return do_sub_reg(ctx
, a
, true, false, false);
2653 static bool trans_sub_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2655 return do_sub_reg(ctx
, a
, false, false, true);
2658 static bool trans_sub_tsv_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2660 return do_sub_reg(ctx
, a
, true, false, true);
2663 static bool trans_sub_b(DisasContext
*ctx
, arg_rrr_cf
*a
)
2665 return do_sub_reg(ctx
, a
, false, true, false);
2668 static bool trans_sub_b_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2670 return do_sub_reg(ctx
, a
, true, true, false);
2673 static bool trans_andcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2675 return do_log_reg(ctx
, a
, tcg_gen_andc_reg
);
2678 static bool trans_and(DisasContext
*ctx
, arg_rrr_cf
*a
)
2680 return do_log_reg(ctx
, a
, tcg_gen_and_reg
);
2683 static bool trans_or(DisasContext
*ctx
, arg_rrr_cf
*a
)
2686 unsigned r2
= a
->r2
;
2687 unsigned r1
= a
->r1
;
2690 if (rt
== 0) { /* NOP */
2691 cond_free(&ctx
->null_cond
);
2694 if (r2
== 0) { /* COPY */
2696 TCGv_reg dest
= dest_gpr(ctx
, rt
);
2697 tcg_gen_movi_reg(dest
, 0);
2698 save_gpr(ctx
, rt
, dest
);
2700 save_gpr(ctx
, rt
, cpu_gr
[r1
]);
2702 cond_free(&ctx
->null_cond
);
2705 #ifndef CONFIG_USER_ONLY
2706 /* These are QEMU extensions and are nops in the real architecture:
2708 * or %r10,%r10,%r10 -- idle loop; wait for interrupt
2709 * or %r31,%r31,%r31 -- death loop; offline cpu
2710 * currently implemented as idle.
2712 if ((rt
== 10 || rt
== 31) && r1
== rt
&& r2
== rt
) { /* PAUSE */
2715 /* No need to check for supervisor, as userland can only pause
2716 until the next timer interrupt. */
2719 /* Advance the instruction queue. */
2720 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
2721 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
2722 nullify_set(ctx
, 0);
2724 /* Tell the qemu main loop to halt until this cpu has work. */
2725 tmp
= tcg_const_i32(1);
2726 tcg_gen_st_i32(tmp
, cpu_env
, -offsetof(HPPACPU
, env
) +
2727 offsetof(CPUState
, halted
));
2728 tcg_temp_free_i32(tmp
);
2729 gen_excp_1(EXCP_HALTED
);
2730 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2732 return nullify_end(ctx
);
2736 return do_log_reg(ctx
, a
, tcg_gen_or_reg
);
2739 static bool trans_xor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2741 return do_log_reg(ctx
, a
, tcg_gen_xor_reg
);
2744 static bool trans_cmpclr(DisasContext
*ctx
, arg_rrr_cf
*a
)
2746 TCGv_reg tcg_r1
, tcg_r2
;
2751 tcg_r1
= load_gpr(ctx
, a
->r1
);
2752 tcg_r2
= load_gpr(ctx
, a
->r2
);
2753 do_cmpclr(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
);
2754 return nullify_end(ctx
);
2757 static bool trans_uxor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2759 TCGv_reg tcg_r1
, tcg_r2
;
2764 tcg_r1
= load_gpr(ctx
, a
->r1
);
2765 tcg_r2
= load_gpr(ctx
, a
->r2
);
2766 do_unit(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, false, tcg_gen_xor_reg
);
2767 return nullify_end(ctx
);
2770 static bool do_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
, bool is_tc
)
2772 TCGv_reg tcg_r1
, tcg_r2
, tmp
;
2777 tcg_r1
= load_gpr(ctx
, a
->r1
);
2778 tcg_r2
= load_gpr(ctx
, a
->r2
);
2779 tmp
= get_temp(ctx
);
2780 tcg_gen_not_reg(tmp
, tcg_r2
);
2781 do_unit(ctx
, a
->t
, tcg_r1
, tmp
, a
->cf
, is_tc
, tcg_gen_add_reg
);
2782 return nullify_end(ctx
);
2785 static bool trans_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2787 return do_uaddcm(ctx
, a
, false);
2790 static bool trans_uaddcm_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2792 return do_uaddcm(ctx
, a
, true);
2795 static bool do_dcor(DisasContext
*ctx
, arg_rr_cf
*a
, bool is_i
)
2801 tmp
= get_temp(ctx
);
2802 tcg_gen_shri_reg(tmp
, cpu_psw_cb
, 3);
2804 tcg_gen_not_reg(tmp
, tmp
);
2806 tcg_gen_andi_reg(tmp
, tmp
, 0x11111111);
2807 tcg_gen_muli_reg(tmp
, tmp
, 6);
2808 do_unit(ctx
, a
->t
, load_gpr(ctx
, a
->r
), tmp
, a
->cf
, false,
2809 is_i
? tcg_gen_add_reg
: tcg_gen_sub_reg
);
2810 return nullify_end(ctx
);
2813 static bool trans_dcor(DisasContext
*ctx
, arg_rr_cf
*a
)
2815 return do_dcor(ctx
, a
, false);
2818 static bool trans_dcor_i(DisasContext
*ctx
, arg_rr_cf
*a
)
2820 return do_dcor(ctx
, a
, true);
2823 static bool trans_ds(DisasContext
*ctx
, arg_rrr_cf
*a
)
2825 TCGv_reg dest
, add1
, add2
, addc
, zero
, in1
, in2
;
2829 in1
= load_gpr(ctx
, a
->r1
);
2830 in2
= load_gpr(ctx
, a
->r2
);
2832 add1
= tcg_temp_new();
2833 add2
= tcg_temp_new();
2834 addc
= tcg_temp_new();
2835 dest
= tcg_temp_new();
2836 zero
= tcg_const_reg(0);
2838 /* Form R1 << 1 | PSW[CB]{8}. */
2839 tcg_gen_add_reg(add1
, in1
, in1
);
2840 tcg_gen_add_reg(add1
, add1
, cpu_psw_cb_msb
);
2842 /* Add or subtract R2, depending on PSW[V]. Proper computation of
2843 carry{8} requires that we subtract via + ~R2 + 1, as described in
2844 the manual. By extracting and masking V, we can produce the
2845 proper inputs to the addition without movcond. */
2846 tcg_gen_sari_reg(addc
, cpu_psw_v
, TARGET_REGISTER_BITS
- 1);
2847 tcg_gen_xor_reg(add2
, in2
, addc
);
2848 tcg_gen_andi_reg(addc
, addc
, 1);
2849 /* ??? This is only correct for 32-bit. */
2850 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, add1
, zero
, add2
, zero
);
2851 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, dest
, cpu_psw_cb_msb
, addc
, zero
);
2853 tcg_temp_free(addc
);
2854 tcg_temp_free(zero
);
2856 /* Write back the result register. */
2857 save_gpr(ctx
, a
->t
, dest
);
2859 /* Write back PSW[CB]. */
2860 tcg_gen_xor_reg(cpu_psw_cb
, add1
, add2
);
2861 tcg_gen_xor_reg(cpu_psw_cb
, cpu_psw_cb
, dest
);
2863 /* Write back PSW[V] for the division step. */
2864 tcg_gen_neg_reg(cpu_psw_v
, cpu_psw_cb_msb
);
2865 tcg_gen_xor_reg(cpu_psw_v
, cpu_psw_v
, in2
);
2867 /* Install the new nullification. */
2870 if (cond_need_sv(a
->cf
>> 1)) {
2871 /* ??? The lshift is supposed to contribute to overflow. */
2872 sv
= do_add_sv(ctx
, dest
, add1
, add2
);
2874 ctx
->null_cond
= do_cond(a
->cf
, dest
, cpu_psw_cb_msb
, sv
);
2877 tcg_temp_free(add1
);
2878 tcg_temp_free(add2
);
2879 tcg_temp_free(dest
);
2881 return nullify_end(ctx
);
2884 static bool trans_addi(DisasContext
*ctx
, arg_rri_cf
*a
)
2886 return do_add_imm(ctx
, a
, false, false);
2889 static bool trans_addi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2891 return do_add_imm(ctx
, a
, true, false);
2894 static bool trans_addi_tc(DisasContext
*ctx
, arg_rri_cf
*a
)
2896 return do_add_imm(ctx
, a
, false, true);
2899 static bool trans_addi_tc_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2901 return do_add_imm(ctx
, a
, true, true);
2904 static bool trans_subi(DisasContext
*ctx
, arg_rri_cf
*a
)
2906 return do_sub_imm(ctx
, a
, false);
2909 static bool trans_subi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2911 return do_sub_imm(ctx
, a
, true);
2914 static bool trans_cmpiclr(DisasContext
*ctx
, arg_rri_cf
*a
)
2916 TCGv_reg tcg_im
, tcg_r2
;
2922 tcg_im
= load_const(ctx
, a
->i
);
2923 tcg_r2
= load_gpr(ctx
, a
->r
);
2924 do_cmpclr(ctx
, a
->t
, tcg_im
, tcg_r2
, a
->cf
);
2926 return nullify_end(ctx
);
2929 static bool trans_ld(DisasContext
*ctx
, arg_ldst
*a
)
2931 return do_load(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2932 a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2935 static bool trans_st(DisasContext
*ctx
, arg_ldst
*a
)
2937 assert(a
->x
== 0 && a
->scale
== 0);
2938 return do_store(ctx
, a
->t
, a
->b
, a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2941 static bool trans_ldc(DisasContext
*ctx
, arg_ldst
*a
)
2943 MemOp mop
= MO_TE
| MO_ALIGN
| a
->size
;
2944 TCGv_reg zero
, dest
, ofs
;
2950 /* Base register modification. Make sure if RT == RB,
2951 we see the result of the load. */
2952 dest
= get_temp(ctx
);
2954 dest
= dest_gpr(ctx
, a
->t
);
2957 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2958 a
->disp
, a
->sp
, a
->m
, ctx
->mmu_idx
== MMU_PHYS_IDX
);
2961 * For hppa1.1, LDCW is undefined unless aligned mod 16.
2962 * However actual hardware succeeds with aligned mod 4.
2963 * Detect this case and log a GUEST_ERROR.
2965 * TODO: HPPA64 relaxes the over-alignment requirement
2966 * with the ,co completer.
2968 gen_helper_ldc_check(addr
);
2970 zero
= tcg_const_reg(0);
2971 tcg_gen_atomic_xchg_reg(dest
, addr
, zero
, ctx
->mmu_idx
, mop
);
2972 tcg_temp_free(zero
);
2975 save_gpr(ctx
, a
->b
, ofs
);
2977 save_gpr(ctx
, a
->t
, dest
);
2979 return nullify_end(ctx
);
2982 static bool trans_stby(DisasContext
*ctx
, arg_stby
*a
)
2989 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, a
->disp
, a
->sp
, a
->m
,
2990 ctx
->mmu_idx
== MMU_PHYS_IDX
);
2991 val
= load_gpr(ctx
, a
->r
);
2993 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2994 gen_helper_stby_e_parallel(cpu_env
, addr
, val
);
2996 gen_helper_stby_e(cpu_env
, addr
, val
);
2999 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3000 gen_helper_stby_b_parallel(cpu_env
, addr
, val
);
3002 gen_helper_stby_b(cpu_env
, addr
, val
);
3006 tcg_gen_andi_reg(ofs
, ofs
, ~3);
3007 save_gpr(ctx
, a
->b
, ofs
);
3010 return nullify_end(ctx
);
3013 static bool trans_lda(DisasContext
*ctx
, arg_ldst
*a
)
3015 int hold_mmu_idx
= ctx
->mmu_idx
;
3017 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
3018 ctx
->mmu_idx
= MMU_PHYS_IDX
;
3020 ctx
->mmu_idx
= hold_mmu_idx
;
3024 static bool trans_sta(DisasContext
*ctx
, arg_ldst
*a
)
3026 int hold_mmu_idx
= ctx
->mmu_idx
;
3028 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
3029 ctx
->mmu_idx
= MMU_PHYS_IDX
;
3031 ctx
->mmu_idx
= hold_mmu_idx
;
3035 static bool trans_ldil(DisasContext
*ctx
, arg_ldil
*a
)
3037 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
3039 tcg_gen_movi_reg(tcg_rt
, a
->i
);
3040 save_gpr(ctx
, a
->t
, tcg_rt
);
3041 cond_free(&ctx
->null_cond
);
3045 static bool trans_addil(DisasContext
*ctx
, arg_addil
*a
)
3047 TCGv_reg tcg_rt
= load_gpr(ctx
, a
->r
);
3048 TCGv_reg tcg_r1
= dest_gpr(ctx
, 1);
3050 tcg_gen_addi_reg(tcg_r1
, tcg_rt
, a
->i
);
3051 save_gpr(ctx
, 1, tcg_r1
);
3052 cond_free(&ctx
->null_cond
);
3056 static bool trans_ldo(DisasContext
*ctx
, arg_ldo
*a
)
3058 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
3060 /* Special case rb == 0, for the LDI pseudo-op.
3061 The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
3063 tcg_gen_movi_reg(tcg_rt
, a
->i
);
3065 tcg_gen_addi_reg(tcg_rt
, cpu_gr
[a
->b
], a
->i
);
3067 save_gpr(ctx
, a
->t
, tcg_rt
);
3068 cond_free(&ctx
->null_cond
);
3072 static bool do_cmpb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3073 unsigned c
, unsigned f
, unsigned n
, int disp
)
3075 TCGv_reg dest
, in2
, sv
;
3078 in2
= load_gpr(ctx
, r
);
3079 dest
= get_temp(ctx
);
3081 tcg_gen_sub_reg(dest
, in1
, in2
);
3084 if (cond_need_sv(c
)) {
3085 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
3088 cond
= do_sub_cond(c
* 2 + f
, dest
, in1
, in2
, sv
);
3089 return do_cbranch(ctx
, disp
, n
, &cond
);
3092 static bool trans_cmpb(DisasContext
*ctx
, arg_cmpb
*a
)
3095 return do_cmpb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3098 static bool trans_cmpbi(DisasContext
*ctx
, arg_cmpbi
*a
)
3101 return do_cmpb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3104 static bool do_addb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3105 unsigned c
, unsigned f
, unsigned n
, int disp
)
3107 TCGv_reg dest
, in2
, sv
, cb_msb
;
3110 in2
= load_gpr(ctx
, r
);
3111 dest
= tcg_temp_new();
3115 if (cond_need_cb(c
)) {
3116 cb_msb
= get_temp(ctx
);
3117 tcg_gen_movi_reg(cb_msb
, 0);
3118 tcg_gen_add2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, cb_msb
);
3120 tcg_gen_add_reg(dest
, in1
, in2
);
3122 if (cond_need_sv(c
)) {
3123 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
3126 cond
= do_cond(c
* 2 + f
, dest
, cb_msb
, sv
);
3127 save_gpr(ctx
, r
, dest
);
3128 tcg_temp_free(dest
);
3129 return do_cbranch(ctx
, disp
, n
, &cond
);
3132 static bool trans_addb(DisasContext
*ctx
, arg_addb
*a
)
3135 return do_addb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3138 static bool trans_addbi(DisasContext
*ctx
, arg_addbi
*a
)
3141 return do_addb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3144 static bool trans_bb_sar(DisasContext
*ctx
, arg_bb_sar
*a
)
3146 TCGv_reg tmp
, tcg_r
;
3151 tmp
= tcg_temp_new();
3152 tcg_r
= load_gpr(ctx
, a
->r
);
3153 tcg_gen_shl_reg(tmp
, tcg_r
, cpu_sar
);
3155 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3157 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3160 static bool trans_bb_imm(DisasContext
*ctx
, arg_bb_imm
*a
)
3162 TCGv_reg tmp
, tcg_r
;
3167 tmp
= tcg_temp_new();
3168 tcg_r
= load_gpr(ctx
, a
->r
);
3169 tcg_gen_shli_reg(tmp
, tcg_r
, a
->p
);
3171 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3173 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3176 static bool trans_movb(DisasContext
*ctx
, arg_movb
*a
)
3183 dest
= dest_gpr(ctx
, a
->r2
);
3185 tcg_gen_movi_reg(dest
, 0);
3187 tcg_gen_mov_reg(dest
, cpu_gr
[a
->r1
]);
3190 cond
= do_sed_cond(a
->c
, dest
);
3191 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3194 static bool trans_movbi(DisasContext
*ctx
, arg_movbi
*a
)
3201 dest
= dest_gpr(ctx
, a
->r
);
3202 tcg_gen_movi_reg(dest
, a
->i
);
3204 cond
= do_sed_cond(a
->c
, dest
);
3205 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3208 static bool trans_shrpw_sar(DisasContext
*ctx
, arg_shrpw_sar
*a
)
3216 dest
= dest_gpr(ctx
, a
->t
);
3218 tcg_gen_ext32u_reg(dest
, load_gpr(ctx
, a
->r2
));
3219 tcg_gen_shr_reg(dest
, dest
, cpu_sar
);
3220 } else if (a
->r1
== a
->r2
) {
3221 TCGv_i32 t32
= tcg_temp_new_i32();
3222 tcg_gen_trunc_reg_i32(t32
, load_gpr(ctx
, a
->r2
));
3223 tcg_gen_rotr_i32(t32
, t32
, cpu_sar
);
3224 tcg_gen_extu_i32_reg(dest
, t32
);
3225 tcg_temp_free_i32(t32
);
3227 TCGv_i64 t
= tcg_temp_new_i64();
3228 TCGv_i64 s
= tcg_temp_new_i64();
3230 tcg_gen_concat_reg_i64(t
, load_gpr(ctx
, a
->r2
), load_gpr(ctx
, a
->r1
));
3231 tcg_gen_extu_reg_i64(s
, cpu_sar
);
3232 tcg_gen_shr_i64(t
, t
, s
);
3233 tcg_gen_trunc_i64_reg(dest
, t
);
3235 tcg_temp_free_i64(t
);
3236 tcg_temp_free_i64(s
);
3238 save_gpr(ctx
, a
->t
, dest
);
3240 /* Install the new nullification. */
3241 cond_free(&ctx
->null_cond
);
3243 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3245 return nullify_end(ctx
);
3248 static bool trans_shrpw_imm(DisasContext
*ctx
, arg_shrpw_imm
*a
)
3250 unsigned sa
= 31 - a
->cpos
;
3257 dest
= dest_gpr(ctx
, a
->t
);
3258 t2
= load_gpr(ctx
, a
->r2
);
3259 if (a
->r1
== a
->r2
) {
3260 TCGv_i32 t32
= tcg_temp_new_i32();
3261 tcg_gen_trunc_reg_i32(t32
, t2
);
3262 tcg_gen_rotri_i32(t32
, t32
, sa
);
3263 tcg_gen_extu_i32_reg(dest
, t32
);
3264 tcg_temp_free_i32(t32
);
3265 } else if (a
->r1
== 0) {
3266 tcg_gen_extract_reg(dest
, t2
, sa
, 32 - sa
);
3268 TCGv_reg t0
= tcg_temp_new();
3269 tcg_gen_extract_reg(t0
, t2
, sa
, 32 - sa
);
3270 tcg_gen_deposit_reg(dest
, t0
, cpu_gr
[a
->r1
], 32 - sa
, sa
);
3273 save_gpr(ctx
, a
->t
, dest
);
3275 /* Install the new nullification. */
3276 cond_free(&ctx
->null_cond
);
3278 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3280 return nullify_end(ctx
);
3283 static bool trans_extrw_sar(DisasContext
*ctx
, arg_extrw_sar
*a
)
3285 unsigned len
= 32 - a
->clen
;
3286 TCGv_reg dest
, src
, tmp
;
3292 dest
= dest_gpr(ctx
, a
->t
);
3293 src
= load_gpr(ctx
, a
->r
);
3294 tmp
= tcg_temp_new();
3296 /* Recall that SAR is using big-endian bit numbering. */
3297 tcg_gen_xori_reg(tmp
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3299 tcg_gen_sar_reg(dest
, src
, tmp
);
3300 tcg_gen_sextract_reg(dest
, dest
, 0, len
);
3302 tcg_gen_shr_reg(dest
, src
, tmp
);
3303 tcg_gen_extract_reg(dest
, dest
, 0, len
);
3306 save_gpr(ctx
, a
->t
, dest
);
3308 /* Install the new nullification. */
3309 cond_free(&ctx
->null_cond
);
3311 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3313 return nullify_end(ctx
);
3316 static bool trans_extrw_imm(DisasContext
*ctx
, arg_extrw_imm
*a
)
3318 unsigned len
= 32 - a
->clen
;
3319 unsigned cpos
= 31 - a
->pos
;
3326 dest
= dest_gpr(ctx
, a
->t
);
3327 src
= load_gpr(ctx
, a
->r
);
3329 tcg_gen_sextract_reg(dest
, src
, cpos
, len
);
3331 tcg_gen_extract_reg(dest
, src
, cpos
, len
);
3333 save_gpr(ctx
, a
->t
, dest
);
3335 /* Install the new nullification. */
3336 cond_free(&ctx
->null_cond
);
3338 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3340 return nullify_end(ctx
);
3343 static bool trans_depwi_imm(DisasContext
*ctx
, arg_depwi_imm
*a
)
3345 unsigned len
= 32 - a
->clen
;
3346 target_sreg mask0
, mask1
;
3352 if (a
->cpos
+ len
> 32) {
3356 dest
= dest_gpr(ctx
, a
->t
);
3357 mask0
= deposit64(0, a
->cpos
, len
, a
->i
);
3358 mask1
= deposit64(-1, a
->cpos
, len
, a
->i
);
3361 TCGv_reg src
= load_gpr(ctx
, a
->t
);
3363 tcg_gen_andi_reg(dest
, src
, mask1
);
3366 tcg_gen_ori_reg(dest
, src
, mask0
);
3368 tcg_gen_movi_reg(dest
, mask0
);
3370 save_gpr(ctx
, a
->t
, dest
);
3372 /* Install the new nullification. */
3373 cond_free(&ctx
->null_cond
);
3375 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3377 return nullify_end(ctx
);
3380 static bool trans_depw_imm(DisasContext
*ctx
, arg_depw_imm
*a
)
3382 unsigned rs
= a
->nz
? a
->t
: 0;
3383 unsigned len
= 32 - a
->clen
;
3389 if (a
->cpos
+ len
> 32) {
3393 dest
= dest_gpr(ctx
, a
->t
);
3394 val
= load_gpr(ctx
, a
->r
);
3396 tcg_gen_deposit_z_reg(dest
, val
, a
->cpos
, len
);
3398 tcg_gen_deposit_reg(dest
, cpu_gr
[rs
], val
, a
->cpos
, len
);
3400 save_gpr(ctx
, a
->t
, dest
);
3402 /* Install the new nullification. */
3403 cond_free(&ctx
->null_cond
);
3405 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3407 return nullify_end(ctx
);
3410 static bool do_depw_sar(DisasContext
*ctx
, unsigned rt
, unsigned c
,
3411 unsigned nz
, unsigned clen
, TCGv_reg val
)
3413 unsigned rs
= nz
? rt
: 0;
3414 unsigned len
= 32 - clen
;
3415 TCGv_reg mask
, tmp
, shift
, dest
;
3416 unsigned msb
= 1U << (len
- 1);
3418 dest
= dest_gpr(ctx
, rt
);
3419 shift
= tcg_temp_new();
3420 tmp
= tcg_temp_new();
3422 /* Convert big-endian bit numbering in SAR to left-shift. */
3423 tcg_gen_xori_reg(shift
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3425 mask
= tcg_const_reg(msb
+ (msb
- 1));
3426 tcg_gen_and_reg(tmp
, val
, mask
);
3428 tcg_gen_shl_reg(mask
, mask
, shift
);
3429 tcg_gen_shl_reg(tmp
, tmp
, shift
);
3430 tcg_gen_andc_reg(dest
, cpu_gr
[rs
], mask
);
3431 tcg_gen_or_reg(dest
, dest
, tmp
);
3433 tcg_gen_shl_reg(dest
, tmp
, shift
);
3435 tcg_temp_free(shift
);
3436 tcg_temp_free(mask
);
3438 save_gpr(ctx
, rt
, dest
);
3440 /* Install the new nullification. */
3441 cond_free(&ctx
->null_cond
);
3443 ctx
->null_cond
= do_sed_cond(c
, dest
);
3445 return nullify_end(ctx
);
3448 static bool trans_depw_sar(DisasContext
*ctx
, arg_depw_sar
*a
)
3453 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_gpr(ctx
, a
->r
));
3456 static bool trans_depwi_sar(DisasContext
*ctx
, arg_depwi_sar
*a
)
3461 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_const(ctx
, a
->i
));
3464 static bool trans_be(DisasContext
*ctx
, arg_be
*a
)
3468 #ifdef CONFIG_USER_ONLY
3469 /* ??? It seems like there should be a good way of using
3470 "be disp(sr2, r0)", the canonical gateway entry mechanism
3471 to our advantage. But that appears to be inconvenient to
3472 manage along side branch delay slots. Therefore we handle
3473 entry into the gateway page via absolute address. */
3474 /* Since we don't implement spaces, just branch. Do notice the special
3475 case of "be disp(*,r0)" using a direct branch to disp, so that we can
3476 goto_tb to the TB containing the syscall. */
3478 return do_dbranch(ctx
, a
->disp
, a
->l
, a
->n
);
3484 tmp
= get_temp(ctx
);
3485 tcg_gen_addi_reg(tmp
, load_gpr(ctx
, a
->b
), a
->disp
);
3486 tmp
= do_ibranch_priv(ctx
, tmp
);
3488 #ifdef CONFIG_USER_ONLY
3489 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3491 TCGv_i64 new_spc
= tcg_temp_new_i64();
3493 load_spr(ctx
, new_spc
, a
->sp
);
3495 copy_iaoq_entry(cpu_gr
[31], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3496 tcg_gen_mov_i64(cpu_sr
[0], cpu_iasq_f
);
3498 if (a
->n
&& use_nullify_skip(ctx
)) {
3499 tcg_gen_mov_reg(cpu_iaoq_f
, tmp
);
3500 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
3501 tcg_gen_mov_i64(cpu_iasq_f
, new_spc
);
3502 tcg_gen_mov_i64(cpu_iasq_b
, cpu_iasq_f
);
3504 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3505 if (ctx
->iaoq_b
== -1) {
3506 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3508 tcg_gen_mov_reg(cpu_iaoq_b
, tmp
);
3509 tcg_gen_mov_i64(cpu_iasq_b
, new_spc
);
3510 nullify_set(ctx
, a
->n
);
3512 tcg_temp_free_i64(new_spc
);
3513 tcg_gen_lookup_and_goto_ptr();
3514 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3515 return nullify_end(ctx
);
3519 static bool trans_bl(DisasContext
*ctx
, arg_bl
*a
)
3521 return do_dbranch(ctx
, iaoq_dest(ctx
, a
->disp
), a
->l
, a
->n
);
3524 static bool trans_b_gate(DisasContext
*ctx
, arg_b_gate
*a
)
3526 target_ureg dest
= iaoq_dest(ctx
, a
->disp
);
3530 /* Make sure the caller hasn't done something weird with the queue.
3531 * ??? This is not quite the same as the PSW[B] bit, which would be
3532 * expensive to track. Real hardware will trap for
3534 * b gateway+4 (in delay slot of first branch)
3535 * However, checking for a non-sequential instruction queue *will*
3536 * diagnose the security hole
3539 * in which instructions at evil would run with increased privs.
3541 if (ctx
->iaoq_b
== -1 || ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
3542 return gen_illegal(ctx
);
3545 #ifndef CONFIG_USER_ONLY
3546 if (ctx
->tb_flags
& PSW_C
) {
3547 CPUHPPAState
*env
= ctx
->cs
->env_ptr
;
3548 int type
= hppa_artype_for_page(env
, ctx
->base
.pc_next
);
3549 /* If we could not find a TLB entry, then we need to generate an
3550 ITLB miss exception so the kernel will provide it.
3551 The resulting TLB fill operation will invalidate this TB and
3552 we will re-translate, at which point we *will* be able to find
3553 the TLB entry and determine if this is in fact a gateway page. */
3555 gen_excp(ctx
, EXCP_ITLB_MISS
);
3558 /* No change for non-gateway pages or for priv decrease. */
3559 if (type
>= 4 && type
- 4 < ctx
->privilege
) {
3560 dest
= deposit32(dest
, 0, 2, type
- 4);
3563 dest
&= -4; /* priv = 0 */
3568 TCGv_reg tmp
= dest_gpr(ctx
, a
->l
);
3569 if (ctx
->privilege
< 3) {
3570 tcg_gen_andi_reg(tmp
, tmp
, -4);
3572 tcg_gen_ori_reg(tmp
, tmp
, ctx
->privilege
);
3573 save_gpr(ctx
, a
->l
, tmp
);
3576 return do_dbranch(ctx
, dest
, 0, a
->n
);
3579 static bool trans_blr(DisasContext
*ctx
, arg_blr
*a
)
3582 TCGv_reg tmp
= get_temp(ctx
);
3583 tcg_gen_shli_reg(tmp
, load_gpr(ctx
, a
->x
), 3);
3584 tcg_gen_addi_reg(tmp
, tmp
, ctx
->iaoq_f
+ 8);
3585 /* The computation here never changes privilege level. */
3586 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3588 /* BLR R0,RX is a good way to load PC+8 into RX. */
3589 return do_dbranch(ctx
, ctx
->iaoq_f
+ 8, a
->l
, a
->n
);
3593 static bool trans_bv(DisasContext
*ctx
, arg_bv
*a
)
3598 dest
= load_gpr(ctx
, a
->b
);
3600 dest
= get_temp(ctx
);
3601 tcg_gen_shli_reg(dest
, load_gpr(ctx
, a
->x
), 3);
3602 tcg_gen_add_reg(dest
, dest
, load_gpr(ctx
, a
->b
));
3604 dest
= do_ibranch_priv(ctx
, dest
);
3605 return do_ibranch(ctx
, dest
, 0, a
->n
);
3608 static bool trans_bve(DisasContext
*ctx
, arg_bve
*a
)
3612 #ifdef CONFIG_USER_ONLY
3613 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3614 return do_ibranch(ctx
, dest
, a
->l
, a
->n
);
3617 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3619 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3620 if (ctx
->iaoq_b
== -1) {
3621 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3623 copy_iaoq_entry(cpu_iaoq_b
, -1, dest
);
3624 tcg_gen_mov_i64(cpu_iasq_b
, space_select(ctx
, 0, dest
));
3626 copy_iaoq_entry(cpu_gr
[a
->l
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3628 nullify_set(ctx
, a
->n
);
3629 tcg_gen_lookup_and_goto_ptr();
3630 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3631 return nullify_end(ctx
);
3639 static void gen_fcpy_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3641 tcg_gen_mov_i32(dst
, src
);
3644 static bool trans_fcpy_f(DisasContext
*ctx
, arg_fclass01
*a
)
3646 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fcpy_f
);
3649 static void gen_fcpy_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3651 tcg_gen_mov_i64(dst
, src
);
3654 static bool trans_fcpy_d(DisasContext
*ctx
, arg_fclass01
*a
)
3656 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fcpy_d
);
3659 static void gen_fabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3661 tcg_gen_andi_i32(dst
, src
, INT32_MAX
);
3664 static bool trans_fabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3666 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fabs_f
);
3669 static void gen_fabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3671 tcg_gen_andi_i64(dst
, src
, INT64_MAX
);
3674 static bool trans_fabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3676 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fabs_d
);
3679 static bool trans_fsqrt_f(DisasContext
*ctx
, arg_fclass01
*a
)
3681 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_s
);
3684 static bool trans_fsqrt_d(DisasContext
*ctx
, arg_fclass01
*a
)
3686 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_d
);
3689 static bool trans_frnd_f(DisasContext
*ctx
, arg_fclass01
*a
)
3691 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_frnd_s
);
3694 static bool trans_frnd_d(DisasContext
*ctx
, arg_fclass01
*a
)
3696 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_frnd_d
);
3699 static void gen_fneg_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3701 tcg_gen_xori_i32(dst
, src
, INT32_MIN
);
3704 static bool trans_fneg_f(DisasContext
*ctx
, arg_fclass01
*a
)
3706 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fneg_f
);
3709 static void gen_fneg_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3711 tcg_gen_xori_i64(dst
, src
, INT64_MIN
);
3714 static bool trans_fneg_d(DisasContext
*ctx
, arg_fclass01
*a
)
3716 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fneg_d
);
3719 static void gen_fnegabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3721 tcg_gen_ori_i32(dst
, src
, INT32_MIN
);
3724 static bool trans_fnegabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3726 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fnegabs_f
);
3729 static void gen_fnegabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3731 tcg_gen_ori_i64(dst
, src
, INT64_MIN
);
3734 static bool trans_fnegabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3736 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fnegabs_d
);
3743 static bool trans_fcnv_d_f(DisasContext
*ctx
, arg_fclass01
*a
)
3745 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_s
);
3748 static bool trans_fcnv_f_d(DisasContext
*ctx
, arg_fclass01
*a
)
3750 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_d
);
3753 static bool trans_fcnv_w_f(DisasContext
*ctx
, arg_fclass01
*a
)
3755 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_s
);
3758 static bool trans_fcnv_q_f(DisasContext
*ctx
, arg_fclass01
*a
)
3760 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_s
);
3763 static bool trans_fcnv_w_d(DisasContext
*ctx
, arg_fclass01
*a
)
3765 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_d
);
3768 static bool trans_fcnv_q_d(DisasContext
*ctx
, arg_fclass01
*a
)
3770 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_d
);
3773 static bool trans_fcnv_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3775 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_w
);
3778 static bool trans_fcnv_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3780 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_w
);
3783 static bool trans_fcnv_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3785 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_dw
);
3788 static bool trans_fcnv_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3790 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_dw
);
3793 static bool trans_fcnv_t_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3795 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_w
);
3798 static bool trans_fcnv_t_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3800 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_w
);
3803 static bool trans_fcnv_t_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3805 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_dw
);
3808 static bool trans_fcnv_t_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3810 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_dw
);
3813 static bool trans_fcnv_uw_f(DisasContext
*ctx
, arg_fclass01
*a
)
3815 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_s
);
3818 static bool trans_fcnv_uq_f(DisasContext
*ctx
, arg_fclass01
*a
)
3820 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_s
);
3823 static bool trans_fcnv_uw_d(DisasContext
*ctx
, arg_fclass01
*a
)
3825 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_d
);
3828 static bool trans_fcnv_uq_d(DisasContext
*ctx
, arg_fclass01
*a
)
3830 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_d
);
3833 static bool trans_fcnv_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3835 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_uw
);
3838 static bool trans_fcnv_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3840 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_uw
);
3843 static bool trans_fcnv_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3845 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_udw
);
3848 static bool trans_fcnv_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3850 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_udw
);
3853 static bool trans_fcnv_t_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3855 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_uw
);
3858 static bool trans_fcnv_t_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3860 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_uw
);
3863 static bool trans_fcnv_t_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3865 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_udw
);
3868 static bool trans_fcnv_t_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3870 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_udw
);
3877 static bool trans_fcmp_f(DisasContext
*ctx
, arg_fclass2
*a
)
3879 TCGv_i32 ta
, tb
, tc
, ty
;
3883 ta
= load_frw0_i32(a
->r1
);
3884 tb
= load_frw0_i32(a
->r2
);
3885 ty
= tcg_const_i32(a
->y
);
3886 tc
= tcg_const_i32(a
->c
);
3888 gen_helper_fcmp_s(cpu_env
, ta
, tb
, ty
, tc
);
3890 tcg_temp_free_i32(ta
);
3891 tcg_temp_free_i32(tb
);
3892 tcg_temp_free_i32(ty
);
3893 tcg_temp_free_i32(tc
);
3895 return nullify_end(ctx
);
3898 static bool trans_fcmp_d(DisasContext
*ctx
, arg_fclass2
*a
)
3905 ta
= load_frd0(a
->r1
);
3906 tb
= load_frd0(a
->r2
);
3907 ty
= tcg_const_i32(a
->y
);
3908 tc
= tcg_const_i32(a
->c
);
3910 gen_helper_fcmp_d(cpu_env
, ta
, tb
, ty
, tc
);
3912 tcg_temp_free_i64(ta
);
3913 tcg_temp_free_i64(tb
);
3914 tcg_temp_free_i32(ty
);
3915 tcg_temp_free_i32(tc
);
3917 return nullify_end(ctx
);
3920 static bool trans_ftest(DisasContext
*ctx
, arg_ftest
*a
)
3927 tcg_gen_ld32u_reg(t
, cpu_env
, offsetof(CPUHPPAState
, fr0_shadow
));
3934 case 0: /* simple */
3935 tcg_gen_andi_reg(t
, t
, 0x4000000);
3936 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3964 TCGv_reg c
= load_const(ctx
, mask
);
3965 tcg_gen_or_reg(t
, t
, c
);
3966 ctx
->null_cond
= cond_make(TCG_COND_EQ
, t
, c
);
3968 tcg_gen_andi_reg(t
, t
, mask
);
3969 ctx
->null_cond
= cond_make_0(TCG_COND_EQ
, t
);
3972 unsigned cbit
= (a
->y
^ 1) - 1;
3974 tcg_gen_extract_reg(t
, t
, 21 - cbit
, 1);
3975 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3980 return nullify_end(ctx
);
3987 static bool trans_fadd_f(DisasContext
*ctx
, arg_fclass3
*a
)
3989 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_s
);
3992 static bool trans_fadd_d(DisasContext
*ctx
, arg_fclass3
*a
)
3994 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_d
);
3997 static bool trans_fsub_f(DisasContext
*ctx
, arg_fclass3
*a
)
3999 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_s
);
4002 static bool trans_fsub_d(DisasContext
*ctx
, arg_fclass3
*a
)
4004 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_d
);
4007 static bool trans_fmpy_f(DisasContext
*ctx
, arg_fclass3
*a
)
4009 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_s
);
4012 static bool trans_fmpy_d(DisasContext
*ctx
, arg_fclass3
*a
)
4014 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_d
);
4017 static bool trans_fdiv_f(DisasContext
*ctx
, arg_fclass3
*a
)
4019 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_s
);
4022 static bool trans_fdiv_d(DisasContext
*ctx
, arg_fclass3
*a
)
4024 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_d
);
4027 static bool trans_xmpyu(DisasContext
*ctx
, arg_xmpyu
*a
)
4033 x
= load_frw0_i64(a
->r1
);
4034 y
= load_frw0_i64(a
->r2
);
4035 tcg_gen_mul_i64(x
, x
, y
);
4037 tcg_temp_free_i64(x
);
4038 tcg_temp_free_i64(y
);
4040 return nullify_end(ctx
);
4043 /* Convert the fmpyadd single-precision register encodings to standard. */
4044 static inline int fmpyadd_s_reg(unsigned r
)
4046 return (r
& 16) * 2 + 16 + (r
& 15);
4049 static bool do_fmpyadd_s(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4051 int tm
= fmpyadd_s_reg(a
->tm
);
4052 int ra
= fmpyadd_s_reg(a
->ra
);
4053 int ta
= fmpyadd_s_reg(a
->ta
);
4054 int rm2
= fmpyadd_s_reg(a
->rm2
);
4055 int rm1
= fmpyadd_s_reg(a
->rm1
);
4059 do_fop_weww(ctx
, tm
, rm1
, rm2
, gen_helper_fmpy_s
);
4060 do_fop_weww(ctx
, ta
, ta
, ra
,
4061 is_sub
? gen_helper_fsub_s
: gen_helper_fadd_s
);
4063 return nullify_end(ctx
);
4066 static bool trans_fmpyadd_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4068 return do_fmpyadd_s(ctx
, a
, false);
4071 static bool trans_fmpysub_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4073 return do_fmpyadd_s(ctx
, a
, true);
4076 static bool do_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4080 do_fop_dedd(ctx
, a
->tm
, a
->rm1
, a
->rm2
, gen_helper_fmpy_d
);
4081 do_fop_dedd(ctx
, a
->ta
, a
->ta
, a
->ra
,
4082 is_sub
? gen_helper_fsub_d
: gen_helper_fadd_d
);
4084 return nullify_end(ctx
);
4087 static bool trans_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4089 return do_fmpyadd_d(ctx
, a
, false);
4092 static bool trans_fmpysub_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4094 return do_fmpyadd_d(ctx
, a
, true);
4097 static bool trans_fmpyfadd_f(DisasContext
*ctx
, arg_fmpyfadd_f
*a
)
4102 x
= load_frw0_i32(a
->rm1
);
4103 y
= load_frw0_i32(a
->rm2
);
4104 z
= load_frw0_i32(a
->ra3
);
4107 gen_helper_fmpynfadd_s(x
, cpu_env
, x
, y
, z
);
4109 gen_helper_fmpyfadd_s(x
, cpu_env
, x
, y
, z
);
4112 tcg_temp_free_i32(y
);
4113 tcg_temp_free_i32(z
);
4114 save_frw_i32(a
->t
, x
);
4115 tcg_temp_free_i32(x
);
4116 return nullify_end(ctx
);
4119 static bool trans_fmpyfadd_d(DisasContext
*ctx
, arg_fmpyfadd_d
*a
)
4124 x
= load_frd0(a
->rm1
);
4125 y
= load_frd0(a
->rm2
);
4126 z
= load_frd0(a
->ra3
);
4129 gen_helper_fmpynfadd_d(x
, cpu_env
, x
, y
, z
);
4131 gen_helper_fmpyfadd_d(x
, cpu_env
, x
, y
, z
);
4134 tcg_temp_free_i64(y
);
4135 tcg_temp_free_i64(z
);
4137 tcg_temp_free_i64(x
);
4138 return nullify_end(ctx
);
4141 static bool trans_diag(DisasContext
*ctx
, arg_diag
*a
)
4143 qemu_log_mask(LOG_UNIMP
, "DIAG opcode ignored\n");
4144 cond_free(&ctx
->null_cond
);
4148 static void hppa_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
4150 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4154 ctx
->tb_flags
= ctx
->base
.tb
->flags
;
4156 #ifdef CONFIG_USER_ONLY
4157 ctx
->privilege
= MMU_USER_IDX
;
4158 ctx
->mmu_idx
= MMU_USER_IDX
;
4159 ctx
->iaoq_f
= ctx
->base
.pc_first
| MMU_USER_IDX
;
4160 ctx
->iaoq_b
= ctx
->base
.tb
->cs_base
| MMU_USER_IDX
;
4162 ctx
->privilege
= (ctx
->tb_flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
4163 ctx
->mmu_idx
= (ctx
->tb_flags
& PSW_D
? ctx
->privilege
: MMU_PHYS_IDX
);
4165 /* Recover the IAOQ values from the GVA + PRIV. */
4166 uint64_t cs_base
= ctx
->base
.tb
->cs_base
;
4167 uint64_t iasq_f
= cs_base
& ~0xffffffffull
;
4168 int32_t diff
= cs_base
;
4170 ctx
->iaoq_f
= (ctx
->base
.pc_first
& ~iasq_f
) + ctx
->privilege
;
4171 ctx
->iaoq_b
= (diff
? ctx
->iaoq_f
+ diff
: -1);
4174 ctx
->iaoq_n_var
= NULL
;
4176 /* Bound the number of instructions by those left on the page. */
4177 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
4178 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
4182 memset(ctx
->tempr
, 0, sizeof(ctx
->tempr
));
4183 memset(ctx
->templ
, 0, sizeof(ctx
->templ
));
4186 static void hppa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4188 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4190 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */
4191 ctx
->null_cond
= cond_make_f();
4192 ctx
->psw_n_nonzero
= false;
4193 if (ctx
->tb_flags
& PSW_N
) {
4194 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
4195 ctx
->psw_n_nonzero
= true;
4197 ctx
->null_lab
= NULL
;
4200 static void hppa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4202 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4204 tcg_gen_insn_start(ctx
->iaoq_f
, ctx
->iaoq_b
);
4207 static bool hppa_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
4208 const CPUBreakpoint
*bp
)
4210 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4212 gen_excp(ctx
, EXCP_DEBUG
);
4213 ctx
->base
.pc_next
+= 4;
4217 static void hppa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
4219 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4220 CPUHPPAState
*env
= cs
->env_ptr
;
4224 /* Execute one insn. */
4225 #ifdef CONFIG_USER_ONLY
4226 if (ctx
->base
.pc_next
< TARGET_PAGE_SIZE
) {
4228 ret
= ctx
->base
.is_jmp
;
4229 assert(ret
!= DISAS_NEXT
);
4233 /* Always fetch the insn, even if nullified, so that we check
4234 the page permissions for execute. */
4235 uint32_t insn
= translator_ldl(env
, ctx
->base
.pc_next
);
4237 /* Set up the IA queue for the next insn.
4238 This will be overwritten by a branch. */
4239 if (ctx
->iaoq_b
== -1) {
4241 ctx
->iaoq_n_var
= get_temp(ctx
);
4242 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
4244 ctx
->iaoq_n
= ctx
->iaoq_b
+ 4;
4245 ctx
->iaoq_n_var
= NULL
;
4248 if (unlikely(ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4249 ctx
->null_cond
.c
= TCG_COND_NEVER
;
4253 if (!decode(ctx
, insn
)) {
4256 ret
= ctx
->base
.is_jmp
;
4257 assert(ctx
->null_lab
== NULL
);
4261 /* Free any temporaries allocated. */
4262 for (i
= 0, n
= ctx
->ntempr
; i
< n
; ++i
) {
4263 tcg_temp_free(ctx
->tempr
[i
]);
4264 ctx
->tempr
[i
] = NULL
;
4266 for (i
= 0, n
= ctx
->ntempl
; i
< n
; ++i
) {
4267 tcg_temp_free_tl(ctx
->templ
[i
]);
4268 ctx
->templ
[i
] = NULL
;
4273 /* Advance the insn queue. Note that this check also detects
4274 a priority change within the instruction queue. */
4275 if (ret
== DISAS_NEXT
&& ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
4276 if (ctx
->iaoq_b
!= -1 && ctx
->iaoq_n
!= -1
4277 && use_goto_tb(ctx
, ctx
->iaoq_b
)
4278 && (ctx
->null_cond
.c
== TCG_COND_NEVER
4279 || ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4280 nullify_set(ctx
, ctx
->null_cond
.c
== TCG_COND_ALWAYS
);
4281 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
4282 ctx
->base
.is_jmp
= ret
= DISAS_NORETURN
;
4284 ctx
->base
.is_jmp
= ret
= DISAS_IAQ_N_STALE
;
4287 ctx
->iaoq_f
= ctx
->iaoq_b
;
4288 ctx
->iaoq_b
= ctx
->iaoq_n
;
4289 ctx
->base
.pc_next
+= 4;
4292 case DISAS_NORETURN
:
4293 case DISAS_IAQ_N_UPDATED
:
4297 case DISAS_IAQ_N_STALE
:
4298 case DISAS_IAQ_N_STALE_EXIT
:
4299 if (ctx
->iaoq_f
== -1) {
4300 tcg_gen_mov_reg(cpu_iaoq_f
, cpu_iaoq_b
);
4301 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
4302 #ifndef CONFIG_USER_ONLY
4303 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
4306 ctx
->base
.is_jmp
= (ret
== DISAS_IAQ_N_STALE_EXIT
4308 : DISAS_IAQ_N_UPDATED
);
4309 } else if (ctx
->iaoq_b
== -1) {
4310 tcg_gen_mov_reg(cpu_iaoq_b
, ctx
->iaoq_n_var
);
4315 g_assert_not_reached();
4319 static void hppa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
4321 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4322 DisasJumpType is_jmp
= ctx
->base
.is_jmp
;
4325 case DISAS_NORETURN
:
4327 case DISAS_TOO_MANY
:
4328 case DISAS_IAQ_N_STALE
:
4329 case DISAS_IAQ_N_STALE_EXIT
:
4330 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
4331 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
4334 case DISAS_IAQ_N_UPDATED
:
4335 if (ctx
->base
.singlestep_enabled
) {
4336 gen_excp_1(EXCP_DEBUG
);
4337 } else if (is_jmp
!= DISAS_IAQ_N_STALE_EXIT
) {
4338 tcg_gen_lookup_and_goto_ptr();
4342 tcg_gen_exit_tb(NULL
, 0);
4345 g_assert_not_reached();
4349 static void hppa_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
4351 target_ulong pc
= dcbase
->pc_first
;
4353 #ifdef CONFIG_USER_ONLY
4356 qemu_log("IN:\n0x00000000: (null)\n");
4359 qemu_log("IN:\n0x000000b0: light-weight-syscall\n");
4362 qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n");
4365 qemu_log("IN:\n0x00000100: syscall\n");
4370 qemu_log("IN: %s\n", lookup_symbol(pc
));
4371 log_target_disas(cs
, pc
, dcbase
->tb
->size
);
4374 static const TranslatorOps hppa_tr_ops
= {
4375 .init_disas_context
= hppa_tr_init_disas_context
,
4376 .tb_start
= hppa_tr_tb_start
,
4377 .insn_start
= hppa_tr_insn_start
,
4378 .breakpoint_check
= hppa_tr_breakpoint_check
,
4379 .translate_insn
= hppa_tr_translate_insn
,
4380 .tb_stop
= hppa_tr_tb_stop
,
4381 .disas_log
= hppa_tr_disas_log
,
4384 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
4387 translator_loop(&hppa_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
4390 void restore_state_to_opc(CPUHPPAState
*env
, TranslationBlock
*tb
,
4393 env
->iaoq_f
= data
[0];
4394 if (data
[1] != (target_ureg
)-1) {
4395 env
->iaoq_b
= data
[1];
4397 /* Since we were executing the instruction at IAOQ_F, and took some
4398 sort of action that provoked the cpu_restore_state, we can infer
4399 that the instruction was not nullified. */