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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170124' into staging
[mirror_qemu.git] / target / i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39 #include "hw/i386/intel_iommu.h"
40 #include "hw/i386/x86-iommu.h"
41
42 #include "exec/ioport.h"
43 #include "standard-headers/asm-x86/hyperv.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "migration/migration.h"
47 #include "exec/memattrs.h"
48 #include "trace.h"
49
50 //#define DEBUG_KVM
51
52 #ifdef DEBUG_KVM
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #else
56 #define DPRINTF(fmt, ...) \
57 do { } while (0)
58 #endif
59
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
62
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
66
67 #ifndef BUS_MCEERR_AR
68 #define BUS_MCEERR_AR 4
69 #endif
70 #ifndef BUS_MCEERR_AO
71 #define BUS_MCEERR_AO 5
72 #endif
73
74 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
75 KVM_CAP_INFO(SET_TSS_ADDR),
76 KVM_CAP_INFO(EXT_CPUID),
77 KVM_CAP_INFO(MP_STATE),
78 KVM_CAP_LAST_INFO
79 };
80
81 static bool has_msr_star;
82 static bool has_msr_hsave_pa;
83 static bool has_msr_tsc_aux;
84 static bool has_msr_tsc_adjust;
85 static bool has_msr_tsc_deadline;
86 static bool has_msr_feature_control;
87 static bool has_msr_misc_enable;
88 static bool has_msr_smbase;
89 static bool has_msr_bndcfgs;
90 static int lm_capable_kernel;
91 static bool has_msr_hv_hypercall;
92 static bool has_msr_hv_crash;
93 static bool has_msr_hv_reset;
94 static bool has_msr_hv_vpindex;
95 static bool has_msr_hv_runtime;
96 static bool has_msr_hv_synic;
97 static bool has_msr_hv_stimer;
98 static bool has_msr_xss;
99
100 static bool has_msr_architectural_pmu;
101 static uint32_t num_architectural_pmu_counters;
102
103 static int has_xsave;
104 static int has_xcrs;
105 static int has_pit_state2;
106
107 static bool has_msr_mcg_ext_ctl;
108
109 static struct kvm_cpuid2 *cpuid_cache;
110
111 int kvm_has_pit_state2(void)
112 {
113 return has_pit_state2;
114 }
115
116 bool kvm_has_smm(void)
117 {
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119 }
120
121 bool kvm_has_adjust_clock_stable(void)
122 {
123 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
124
125 return (ret == KVM_CLOCK_TSC_STABLE);
126 }
127
128 bool kvm_allows_irq0_override(void)
129 {
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131 }
132
133 static bool kvm_x2apic_api_set_flags(uint64_t flags)
134 {
135 KVMState *s = KVM_STATE(current_machine->accelerator);
136
137 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
138 }
139
140 #define MEMORIZE(fn, _result) \
141 ({ \
142 static bool _memorized; \
143 \
144 if (_memorized) { \
145 return _result; \
146 } \
147 _memorized = true; \
148 _result = fn; \
149 })
150
151 static bool has_x2apic_api;
152
153 bool kvm_has_x2apic_api(void)
154 {
155 return has_x2apic_api;
156 }
157
158 bool kvm_enable_x2apic(void)
159 {
160 return MEMORIZE(
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
163 has_x2apic_api);
164 }
165
166 static int kvm_get_tsc(CPUState *cs)
167 {
168 X86CPU *cpu = X86_CPU(cs);
169 CPUX86State *env = &cpu->env;
170 struct {
171 struct kvm_msrs info;
172 struct kvm_msr_entry entries[1];
173 } msr_data;
174 int ret;
175
176 if (env->tsc_valid) {
177 return 0;
178 }
179
180 msr_data.info.nmsrs = 1;
181 msr_data.entries[0].index = MSR_IA32_TSC;
182 env->tsc_valid = !runstate_is_running();
183
184 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
185 if (ret < 0) {
186 return ret;
187 }
188
189 assert(ret == 1);
190 env->tsc = msr_data.entries[0].data;
191 return 0;
192 }
193
194 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
195 {
196 kvm_get_tsc(cpu);
197 }
198
199 void kvm_synchronize_all_tsc(void)
200 {
201 CPUState *cpu;
202
203 if (kvm_enabled()) {
204 CPU_FOREACH(cpu) {
205 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
206 }
207 }
208 }
209
210 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
211 {
212 struct kvm_cpuid2 *cpuid;
213 int r, size;
214
215 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
216 cpuid = g_malloc0(size);
217 cpuid->nent = max;
218 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
219 if (r == 0 && cpuid->nent >= max) {
220 r = -E2BIG;
221 }
222 if (r < 0) {
223 if (r == -E2BIG) {
224 g_free(cpuid);
225 return NULL;
226 } else {
227 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
228 strerror(-r));
229 exit(1);
230 }
231 }
232 return cpuid;
233 }
234
235 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
236 * for all entries.
237 */
238 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
239 {
240 struct kvm_cpuid2 *cpuid;
241 int max = 1;
242
243 if (cpuid_cache != NULL) {
244 return cpuid_cache;
245 }
246 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
247 max *= 2;
248 }
249 cpuid_cache = cpuid;
250 return cpuid;
251 }
252
253 static const struct kvm_para_features {
254 int cap;
255 int feature;
256 } para_features[] = {
257 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
258 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
259 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
260 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
261 };
262
263 static int get_para_features(KVMState *s)
264 {
265 int i, features = 0;
266
267 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
268 if (kvm_check_extension(s, para_features[i].cap)) {
269 features |= (1 << para_features[i].feature);
270 }
271 }
272
273 return features;
274 }
275
276
277 /* Returns the value for a specific register on the cpuid entry
278 */
279 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
280 {
281 uint32_t ret = 0;
282 switch (reg) {
283 case R_EAX:
284 ret = entry->eax;
285 break;
286 case R_EBX:
287 ret = entry->ebx;
288 break;
289 case R_ECX:
290 ret = entry->ecx;
291 break;
292 case R_EDX:
293 ret = entry->edx;
294 break;
295 }
296 return ret;
297 }
298
299 /* Find matching entry for function/index on kvm_cpuid2 struct
300 */
301 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
302 uint32_t function,
303 uint32_t index)
304 {
305 int i;
306 for (i = 0; i < cpuid->nent; ++i) {
307 if (cpuid->entries[i].function == function &&
308 cpuid->entries[i].index == index) {
309 return &cpuid->entries[i];
310 }
311 }
312 /* not found: */
313 return NULL;
314 }
315
316 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
317 uint32_t index, int reg)
318 {
319 struct kvm_cpuid2 *cpuid;
320 uint32_t ret = 0;
321 uint32_t cpuid_1_edx;
322 bool found = false;
323
324 cpuid = get_supported_cpuid(s);
325
326 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
327 if (entry) {
328 found = true;
329 ret = cpuid_entry_get_reg(entry, reg);
330 }
331
332 /* Fixups for the data returned by KVM, below */
333
334 if (function == 1 && reg == R_EDX) {
335 /* KVM before 2.6.30 misreports the following features */
336 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
337 } else if (function == 1 && reg == R_ECX) {
338 /* We can set the hypervisor flag, even if KVM does not return it on
339 * GET_SUPPORTED_CPUID
340 */
341 ret |= CPUID_EXT_HYPERVISOR;
342 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
343 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
344 * and the irqchip is in the kernel.
345 */
346 if (kvm_irqchip_in_kernel() &&
347 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
348 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
349 }
350
351 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
352 * without the in-kernel irqchip
353 */
354 if (!kvm_irqchip_in_kernel()) {
355 ret &= ~CPUID_EXT_X2APIC;
356 }
357 } else if (function == 6 && reg == R_EAX) {
358 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
359 } else if (function == 0x80000001 && reg == R_EDX) {
360 /* On Intel, kvm returns cpuid according to the Intel spec,
361 * so add missing bits according to the AMD spec:
362 */
363 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
364 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
365 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
366 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
367 * be enabled without the in-kernel irqchip
368 */
369 if (!kvm_irqchip_in_kernel()) {
370 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
371 }
372 }
373
374 /* fallback for older kernels */
375 if ((function == KVM_CPUID_FEATURES) && !found) {
376 ret = get_para_features(s);
377 }
378
379 return ret;
380 }
381
382 typedef struct HWPoisonPage {
383 ram_addr_t ram_addr;
384 QLIST_ENTRY(HWPoisonPage) list;
385 } HWPoisonPage;
386
387 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
388 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
389
390 static void kvm_unpoison_all(void *param)
391 {
392 HWPoisonPage *page, *next_page;
393
394 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
395 QLIST_REMOVE(page, list);
396 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
397 g_free(page);
398 }
399 }
400
401 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
402 {
403 HWPoisonPage *page;
404
405 QLIST_FOREACH(page, &hwpoison_page_list, list) {
406 if (page->ram_addr == ram_addr) {
407 return;
408 }
409 }
410 page = g_new(HWPoisonPage, 1);
411 page->ram_addr = ram_addr;
412 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
413 }
414
415 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
416 int *max_banks)
417 {
418 int r;
419
420 r = kvm_check_extension(s, KVM_CAP_MCE);
421 if (r > 0) {
422 *max_banks = r;
423 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
424 }
425 return -ENOSYS;
426 }
427
428 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
429 {
430 CPUState *cs = CPU(cpu);
431 CPUX86State *env = &cpu->env;
432 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
433 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
434 uint64_t mcg_status = MCG_STATUS_MCIP;
435 int flags = 0;
436
437 if (code == BUS_MCEERR_AR) {
438 status |= MCI_STATUS_AR | 0x134;
439 mcg_status |= MCG_STATUS_EIPV;
440 } else {
441 status |= 0xc0;
442 mcg_status |= MCG_STATUS_RIPV;
443 }
444
445 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
446 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
447 * guest kernel back into env->mcg_ext_ctl.
448 */
449 cpu_synchronize_state(cs);
450 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
451 mcg_status |= MCG_STATUS_LMCE;
452 flags = 0;
453 }
454
455 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
456 (MCM_ADDR_PHYS << 6) | 0xc, flags);
457 }
458
459 static void hardware_memory_error(void)
460 {
461 fprintf(stderr, "Hardware memory error!\n");
462 exit(1);
463 }
464
465 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
466 {
467 X86CPU *cpu = X86_CPU(c);
468 CPUX86State *env = &cpu->env;
469 ram_addr_t ram_addr;
470 hwaddr paddr;
471
472 if ((env->mcg_cap & MCG_SER_P) && addr
473 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
474 ram_addr = qemu_ram_addr_from_host(addr);
475 if (ram_addr == RAM_ADDR_INVALID ||
476 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
477 fprintf(stderr, "Hardware memory error for memory used by "
478 "QEMU itself instead of guest system!\n");
479 /* Hope we are lucky for AO MCE */
480 if (code == BUS_MCEERR_AO) {
481 return 0;
482 } else {
483 hardware_memory_error();
484 }
485 }
486 kvm_hwpoison_page_add(ram_addr);
487 kvm_mce_inject(cpu, paddr, code);
488 } else {
489 if (code == BUS_MCEERR_AO) {
490 return 0;
491 } else if (code == BUS_MCEERR_AR) {
492 hardware_memory_error();
493 } else {
494 return 1;
495 }
496 }
497 return 0;
498 }
499
500 int kvm_arch_on_sigbus(int code, void *addr)
501 {
502 X86CPU *cpu = X86_CPU(first_cpu);
503
504 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
505 ram_addr_t ram_addr;
506 hwaddr paddr;
507
508 /* Hope we are lucky for AO MCE */
509 ram_addr = qemu_ram_addr_from_host(addr);
510 if (ram_addr == RAM_ADDR_INVALID ||
511 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
512 addr, &paddr)) {
513 fprintf(stderr, "Hardware memory error for memory used by "
514 "QEMU itself instead of guest system!: %p\n", addr);
515 return 0;
516 }
517 kvm_hwpoison_page_add(ram_addr);
518 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
519 } else {
520 if (code == BUS_MCEERR_AO) {
521 return 0;
522 } else if (code == BUS_MCEERR_AR) {
523 hardware_memory_error();
524 } else {
525 return 1;
526 }
527 }
528 return 0;
529 }
530
531 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
532 {
533 CPUX86State *env = &cpu->env;
534
535 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
536 unsigned int bank, bank_num = env->mcg_cap & 0xff;
537 struct kvm_x86_mce mce;
538
539 env->exception_injected = -1;
540
541 /*
542 * There must be at least one bank in use if an MCE is pending.
543 * Find it and use its values for the event injection.
544 */
545 for (bank = 0; bank < bank_num; bank++) {
546 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
547 break;
548 }
549 }
550 assert(bank < bank_num);
551
552 mce.bank = bank;
553 mce.status = env->mce_banks[bank * 4 + 1];
554 mce.mcg_status = env->mcg_status;
555 mce.addr = env->mce_banks[bank * 4 + 2];
556 mce.misc = env->mce_banks[bank * 4 + 3];
557
558 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
559 }
560 return 0;
561 }
562
563 static void cpu_update_state(void *opaque, int running, RunState state)
564 {
565 CPUX86State *env = opaque;
566
567 if (running) {
568 env->tsc_valid = false;
569 }
570 }
571
572 unsigned long kvm_arch_vcpu_id(CPUState *cs)
573 {
574 X86CPU *cpu = X86_CPU(cs);
575 return cpu->apic_id;
576 }
577
578 #ifndef KVM_CPUID_SIGNATURE_NEXT
579 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
580 #endif
581
582 static bool hyperv_hypercall_available(X86CPU *cpu)
583 {
584 return cpu->hyperv_vapic ||
585 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
586 }
587
588 static bool hyperv_enabled(X86CPU *cpu)
589 {
590 CPUState *cs = CPU(cpu);
591 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
592 (hyperv_hypercall_available(cpu) ||
593 cpu->hyperv_time ||
594 cpu->hyperv_relaxed_timing ||
595 cpu->hyperv_crash ||
596 cpu->hyperv_reset ||
597 cpu->hyperv_vpindex ||
598 cpu->hyperv_runtime ||
599 cpu->hyperv_synic ||
600 cpu->hyperv_stimer);
601 }
602
603 static int kvm_arch_set_tsc_khz(CPUState *cs)
604 {
605 X86CPU *cpu = X86_CPU(cs);
606 CPUX86State *env = &cpu->env;
607 int r;
608
609 if (!env->tsc_khz) {
610 return 0;
611 }
612
613 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
614 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
615 -ENOTSUP;
616 if (r < 0) {
617 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
618 * TSC frequency doesn't match the one we want.
619 */
620 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
621 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
622 -ENOTSUP;
623 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
624 error_report("warning: TSC frequency mismatch between "
625 "VM (%" PRId64 " kHz) and host (%d kHz), "
626 "and TSC scaling unavailable",
627 env->tsc_khz, cur_freq);
628 return r;
629 }
630 }
631
632 return 0;
633 }
634
635 static int hyperv_handle_properties(CPUState *cs)
636 {
637 X86CPU *cpu = X86_CPU(cs);
638 CPUX86State *env = &cpu->env;
639
640 if (cpu->hyperv_time &&
641 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
642 cpu->hyperv_time = false;
643 }
644
645 if (cpu->hyperv_relaxed_timing) {
646 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
647 }
648 if (cpu->hyperv_vapic) {
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
650 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
651 }
652 if (cpu->hyperv_time) {
653 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
654 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
655 env->features[FEAT_HYPERV_EAX] |= 0x200;
656 }
657 if (cpu->hyperv_crash && has_msr_hv_crash) {
658 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
659 }
660 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
661 if (cpu->hyperv_reset && has_msr_hv_reset) {
662 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
663 }
664 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
665 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
666 }
667 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
668 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
669 }
670 if (cpu->hyperv_synic) {
671 int sint;
672
673 if (!has_msr_hv_synic ||
674 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
675 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
676 return -ENOSYS;
677 }
678
679 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
680 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
681 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
682 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
683 }
684 }
685 if (cpu->hyperv_stimer) {
686 if (!has_msr_hv_stimer) {
687 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
688 return -ENOSYS;
689 }
690 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
691 }
692 return 0;
693 }
694
695 static Error *invtsc_mig_blocker;
696
697 #define KVM_MAX_CPUID_ENTRIES 100
698
699 int kvm_arch_init_vcpu(CPUState *cs)
700 {
701 struct {
702 struct kvm_cpuid2 cpuid;
703 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
704 } QEMU_PACKED cpuid_data;
705 X86CPU *cpu = X86_CPU(cs);
706 CPUX86State *env = &cpu->env;
707 uint32_t limit, i, j, cpuid_i;
708 uint32_t unused;
709 struct kvm_cpuid_entry2 *c;
710 uint32_t signature[3];
711 int kvm_base = KVM_CPUID_SIGNATURE;
712 int r;
713
714 memset(&cpuid_data, 0, sizeof(cpuid_data));
715
716 cpuid_i = 0;
717
718 /* Paravirtualization CPUIDs */
719 if (hyperv_enabled(cpu)) {
720 c = &cpuid_data.entries[cpuid_i++];
721 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
722 if (!cpu->hyperv_vendor_id) {
723 memcpy(signature, "Microsoft Hv", 12);
724 } else {
725 size_t len = strlen(cpu->hyperv_vendor_id);
726
727 if (len > 12) {
728 error_report("hv-vendor-id truncated to 12 characters");
729 len = 12;
730 }
731 memset(signature, 0, 12);
732 memcpy(signature, cpu->hyperv_vendor_id, len);
733 }
734 c->eax = HYPERV_CPUID_MIN;
735 c->ebx = signature[0];
736 c->ecx = signature[1];
737 c->edx = signature[2];
738
739 c = &cpuid_data.entries[cpuid_i++];
740 c->function = HYPERV_CPUID_INTERFACE;
741 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
742 c->eax = signature[0];
743 c->ebx = 0;
744 c->ecx = 0;
745 c->edx = 0;
746
747 c = &cpuid_data.entries[cpuid_i++];
748 c->function = HYPERV_CPUID_VERSION;
749 c->eax = 0x00001bbc;
750 c->ebx = 0x00060001;
751
752 c = &cpuid_data.entries[cpuid_i++];
753 c->function = HYPERV_CPUID_FEATURES;
754 r = hyperv_handle_properties(cs);
755 if (r) {
756 return r;
757 }
758 c->eax = env->features[FEAT_HYPERV_EAX];
759 c->ebx = env->features[FEAT_HYPERV_EBX];
760 c->edx = env->features[FEAT_HYPERV_EDX];
761
762 c = &cpuid_data.entries[cpuid_i++];
763 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
764 if (cpu->hyperv_relaxed_timing) {
765 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
766 }
767 if (cpu->hyperv_vapic) {
768 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
769 }
770 c->ebx = cpu->hyperv_spinlock_attempts;
771
772 c = &cpuid_data.entries[cpuid_i++];
773 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
774 c->eax = 0x40;
775 c->ebx = 0x40;
776
777 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
778 has_msr_hv_hypercall = true;
779 }
780
781 if (cpu->expose_kvm) {
782 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
783 c = &cpuid_data.entries[cpuid_i++];
784 c->function = KVM_CPUID_SIGNATURE | kvm_base;
785 c->eax = KVM_CPUID_FEATURES | kvm_base;
786 c->ebx = signature[0];
787 c->ecx = signature[1];
788 c->edx = signature[2];
789
790 c = &cpuid_data.entries[cpuid_i++];
791 c->function = KVM_CPUID_FEATURES | kvm_base;
792 c->eax = env->features[FEAT_KVM];
793 }
794
795 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
796
797 for (i = 0; i <= limit; i++) {
798 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
799 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
800 abort();
801 }
802 c = &cpuid_data.entries[cpuid_i++];
803
804 switch (i) {
805 case 2: {
806 /* Keep reading function 2 till all the input is received */
807 int times;
808
809 c->function = i;
810 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
811 KVM_CPUID_FLAG_STATE_READ_NEXT;
812 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
813 times = c->eax & 0xff;
814
815 for (j = 1; j < times; ++j) {
816 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
817 fprintf(stderr, "cpuid_data is full, no space for "
818 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
819 abort();
820 }
821 c = &cpuid_data.entries[cpuid_i++];
822 c->function = i;
823 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
824 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
825 }
826 break;
827 }
828 case 4:
829 case 0xb:
830 case 0xd:
831 for (j = 0; ; j++) {
832 if (i == 0xd && j == 64) {
833 break;
834 }
835 c->function = i;
836 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
837 c->index = j;
838 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
839
840 if (i == 4 && c->eax == 0) {
841 break;
842 }
843 if (i == 0xb && !(c->ecx & 0xff00)) {
844 break;
845 }
846 if (i == 0xd && c->eax == 0) {
847 continue;
848 }
849 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
850 fprintf(stderr, "cpuid_data is full, no space for "
851 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
852 abort();
853 }
854 c = &cpuid_data.entries[cpuid_i++];
855 }
856 break;
857 default:
858 c->function = i;
859 c->flags = 0;
860 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
861 break;
862 }
863 }
864
865 if (limit >= 0x0a) {
866 uint32_t ver;
867
868 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
869 if ((ver & 0xff) > 0) {
870 has_msr_architectural_pmu = true;
871 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
872
873 /* Shouldn't be more than 32, since that's the number of bits
874 * available in EBX to tell us _which_ counters are available.
875 * Play it safe.
876 */
877 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
878 num_architectural_pmu_counters = MAX_GP_COUNTERS;
879 }
880 }
881 }
882
883 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
884
885 for (i = 0x80000000; i <= limit; i++) {
886 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
887 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
888 abort();
889 }
890 c = &cpuid_data.entries[cpuid_i++];
891
892 c->function = i;
893 c->flags = 0;
894 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
895 }
896
897 /* Call Centaur's CPUID instructions they are supported. */
898 if (env->cpuid_xlevel2 > 0) {
899 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
900
901 for (i = 0xC0000000; i <= limit; i++) {
902 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
903 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
904 abort();
905 }
906 c = &cpuid_data.entries[cpuid_i++];
907
908 c->function = i;
909 c->flags = 0;
910 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
911 }
912 }
913
914 cpuid_data.cpuid.nent = cpuid_i;
915
916 if (((env->cpuid_version >> 8)&0xF) >= 6
917 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
918 (CPUID_MCE | CPUID_MCA)
919 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
920 uint64_t mcg_cap, unsupported_caps;
921 int banks;
922 int ret;
923
924 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
925 if (ret < 0) {
926 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
927 return ret;
928 }
929
930 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
931 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
932 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
933 return -ENOTSUP;
934 }
935
936 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
937 if (unsupported_caps) {
938 if (unsupported_caps & MCG_LMCE_P) {
939 error_report("kvm: LMCE not supported");
940 return -ENOTSUP;
941 }
942 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
943 unsupported_caps);
944 }
945
946 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
947 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
948 if (ret < 0) {
949 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
950 return ret;
951 }
952 }
953
954 qemu_add_vm_change_state_handler(cpu_update_state, env);
955
956 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
957 if (c) {
958 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
959 !!(c->ecx & CPUID_EXT_SMX);
960 }
961
962 if (env->mcg_cap & MCG_LMCE_P) {
963 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
964 }
965
966 if (!env->user_tsc_khz) {
967 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
968 invtsc_mig_blocker == NULL) {
969 /* for migration */
970 error_setg(&invtsc_mig_blocker,
971 "State blocked by non-migratable CPU device"
972 " (invtsc flag)");
973 migrate_add_blocker(invtsc_mig_blocker);
974 /* for savevm */
975 vmstate_x86_cpu.unmigratable = 1;
976 }
977 }
978
979 cpuid_data.cpuid.padding = 0;
980 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
981 if (r) {
982 return r;
983 }
984
985 r = kvm_arch_set_tsc_khz(cs);
986 if (r < 0) {
987 return r;
988 }
989
990 /* vcpu's TSC frequency is either specified by user, or following
991 * the value used by KVM if the former is not present. In the
992 * latter case, we query it from KVM and record in env->tsc_khz,
993 * so that vcpu's TSC frequency can be migrated later via this field.
994 */
995 if (!env->tsc_khz) {
996 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
997 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
998 -ENOTSUP;
999 if (r > 0) {
1000 env->tsc_khz = r;
1001 }
1002 }
1003
1004 if (has_xsave) {
1005 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1006 }
1007 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1008
1009 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1010 has_msr_tsc_aux = false;
1011 }
1012
1013 return 0;
1014 }
1015
1016 void kvm_arch_reset_vcpu(X86CPU *cpu)
1017 {
1018 CPUX86State *env = &cpu->env;
1019
1020 env->exception_injected = -1;
1021 env->interrupt_injected = -1;
1022 env->xcr0 = 1;
1023 if (kvm_irqchip_in_kernel()) {
1024 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1025 KVM_MP_STATE_UNINITIALIZED;
1026 } else {
1027 env->mp_state = KVM_MP_STATE_RUNNABLE;
1028 }
1029 }
1030
1031 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1032 {
1033 CPUX86State *env = &cpu->env;
1034
1035 /* APs get directly into wait-for-SIPI state. */
1036 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1037 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1038 }
1039 }
1040
1041 static int kvm_get_supported_msrs(KVMState *s)
1042 {
1043 static int kvm_supported_msrs;
1044 int ret = 0;
1045
1046 /* first time */
1047 if (kvm_supported_msrs == 0) {
1048 struct kvm_msr_list msr_list, *kvm_msr_list;
1049
1050 kvm_supported_msrs = -1;
1051
1052 /* Obtain MSR list from KVM. These are the MSRs that we must
1053 * save/restore */
1054 msr_list.nmsrs = 0;
1055 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1056 if (ret < 0 && ret != -E2BIG) {
1057 return ret;
1058 }
1059 /* Old kernel modules had a bug and could write beyond the provided
1060 memory. Allocate at least a safe amount of 1K. */
1061 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1062 msr_list.nmsrs *
1063 sizeof(msr_list.indices[0])));
1064
1065 kvm_msr_list->nmsrs = msr_list.nmsrs;
1066 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1067 if (ret >= 0) {
1068 int i;
1069
1070 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1071 if (kvm_msr_list->indices[i] == MSR_STAR) {
1072 has_msr_star = true;
1073 continue;
1074 }
1075 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1076 has_msr_hsave_pa = true;
1077 continue;
1078 }
1079 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1080 has_msr_tsc_aux = true;
1081 continue;
1082 }
1083 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1084 has_msr_tsc_adjust = true;
1085 continue;
1086 }
1087 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1088 has_msr_tsc_deadline = true;
1089 continue;
1090 }
1091 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1092 has_msr_smbase = true;
1093 continue;
1094 }
1095 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1096 has_msr_misc_enable = true;
1097 continue;
1098 }
1099 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1100 has_msr_bndcfgs = true;
1101 continue;
1102 }
1103 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1104 has_msr_xss = true;
1105 continue;
1106 }
1107 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1108 has_msr_hv_crash = true;
1109 continue;
1110 }
1111 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1112 has_msr_hv_reset = true;
1113 continue;
1114 }
1115 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1116 has_msr_hv_vpindex = true;
1117 continue;
1118 }
1119 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1120 has_msr_hv_runtime = true;
1121 continue;
1122 }
1123 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1124 has_msr_hv_synic = true;
1125 continue;
1126 }
1127 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1128 has_msr_hv_stimer = true;
1129 continue;
1130 }
1131 }
1132 }
1133
1134 g_free(kvm_msr_list);
1135 }
1136
1137 return ret;
1138 }
1139
1140 static Notifier smram_machine_done;
1141 static KVMMemoryListener smram_listener;
1142 static AddressSpace smram_address_space;
1143 static MemoryRegion smram_as_root;
1144 static MemoryRegion smram_as_mem;
1145
1146 static void register_smram_listener(Notifier *n, void *unused)
1147 {
1148 MemoryRegion *smram =
1149 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1150
1151 /* Outer container... */
1152 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1153 memory_region_set_enabled(&smram_as_root, true);
1154
1155 /* ... with two regions inside: normal system memory with low
1156 * priority, and...
1157 */
1158 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1159 get_system_memory(), 0, ~0ull);
1160 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1161 memory_region_set_enabled(&smram_as_mem, true);
1162
1163 if (smram) {
1164 /* ... SMRAM with higher priority */
1165 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1166 memory_region_set_enabled(smram, true);
1167 }
1168
1169 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1170 kvm_memory_listener_register(kvm_state, &smram_listener,
1171 &smram_address_space, 1);
1172 }
1173
1174 int kvm_arch_init(MachineState *ms, KVMState *s)
1175 {
1176 uint64_t identity_base = 0xfffbc000;
1177 uint64_t shadow_mem;
1178 int ret;
1179 struct utsname utsname;
1180
1181 #ifdef KVM_CAP_XSAVE
1182 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1183 #endif
1184
1185 #ifdef KVM_CAP_XCRS
1186 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1187 #endif
1188
1189 #ifdef KVM_CAP_PIT_STATE2
1190 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1191 #endif
1192
1193 ret = kvm_get_supported_msrs(s);
1194 if (ret < 0) {
1195 return ret;
1196 }
1197
1198 uname(&utsname);
1199 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1200
1201 /*
1202 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1203 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1204 * Since these must be part of guest physical memory, we need to allocate
1205 * them, both by setting their start addresses in the kernel and by
1206 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1207 *
1208 * Older KVM versions may not support setting the identity map base. In
1209 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1210 * size.
1211 */
1212 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1213 /* Allows up to 16M BIOSes. */
1214 identity_base = 0xfeffc000;
1215
1216 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1217 if (ret < 0) {
1218 return ret;
1219 }
1220 }
1221
1222 /* Set TSS base one page after EPT identity map. */
1223 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1224 if (ret < 0) {
1225 return ret;
1226 }
1227
1228 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1229 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1230 if (ret < 0) {
1231 fprintf(stderr, "e820_add_entry() table is full\n");
1232 return ret;
1233 }
1234 qemu_register_reset(kvm_unpoison_all, NULL);
1235
1236 shadow_mem = machine_kvm_shadow_mem(ms);
1237 if (shadow_mem != -1) {
1238 shadow_mem /= 4096;
1239 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1240 if (ret < 0) {
1241 return ret;
1242 }
1243 }
1244
1245 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1246 smram_machine_done.notify = register_smram_listener;
1247 qemu_add_machine_init_done_notifier(&smram_machine_done);
1248 }
1249 return 0;
1250 }
1251
1252 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1253 {
1254 lhs->selector = rhs->selector;
1255 lhs->base = rhs->base;
1256 lhs->limit = rhs->limit;
1257 lhs->type = 3;
1258 lhs->present = 1;
1259 lhs->dpl = 3;
1260 lhs->db = 0;
1261 lhs->s = 1;
1262 lhs->l = 0;
1263 lhs->g = 0;
1264 lhs->avl = 0;
1265 lhs->unusable = 0;
1266 }
1267
1268 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1269 {
1270 unsigned flags = rhs->flags;
1271 lhs->selector = rhs->selector;
1272 lhs->base = rhs->base;
1273 lhs->limit = rhs->limit;
1274 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1275 lhs->present = (flags & DESC_P_MASK) != 0;
1276 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1277 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1278 lhs->s = (flags & DESC_S_MASK) != 0;
1279 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1280 lhs->g = (flags & DESC_G_MASK) != 0;
1281 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1282 lhs->unusable = !lhs->present;
1283 lhs->padding = 0;
1284 }
1285
1286 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1287 {
1288 lhs->selector = rhs->selector;
1289 lhs->base = rhs->base;
1290 lhs->limit = rhs->limit;
1291 if (rhs->unusable) {
1292 lhs->flags = 0;
1293 } else {
1294 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1295 (rhs->present * DESC_P_MASK) |
1296 (rhs->dpl << DESC_DPL_SHIFT) |
1297 (rhs->db << DESC_B_SHIFT) |
1298 (rhs->s * DESC_S_MASK) |
1299 (rhs->l << DESC_L_SHIFT) |
1300 (rhs->g * DESC_G_MASK) |
1301 (rhs->avl * DESC_AVL_MASK);
1302 }
1303 }
1304
1305 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1306 {
1307 if (set) {
1308 *kvm_reg = *qemu_reg;
1309 } else {
1310 *qemu_reg = *kvm_reg;
1311 }
1312 }
1313
1314 static int kvm_getput_regs(X86CPU *cpu, int set)
1315 {
1316 CPUX86State *env = &cpu->env;
1317 struct kvm_regs regs;
1318 int ret = 0;
1319
1320 if (!set) {
1321 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1322 if (ret < 0) {
1323 return ret;
1324 }
1325 }
1326
1327 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1328 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1329 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1330 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1331 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1332 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1333 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1334 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1335 #ifdef TARGET_X86_64
1336 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1337 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1338 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1339 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1340 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1341 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1342 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1343 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1344 #endif
1345
1346 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1347 kvm_getput_reg(&regs.rip, &env->eip, set);
1348
1349 if (set) {
1350 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1351 }
1352
1353 return ret;
1354 }
1355
1356 static int kvm_put_fpu(X86CPU *cpu)
1357 {
1358 CPUX86State *env = &cpu->env;
1359 struct kvm_fpu fpu;
1360 int i;
1361
1362 memset(&fpu, 0, sizeof fpu);
1363 fpu.fsw = env->fpus & ~(7 << 11);
1364 fpu.fsw |= (env->fpstt & 7) << 11;
1365 fpu.fcw = env->fpuc;
1366 fpu.last_opcode = env->fpop;
1367 fpu.last_ip = env->fpip;
1368 fpu.last_dp = env->fpdp;
1369 for (i = 0; i < 8; ++i) {
1370 fpu.ftwx |= (!env->fptags[i]) << i;
1371 }
1372 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1373 for (i = 0; i < CPU_NB_REGS; i++) {
1374 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1375 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1376 }
1377 fpu.mxcsr = env->mxcsr;
1378
1379 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1380 }
1381
1382 #define XSAVE_FCW_FSW 0
1383 #define XSAVE_FTW_FOP 1
1384 #define XSAVE_CWD_RIP 2
1385 #define XSAVE_CWD_RDP 4
1386 #define XSAVE_MXCSR 6
1387 #define XSAVE_ST_SPACE 8
1388 #define XSAVE_XMM_SPACE 40
1389 #define XSAVE_XSTATE_BV 128
1390 #define XSAVE_YMMH_SPACE 144
1391 #define XSAVE_BNDREGS 240
1392 #define XSAVE_BNDCSR 256
1393 #define XSAVE_OPMASK 272
1394 #define XSAVE_ZMM_Hi256 288
1395 #define XSAVE_Hi16_ZMM 416
1396 #define XSAVE_PKRU 672
1397
1398 #define XSAVE_BYTE_OFFSET(word_offset) \
1399 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1400
1401 #define ASSERT_OFFSET(word_offset, field) \
1402 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1403 offsetof(X86XSaveArea, field))
1404
1405 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1406 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1407 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1408 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1409 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1410 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1411 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1412 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1413 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1414 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1415 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1416 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1417 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1418 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1419 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1420
1421 static int kvm_put_xsave(X86CPU *cpu)
1422 {
1423 CPUX86State *env = &cpu->env;
1424 X86XSaveArea *xsave = env->kvm_xsave_buf;
1425 uint16_t cwd, swd, twd;
1426 int i;
1427
1428 if (!has_xsave) {
1429 return kvm_put_fpu(cpu);
1430 }
1431
1432 memset(xsave, 0, sizeof(struct kvm_xsave));
1433 twd = 0;
1434 swd = env->fpus & ~(7 << 11);
1435 swd |= (env->fpstt & 7) << 11;
1436 cwd = env->fpuc;
1437 for (i = 0; i < 8; ++i) {
1438 twd |= (!env->fptags[i]) << i;
1439 }
1440 xsave->legacy.fcw = cwd;
1441 xsave->legacy.fsw = swd;
1442 xsave->legacy.ftw = twd;
1443 xsave->legacy.fpop = env->fpop;
1444 xsave->legacy.fpip = env->fpip;
1445 xsave->legacy.fpdp = env->fpdp;
1446 memcpy(&xsave->legacy.fpregs, env->fpregs,
1447 sizeof env->fpregs);
1448 xsave->legacy.mxcsr = env->mxcsr;
1449 xsave->header.xstate_bv = env->xstate_bv;
1450 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1451 sizeof env->bnd_regs);
1452 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1453 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1454 sizeof env->opmask_regs);
1455
1456 for (i = 0; i < CPU_NB_REGS; i++) {
1457 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1458 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1459 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1460 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1461 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1462 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1463 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1464 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1465 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1466 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1467 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1468 }
1469
1470 #ifdef TARGET_X86_64
1471 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1472 16 * sizeof env->xmm_regs[16]);
1473 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1474 #endif
1475 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1476 }
1477
1478 static int kvm_put_xcrs(X86CPU *cpu)
1479 {
1480 CPUX86State *env = &cpu->env;
1481 struct kvm_xcrs xcrs = {};
1482
1483 if (!has_xcrs) {
1484 return 0;
1485 }
1486
1487 xcrs.nr_xcrs = 1;
1488 xcrs.flags = 0;
1489 xcrs.xcrs[0].xcr = 0;
1490 xcrs.xcrs[0].value = env->xcr0;
1491 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1492 }
1493
1494 static int kvm_put_sregs(X86CPU *cpu)
1495 {
1496 CPUX86State *env = &cpu->env;
1497 struct kvm_sregs sregs;
1498
1499 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1500 if (env->interrupt_injected >= 0) {
1501 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1502 (uint64_t)1 << (env->interrupt_injected % 64);
1503 }
1504
1505 if ((env->eflags & VM_MASK)) {
1506 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1507 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1508 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1509 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1510 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1511 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1512 } else {
1513 set_seg(&sregs.cs, &env->segs[R_CS]);
1514 set_seg(&sregs.ds, &env->segs[R_DS]);
1515 set_seg(&sregs.es, &env->segs[R_ES]);
1516 set_seg(&sregs.fs, &env->segs[R_FS]);
1517 set_seg(&sregs.gs, &env->segs[R_GS]);
1518 set_seg(&sregs.ss, &env->segs[R_SS]);
1519 }
1520
1521 set_seg(&sregs.tr, &env->tr);
1522 set_seg(&sregs.ldt, &env->ldt);
1523
1524 sregs.idt.limit = env->idt.limit;
1525 sregs.idt.base = env->idt.base;
1526 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1527 sregs.gdt.limit = env->gdt.limit;
1528 sregs.gdt.base = env->gdt.base;
1529 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1530
1531 sregs.cr0 = env->cr[0];
1532 sregs.cr2 = env->cr[2];
1533 sregs.cr3 = env->cr[3];
1534 sregs.cr4 = env->cr[4];
1535
1536 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1537 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1538
1539 sregs.efer = env->efer;
1540
1541 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1542 }
1543
1544 static void kvm_msr_buf_reset(X86CPU *cpu)
1545 {
1546 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1547 }
1548
1549 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1550 {
1551 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1552 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1553 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1554
1555 assert((void *)(entry + 1) <= limit);
1556
1557 entry->index = index;
1558 entry->reserved = 0;
1559 entry->data = value;
1560 msrs->nmsrs++;
1561 }
1562
1563 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1564 {
1565 kvm_msr_buf_reset(cpu);
1566 kvm_msr_entry_add(cpu, index, value);
1567
1568 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1569 }
1570
1571 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1572 {
1573 int ret;
1574
1575 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1576 assert(ret == 1);
1577 }
1578
1579 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1580 {
1581 CPUX86State *env = &cpu->env;
1582 int ret;
1583
1584 if (!has_msr_tsc_deadline) {
1585 return 0;
1586 }
1587
1588 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1589 if (ret < 0) {
1590 return ret;
1591 }
1592
1593 assert(ret == 1);
1594 return 0;
1595 }
1596
1597 /*
1598 * Provide a separate write service for the feature control MSR in order to
1599 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1600 * before writing any other state because forcibly leaving nested mode
1601 * invalidates the VCPU state.
1602 */
1603 static int kvm_put_msr_feature_control(X86CPU *cpu)
1604 {
1605 int ret;
1606
1607 if (!has_msr_feature_control) {
1608 return 0;
1609 }
1610
1611 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1612 cpu->env.msr_ia32_feature_control);
1613 if (ret < 0) {
1614 return ret;
1615 }
1616
1617 assert(ret == 1);
1618 return 0;
1619 }
1620
1621 static int kvm_put_msrs(X86CPU *cpu, int level)
1622 {
1623 CPUX86State *env = &cpu->env;
1624 int i;
1625 int ret;
1626
1627 kvm_msr_buf_reset(cpu);
1628
1629 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1630 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1631 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1632 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1633 if (has_msr_star) {
1634 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1635 }
1636 if (has_msr_hsave_pa) {
1637 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1638 }
1639 if (has_msr_tsc_aux) {
1640 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1641 }
1642 if (has_msr_tsc_adjust) {
1643 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1644 }
1645 if (has_msr_misc_enable) {
1646 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1647 env->msr_ia32_misc_enable);
1648 }
1649 if (has_msr_smbase) {
1650 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1651 }
1652 if (has_msr_bndcfgs) {
1653 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1654 }
1655 if (has_msr_xss) {
1656 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1657 }
1658 #ifdef TARGET_X86_64
1659 if (lm_capable_kernel) {
1660 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1661 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1662 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1663 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1664 }
1665 #endif
1666 /*
1667 * The following MSRs have side effects on the guest or are too heavy
1668 * for normal writeback. Limit them to reset or full state updates.
1669 */
1670 if (level >= KVM_PUT_RESET_STATE) {
1671 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1672 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1673 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1674 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1675 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1676 }
1677 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1678 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1679 }
1680 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1681 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1682 }
1683 if (has_msr_architectural_pmu) {
1684 /* Stop the counter. */
1685 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1686 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1687
1688 /* Set the counter values. */
1689 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1690 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1691 env->msr_fixed_counters[i]);
1692 }
1693 for (i = 0; i < num_architectural_pmu_counters; i++) {
1694 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1695 env->msr_gp_counters[i]);
1696 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1697 env->msr_gp_evtsel[i]);
1698 }
1699 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1700 env->msr_global_status);
1701 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1702 env->msr_global_ovf_ctrl);
1703
1704 /* Now start the PMU. */
1705 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1706 env->msr_fixed_ctr_ctrl);
1707 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1708 env->msr_global_ctrl);
1709 }
1710 if (has_msr_hv_hypercall) {
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1712 env->msr_hv_guest_os_id);
1713 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1714 env->msr_hv_hypercall);
1715 }
1716 if (cpu->hyperv_vapic) {
1717 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1718 env->msr_hv_vapic);
1719 }
1720 if (cpu->hyperv_time) {
1721 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1722 }
1723 if (has_msr_hv_crash) {
1724 int j;
1725
1726 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1727 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1728 env->msr_hv_crash_params[j]);
1729
1730 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1731 HV_X64_MSR_CRASH_CTL_NOTIFY);
1732 }
1733 if (has_msr_hv_runtime) {
1734 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1735 }
1736 if (cpu->hyperv_synic) {
1737 int j;
1738
1739 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1740 env->msr_hv_synic_control);
1741 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1742 env->msr_hv_synic_version);
1743 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1744 env->msr_hv_synic_evt_page);
1745 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1746 env->msr_hv_synic_msg_page);
1747
1748 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1749 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1750 env->msr_hv_synic_sint[j]);
1751 }
1752 }
1753 if (has_msr_hv_stimer) {
1754 int j;
1755
1756 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1757 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1758 env->msr_hv_stimer_config[j]);
1759 }
1760
1761 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1762 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1763 env->msr_hv_stimer_count[j]);
1764 }
1765 }
1766 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1767 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1768
1769 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1770 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1771 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1772 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1773 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1774 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1775 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1776 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1777 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1778 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1779 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1780 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1781 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1782 /* The CPU GPs if we write to a bit above the physical limit of
1783 * the host CPU (and KVM emulates that)
1784 */
1785 uint64_t mask = env->mtrr_var[i].mask;
1786 mask &= phys_mask;
1787
1788 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1789 env->mtrr_var[i].base);
1790 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1791 }
1792 }
1793
1794 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1795 * kvm_put_msr_feature_control. */
1796 }
1797 if (env->mcg_cap) {
1798 int i;
1799
1800 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1801 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1802 if (has_msr_mcg_ext_ctl) {
1803 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1804 }
1805 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1806 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1807 }
1808 }
1809
1810 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1811 if (ret < 0) {
1812 return ret;
1813 }
1814
1815 assert(ret == cpu->kvm_msr_buf->nmsrs);
1816 return 0;
1817 }
1818
1819
1820 static int kvm_get_fpu(X86CPU *cpu)
1821 {
1822 CPUX86State *env = &cpu->env;
1823 struct kvm_fpu fpu;
1824 int i, ret;
1825
1826 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1827 if (ret < 0) {
1828 return ret;
1829 }
1830
1831 env->fpstt = (fpu.fsw >> 11) & 7;
1832 env->fpus = fpu.fsw;
1833 env->fpuc = fpu.fcw;
1834 env->fpop = fpu.last_opcode;
1835 env->fpip = fpu.last_ip;
1836 env->fpdp = fpu.last_dp;
1837 for (i = 0; i < 8; ++i) {
1838 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1839 }
1840 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1841 for (i = 0; i < CPU_NB_REGS; i++) {
1842 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1843 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1844 }
1845 env->mxcsr = fpu.mxcsr;
1846
1847 return 0;
1848 }
1849
1850 static int kvm_get_xsave(X86CPU *cpu)
1851 {
1852 CPUX86State *env = &cpu->env;
1853 X86XSaveArea *xsave = env->kvm_xsave_buf;
1854 int ret, i;
1855 uint16_t cwd, swd, twd;
1856
1857 if (!has_xsave) {
1858 return kvm_get_fpu(cpu);
1859 }
1860
1861 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1862 if (ret < 0) {
1863 return ret;
1864 }
1865
1866 cwd = xsave->legacy.fcw;
1867 swd = xsave->legacy.fsw;
1868 twd = xsave->legacy.ftw;
1869 env->fpop = xsave->legacy.fpop;
1870 env->fpstt = (swd >> 11) & 7;
1871 env->fpus = swd;
1872 env->fpuc = cwd;
1873 for (i = 0; i < 8; ++i) {
1874 env->fptags[i] = !((twd >> i) & 1);
1875 }
1876 env->fpip = xsave->legacy.fpip;
1877 env->fpdp = xsave->legacy.fpdp;
1878 env->mxcsr = xsave->legacy.mxcsr;
1879 memcpy(env->fpregs, &xsave->legacy.fpregs,
1880 sizeof env->fpregs);
1881 env->xstate_bv = xsave->header.xstate_bv;
1882 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1883 sizeof env->bnd_regs);
1884 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1885 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1886 sizeof env->opmask_regs);
1887
1888 for (i = 0; i < CPU_NB_REGS; i++) {
1889 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1890 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1891 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1892 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1893 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1894 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1895 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1896 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1897 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1898 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1899 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1900 }
1901
1902 #ifdef TARGET_X86_64
1903 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1904 16 * sizeof env->xmm_regs[16]);
1905 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1906 #endif
1907 return 0;
1908 }
1909
1910 static int kvm_get_xcrs(X86CPU *cpu)
1911 {
1912 CPUX86State *env = &cpu->env;
1913 int i, ret;
1914 struct kvm_xcrs xcrs;
1915
1916 if (!has_xcrs) {
1917 return 0;
1918 }
1919
1920 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1921 if (ret < 0) {
1922 return ret;
1923 }
1924
1925 for (i = 0; i < xcrs.nr_xcrs; i++) {
1926 /* Only support xcr0 now */
1927 if (xcrs.xcrs[i].xcr == 0) {
1928 env->xcr0 = xcrs.xcrs[i].value;
1929 break;
1930 }
1931 }
1932 return 0;
1933 }
1934
1935 static int kvm_get_sregs(X86CPU *cpu)
1936 {
1937 CPUX86State *env = &cpu->env;
1938 struct kvm_sregs sregs;
1939 uint32_t hflags;
1940 int bit, i, ret;
1941
1942 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1943 if (ret < 0) {
1944 return ret;
1945 }
1946
1947 /* There can only be one pending IRQ set in the bitmap at a time, so try
1948 to find it and save its number instead (-1 for none). */
1949 env->interrupt_injected = -1;
1950 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1951 if (sregs.interrupt_bitmap[i]) {
1952 bit = ctz64(sregs.interrupt_bitmap[i]);
1953 env->interrupt_injected = i * 64 + bit;
1954 break;
1955 }
1956 }
1957
1958 get_seg(&env->segs[R_CS], &sregs.cs);
1959 get_seg(&env->segs[R_DS], &sregs.ds);
1960 get_seg(&env->segs[R_ES], &sregs.es);
1961 get_seg(&env->segs[R_FS], &sregs.fs);
1962 get_seg(&env->segs[R_GS], &sregs.gs);
1963 get_seg(&env->segs[R_SS], &sregs.ss);
1964
1965 get_seg(&env->tr, &sregs.tr);
1966 get_seg(&env->ldt, &sregs.ldt);
1967
1968 env->idt.limit = sregs.idt.limit;
1969 env->idt.base = sregs.idt.base;
1970 env->gdt.limit = sregs.gdt.limit;
1971 env->gdt.base = sregs.gdt.base;
1972
1973 env->cr[0] = sregs.cr0;
1974 env->cr[2] = sregs.cr2;
1975 env->cr[3] = sregs.cr3;
1976 env->cr[4] = sregs.cr4;
1977
1978 env->efer = sregs.efer;
1979
1980 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1981
1982 #define HFLAG_COPY_MASK \
1983 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1984 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1985 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1986 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1987
1988 hflags = env->hflags & HFLAG_COPY_MASK;
1989 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1990 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1991 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1992 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1993 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1994
1995 if (env->cr[4] & CR4_OSFXSR_MASK) {
1996 hflags |= HF_OSFXSR_MASK;
1997 }
1998
1999 if (env->efer & MSR_EFER_LMA) {
2000 hflags |= HF_LMA_MASK;
2001 }
2002
2003 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2004 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2005 } else {
2006 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
2007 (DESC_B_SHIFT - HF_CS32_SHIFT);
2008 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
2009 (DESC_B_SHIFT - HF_SS32_SHIFT);
2010 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2011 !(hflags & HF_CS32_MASK)) {
2012 hflags |= HF_ADDSEG_MASK;
2013 } else {
2014 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2015 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2016 }
2017 }
2018 env->hflags = hflags;
2019
2020 return 0;
2021 }
2022
2023 static int kvm_get_msrs(X86CPU *cpu)
2024 {
2025 CPUX86State *env = &cpu->env;
2026 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2027 int ret, i;
2028 uint64_t mtrr_top_bits;
2029
2030 kvm_msr_buf_reset(cpu);
2031
2032 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2033 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2034 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2035 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2036 if (has_msr_star) {
2037 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2038 }
2039 if (has_msr_hsave_pa) {
2040 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2041 }
2042 if (has_msr_tsc_aux) {
2043 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2044 }
2045 if (has_msr_tsc_adjust) {
2046 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2047 }
2048 if (has_msr_tsc_deadline) {
2049 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2050 }
2051 if (has_msr_misc_enable) {
2052 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2053 }
2054 if (has_msr_smbase) {
2055 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2056 }
2057 if (has_msr_feature_control) {
2058 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2059 }
2060 if (has_msr_bndcfgs) {
2061 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2062 }
2063 if (has_msr_xss) {
2064 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2065 }
2066
2067
2068 if (!env->tsc_valid) {
2069 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2070 env->tsc_valid = !runstate_is_running();
2071 }
2072
2073 #ifdef TARGET_X86_64
2074 if (lm_capable_kernel) {
2075 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2076 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2077 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2078 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2079 }
2080 #endif
2081 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2082 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2083 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2084 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2085 }
2086 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2087 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2088 }
2089 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2090 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2091 }
2092 if (has_msr_architectural_pmu) {
2093 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2094 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2095 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2096 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2097 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2098 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2099 }
2100 for (i = 0; i < num_architectural_pmu_counters; i++) {
2101 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2102 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2103 }
2104 }
2105
2106 if (env->mcg_cap) {
2107 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2108 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2109 if (has_msr_mcg_ext_ctl) {
2110 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2111 }
2112 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2113 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2114 }
2115 }
2116
2117 if (has_msr_hv_hypercall) {
2118 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2119 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2120 }
2121 if (cpu->hyperv_vapic) {
2122 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2123 }
2124 if (cpu->hyperv_time) {
2125 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2126 }
2127 if (has_msr_hv_crash) {
2128 int j;
2129
2130 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2131 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2132 }
2133 }
2134 if (has_msr_hv_runtime) {
2135 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2136 }
2137 if (cpu->hyperv_synic) {
2138 uint32_t msr;
2139
2140 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2141 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2142 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2143 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2144 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2145 kvm_msr_entry_add(cpu, msr, 0);
2146 }
2147 }
2148 if (has_msr_hv_stimer) {
2149 uint32_t msr;
2150
2151 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2152 msr++) {
2153 kvm_msr_entry_add(cpu, msr, 0);
2154 }
2155 }
2156 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2157 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2158 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2159 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2160 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2161 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2162 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2163 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2164 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2165 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2166 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2167 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2168 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2169 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2170 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2171 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2172 }
2173 }
2174
2175 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2176 if (ret < 0) {
2177 return ret;
2178 }
2179
2180 assert(ret == cpu->kvm_msr_buf->nmsrs);
2181 /*
2182 * MTRR masks: Each mask consists of 5 parts
2183 * a 10..0: must be zero
2184 * b 11 : valid bit
2185 * c n-1.12: actual mask bits
2186 * d 51..n: reserved must be zero
2187 * e 63.52: reserved must be zero
2188 *
2189 * 'n' is the number of physical bits supported by the CPU and is
2190 * apparently always <= 52. We know our 'n' but don't know what
2191 * the destinations 'n' is; it might be smaller, in which case
2192 * it masks (c) on loading. It might be larger, in which case
2193 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2194 * we're migrating to.
2195 */
2196
2197 if (cpu->fill_mtrr_mask) {
2198 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2199 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2200 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2201 } else {
2202 mtrr_top_bits = 0;
2203 }
2204
2205 for (i = 0; i < ret; i++) {
2206 uint32_t index = msrs[i].index;
2207 switch (index) {
2208 case MSR_IA32_SYSENTER_CS:
2209 env->sysenter_cs = msrs[i].data;
2210 break;
2211 case MSR_IA32_SYSENTER_ESP:
2212 env->sysenter_esp = msrs[i].data;
2213 break;
2214 case MSR_IA32_SYSENTER_EIP:
2215 env->sysenter_eip = msrs[i].data;
2216 break;
2217 case MSR_PAT:
2218 env->pat = msrs[i].data;
2219 break;
2220 case MSR_STAR:
2221 env->star = msrs[i].data;
2222 break;
2223 #ifdef TARGET_X86_64
2224 case MSR_CSTAR:
2225 env->cstar = msrs[i].data;
2226 break;
2227 case MSR_KERNELGSBASE:
2228 env->kernelgsbase = msrs[i].data;
2229 break;
2230 case MSR_FMASK:
2231 env->fmask = msrs[i].data;
2232 break;
2233 case MSR_LSTAR:
2234 env->lstar = msrs[i].data;
2235 break;
2236 #endif
2237 case MSR_IA32_TSC:
2238 env->tsc = msrs[i].data;
2239 break;
2240 case MSR_TSC_AUX:
2241 env->tsc_aux = msrs[i].data;
2242 break;
2243 case MSR_TSC_ADJUST:
2244 env->tsc_adjust = msrs[i].data;
2245 break;
2246 case MSR_IA32_TSCDEADLINE:
2247 env->tsc_deadline = msrs[i].data;
2248 break;
2249 case MSR_VM_HSAVE_PA:
2250 env->vm_hsave = msrs[i].data;
2251 break;
2252 case MSR_KVM_SYSTEM_TIME:
2253 env->system_time_msr = msrs[i].data;
2254 break;
2255 case MSR_KVM_WALL_CLOCK:
2256 env->wall_clock_msr = msrs[i].data;
2257 break;
2258 case MSR_MCG_STATUS:
2259 env->mcg_status = msrs[i].data;
2260 break;
2261 case MSR_MCG_CTL:
2262 env->mcg_ctl = msrs[i].data;
2263 break;
2264 case MSR_MCG_EXT_CTL:
2265 env->mcg_ext_ctl = msrs[i].data;
2266 break;
2267 case MSR_IA32_MISC_ENABLE:
2268 env->msr_ia32_misc_enable = msrs[i].data;
2269 break;
2270 case MSR_IA32_SMBASE:
2271 env->smbase = msrs[i].data;
2272 break;
2273 case MSR_IA32_FEATURE_CONTROL:
2274 env->msr_ia32_feature_control = msrs[i].data;
2275 break;
2276 case MSR_IA32_BNDCFGS:
2277 env->msr_bndcfgs = msrs[i].data;
2278 break;
2279 case MSR_IA32_XSS:
2280 env->xss = msrs[i].data;
2281 break;
2282 default:
2283 if (msrs[i].index >= MSR_MC0_CTL &&
2284 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2285 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2286 }
2287 break;
2288 case MSR_KVM_ASYNC_PF_EN:
2289 env->async_pf_en_msr = msrs[i].data;
2290 break;
2291 case MSR_KVM_PV_EOI_EN:
2292 env->pv_eoi_en_msr = msrs[i].data;
2293 break;
2294 case MSR_KVM_STEAL_TIME:
2295 env->steal_time_msr = msrs[i].data;
2296 break;
2297 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2298 env->msr_fixed_ctr_ctrl = msrs[i].data;
2299 break;
2300 case MSR_CORE_PERF_GLOBAL_CTRL:
2301 env->msr_global_ctrl = msrs[i].data;
2302 break;
2303 case MSR_CORE_PERF_GLOBAL_STATUS:
2304 env->msr_global_status = msrs[i].data;
2305 break;
2306 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2307 env->msr_global_ovf_ctrl = msrs[i].data;
2308 break;
2309 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2310 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2311 break;
2312 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2313 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2314 break;
2315 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2316 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2317 break;
2318 case HV_X64_MSR_HYPERCALL:
2319 env->msr_hv_hypercall = msrs[i].data;
2320 break;
2321 case HV_X64_MSR_GUEST_OS_ID:
2322 env->msr_hv_guest_os_id = msrs[i].data;
2323 break;
2324 case HV_X64_MSR_APIC_ASSIST_PAGE:
2325 env->msr_hv_vapic = msrs[i].data;
2326 break;
2327 case HV_X64_MSR_REFERENCE_TSC:
2328 env->msr_hv_tsc = msrs[i].data;
2329 break;
2330 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2331 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2332 break;
2333 case HV_X64_MSR_VP_RUNTIME:
2334 env->msr_hv_runtime = msrs[i].data;
2335 break;
2336 case HV_X64_MSR_SCONTROL:
2337 env->msr_hv_synic_control = msrs[i].data;
2338 break;
2339 case HV_X64_MSR_SVERSION:
2340 env->msr_hv_synic_version = msrs[i].data;
2341 break;
2342 case HV_X64_MSR_SIEFP:
2343 env->msr_hv_synic_evt_page = msrs[i].data;
2344 break;
2345 case HV_X64_MSR_SIMP:
2346 env->msr_hv_synic_msg_page = msrs[i].data;
2347 break;
2348 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2349 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2350 break;
2351 case HV_X64_MSR_STIMER0_CONFIG:
2352 case HV_X64_MSR_STIMER1_CONFIG:
2353 case HV_X64_MSR_STIMER2_CONFIG:
2354 case HV_X64_MSR_STIMER3_CONFIG:
2355 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2356 msrs[i].data;
2357 break;
2358 case HV_X64_MSR_STIMER0_COUNT:
2359 case HV_X64_MSR_STIMER1_COUNT:
2360 case HV_X64_MSR_STIMER2_COUNT:
2361 case HV_X64_MSR_STIMER3_COUNT:
2362 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2363 msrs[i].data;
2364 break;
2365 case MSR_MTRRdefType:
2366 env->mtrr_deftype = msrs[i].data;
2367 break;
2368 case MSR_MTRRfix64K_00000:
2369 env->mtrr_fixed[0] = msrs[i].data;
2370 break;
2371 case MSR_MTRRfix16K_80000:
2372 env->mtrr_fixed[1] = msrs[i].data;
2373 break;
2374 case MSR_MTRRfix16K_A0000:
2375 env->mtrr_fixed[2] = msrs[i].data;
2376 break;
2377 case MSR_MTRRfix4K_C0000:
2378 env->mtrr_fixed[3] = msrs[i].data;
2379 break;
2380 case MSR_MTRRfix4K_C8000:
2381 env->mtrr_fixed[4] = msrs[i].data;
2382 break;
2383 case MSR_MTRRfix4K_D0000:
2384 env->mtrr_fixed[5] = msrs[i].data;
2385 break;
2386 case MSR_MTRRfix4K_D8000:
2387 env->mtrr_fixed[6] = msrs[i].data;
2388 break;
2389 case MSR_MTRRfix4K_E0000:
2390 env->mtrr_fixed[7] = msrs[i].data;
2391 break;
2392 case MSR_MTRRfix4K_E8000:
2393 env->mtrr_fixed[8] = msrs[i].data;
2394 break;
2395 case MSR_MTRRfix4K_F0000:
2396 env->mtrr_fixed[9] = msrs[i].data;
2397 break;
2398 case MSR_MTRRfix4K_F8000:
2399 env->mtrr_fixed[10] = msrs[i].data;
2400 break;
2401 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2402 if (index & 1) {
2403 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2404 mtrr_top_bits;
2405 } else {
2406 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2407 }
2408 break;
2409 }
2410 }
2411
2412 return 0;
2413 }
2414
2415 static int kvm_put_mp_state(X86CPU *cpu)
2416 {
2417 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2418
2419 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2420 }
2421
2422 static int kvm_get_mp_state(X86CPU *cpu)
2423 {
2424 CPUState *cs = CPU(cpu);
2425 CPUX86State *env = &cpu->env;
2426 struct kvm_mp_state mp_state;
2427 int ret;
2428
2429 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2430 if (ret < 0) {
2431 return ret;
2432 }
2433 env->mp_state = mp_state.mp_state;
2434 if (kvm_irqchip_in_kernel()) {
2435 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2436 }
2437 return 0;
2438 }
2439
2440 static int kvm_get_apic(X86CPU *cpu)
2441 {
2442 DeviceState *apic = cpu->apic_state;
2443 struct kvm_lapic_state kapic;
2444 int ret;
2445
2446 if (apic && kvm_irqchip_in_kernel()) {
2447 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2448 if (ret < 0) {
2449 return ret;
2450 }
2451
2452 kvm_get_apic_state(apic, &kapic);
2453 }
2454 return 0;
2455 }
2456
2457 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2458 {
2459 CPUState *cs = CPU(cpu);
2460 CPUX86State *env = &cpu->env;
2461 struct kvm_vcpu_events events = {};
2462
2463 if (!kvm_has_vcpu_events()) {
2464 return 0;
2465 }
2466
2467 events.exception.injected = (env->exception_injected >= 0);
2468 events.exception.nr = env->exception_injected;
2469 events.exception.has_error_code = env->has_error_code;
2470 events.exception.error_code = env->error_code;
2471 events.exception.pad = 0;
2472
2473 events.interrupt.injected = (env->interrupt_injected >= 0);
2474 events.interrupt.nr = env->interrupt_injected;
2475 events.interrupt.soft = env->soft_interrupt;
2476
2477 events.nmi.injected = env->nmi_injected;
2478 events.nmi.pending = env->nmi_pending;
2479 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2480 events.nmi.pad = 0;
2481
2482 events.sipi_vector = env->sipi_vector;
2483 events.flags = 0;
2484
2485 if (has_msr_smbase) {
2486 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2487 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2488 if (kvm_irqchip_in_kernel()) {
2489 /* As soon as these are moved to the kernel, remove them
2490 * from cs->interrupt_request.
2491 */
2492 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2493 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2494 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2495 } else {
2496 /* Keep these in cs->interrupt_request. */
2497 events.smi.pending = 0;
2498 events.smi.latched_init = 0;
2499 }
2500 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2501 }
2502
2503 if (level >= KVM_PUT_RESET_STATE) {
2504 events.flags |=
2505 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2506 }
2507
2508 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2509 }
2510
2511 static int kvm_get_vcpu_events(X86CPU *cpu)
2512 {
2513 CPUX86State *env = &cpu->env;
2514 struct kvm_vcpu_events events;
2515 int ret;
2516
2517 if (!kvm_has_vcpu_events()) {
2518 return 0;
2519 }
2520
2521 memset(&events, 0, sizeof(events));
2522 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2523 if (ret < 0) {
2524 return ret;
2525 }
2526 env->exception_injected =
2527 events.exception.injected ? events.exception.nr : -1;
2528 env->has_error_code = events.exception.has_error_code;
2529 env->error_code = events.exception.error_code;
2530
2531 env->interrupt_injected =
2532 events.interrupt.injected ? events.interrupt.nr : -1;
2533 env->soft_interrupt = events.interrupt.soft;
2534
2535 env->nmi_injected = events.nmi.injected;
2536 env->nmi_pending = events.nmi.pending;
2537 if (events.nmi.masked) {
2538 env->hflags2 |= HF2_NMI_MASK;
2539 } else {
2540 env->hflags2 &= ~HF2_NMI_MASK;
2541 }
2542
2543 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2544 if (events.smi.smm) {
2545 env->hflags |= HF_SMM_MASK;
2546 } else {
2547 env->hflags &= ~HF_SMM_MASK;
2548 }
2549 if (events.smi.pending) {
2550 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2551 } else {
2552 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2553 }
2554 if (events.smi.smm_inside_nmi) {
2555 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2556 } else {
2557 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2558 }
2559 if (events.smi.latched_init) {
2560 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2561 } else {
2562 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2563 }
2564 }
2565
2566 env->sipi_vector = events.sipi_vector;
2567
2568 return 0;
2569 }
2570
2571 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2572 {
2573 CPUState *cs = CPU(cpu);
2574 CPUX86State *env = &cpu->env;
2575 int ret = 0;
2576 unsigned long reinject_trap = 0;
2577
2578 if (!kvm_has_vcpu_events()) {
2579 if (env->exception_injected == 1) {
2580 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2581 } else if (env->exception_injected == 3) {
2582 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2583 }
2584 env->exception_injected = -1;
2585 }
2586
2587 /*
2588 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2589 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2590 * by updating the debug state once again if single-stepping is on.
2591 * Another reason to call kvm_update_guest_debug here is a pending debug
2592 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2593 * reinject them via SET_GUEST_DEBUG.
2594 */
2595 if (reinject_trap ||
2596 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2597 ret = kvm_update_guest_debug(cs, reinject_trap);
2598 }
2599 return ret;
2600 }
2601
2602 static int kvm_put_debugregs(X86CPU *cpu)
2603 {
2604 CPUX86State *env = &cpu->env;
2605 struct kvm_debugregs dbgregs;
2606 int i;
2607
2608 if (!kvm_has_debugregs()) {
2609 return 0;
2610 }
2611
2612 for (i = 0; i < 4; i++) {
2613 dbgregs.db[i] = env->dr[i];
2614 }
2615 dbgregs.dr6 = env->dr[6];
2616 dbgregs.dr7 = env->dr[7];
2617 dbgregs.flags = 0;
2618
2619 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2620 }
2621
2622 static int kvm_get_debugregs(X86CPU *cpu)
2623 {
2624 CPUX86State *env = &cpu->env;
2625 struct kvm_debugregs dbgregs;
2626 int i, ret;
2627
2628 if (!kvm_has_debugregs()) {
2629 return 0;
2630 }
2631
2632 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2633 if (ret < 0) {
2634 return ret;
2635 }
2636 for (i = 0; i < 4; i++) {
2637 env->dr[i] = dbgregs.db[i];
2638 }
2639 env->dr[4] = env->dr[6] = dbgregs.dr6;
2640 env->dr[5] = env->dr[7] = dbgregs.dr7;
2641
2642 return 0;
2643 }
2644
2645 int kvm_arch_put_registers(CPUState *cpu, int level)
2646 {
2647 X86CPU *x86_cpu = X86_CPU(cpu);
2648 int ret;
2649
2650 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2651
2652 if (level >= KVM_PUT_RESET_STATE) {
2653 ret = kvm_put_msr_feature_control(x86_cpu);
2654 if (ret < 0) {
2655 return ret;
2656 }
2657 }
2658
2659 if (level == KVM_PUT_FULL_STATE) {
2660 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2661 * because TSC frequency mismatch shouldn't abort migration,
2662 * unless the user explicitly asked for a more strict TSC
2663 * setting (e.g. using an explicit "tsc-freq" option).
2664 */
2665 kvm_arch_set_tsc_khz(cpu);
2666 }
2667
2668 ret = kvm_getput_regs(x86_cpu, 1);
2669 if (ret < 0) {
2670 return ret;
2671 }
2672 ret = kvm_put_xsave(x86_cpu);
2673 if (ret < 0) {
2674 return ret;
2675 }
2676 ret = kvm_put_xcrs(x86_cpu);
2677 if (ret < 0) {
2678 return ret;
2679 }
2680 ret = kvm_put_sregs(x86_cpu);
2681 if (ret < 0) {
2682 return ret;
2683 }
2684 /* must be before kvm_put_msrs */
2685 ret = kvm_inject_mce_oldstyle(x86_cpu);
2686 if (ret < 0) {
2687 return ret;
2688 }
2689 ret = kvm_put_msrs(x86_cpu, level);
2690 if (ret < 0) {
2691 return ret;
2692 }
2693 if (level >= KVM_PUT_RESET_STATE) {
2694 ret = kvm_put_mp_state(x86_cpu);
2695 if (ret < 0) {
2696 return ret;
2697 }
2698 }
2699
2700 ret = kvm_put_tscdeadline_msr(x86_cpu);
2701 if (ret < 0) {
2702 return ret;
2703 }
2704
2705 ret = kvm_put_vcpu_events(x86_cpu, level);
2706 if (ret < 0) {
2707 return ret;
2708 }
2709 ret = kvm_put_debugregs(x86_cpu);
2710 if (ret < 0) {
2711 return ret;
2712 }
2713 /* must be last */
2714 ret = kvm_guest_debug_workarounds(x86_cpu);
2715 if (ret < 0) {
2716 return ret;
2717 }
2718 return 0;
2719 }
2720
2721 int kvm_arch_get_registers(CPUState *cs)
2722 {
2723 X86CPU *cpu = X86_CPU(cs);
2724 int ret;
2725
2726 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2727
2728 ret = kvm_getput_regs(cpu, 0);
2729 if (ret < 0) {
2730 goto out;
2731 }
2732 ret = kvm_get_xsave(cpu);
2733 if (ret < 0) {
2734 goto out;
2735 }
2736 ret = kvm_get_xcrs(cpu);
2737 if (ret < 0) {
2738 goto out;
2739 }
2740 ret = kvm_get_sregs(cpu);
2741 if (ret < 0) {
2742 goto out;
2743 }
2744 ret = kvm_get_msrs(cpu);
2745 if (ret < 0) {
2746 goto out;
2747 }
2748 ret = kvm_get_mp_state(cpu);
2749 if (ret < 0) {
2750 goto out;
2751 }
2752 ret = kvm_get_apic(cpu);
2753 if (ret < 0) {
2754 goto out;
2755 }
2756 ret = kvm_get_vcpu_events(cpu);
2757 if (ret < 0) {
2758 goto out;
2759 }
2760 ret = kvm_get_debugregs(cpu);
2761 if (ret < 0) {
2762 goto out;
2763 }
2764 ret = 0;
2765 out:
2766 cpu_sync_bndcs_hflags(&cpu->env);
2767 return ret;
2768 }
2769
2770 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2771 {
2772 X86CPU *x86_cpu = X86_CPU(cpu);
2773 CPUX86State *env = &x86_cpu->env;
2774 int ret;
2775
2776 /* Inject NMI */
2777 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2778 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2779 qemu_mutex_lock_iothread();
2780 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2781 qemu_mutex_unlock_iothread();
2782 DPRINTF("injected NMI\n");
2783 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2784 if (ret < 0) {
2785 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2786 strerror(-ret));
2787 }
2788 }
2789 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2790 qemu_mutex_lock_iothread();
2791 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2792 qemu_mutex_unlock_iothread();
2793 DPRINTF("injected SMI\n");
2794 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2795 if (ret < 0) {
2796 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2797 strerror(-ret));
2798 }
2799 }
2800 }
2801
2802 if (!kvm_pic_in_kernel()) {
2803 qemu_mutex_lock_iothread();
2804 }
2805
2806 /* Force the VCPU out of its inner loop to process any INIT requests
2807 * or (for userspace APIC, but it is cheap to combine the checks here)
2808 * pending TPR access reports.
2809 */
2810 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2811 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2812 !(env->hflags & HF_SMM_MASK)) {
2813 cpu->exit_request = 1;
2814 }
2815 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2816 cpu->exit_request = 1;
2817 }
2818 }
2819
2820 if (!kvm_pic_in_kernel()) {
2821 /* Try to inject an interrupt if the guest can accept it */
2822 if (run->ready_for_interrupt_injection &&
2823 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2824 (env->eflags & IF_MASK)) {
2825 int irq;
2826
2827 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2828 irq = cpu_get_pic_interrupt(env);
2829 if (irq >= 0) {
2830 struct kvm_interrupt intr;
2831
2832 intr.irq = irq;
2833 DPRINTF("injected interrupt %d\n", irq);
2834 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2835 if (ret < 0) {
2836 fprintf(stderr,
2837 "KVM: injection failed, interrupt lost (%s)\n",
2838 strerror(-ret));
2839 }
2840 }
2841 }
2842
2843 /* If we have an interrupt but the guest is not ready to receive an
2844 * interrupt, request an interrupt window exit. This will
2845 * cause a return to userspace as soon as the guest is ready to
2846 * receive interrupts. */
2847 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2848 run->request_interrupt_window = 1;
2849 } else {
2850 run->request_interrupt_window = 0;
2851 }
2852
2853 DPRINTF("setting tpr\n");
2854 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2855
2856 qemu_mutex_unlock_iothread();
2857 }
2858 }
2859
2860 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2861 {
2862 X86CPU *x86_cpu = X86_CPU(cpu);
2863 CPUX86State *env = &x86_cpu->env;
2864
2865 if (run->flags & KVM_RUN_X86_SMM) {
2866 env->hflags |= HF_SMM_MASK;
2867 } else {
2868 env->hflags &= ~HF_SMM_MASK;
2869 }
2870 if (run->if_flag) {
2871 env->eflags |= IF_MASK;
2872 } else {
2873 env->eflags &= ~IF_MASK;
2874 }
2875
2876 /* We need to protect the apic state against concurrent accesses from
2877 * different threads in case the userspace irqchip is used. */
2878 if (!kvm_irqchip_in_kernel()) {
2879 qemu_mutex_lock_iothread();
2880 }
2881 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2882 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2883 if (!kvm_irqchip_in_kernel()) {
2884 qemu_mutex_unlock_iothread();
2885 }
2886 return cpu_get_mem_attrs(env);
2887 }
2888
2889 int kvm_arch_process_async_events(CPUState *cs)
2890 {
2891 X86CPU *cpu = X86_CPU(cs);
2892 CPUX86State *env = &cpu->env;
2893
2894 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2895 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2896 assert(env->mcg_cap);
2897
2898 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2899
2900 kvm_cpu_synchronize_state(cs);
2901
2902 if (env->exception_injected == EXCP08_DBLE) {
2903 /* this means triple fault */
2904 qemu_system_reset_request();
2905 cs->exit_request = 1;
2906 return 0;
2907 }
2908 env->exception_injected = EXCP12_MCHK;
2909 env->has_error_code = 0;
2910
2911 cs->halted = 0;
2912 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2913 env->mp_state = KVM_MP_STATE_RUNNABLE;
2914 }
2915 }
2916
2917 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2918 !(env->hflags & HF_SMM_MASK)) {
2919 kvm_cpu_synchronize_state(cs);
2920 do_cpu_init(cpu);
2921 }
2922
2923 if (kvm_irqchip_in_kernel()) {
2924 return 0;
2925 }
2926
2927 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2928 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2929 apic_poll_irq(cpu->apic_state);
2930 }
2931 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2932 (env->eflags & IF_MASK)) ||
2933 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2934 cs->halted = 0;
2935 }
2936 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2937 kvm_cpu_synchronize_state(cs);
2938 do_cpu_sipi(cpu);
2939 }
2940 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2941 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2942 kvm_cpu_synchronize_state(cs);
2943 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2944 env->tpr_access_type);
2945 }
2946
2947 return cs->halted;
2948 }
2949
2950 static int kvm_handle_halt(X86CPU *cpu)
2951 {
2952 CPUState *cs = CPU(cpu);
2953 CPUX86State *env = &cpu->env;
2954
2955 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2956 (env->eflags & IF_MASK)) &&
2957 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2958 cs->halted = 1;
2959 return EXCP_HLT;
2960 }
2961
2962 return 0;
2963 }
2964
2965 static int kvm_handle_tpr_access(X86CPU *cpu)
2966 {
2967 CPUState *cs = CPU(cpu);
2968 struct kvm_run *run = cs->kvm_run;
2969
2970 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2971 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2972 : TPR_ACCESS_READ);
2973 return 1;
2974 }
2975
2976 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2977 {
2978 static const uint8_t int3 = 0xcc;
2979
2980 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2981 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2982 return -EINVAL;
2983 }
2984 return 0;
2985 }
2986
2987 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2988 {
2989 uint8_t int3;
2990
2991 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2992 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2993 return -EINVAL;
2994 }
2995 return 0;
2996 }
2997
2998 static struct {
2999 target_ulong addr;
3000 int len;
3001 int type;
3002 } hw_breakpoint[4];
3003
3004 static int nb_hw_breakpoint;
3005
3006 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3007 {
3008 int n;
3009
3010 for (n = 0; n < nb_hw_breakpoint; n++) {
3011 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3012 (hw_breakpoint[n].len == len || len == -1)) {
3013 return n;
3014 }
3015 }
3016 return -1;
3017 }
3018
3019 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3020 target_ulong len, int type)
3021 {
3022 switch (type) {
3023 case GDB_BREAKPOINT_HW:
3024 len = 1;
3025 break;
3026 case GDB_WATCHPOINT_WRITE:
3027 case GDB_WATCHPOINT_ACCESS:
3028 switch (len) {
3029 case 1:
3030 break;
3031 case 2:
3032 case 4:
3033 case 8:
3034 if (addr & (len - 1)) {
3035 return -EINVAL;
3036 }
3037 break;
3038 default:
3039 return -EINVAL;
3040 }
3041 break;
3042 default:
3043 return -ENOSYS;
3044 }
3045
3046 if (nb_hw_breakpoint == 4) {
3047 return -ENOBUFS;
3048 }
3049 if (find_hw_breakpoint(addr, len, type) >= 0) {
3050 return -EEXIST;
3051 }
3052 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3053 hw_breakpoint[nb_hw_breakpoint].len = len;
3054 hw_breakpoint[nb_hw_breakpoint].type = type;
3055 nb_hw_breakpoint++;
3056
3057 return 0;
3058 }
3059
3060 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3061 target_ulong len, int type)
3062 {
3063 int n;
3064
3065 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3066 if (n < 0) {
3067 return -ENOENT;
3068 }
3069 nb_hw_breakpoint--;
3070 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3071
3072 return 0;
3073 }
3074
3075 void kvm_arch_remove_all_hw_breakpoints(void)
3076 {
3077 nb_hw_breakpoint = 0;
3078 }
3079
3080 static CPUWatchpoint hw_watchpoint;
3081
3082 static int kvm_handle_debug(X86CPU *cpu,
3083 struct kvm_debug_exit_arch *arch_info)
3084 {
3085 CPUState *cs = CPU(cpu);
3086 CPUX86State *env = &cpu->env;
3087 int ret = 0;
3088 int n;
3089
3090 if (arch_info->exception == 1) {
3091 if (arch_info->dr6 & (1 << 14)) {
3092 if (cs->singlestep_enabled) {
3093 ret = EXCP_DEBUG;
3094 }
3095 } else {
3096 for (n = 0; n < 4; n++) {
3097 if (arch_info->dr6 & (1 << n)) {
3098 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3099 case 0x0:
3100 ret = EXCP_DEBUG;
3101 break;
3102 case 0x1:
3103 ret = EXCP_DEBUG;
3104 cs->watchpoint_hit = &hw_watchpoint;
3105 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3106 hw_watchpoint.flags = BP_MEM_WRITE;
3107 break;
3108 case 0x3:
3109 ret = EXCP_DEBUG;
3110 cs->watchpoint_hit = &hw_watchpoint;
3111 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3112 hw_watchpoint.flags = BP_MEM_ACCESS;
3113 break;
3114 }
3115 }
3116 }
3117 }
3118 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3119 ret = EXCP_DEBUG;
3120 }
3121 if (ret == 0) {
3122 cpu_synchronize_state(cs);
3123 assert(env->exception_injected == -1);
3124
3125 /* pass to guest */
3126 env->exception_injected = arch_info->exception;
3127 env->has_error_code = 0;
3128 }
3129
3130 return ret;
3131 }
3132
3133 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3134 {
3135 const uint8_t type_code[] = {
3136 [GDB_BREAKPOINT_HW] = 0x0,
3137 [GDB_WATCHPOINT_WRITE] = 0x1,
3138 [GDB_WATCHPOINT_ACCESS] = 0x3
3139 };
3140 const uint8_t len_code[] = {
3141 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3142 };
3143 int n;
3144
3145 if (kvm_sw_breakpoints_active(cpu)) {
3146 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3147 }
3148 if (nb_hw_breakpoint > 0) {
3149 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3150 dbg->arch.debugreg[7] = 0x0600;
3151 for (n = 0; n < nb_hw_breakpoint; n++) {
3152 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3153 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3154 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3155 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3156 }
3157 }
3158 }
3159
3160 static bool host_supports_vmx(void)
3161 {
3162 uint32_t ecx, unused;
3163
3164 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3165 return ecx & CPUID_EXT_VMX;
3166 }
3167
3168 #define VMX_INVALID_GUEST_STATE 0x80000021
3169
3170 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3171 {
3172 X86CPU *cpu = X86_CPU(cs);
3173 uint64_t code;
3174 int ret;
3175
3176 switch (run->exit_reason) {
3177 case KVM_EXIT_HLT:
3178 DPRINTF("handle_hlt\n");
3179 qemu_mutex_lock_iothread();
3180 ret = kvm_handle_halt(cpu);
3181 qemu_mutex_unlock_iothread();
3182 break;
3183 case KVM_EXIT_SET_TPR:
3184 ret = 0;
3185 break;
3186 case KVM_EXIT_TPR_ACCESS:
3187 qemu_mutex_lock_iothread();
3188 ret = kvm_handle_tpr_access(cpu);
3189 qemu_mutex_unlock_iothread();
3190 break;
3191 case KVM_EXIT_FAIL_ENTRY:
3192 code = run->fail_entry.hardware_entry_failure_reason;
3193 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3194 code);
3195 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3196 fprintf(stderr,
3197 "\nIf you're running a guest on an Intel machine without "
3198 "unrestricted mode\n"
3199 "support, the failure can be most likely due to the guest "
3200 "entering an invalid\n"
3201 "state for Intel VT. For example, the guest maybe running "
3202 "in big real mode\n"
3203 "which is not supported on less recent Intel processors."
3204 "\n\n");
3205 }
3206 ret = -1;
3207 break;
3208 case KVM_EXIT_EXCEPTION:
3209 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3210 run->ex.exception, run->ex.error_code);
3211 ret = -1;
3212 break;
3213 case KVM_EXIT_DEBUG:
3214 DPRINTF("kvm_exit_debug\n");
3215 qemu_mutex_lock_iothread();
3216 ret = kvm_handle_debug(cpu, &run->debug.arch);
3217 qemu_mutex_unlock_iothread();
3218 break;
3219 case KVM_EXIT_HYPERV:
3220 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3221 break;
3222 case KVM_EXIT_IOAPIC_EOI:
3223 ioapic_eoi_broadcast(run->eoi.vector);
3224 ret = 0;
3225 break;
3226 default:
3227 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3228 ret = -1;
3229 break;
3230 }
3231
3232 return ret;
3233 }
3234
3235 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3236 {
3237 X86CPU *cpu = X86_CPU(cs);
3238 CPUX86State *env = &cpu->env;
3239
3240 kvm_cpu_synchronize_state(cs);
3241 return !(env->cr[0] & CR0_PE_MASK) ||
3242 ((env->segs[R_CS].selector & 3) != 3);
3243 }
3244
3245 void kvm_arch_init_irq_routing(KVMState *s)
3246 {
3247 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3248 /* If kernel can't do irq routing, interrupt source
3249 * override 0->2 cannot be set up as required by HPET.
3250 * So we have to disable it.
3251 */
3252 no_hpet = 1;
3253 }
3254 /* We know at this point that we're using the in-kernel
3255 * irqchip, so we can use irqfds, and on x86 we know
3256 * we can use msi via irqfd and GSI routing.
3257 */
3258 kvm_msi_via_irqfd_allowed = true;
3259 kvm_gsi_routing_allowed = true;
3260
3261 if (kvm_irqchip_is_split()) {
3262 int i;
3263
3264 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3265 MSI routes for signaling interrupts to the local apics. */
3266 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3267 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3268 error_report("Could not enable split IRQ mode.");
3269 exit(1);
3270 }
3271 }
3272 }
3273 }
3274
3275 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3276 {
3277 int ret;
3278 if (machine_kernel_irqchip_split(ms)) {
3279 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3280 if (ret) {
3281 error_report("Could not enable split irqchip mode: %s",
3282 strerror(-ret));
3283 exit(1);
3284 } else {
3285 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3286 kvm_split_irqchip = true;
3287 return 1;
3288 }
3289 } else {
3290 return 0;
3291 }
3292 }
3293
3294 /* Classic KVM device assignment interface. Will remain x86 only. */
3295 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3296 uint32_t flags, uint32_t *dev_id)
3297 {
3298 struct kvm_assigned_pci_dev dev_data = {
3299 .segnr = dev_addr->domain,
3300 .busnr = dev_addr->bus,
3301 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3302 .flags = flags,
3303 };
3304 int ret;
3305
3306 dev_data.assigned_dev_id =
3307 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3308
3309 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3310 if (ret < 0) {
3311 return ret;
3312 }
3313
3314 *dev_id = dev_data.assigned_dev_id;
3315
3316 return 0;
3317 }
3318
3319 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3320 {
3321 struct kvm_assigned_pci_dev dev_data = {
3322 .assigned_dev_id = dev_id,
3323 };
3324
3325 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3326 }
3327
3328 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3329 uint32_t irq_type, uint32_t guest_irq)
3330 {
3331 struct kvm_assigned_irq assigned_irq = {
3332 .assigned_dev_id = dev_id,
3333 .guest_irq = guest_irq,
3334 .flags = irq_type,
3335 };
3336
3337 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3338 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3339 } else {
3340 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3341 }
3342 }
3343
3344 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3345 uint32_t guest_irq)
3346 {
3347 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3348 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3349
3350 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3351 }
3352
3353 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3354 {
3355 struct kvm_assigned_pci_dev dev_data = {
3356 .assigned_dev_id = dev_id,
3357 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3358 };
3359
3360 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3361 }
3362
3363 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3364 uint32_t type)
3365 {
3366 struct kvm_assigned_irq assigned_irq = {
3367 .assigned_dev_id = dev_id,
3368 .flags = type,
3369 };
3370
3371 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3372 }
3373
3374 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3375 {
3376 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3377 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3378 }
3379
3380 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3381 {
3382 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3383 KVM_DEV_IRQ_GUEST_MSI, virq);
3384 }
3385
3386 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3387 {
3388 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3389 KVM_DEV_IRQ_HOST_MSI);
3390 }
3391
3392 bool kvm_device_msix_supported(KVMState *s)
3393 {
3394 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3395 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3396 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3397 }
3398
3399 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3400 uint32_t nr_vectors)
3401 {
3402 struct kvm_assigned_msix_nr msix_nr = {
3403 .assigned_dev_id = dev_id,
3404 .entry_nr = nr_vectors,
3405 };
3406
3407 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3408 }
3409
3410 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3411 int virq)
3412 {
3413 struct kvm_assigned_msix_entry msix_entry = {
3414 .assigned_dev_id = dev_id,
3415 .gsi = virq,
3416 .entry = vector,
3417 };
3418
3419 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3420 }
3421
3422 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3423 {
3424 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3425 KVM_DEV_IRQ_GUEST_MSIX, 0);
3426 }
3427
3428 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3429 {
3430 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3431 KVM_DEV_IRQ_HOST_MSIX);
3432 }
3433
3434 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3435 uint64_t address, uint32_t data, PCIDevice *dev)
3436 {
3437 X86IOMMUState *iommu = x86_iommu_get_default();
3438
3439 if (iommu) {
3440 int ret;
3441 MSIMessage src, dst;
3442 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3443
3444 src.address = route->u.msi.address_hi;
3445 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3446 src.address |= route->u.msi.address_lo;
3447 src.data = route->u.msi.data;
3448
3449 ret = class->int_remap(iommu, &src, &dst, dev ? \
3450 pci_requester_id(dev) : \
3451 X86_IOMMU_SID_INVALID);
3452 if (ret) {
3453 trace_kvm_x86_fixup_msi_error(route->gsi);
3454 return 1;
3455 }
3456
3457 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3458 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3459 route->u.msi.data = dst.data;
3460 }
3461
3462 return 0;
3463 }
3464
3465 typedef struct MSIRouteEntry MSIRouteEntry;
3466
3467 struct MSIRouteEntry {
3468 PCIDevice *dev; /* Device pointer */
3469 int vector; /* MSI/MSIX vector index */
3470 int virq; /* Virtual IRQ index */
3471 QLIST_ENTRY(MSIRouteEntry) list;
3472 };
3473
3474 /* List of used GSI routes */
3475 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3476 QLIST_HEAD_INITIALIZER(msi_route_list);
3477
3478 static void kvm_update_msi_routes_all(void *private, bool global,
3479 uint32_t index, uint32_t mask)
3480 {
3481 int cnt = 0;
3482 MSIRouteEntry *entry;
3483 MSIMessage msg;
3484 /* TODO: explicit route update */
3485 QLIST_FOREACH(entry, &msi_route_list, list) {
3486 cnt++;
3487 msg = pci_get_msi_message(entry->dev, entry->vector);
3488 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3489 msg, entry->dev);
3490 }
3491 kvm_irqchip_commit_routes(kvm_state);
3492 trace_kvm_x86_update_msi_routes(cnt);
3493 }
3494
3495 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3496 int vector, PCIDevice *dev)
3497 {
3498 static bool notify_list_inited = false;
3499 MSIRouteEntry *entry;
3500
3501 if (!dev) {
3502 /* These are (possibly) IOAPIC routes only used for split
3503 * kernel irqchip mode, while what we are housekeeping are
3504 * PCI devices only. */
3505 return 0;
3506 }
3507
3508 entry = g_new0(MSIRouteEntry, 1);
3509 entry->dev = dev;
3510 entry->vector = vector;
3511 entry->virq = route->gsi;
3512 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3513
3514 trace_kvm_x86_add_msi_route(route->gsi);
3515
3516 if (!notify_list_inited) {
3517 /* For the first time we do add route, add ourselves into
3518 * IOMMU's IEC notify list if needed. */
3519 X86IOMMUState *iommu = x86_iommu_get_default();
3520 if (iommu) {
3521 x86_iommu_iec_register_notifier(iommu,
3522 kvm_update_msi_routes_all,
3523 NULL);
3524 }
3525 notify_list_inited = true;
3526 }
3527 return 0;
3528 }
3529
3530 int kvm_arch_release_virq_post(int virq)
3531 {
3532 MSIRouteEntry *entry, *next;
3533 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3534 if (entry->virq == virq) {
3535 trace_kvm_x86_remove_msi_route(virq);
3536 QLIST_REMOVE(entry, list);
3537 break;
3538 }
3539 }
3540 return 0;
3541 }
3542
3543 int kvm_arch_msi_data_to_gsi(uint32_t data)
3544 {
3545 abort();
3546 }
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