1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2021 Loongson Technology Corporation Limited
8 #include "qemu/osdep.h"
10 #include "qemu/qemu-print.h"
11 #include "qapi/error.h"
12 #include "qemu/module.h"
13 #include "sysemu/qtest.h"
14 #include "exec/cpu_ldst.h"
15 #include "exec/exec-all.h"
17 #include "internals.h"
18 #include "fpu/softfloat-helpers.h"
20 #ifndef CONFIG_USER_ONLY
21 #include "sysemu/reset.h"
26 const char * const regnames
[32] = {
27 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
28 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
29 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
30 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
33 const char * const fregnames
[32] = {
34 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
35 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
36 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
37 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
40 static const char * const excp_names
[] = {
41 [EXCCODE_INT
] = "Interrupt",
42 [EXCCODE_PIL
] = "Page invalid exception for load",
43 [EXCCODE_PIS
] = "Page invalid exception for store",
44 [EXCCODE_PIF
] = "Page invalid exception for fetch",
45 [EXCCODE_PME
] = "Page modified exception",
46 [EXCCODE_PNR
] = "Page Not Readable exception",
47 [EXCCODE_PNX
] = "Page Not Executable exception",
48 [EXCCODE_PPI
] = "Page Privilege error",
49 [EXCCODE_ADEF
] = "Address error for instruction fetch",
50 [EXCCODE_ADEM
] = "Address error for Memory access",
51 [EXCCODE_SYS
] = "Syscall",
52 [EXCCODE_BRK
] = "Break",
53 [EXCCODE_INE
] = "Instruction Non-Existent",
54 [EXCCODE_IPE
] = "Instruction privilege error",
55 [EXCCODE_FPD
] = "Floating Point Disabled",
56 [EXCCODE_FPE
] = "Floating Point Exception",
57 [EXCCODE_DBP
] = "Debug breakpoint",
58 [EXCCODE_BCE
] = "Bound Check Exception",
59 [EXCCODE_SXD
] = "128 bit vector instructions Disable exception",
60 [EXCCODE_ASXD
] = "256 bit vector instructions Disable exception",
63 const char *loongarch_exception_name(int32_t exception
)
65 assert(excp_names
[exception
]);
66 return excp_names
[exception
];
69 void G_NORETURN
do_raise_exception(CPULoongArchState
*env
,
73 CPUState
*cs
= env_cpu(env
);
75 qemu_log_mask(CPU_LOG_INT
, "%s: %d (%s)\n",
78 loongarch_exception_name(exception
));
79 cs
->exception_index
= exception
;
81 cpu_loop_exit_restore(cs
, pc
);
84 static void loongarch_cpu_set_pc(CPUState
*cs
, vaddr value
)
86 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
87 CPULoongArchState
*env
= &cpu
->env
;
92 static vaddr
loongarch_cpu_get_pc(CPUState
*cs
)
94 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
95 CPULoongArchState
*env
= &cpu
->env
;
100 #ifndef CONFIG_USER_ONLY
101 #include "hw/loongarch/virt.h"
103 void loongarch_cpu_set_irq(void *opaque
, int irq
, int level
)
105 LoongArchCPU
*cpu
= opaque
;
106 CPULoongArchState
*env
= &cpu
->env
;
107 CPUState
*cs
= CPU(cpu
);
109 if (irq
< 0 || irq
>= N_IRQS
) {
113 env
->CSR_ESTAT
= deposit64(env
->CSR_ESTAT
, irq
, 1, level
!= 0);
115 if (FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
)) {
116 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
118 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
122 static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState
*env
)
126 ret
= (FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
) &&
127 !(FIELD_EX64(env
->CSR_DBG
, CSR_DBG
, DST
)));
132 /* Check if there is pending and not masked out interrupt */
133 static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState
*env
)
138 pending
= FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
);
139 status
= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, LIE
);
141 return (pending
& status
) != 0;
144 static void loongarch_cpu_do_interrupt(CPUState
*cs
)
146 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
147 CPULoongArchState
*env
= &cpu
->env
;
148 bool update_badinstr
= 1;
151 bool tlbfill
= FIELD_EX64(env
->CSR_TLBRERA
, CSR_TLBRERA
, ISTLBR
);
152 uint32_t vec_size
= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, VS
);
154 if (cs
->exception_index
!= EXCCODE_INT
) {
155 if (cs
->exception_index
< 0 ||
156 cs
->exception_index
>= ARRAY_SIZE(excp_names
)) {
159 name
= excp_names
[cs
->exception_index
];
162 qemu_log_mask(CPU_LOG_INT
,
163 "%s enter: pc " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
164 " TLBRERA " TARGET_FMT_lx
" %s exception\n", __func__
,
165 env
->pc
, env
->CSR_ERA
, env
->CSR_TLBRERA
, name
);
168 switch (cs
->exception_index
) {
170 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DCL
, 1);
171 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, ECODE
, 0xC);
174 env
->CSR_DERA
= env
->pc
;
175 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DST
, 1);
176 set_pc(env
, env
->CSR_EENTRY
+ 0x480);
179 if (FIELD_EX64(env
->CSR_DBG
, CSR_DBG
, DST
)) {
180 env
->CSR_DBG
= FIELD_DP64(env
->CSR_DBG
, CSR_DBG
, DEI
, 1);
186 cause
= cs
->exception_index
;
197 env
->CSR_BADV
= env
->pc
;
207 cause
= cs
->exception_index
;
210 qemu_log("Error: exception(%d) has not been supported\n",
211 cs
->exception_index
);
215 if (update_badinstr
) {
216 env
->CSR_BADI
= cpu_ldl_code(env
, env
->pc
);
219 /* Save PLV and IE */
221 env
->CSR_TLBRPRMD
= FIELD_DP64(env
->CSR_TLBRPRMD
, CSR_TLBRPRMD
, PPLV
,
222 FIELD_EX64(env
->CSR_CRMD
,
224 env
->CSR_TLBRPRMD
= FIELD_DP64(env
->CSR_TLBRPRMD
, CSR_TLBRPRMD
, PIE
,
225 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
));
226 /* set the DA mode */
227 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DA
, 1);
228 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PG
, 0);
229 env
->CSR_TLBRERA
= FIELD_DP64(env
->CSR_TLBRERA
, CSR_TLBRERA
,
232 env
->CSR_ESTAT
= FIELD_DP64(env
->CSR_ESTAT
, CSR_ESTAT
, ECODE
,
233 EXCODE_MCODE(cause
));
234 env
->CSR_ESTAT
= FIELD_DP64(env
->CSR_ESTAT
, CSR_ESTAT
, ESUBCODE
,
235 EXCODE_SUBCODE(cause
));
236 env
->CSR_PRMD
= FIELD_DP64(env
->CSR_PRMD
, CSR_PRMD
, PPLV
,
237 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, PLV
));
238 env
->CSR_PRMD
= FIELD_DP64(env
->CSR_PRMD
, CSR_PRMD
, PIE
,
239 FIELD_EX64(env
->CSR_CRMD
, CSR_CRMD
, IE
));
240 env
->CSR_ERA
= env
->pc
;
243 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PLV
, 0);
244 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, IE
, 0);
247 vec_size
= (1 << vec_size
) * 4;
250 if (cs
->exception_index
== EXCCODE_INT
) {
253 uint32_t pending
= FIELD_EX64(env
->CSR_ESTAT
, CSR_ESTAT
, IS
);
254 pending
&= FIELD_EX64(env
->CSR_ECFG
, CSR_ECFG
, LIE
);
256 /* Find the highest-priority interrupt. */
257 vector
= 31 - clz32(pending
);
258 set_pc(env
, env
->CSR_EENTRY
+ \
259 (EXCCODE_EXTERNAL_INT
+ vector
) * vec_size
);
260 qemu_log_mask(CPU_LOG_INT
,
261 "%s: PC " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
262 " cause %d\n" " A " TARGET_FMT_lx
" D "
263 TARGET_FMT_lx
" vector = %d ExC " TARGET_FMT_lx
"ExS"
265 __func__
, env
->pc
, env
->CSR_ERA
,
266 cause
, env
->CSR_BADV
, env
->CSR_DERA
, vector
,
267 env
->CSR_ECFG
, env
->CSR_ESTAT
);
270 set_pc(env
, env
->CSR_TLBRENTRY
);
272 set_pc(env
, env
->CSR_EENTRY
+ EXCODE_MCODE(cause
) * vec_size
);
274 qemu_log_mask(CPU_LOG_INT
,
275 "%s: PC " TARGET_FMT_lx
" ERA " TARGET_FMT_lx
276 " cause %d%s\n, ESTAT " TARGET_FMT_lx
277 " EXCFG " TARGET_FMT_lx
" BADVA " TARGET_FMT_lx
278 "BADI " TARGET_FMT_lx
" SYS_NUM " TARGET_FMT_lu
279 " cpu %d asid " TARGET_FMT_lx
"\n", __func__
, env
->pc
,
280 tlbfill
? env
->CSR_TLBRERA
: env
->CSR_ERA
,
281 cause
, tlbfill
? "(refill)" : "", env
->CSR_ESTAT
,
283 tlbfill
? env
->CSR_TLBRBADV
: env
->CSR_BADV
,
284 env
->CSR_BADI
, env
->gpr
[11], cs
->cpu_index
,
287 cs
->exception_index
= -1;
290 static void loongarch_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
291 vaddr addr
, unsigned size
,
292 MMUAccessType access_type
,
293 int mmu_idx
, MemTxAttrs attrs
,
294 MemTxResult response
,
297 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
298 CPULoongArchState
*env
= &cpu
->env
;
300 if (access_type
== MMU_INST_FETCH
) {
301 do_raise_exception(env
, EXCCODE_ADEF
, retaddr
);
303 do_raise_exception(env
, EXCCODE_ADEM
, retaddr
);
307 static bool loongarch_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
309 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
310 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
311 CPULoongArchState
*env
= &cpu
->env
;
313 if (cpu_loongarch_hw_interrupts_enabled(env
) &&
314 cpu_loongarch_hw_interrupts_pending(env
)) {
316 cs
->exception_index
= EXCCODE_INT
;
317 loongarch_cpu_do_interrupt(cs
);
326 static void loongarch_cpu_synchronize_from_tb(CPUState
*cs
,
327 const TranslationBlock
*tb
)
329 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
330 CPULoongArchState
*env
= &cpu
->env
;
332 tcg_debug_assert(!(cs
->tcg_cflags
& CF_PCREL
));
336 static void loongarch_restore_state_to_opc(CPUState
*cs
,
337 const TranslationBlock
*tb
,
338 const uint64_t *data
)
340 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
341 CPULoongArchState
*env
= &cpu
->env
;
343 set_pc(env
, data
[0]);
345 #endif /* CONFIG_TCG */
347 static bool loongarch_cpu_has_work(CPUState
*cs
)
349 #ifdef CONFIG_USER_ONLY
352 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
353 CPULoongArchState
*env
= &cpu
->env
;
354 bool has_work
= false;
356 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
357 cpu_loongarch_hw_interrupts_pending(env
)) {
365 static void loongarch_la464_initfn(Object
*obj
)
367 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
368 CPULoongArchState
*env
= &cpu
->env
;
371 for (i
= 0; i
< 21; i
++) {
372 env
->cpucfg
[i
] = 0x0;
375 cpu
->dtb_compatible
= "loongarch,Loongson-3A5000";
376 env
->cpucfg
[0] = 0x14c010; /* PRID */
379 data
= FIELD_DP32(data
, CPUCFG1
, ARCH
, 2);
380 data
= FIELD_DP32(data
, CPUCFG1
, PGMMU
, 1);
381 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR
, 1);
382 data
= FIELD_DP32(data
, CPUCFG1
, PALEN
, 0x2f);
383 data
= FIELD_DP32(data
, CPUCFG1
, VALEN
, 0x2f);
384 data
= FIELD_DP32(data
, CPUCFG1
, UAL
, 1);
385 data
= FIELD_DP32(data
, CPUCFG1
, RI
, 1);
386 data
= FIELD_DP32(data
, CPUCFG1
, EP
, 1);
387 data
= FIELD_DP32(data
, CPUCFG1
, RPLV
, 1);
388 data
= FIELD_DP32(data
, CPUCFG1
, HP
, 1);
389 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR_BRD
, 1);
390 env
->cpucfg
[1] = data
;
393 data
= FIELD_DP32(data
, CPUCFG2
, FP
, 1);
394 data
= FIELD_DP32(data
, CPUCFG2
, FP_SP
, 1);
395 data
= FIELD_DP32(data
, CPUCFG2
, FP_DP
, 1);
396 data
= FIELD_DP32(data
, CPUCFG2
, FP_VER
, 1);
397 data
= FIELD_DP32(data
, CPUCFG2
, LSX
, 1),
398 data
= FIELD_DP32(data
, CPUCFG2
, LASX
, 1),
399 data
= FIELD_DP32(data
, CPUCFG2
, LLFTP
, 1);
400 data
= FIELD_DP32(data
, CPUCFG2
, LLFTP_VER
, 1);
401 data
= FIELD_DP32(data
, CPUCFG2
, LSPW
, 1);
402 data
= FIELD_DP32(data
, CPUCFG2
, LAM
, 1);
403 env
->cpucfg
[2] = data
;
405 env
->cpucfg
[4] = 100 * 1000 * 1000; /* Crystal frequency */
408 data
= FIELD_DP32(data
, CPUCFG5
, CC_MUL
, 1);
409 data
= FIELD_DP32(data
, CPUCFG5
, CC_DIV
, 1);
410 env
->cpucfg
[5] = data
;
413 data
= FIELD_DP32(data
, CPUCFG16
, L1_IUPRE
, 1);
414 data
= FIELD_DP32(data
, CPUCFG16
, L1_DPRE
, 1);
415 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUPRE
, 1);
416 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUUNIFY
, 1);
417 data
= FIELD_DP32(data
, CPUCFG16
, L2_IUPRIV
, 1);
418 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUPRE
, 1);
419 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUUNIFY
, 1);
420 data
= FIELD_DP32(data
, CPUCFG16
, L3_IUINCL
, 1);
421 env
->cpucfg
[16] = data
;
424 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_WAYS
, 3);
425 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_SETS
, 8);
426 data
= FIELD_DP32(data
, CPUCFG17
, L1IU_SIZE
, 6);
427 env
->cpucfg
[17] = data
;
430 data
= FIELD_DP32(data
, CPUCFG18
, L1D_WAYS
, 3);
431 data
= FIELD_DP32(data
, CPUCFG18
, L1D_SETS
, 8);
432 data
= FIELD_DP32(data
, CPUCFG18
, L1D_SIZE
, 6);
433 env
->cpucfg
[18] = data
;
436 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_WAYS
, 15);
437 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_SETS
, 8);
438 data
= FIELD_DP32(data
, CPUCFG19
, L2IU_SIZE
, 6);
439 env
->cpucfg
[19] = data
;
442 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_WAYS
, 15);
443 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_SETS
, 14);
444 data
= FIELD_DP32(data
, CPUCFG20
, L3IU_SIZE
, 6);
445 env
->cpucfg
[20] = data
;
447 env
->CSR_ASID
= FIELD_DP64(0, CSR_ASID
, ASIDBITS
, 0xa);
448 loongarch_cpu_post_init(obj
);
451 static void loongarch_la132_initfn(Object
*obj
)
453 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
454 CPULoongArchState
*env
= &cpu
->env
;
458 for (i
= 0; i
< 21; i
++) {
459 env
->cpucfg
[i
] = 0x0;
462 cpu
->dtb_compatible
= "loongarch,Loongson-1C103";
463 env
->cpucfg
[0] = 0x148042; /* PRID */
466 data
= FIELD_DP32(data
, CPUCFG1
, ARCH
, 1); /* LA32 */
467 data
= FIELD_DP32(data
, CPUCFG1
, PGMMU
, 1);
468 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR
, 1);
469 data
= FIELD_DP32(data
, CPUCFG1
, PALEN
, 0x1f); /* 32 bits */
470 data
= FIELD_DP32(data
, CPUCFG1
, VALEN
, 0x1f); /* 32 bits */
471 data
= FIELD_DP32(data
, CPUCFG1
, UAL
, 1);
472 data
= FIELD_DP32(data
, CPUCFG1
, RI
, 0);
473 data
= FIELD_DP32(data
, CPUCFG1
, EP
, 0);
474 data
= FIELD_DP32(data
, CPUCFG1
, RPLV
, 0);
475 data
= FIELD_DP32(data
, CPUCFG1
, HP
, 1);
476 data
= FIELD_DP32(data
, CPUCFG1
, IOCSR_BRD
, 1);
477 env
->cpucfg
[1] = data
;
480 static void loongarch_max_initfn(Object
*obj
)
482 /* '-cpu max' for TCG: we use cpu la464. */
483 loongarch_la464_initfn(obj
);
486 static void loongarch_cpu_list_entry(gpointer data
, gpointer user_data
)
488 const char *typename
= object_class_get_name(OBJECT_CLASS(data
));
490 qemu_printf("%s\n", typename
);
493 void loongarch_cpu_list(void)
496 list
= object_class_get_list_sorted(TYPE_LOONGARCH_CPU
, false);
497 g_slist_foreach(list
, loongarch_cpu_list_entry
, NULL
);
501 static void loongarch_cpu_reset_hold(Object
*obj
)
503 CPUState
*cs
= CPU(obj
);
504 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
505 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_GET_CLASS(cpu
);
506 CPULoongArchState
*env
= &cpu
->env
;
508 if (lacc
->parent_phases
.hold
) {
509 lacc
->parent_phases
.hold(obj
);
512 env
->fcsr0_mask
= FCSR0_M1
| FCSR0_M2
| FCSR0_M3
;
516 /* Set csr registers value after reset */
517 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PLV
, 0);
518 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, IE
, 0);
519 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DA
, 1);
520 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, PG
, 0);
521 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DATF
, 1);
522 env
->CSR_CRMD
= FIELD_DP64(env
->CSR_CRMD
, CSR_CRMD
, DATM
, 1);
524 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, FPE
, 0);
525 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, SXE
, 0);
526 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, ASXE
, 0);
527 env
->CSR_EUEN
= FIELD_DP64(env
->CSR_EUEN
, CSR_EUEN
, BTE
, 0);
531 env
->CSR_ECFG
= FIELD_DP64(env
->CSR_ECFG
, CSR_ECFG
, VS
, 0);
532 env
->CSR_ECFG
= FIELD_DP64(env
->CSR_ECFG
, CSR_ECFG
, LIE
, 0);
534 env
->CSR_ESTAT
= env
->CSR_ESTAT
& (~MAKE_64BIT_MASK(0, 2));
535 env
->CSR_RVACFG
= FIELD_DP64(env
->CSR_RVACFG
, CSR_RVACFG
, RBITS
, 0);
536 env
->CSR_TCFG
= FIELD_DP64(env
->CSR_TCFG
, CSR_TCFG
, EN
, 0);
537 env
->CSR_LLBCTL
= FIELD_DP64(env
->CSR_LLBCTL
, CSR_LLBCTL
, KLO
, 0);
538 env
->CSR_TLBRERA
= FIELD_DP64(env
->CSR_TLBRERA
, CSR_TLBRERA
, ISTLBR
, 0);
539 env
->CSR_MERRCTL
= FIELD_DP64(env
->CSR_MERRCTL
, CSR_MERRCTL
, ISMERR
, 0);
541 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, TLB_TYPE
, 2);
542 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, MTLB_ENTRY
, 63);
543 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, STLB_WAYS
, 7);
544 env
->CSR_PRCFG3
= FIELD_DP64(env
->CSR_PRCFG3
, CSR_PRCFG3
, STLB_SETS
, 8);
546 for (n
= 0; n
< 4; n
++) {
547 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV0
, 0);
548 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV1
, 0);
549 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV2
, 0);
550 env
->CSR_DMW
[n
] = FIELD_DP64(env
->CSR_DMW
[n
], CSR_DMW
, PLV3
, 0);
553 #ifndef CONFIG_USER_ONLY
554 env
->pc
= 0x1c000000;
555 memset(env
->tlb
, 0, sizeof(env
->tlb
));
558 restore_fp_status(env
);
559 cs
->exception_index
= -1;
562 static void loongarch_cpu_disas_set_info(CPUState
*s
, disassemble_info
*info
)
564 info
->print_insn
= print_insn_loongarch
;
567 static void loongarch_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
569 CPUState
*cs
= CPU(dev
);
570 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_GET_CLASS(dev
);
571 Error
*local_err
= NULL
;
573 cpu_exec_realizefn(cs
, &local_err
);
574 if (local_err
!= NULL
) {
575 error_propagate(errp
, local_err
);
579 loongarch_cpu_register_gdb_regs_for_features(cs
);
584 lacc
->parent_realize(dev
, errp
);
587 #ifndef CONFIG_USER_ONLY
588 static void loongarch_qemu_write(void *opaque
, hwaddr addr
,
589 uint64_t val
, unsigned size
)
591 qemu_log_mask(LOG_UNIMP
, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx
"\n",
595 static uint64_t loongarch_qemu_read(void *opaque
, hwaddr addr
, unsigned size
)
601 return 1ULL << IOCSRF_MSI
| 1ULL << IOCSRF_EXTIOI
|
602 1ULL << IOCSRF_CSRIPI
;
604 return 0x6e6f73676e6f6f4cULL
; /* "Loongson" */
606 return 0x303030354133ULL
; /* "3A5000" */
608 return 1ULL << IOCSRM_EXTIOI_EN
;
613 static const MemoryRegionOps loongarch_qemu_ops
= {
614 .read
= loongarch_qemu_read
,
615 .write
= loongarch_qemu_write
,
616 .endianness
= DEVICE_LITTLE_ENDIAN
,
618 .min_access_size
= 4,
619 .max_access_size
= 8,
622 .min_access_size
= 8,
623 .max_access_size
= 8,
628 static bool loongarch_get_lsx(Object
*obj
, Error
**errp
)
630 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
633 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
)) {
641 static void loongarch_set_lsx(Object
*obj
, bool value
, Error
**errp
)
643 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
646 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
, 1);
648 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
, 0);
649 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
, 0);
653 static bool loongarch_get_lasx(Object
*obj
, Error
**errp
)
655 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
658 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
)) {
666 static void loongarch_set_lasx(Object
*obj
, bool value
, Error
**errp
)
668 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
671 if (!FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
)) {
672 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
, 1);
674 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
, 1);
676 cpu
->env
.cpucfg
[2] = FIELD_DP32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
, 0);
680 void loongarch_cpu_post_init(Object
*obj
)
682 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
684 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LSX
)) {
685 object_property_add_bool(obj
, "lsx", loongarch_get_lsx
,
688 if (FIELD_EX32(cpu
->env
.cpucfg
[2], CPUCFG2
, LASX
)) {
689 object_property_add_bool(obj
, "lasx", loongarch_get_lasx
,
694 static void loongarch_cpu_init(Object
*obj
)
696 #ifndef CONFIG_USER_ONLY
697 LoongArchCPU
*cpu
= LOONGARCH_CPU(obj
);
698 CPULoongArchState
*env
= &cpu
->env
;
700 qdev_init_gpio_in(DEVICE(cpu
), loongarch_cpu_set_irq
, N_IRQS
);
701 timer_init_ns(&cpu
->timer
, QEMU_CLOCK_VIRTUAL
,
702 &loongarch_constant_timer_cb
, cpu
);
703 memory_region_init_io(&env
->system_iocsr
, OBJECT(cpu
), NULL
,
704 env
, "iocsr", UINT64_MAX
);
705 address_space_init(&env
->address_space_iocsr
, &env
->system_iocsr
, "IOCSR");
706 memory_region_init_io(&env
->iocsr_mem
, OBJECT(cpu
), &loongarch_qemu_ops
,
707 NULL
, "iocsr_misc", 0x428);
708 memory_region_add_subregion(&env
->system_iocsr
, 0, &env
->iocsr_mem
);
712 static ObjectClass
*loongarch_cpu_class_by_name(const char *cpu_model
)
716 oc
= object_class_by_name(cpu_model
);
718 g_autofree
char *typename
719 = g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model
);
720 oc
= object_class_by_name(typename
);
726 if (object_class_dynamic_cast(oc
, TYPE_LOONGARCH_CPU
)) {
732 void loongarch_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
734 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
735 CPULoongArchState
*env
= &cpu
->env
;
738 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
739 qemu_fprintf(f
, " FCSR0 0x%08x fp_status 0x%02x\n", env
->fcsr0
,
740 get_float_exception_flags(&env
->fp_status
));
743 for (i
= 0; i
< 32; i
++) {
745 qemu_fprintf(f
, " GPR%02d:", i
);
747 qemu_fprintf(f
, " %s %016" PRIx64
, regnames
[i
], env
->gpr
[i
]);
749 qemu_fprintf(f
, "\n");
753 qemu_fprintf(f
, "CRMD=%016" PRIx64
"\n", env
->CSR_CRMD
);
754 qemu_fprintf(f
, "PRMD=%016" PRIx64
"\n", env
->CSR_PRMD
);
755 qemu_fprintf(f
, "EUEN=%016" PRIx64
"\n", env
->CSR_EUEN
);
756 qemu_fprintf(f
, "ESTAT=%016" PRIx64
"\n", env
->CSR_ESTAT
);
757 qemu_fprintf(f
, "ERA=%016" PRIx64
"\n", env
->CSR_ERA
);
758 qemu_fprintf(f
, "BADV=%016" PRIx64
"\n", env
->CSR_BADV
);
759 qemu_fprintf(f
, "BADI=%016" PRIx64
"\n", env
->CSR_BADI
);
760 qemu_fprintf(f
, "EENTRY=%016" PRIx64
"\n", env
->CSR_EENTRY
);
761 qemu_fprintf(f
, "PRCFG1=%016" PRIx64
", PRCFG2=%016" PRIx64
","
762 " PRCFG3=%016" PRIx64
"\n",
763 env
->CSR_PRCFG1
, env
->CSR_PRCFG3
, env
->CSR_PRCFG3
);
764 qemu_fprintf(f
, "TLBRENTRY=%016" PRIx64
"\n", env
->CSR_TLBRENTRY
);
765 qemu_fprintf(f
, "TLBRBADV=%016" PRIx64
"\n", env
->CSR_TLBRBADV
);
766 qemu_fprintf(f
, "TLBRERA=%016" PRIx64
"\n", env
->CSR_TLBRERA
);
767 qemu_fprintf(f
, "TCFG=%016" PRIx64
"\n", env
->CSR_TCFG
);
768 qemu_fprintf(f
, "TVAL=%016" PRIx64
"\n", env
->CSR_TVAL
);
771 if (flags
& CPU_DUMP_FPU
) {
772 for (i
= 0; i
< 32; i
++) {
773 qemu_fprintf(f
, " %s %016" PRIx64
, fregnames
[i
], env
->fpr
[i
].vreg
.D(0));
775 qemu_fprintf(f
, "\n");
782 #include "hw/core/tcg-cpu-ops.h"
784 static struct TCGCPUOps loongarch_tcg_ops
= {
785 .initialize
= loongarch_translate_init
,
786 .synchronize_from_tb
= loongarch_cpu_synchronize_from_tb
,
787 .restore_state_to_opc
= loongarch_restore_state_to_opc
,
789 #ifndef CONFIG_USER_ONLY
790 .tlb_fill
= loongarch_cpu_tlb_fill
,
791 .cpu_exec_interrupt
= loongarch_cpu_exec_interrupt
,
792 .do_interrupt
= loongarch_cpu_do_interrupt
,
793 .do_transaction_failed
= loongarch_cpu_do_transaction_failed
,
796 #endif /* CONFIG_TCG */
798 #ifndef CONFIG_USER_ONLY
799 #include "hw/core/sysemu-cpu-ops.h"
801 static const struct SysemuCPUOps loongarch_sysemu_ops
= {
802 .get_phys_page_debug
= loongarch_cpu_get_phys_page_debug
,
805 static int64_t loongarch_cpu_get_arch_id(CPUState
*cs
)
807 LoongArchCPU
*cpu
= LOONGARCH_CPU(cs
);
813 static void loongarch_cpu_class_init(ObjectClass
*c
, void *data
)
815 LoongArchCPUClass
*lacc
= LOONGARCH_CPU_CLASS(c
);
816 CPUClass
*cc
= CPU_CLASS(c
);
817 DeviceClass
*dc
= DEVICE_CLASS(c
);
818 ResettableClass
*rc
= RESETTABLE_CLASS(c
);
820 device_class_set_parent_realize(dc
, loongarch_cpu_realizefn
,
821 &lacc
->parent_realize
);
822 resettable_class_set_parent_phases(rc
, NULL
, loongarch_cpu_reset_hold
, NULL
,
823 &lacc
->parent_phases
);
825 cc
->class_by_name
= loongarch_cpu_class_by_name
;
826 cc
->has_work
= loongarch_cpu_has_work
;
827 cc
->dump_state
= loongarch_cpu_dump_state
;
828 cc
->set_pc
= loongarch_cpu_set_pc
;
829 cc
->get_pc
= loongarch_cpu_get_pc
;
830 #ifndef CONFIG_USER_ONLY
831 cc
->get_arch_id
= loongarch_cpu_get_arch_id
;
832 dc
->vmsd
= &vmstate_loongarch_cpu
;
833 cc
->sysemu_ops
= &loongarch_sysemu_ops
;
835 cc
->disas_set_info
= loongarch_cpu_disas_set_info
;
836 cc
->gdb_read_register
= loongarch_cpu_gdb_read_register
;
837 cc
->gdb_write_register
= loongarch_cpu_gdb_write_register
;
838 cc
->gdb_stop_before_watchpoint
= true;
841 cc
->tcg_ops
= &loongarch_tcg_ops
;
845 static const gchar
*loongarch32_gdb_arch_name(CPUState
*cs
)
847 return "loongarch32";
850 static void loongarch32_cpu_class_init(ObjectClass
*c
, void *data
)
852 CPUClass
*cc
= CPU_CLASS(c
);
854 cc
->gdb_num_core_regs
= 35;
855 cc
->gdb_core_xml_file
= "loongarch-base32.xml";
856 cc
->gdb_arch_name
= loongarch32_gdb_arch_name
;
859 static const gchar
*loongarch64_gdb_arch_name(CPUState
*cs
)
861 return "loongarch64";
864 static void loongarch64_cpu_class_init(ObjectClass
*c
, void *data
)
866 CPUClass
*cc
= CPU_CLASS(c
);
868 cc
->gdb_num_core_regs
= 35;
869 cc
->gdb_core_xml_file
= "loongarch-base64.xml";
870 cc
->gdb_arch_name
= loongarch64_gdb_arch_name
;
873 #define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \
875 .parent = TYPE_LOONGARCH##size##_CPU, \
876 .instance_init = initfn, \
877 .name = LOONGARCH_CPU_TYPE_NAME(model), \
880 static const TypeInfo loongarch_cpu_type_infos
[] = {
882 .name
= TYPE_LOONGARCH_CPU
,
884 .instance_size
= sizeof(LoongArchCPU
),
885 .instance_align
= __alignof(LoongArchCPU
),
886 .instance_init
= loongarch_cpu_init
,
889 .class_size
= sizeof(LoongArchCPUClass
),
890 .class_init
= loongarch_cpu_class_init
,
893 .name
= TYPE_LOONGARCH32_CPU
,
894 .parent
= TYPE_LOONGARCH_CPU
,
897 .class_init
= loongarch32_cpu_class_init
,
900 .name
= TYPE_LOONGARCH64_CPU
,
901 .parent
= TYPE_LOONGARCH_CPU
,
904 .class_init
= loongarch64_cpu_class_init
,
906 DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn
),
907 DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn
),
908 DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn
),
911 DEFINE_TYPES(loongarch_cpu_type_infos
)