target/loongarch/insn_trans/trans_branch.c.inc

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (c) 2021 Loongson Technology Corporation Limited
   4  */
   5
   6 static bool trans_b(DisasContext *ctx, arg_b *a)
   7 {
   8     gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
   9     ctx->base.is_jmp = DISAS_NORETURN;
  10     return true;
  11 }
  12
  13 static bool trans_bl(DisasContext *ctx, arg_bl *a)
  14 {
  15     tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
  16     gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
  17     ctx->base.is_jmp = DISAS_NORETURN;
  18     return true;
  19 }
  20
  21 static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
  22 {
  23     TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
  24     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
  25
  26     tcg_gen_addi_tl(cpu_pc, src1, a->offs);
  27     tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
  28     gen_set_gpr(a->rd, dest, EXT_NONE);
  29     tcg_gen_lookup_and_goto_ptr();
  30     ctx->base.is_jmp = DISAS_NORETURN;
  31     return true;
  32 }
  33
  34 static void gen_bc(DisasContext *ctx, TCGv src1, TCGv src2,
  35                    target_long offs, TCGCond cond)
  36 {
  37     TCGLabel *l = gen_new_label();
  38     tcg_gen_brcond_tl(cond, src1, src2, l);
  39     gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
  40     gen_set_label(l);
  41     gen_goto_tb(ctx, 0, ctx->base.pc_next + offs);
  42     ctx->base.is_jmp = DISAS_NORETURN;
  43 }
  44
  45 static bool gen_rr_bc(DisasContext *ctx, arg_rr_offs *a, TCGCond cond)
  46 {
  47     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
  48     TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
  49
  50     gen_bc(ctx, src1, src2, a->offs, cond);
  51     return true;
  52 }
  53
  54 static bool gen_rz_bc(DisasContext *ctx, arg_r_offs *a, TCGCond cond)
  55 {
  56     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
  57     TCGv src2 = tcg_constant_tl(0);
  58
  59     gen_bc(ctx, src1, src2, a->offs, cond);
  60     return true;
  61 }
  62
  63 static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond)
  64 {
  65     TCGv src1 = tcg_temp_new();
  66     TCGv src2 = tcg_constant_tl(0);
  67
  68     tcg_gen_ld8u_tl(src1, cpu_env,
  69                     offsetof(CPULoongArchState, cf[a->cj]));
  70     gen_bc(ctx, src1, src2, a->offs, cond);
  71     return true;
  72 }
  73
  74 TRANS(beq, gen_rr_bc, TCG_COND_EQ)
  75 TRANS(bne, gen_rr_bc, TCG_COND_NE)
  76 TRANS(blt, gen_rr_bc, TCG_COND_LT)
  77 TRANS(bge, gen_rr_bc, TCG_COND_GE)
  78 TRANS(bltu, gen_rr_bc, TCG_COND_LTU)
  79 TRANS(bgeu, gen_rr_bc, TCG_COND_GEU)
  80 TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
  81 TRANS(bnez, gen_rz_bc, TCG_COND_NE)
  82 TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
  83 TRANS(bcnez, gen_cz_bc, TCG_COND_NE)