target/m68k/cpu.h

   1 /*
   2  * m68k virtual CPU header
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery
   5  *  Written by Paul Brook
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef M68K_CPU_H
  22 #define M68K_CPU_H
  23
  24 #define TARGET_LONG_BITS 32
  25
  26 #define CPUArchState struct CPUM68KState
  27
  28 #include "qemu-common.h"
  29 #include "exec/cpu-defs.h"
  30 #include "cpu-qom.h"
  31 #include "fpu/softfloat.h"
  32
  33 #define OS_BYTE     0
  34 #define OS_WORD     1
  35 #define OS_LONG     2
  36 #define OS_SINGLE   3
  37 #define OS_DOUBLE   4
  38 #define OS_EXTENDED 5
  39 #define OS_PACKED   6
  40
  41 #define MAX_QREGS 32
  42
  43 #define EXCP_ACCESS         2   /* Access (MMU) error.  */
  44 #define EXCP_ADDRESS        3   /* Address error.  */
  45 #define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  46 #define EXCP_DIV0           5   /* Divide by zero */
  47 #define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  48 #define EXCP_TRACE          9
  49 #define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  50 #define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  51 #define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  52 #define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  53 #define EXCP_FORMAT         14  /* RTE format error.  */
  54 #define EXCP_UNINITIALIZED  15
  55 #define EXCP_TRAP0          32   /* User trap #0.  */
  56 #define EXCP_TRAP15         47   /* User trap #15.  */
  57 #define EXCP_UNSUPPORTED    61
  58 #define EXCP_ICE            13
  59
  60 #define EXCP_RTE            0x100
  61 #define EXCP_HALT_INSN      0x101
  62
  63 #define NB_MMU_MODES 2
  64 #define TARGET_INSN_START_EXTRA_WORDS 1
  65
  66 typedef struct CPUM68KState {
  67     uint32_t dregs[8];
  68     uint32_t aregs[8];
  69     uint32_t pc;
  70     uint32_t sr;
  71
  72     /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  73     int current_sp;
  74     uint32_t sp[2];
  75
  76     /* Condition flags.  */
  77     uint32_t cc_op;
  78     uint32_t cc_x; /* always 0/1 */
  79     uint32_t cc_n; /* in bit 31 (i.e. negative) */
  80     uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
  81     uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
  82     uint32_t cc_z; /* == 0 or unused */
  83
  84     float64 fregs[8];
  85     float64 fp_result;
  86     uint32_t fpcr;
  87     uint32_t fpsr;
  88     float_status fp_status;
  89
  90     uint64_t mactmp;
  91     /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
  92        two 8-bit parts.  We store a single 64-bit value and
  93        rearrange/extend this when changing modes.  */
  94     uint64_t macc[4];
  95     uint32_t macsr;
  96     uint32_t mac_mask;
  97
  98     /* MMU status.  */
  99     struct {
 100         uint32_t ar;
 101     } mmu;
 102
 103     /* Control registers.  */
 104     uint32_t vbr;
 105     uint32_t mbar;
 106     uint32_t rambar0;
 107     uint32_t cacr;
 108
 109     int pending_vector;
 110     int pending_level;
 111
 112     uint32_t qregs[MAX_QREGS];
 113
 114     CPU_COMMON
 115
 116     /* Fields from here on are preserved across CPU reset. */
 117     uint32_t features;
 118 } CPUM68KState;
 119
 120 /**
 121  * M68kCPU:
 122  * @env: #CPUM68KState
 123  *
 124  * A Motorola 68k CPU.
 125  */
 126 struct M68kCPU {
 127     /*< private >*/
 128     CPUState parent_obj;
 129     /*< public >*/
 130
 131     CPUM68KState env;
 132 };
 133
 134 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
 135 {
 136     return container_of(env, M68kCPU, env);
 137 }
 138
 139 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
 140
 141 #define ENV_OFFSET offsetof(M68kCPU, env)
 142
 143 void m68k_cpu_do_interrupt(CPUState *cpu);
 144 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
 145 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 146                          int flags);
 147 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 148 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 149 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 150
 151 void m68k_tcg_init(void);
 152 void m68k_cpu_init_gdb(M68kCPU *cpu);
 153 M68kCPU *cpu_m68k_init(const char *cpu_model);
 154 /* you can call this signal handler from your SIGBUS and SIGSEGV
 155    signal handlers to inform the virtual CPU of exceptions. non zero
 156    is returned if the signal was handled by the virtual CPU.  */
 157 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 158                            void *puc);
 159 uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
 160 void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
 161
 162
 163 /* Instead of computing the condition codes after each m68k instruction,
 164  * QEMU just stores one operand (called CC_SRC), the result
 165  * (called CC_DEST) and the type of operation (called CC_OP). When the
 166  * condition codes are needed, the condition codes can be calculated
 167  * using this information. Condition codes are not generated if they
 168  * are only needed for conditional branches.
 169  */
 170 typedef enum {
 171     /* Translator only -- use env->cc_op.  */
 172     CC_OP_DYNAMIC = -1,
 173
 174     /* Each flag bit computed into cc_[xcnvz].  */
 175     CC_OP_FLAGS,
 176
 177     /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v.  */
 178     CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
 179     CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
 180
 181     /* X in cc_x, {N,Z,C,V} via cc_n/cc_v.  */
 182     CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
 183
 184     /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n.  */
 185     CC_OP_LOGIC,
 186
 187     CC_OP_NB
 188 } CCOp;
 189
 190 #define CCF_C 0x01
 191 #define CCF_V 0x02
 192 #define CCF_Z 0x04
 193 #define CCF_N 0x08
 194 #define CCF_X 0x10
 195
 196 #define SR_I_SHIFT 8
 197 #define SR_I  0x0700
 198 #define SR_M  0x1000
 199 #define SR_S  0x2000
 200 #define SR_T  0x8000
 201
 202 #define M68K_SSP    0
 203 #define M68K_USP    1
 204
 205 /* CACR fields are implementation defined, but some bits are common.  */
 206 #define M68K_CACR_EUSP  0x10
 207
 208 #define MACSR_PAV0  0x100
 209 #define MACSR_OMC   0x080
 210 #define MACSR_SU    0x040
 211 #define MACSR_FI    0x020
 212 #define MACSR_RT    0x010
 213 #define MACSR_N     0x008
 214 #define MACSR_Z     0x004
 215 #define MACSR_V     0x002
 216 #define MACSR_EV    0x001
 217
 218 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
 219 void m68k_switch_sp(CPUM68KState *env);
 220
 221 #define M68K_FPCR_PREC (1 << 6)
 222
 223 void do_m68k_semihosting(CPUM68KState *env, int nr);
 224
 225 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 226    Each feature covers the subset of instructions common to the
 227    ISA revisions mentioned.  */
 228
 229 enum m68k_features {
 230     M68K_FEATURE_M68000,
 231     M68K_FEATURE_CF_ISA_A,
 232     M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 233     M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 234     M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 235     M68K_FEATURE_CF_FPU,
 236     M68K_FEATURE_CF_MAC,
 237     M68K_FEATURE_CF_EMAC,
 238     M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 239     M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 240     M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 241     M68K_FEATURE_WORD_INDEX, /* word sized address index registers.  */
 242     M68K_FEATURE_SCALED_INDEX, /* scaled address index registers.  */
 243     M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
 244     M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
 245     M68K_FEATURE_BCCL, /* Long conditional branches.  */
 246     M68K_FEATURE_BITFIELD, /* Bit field insns.  */
 247     M68K_FEATURE_FPU,
 248     M68K_FEATURE_CAS,
 249     M68K_FEATURE_BKPT,
 250 };
 251
 252 static inline int m68k_feature(CPUM68KState *env, int feature)
 253 {
 254     return (env->features & (1u << feature)) != 0;
 255 }
 256
 257 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 258
 259 void register_m68k_insns (CPUM68KState *env);
 260
 261 #ifdef CONFIG_USER_ONLY
 262 /* Coldfire Linux uses 8k pages
 263  * and m68k linux uses 4k pages
 264  * use the smaller one
 265  */
 266 #define TARGET_PAGE_BITS 12
 267 #else
 268 /* Smallest TLB entry size is 1k.  */
 269 #define TARGET_PAGE_BITS 10
 270 #endif
 271
 272 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 273 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 274
 275 #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
 276
 277 #define cpu_signal_handler cpu_m68k_signal_handler
 278 #define cpu_list m68k_cpu_list
 279
 280 /* MMU modes definitions */
 281 #define MMU_MODE0_SUFFIX _kernel
 282 #define MMU_MODE1_SUFFIX _user
 283 #define MMU_USER_IDX 1
 284 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
 285 {
 286     return (env->sr & SR_S) == 0 ? 1 : 0;
 287 }
 288
 289 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 290                               int mmu_idx);
 291
 292 #include "exec/cpu-all.h"
 293
 294 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
 295                                         target_ulong *cs_base, uint32_t *flags)
 296 {
 297     *pc = env->pc;
 298     *cs_base = 0;
 299     *flags = (env->fpcr & M68K_FPCR_PREC)       /* Bit  6 */
 300             | (env->sr & SR_S)                  /* Bit  13 */
 301             | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
 302 }
 303
 304 #endif