2 * RISC-V Control and Status Registers.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "qemu/timer.h"
25 #include "time_helper.h"
26 #include "qemu/main-loop.h"
27 #include "exec/exec-all.h"
28 #include "exec/tb-flush.h"
29 #include "sysemu/cpu-timers.h"
30 #include "qemu/guest-random.h"
31 #include "qapi/error.h"
33 /* CSR function table public API */
34 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
)
36 *ops
= csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)];
39 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
)
41 csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)] = *ops
;
45 #if !defined(CONFIG_USER_ONLY)
46 static RISCVException
smstateen_acc_ok(CPURISCVState
*env
, int index
,
49 bool virt
= riscv_cpu_virt_enabled(env
);
51 if (env
->priv
== PRV_M
|| !riscv_cpu_cfg(env
)->ext_smstateen
) {
52 return RISCV_EXCP_NONE
;
55 if (!(env
->mstateen
[index
] & bit
)) {
56 return RISCV_EXCP_ILLEGAL_INST
;
60 if (!(env
->hstateen
[index
] & bit
)) {
61 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
64 if (env
->priv
== PRV_U
&& !(env
->sstateen
[index
] & bit
)) {
65 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
69 if (env
->priv
== PRV_U
&& riscv_has_ext(env
, RVS
)) {
70 if (!(env
->sstateen
[index
] & bit
)) {
71 return RISCV_EXCP_ILLEGAL_INST
;
75 return RISCV_EXCP_NONE
;
79 static RISCVException
fs(CPURISCVState
*env
, int csrno
)
81 #if !defined(CONFIG_USER_ONLY)
82 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
) &&
83 !riscv_cpu_cfg(env
)->ext_zfinx
) {
84 return RISCV_EXCP_ILLEGAL_INST
;
87 return RISCV_EXCP_NONE
;
90 static RISCVException
vs(CPURISCVState
*env
, int csrno
)
92 RISCVCPU
*cpu
= env_archcpu(env
);
94 if (cpu
->cfg
.ext_zve32f
) {
95 #if !defined(CONFIG_USER_ONLY)
96 if (!env
->debugger
&& !riscv_cpu_vector_enabled(env
)) {
97 return RISCV_EXCP_ILLEGAL_INST
;
100 return RISCV_EXCP_NONE
;
102 return RISCV_EXCP_ILLEGAL_INST
;
105 static RISCVException
ctr(CPURISCVState
*env
, int csrno
)
107 #if !defined(CONFIG_USER_ONLY)
108 RISCVCPU
*cpu
= env_archcpu(env
);
110 target_ulong ctr_mask
;
111 int base_csrno
= CSR_CYCLE
;
112 bool rv32
= riscv_cpu_mxl(env
) == MXL_RV32
? true : false;
114 if (rv32
&& csrno
>= CSR_CYCLEH
) {
115 /* Offset for RV32 hpmcounternh counters */
118 ctr_index
= csrno
- base_csrno
;
119 ctr_mask
= BIT(ctr_index
);
121 if ((csrno
>= CSR_CYCLE
&& csrno
<= CSR_INSTRET
) ||
122 (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_INSTRETH
)) {
123 goto skip_ext_pmu_check
;
126 if (!(cpu
->pmu_avail_ctrs
& ctr_mask
)) {
127 /* No counter is enabled in PMU or the counter is out of range */
128 return RISCV_EXCP_ILLEGAL_INST
;
134 return RISCV_EXCP_NONE
;
137 if (env
->priv
< PRV_M
&& !get_field(env
->mcounteren
, ctr_mask
)) {
138 return RISCV_EXCP_ILLEGAL_INST
;
141 if (riscv_cpu_virt_enabled(env
)) {
142 if (!get_field(env
->hcounteren
, ctr_mask
) ||
143 (env
->priv
== PRV_U
&& !get_field(env
->scounteren
, ctr_mask
))) {
144 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
148 if (riscv_has_ext(env
, RVS
) && env
->priv
== PRV_U
&&
149 !get_field(env
->scounteren
, ctr_mask
)) {
150 return RISCV_EXCP_ILLEGAL_INST
;
154 return RISCV_EXCP_NONE
;
157 static RISCVException
ctr32(CPURISCVState
*env
, int csrno
)
159 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
160 return RISCV_EXCP_ILLEGAL_INST
;
163 return ctr(env
, csrno
);
166 #if !defined(CONFIG_USER_ONLY)
167 static RISCVException
mctr(CPURISCVState
*env
, int csrno
)
169 int pmu_num
= riscv_cpu_cfg(env
)->pmu_num
;
171 int base_csrno
= CSR_MHPMCOUNTER3
;
173 if ((riscv_cpu_mxl(env
) == MXL_RV32
) && csrno
>= CSR_MCYCLEH
) {
174 /* Offset for RV32 mhpmcounternh counters */
177 ctr_index
= csrno
- base_csrno
;
178 if (!pmu_num
|| ctr_index
>= pmu_num
) {
179 /* The PMU is not enabled or counter is out of range*/
180 return RISCV_EXCP_ILLEGAL_INST
;
183 return RISCV_EXCP_NONE
;
186 static RISCVException
mctr32(CPURISCVState
*env
, int csrno
)
188 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
189 return RISCV_EXCP_ILLEGAL_INST
;
192 return mctr(env
, csrno
);
195 static RISCVException
sscofpmf(CPURISCVState
*env
, int csrno
)
197 RISCVCPU
*cpu
= env_archcpu(env
);
199 if (!cpu
->cfg
.ext_sscofpmf
) {
200 return RISCV_EXCP_ILLEGAL_INST
;
203 return RISCV_EXCP_NONE
;
206 static RISCVException
any(CPURISCVState
*env
, int csrno
)
208 return RISCV_EXCP_NONE
;
211 static RISCVException
any32(CPURISCVState
*env
, int csrno
)
213 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
214 return RISCV_EXCP_ILLEGAL_INST
;
217 return any(env
, csrno
);
221 static int aia_any(CPURISCVState
*env
, int csrno
)
223 if (!riscv_cpu_cfg(env
)->ext_smaia
) {
224 return RISCV_EXCP_ILLEGAL_INST
;
227 return any(env
, csrno
);
230 static int aia_any32(CPURISCVState
*env
, int csrno
)
232 if (!riscv_cpu_cfg(env
)->ext_smaia
) {
233 return RISCV_EXCP_ILLEGAL_INST
;
236 return any32(env
, csrno
);
239 static RISCVException
smode(CPURISCVState
*env
, int csrno
)
241 if (riscv_has_ext(env
, RVS
)) {
242 return RISCV_EXCP_NONE
;
245 return RISCV_EXCP_ILLEGAL_INST
;
248 static int smode32(CPURISCVState
*env
, int csrno
)
250 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
251 return RISCV_EXCP_ILLEGAL_INST
;
254 return smode(env
, csrno
);
257 static int aia_smode(CPURISCVState
*env
, int csrno
)
259 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
260 return RISCV_EXCP_ILLEGAL_INST
;
263 return smode(env
, csrno
);
266 static int aia_smode32(CPURISCVState
*env
, int csrno
)
268 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
269 return RISCV_EXCP_ILLEGAL_INST
;
272 return smode32(env
, csrno
);
275 static RISCVException
hmode(CPURISCVState
*env
, int csrno
)
277 if (riscv_has_ext(env
, RVH
)) {
278 return RISCV_EXCP_NONE
;
281 return RISCV_EXCP_ILLEGAL_INST
;
284 static RISCVException
hmode32(CPURISCVState
*env
, int csrno
)
286 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
287 return RISCV_EXCP_ILLEGAL_INST
;
290 return hmode(env
, csrno
);
294 static RISCVException
umode(CPURISCVState
*env
, int csrno
)
296 if (riscv_has_ext(env
, RVU
)) {
297 return RISCV_EXCP_NONE
;
300 return RISCV_EXCP_ILLEGAL_INST
;
303 static RISCVException
umode32(CPURISCVState
*env
, int csrno
)
305 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
306 return RISCV_EXCP_ILLEGAL_INST
;
309 return umode(env
, csrno
);
312 static RISCVException
mstateen(CPURISCVState
*env
, int csrno
)
314 RISCVCPU
*cpu
= env_archcpu(env
);
316 if (!cpu
->cfg
.ext_smstateen
) {
317 return RISCV_EXCP_ILLEGAL_INST
;
320 return any(env
, csrno
);
323 static RISCVException
hstateen_pred(CPURISCVState
*env
, int csrno
, int base
)
325 RISCVCPU
*cpu
= env_archcpu(env
);
327 if (!cpu
->cfg
.ext_smstateen
) {
328 return RISCV_EXCP_ILLEGAL_INST
;
331 RISCVException ret
= hmode(env
, csrno
);
332 if (ret
!= RISCV_EXCP_NONE
) {
337 return RISCV_EXCP_NONE
;
340 if (env
->priv
< PRV_M
) {
341 if (!(env
->mstateen
[csrno
- base
] & SMSTATEEN_STATEEN
)) {
342 return RISCV_EXCP_ILLEGAL_INST
;
346 return RISCV_EXCP_NONE
;
349 static RISCVException
hstateen(CPURISCVState
*env
, int csrno
)
351 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0
);
354 static RISCVException
hstateenh(CPURISCVState
*env
, int csrno
)
356 return hstateen_pred(env
, csrno
, CSR_HSTATEEN0H
);
359 static RISCVException
sstateen(CPURISCVState
*env
, int csrno
)
361 bool virt
= riscv_cpu_virt_enabled(env
);
362 int index
= csrno
- CSR_SSTATEEN0
;
364 if (!riscv_cpu_cfg(env
)->ext_smstateen
) {
365 return RISCV_EXCP_ILLEGAL_INST
;
368 RISCVException ret
= smode(env
, csrno
);
369 if (ret
!= RISCV_EXCP_NONE
) {
374 return RISCV_EXCP_NONE
;
377 if (env
->priv
< PRV_M
) {
378 if (!(env
->mstateen
[index
] & SMSTATEEN_STATEEN
)) {
379 return RISCV_EXCP_ILLEGAL_INST
;
383 if (!(env
->hstateen
[index
] & SMSTATEEN_STATEEN
)) {
384 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
389 return RISCV_EXCP_NONE
;
392 static RISCVException
sstc(CPURISCVState
*env
, int csrno
)
394 RISCVCPU
*cpu
= env_archcpu(env
);
395 bool hmode_check
= false;
397 if (!cpu
->cfg
.ext_sstc
|| !env
->rdtime_fn
) {
398 return RISCV_EXCP_ILLEGAL_INST
;
401 if ((csrno
== CSR_VSTIMECMP
) || (csrno
== CSR_VSTIMECMPH
)) {
405 RISCVException ret
= hmode_check
? hmode(env
, csrno
) : smode(env
, csrno
);
406 if (ret
!= RISCV_EXCP_NONE
) {
411 return RISCV_EXCP_NONE
;
414 if (env
->priv
== PRV_M
) {
415 return RISCV_EXCP_NONE
;
419 * No need of separate function for rv32 as menvcfg stores both menvcfg
422 if (!(get_field(env
->mcounteren
, COUNTEREN_TM
) &&
423 get_field(env
->menvcfg
, MENVCFG_STCE
))) {
424 return RISCV_EXCP_ILLEGAL_INST
;
427 if (riscv_cpu_virt_enabled(env
)) {
428 if (!(get_field(env
->hcounteren
, COUNTEREN_TM
) &&
429 get_field(env
->henvcfg
, HENVCFG_STCE
))) {
430 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
434 return RISCV_EXCP_NONE
;
437 static RISCVException
sstc_32(CPURISCVState
*env
, int csrno
)
439 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
440 return RISCV_EXCP_ILLEGAL_INST
;
443 return sstc(env
, csrno
);
446 /* Checks if PointerMasking registers could be accessed */
447 static RISCVException
pointer_masking(CPURISCVState
*env
, int csrno
)
449 /* Check if j-ext is present */
450 if (riscv_has_ext(env
, RVJ
)) {
451 return RISCV_EXCP_NONE
;
453 return RISCV_EXCP_ILLEGAL_INST
;
456 static int aia_hmode(CPURISCVState
*env
, int csrno
)
458 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
459 return RISCV_EXCP_ILLEGAL_INST
;
462 return hmode(env
, csrno
);
465 static int aia_hmode32(CPURISCVState
*env
, int csrno
)
467 if (!riscv_cpu_cfg(env
)->ext_ssaia
) {
468 return RISCV_EXCP_ILLEGAL_INST
;
471 return hmode32(env
, csrno
);
474 static RISCVException
pmp(CPURISCVState
*env
, int csrno
)
476 if (riscv_cpu_cfg(env
)->pmp
) {
477 if (csrno
<= CSR_PMPCFG3
) {
478 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
480 /* TODO: RV128 restriction check */
481 if ((reg_index
& 1) && (riscv_cpu_mxl(env
) == MXL_RV64
)) {
482 return RISCV_EXCP_ILLEGAL_INST
;
486 return RISCV_EXCP_NONE
;
489 return RISCV_EXCP_ILLEGAL_INST
;
492 static RISCVException
epmp(CPURISCVState
*env
, int csrno
)
494 if (riscv_cpu_cfg(env
)->epmp
) {
495 return RISCV_EXCP_NONE
;
498 return RISCV_EXCP_ILLEGAL_INST
;
501 static RISCVException
debug(CPURISCVState
*env
, int csrno
)
503 if (riscv_cpu_cfg(env
)->debug
) {
504 return RISCV_EXCP_NONE
;
507 return RISCV_EXCP_ILLEGAL_INST
;
511 static RISCVException
seed(CPURISCVState
*env
, int csrno
)
513 if (!riscv_cpu_cfg(env
)->ext_zkr
) {
514 return RISCV_EXCP_ILLEGAL_INST
;
517 #if !defined(CONFIG_USER_ONLY)
519 return RISCV_EXCP_NONE
;
523 * With a CSR read-write instruction:
524 * 1) The seed CSR is always available in machine mode as normal.
525 * 2) Attempted access to seed from virtual modes VS and VU always raises
526 * an exception(virtual instruction exception only if mseccfg.sseed=1).
527 * 3) Without the corresponding access control bit set to 1, any attempted
528 * access to seed from U, S or HS modes will raise an illegal instruction
531 if (env
->priv
== PRV_M
) {
532 return RISCV_EXCP_NONE
;
533 } else if (riscv_cpu_virt_enabled(env
)) {
534 if (env
->mseccfg
& MSECCFG_SSEED
) {
535 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
537 return RISCV_EXCP_ILLEGAL_INST
;
540 if (env
->priv
== PRV_S
&& (env
->mseccfg
& MSECCFG_SSEED
)) {
541 return RISCV_EXCP_NONE
;
542 } else if (env
->priv
== PRV_U
&& (env
->mseccfg
& MSECCFG_USEED
)) {
543 return RISCV_EXCP_NONE
;
545 return RISCV_EXCP_ILLEGAL_INST
;
549 return RISCV_EXCP_NONE
;
553 /* User Floating-Point CSRs */
554 static RISCVException
read_fflags(CPURISCVState
*env
, int csrno
,
557 *val
= riscv_cpu_get_fflags(env
);
558 return RISCV_EXCP_NONE
;
561 static RISCVException
write_fflags(CPURISCVState
*env
, int csrno
,
564 #if !defined(CONFIG_USER_ONLY)
565 if (riscv_has_ext(env
, RVF
)) {
566 env
->mstatus
|= MSTATUS_FS
;
569 riscv_cpu_set_fflags(env
, val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
));
570 return RISCV_EXCP_NONE
;
573 static RISCVException
read_frm(CPURISCVState
*env
, int csrno
,
577 return RISCV_EXCP_NONE
;
580 static RISCVException
write_frm(CPURISCVState
*env
, int csrno
,
583 #if !defined(CONFIG_USER_ONLY)
584 if (riscv_has_ext(env
, RVF
)) {
585 env
->mstatus
|= MSTATUS_FS
;
588 env
->frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
589 return RISCV_EXCP_NONE
;
592 static RISCVException
read_fcsr(CPURISCVState
*env
, int csrno
,
595 *val
= (riscv_cpu_get_fflags(env
) << FSR_AEXC_SHIFT
)
596 | (env
->frm
<< FSR_RD_SHIFT
);
597 return RISCV_EXCP_NONE
;
600 static RISCVException
write_fcsr(CPURISCVState
*env
, int csrno
,
603 #if !defined(CONFIG_USER_ONLY)
604 if (riscv_has_ext(env
, RVF
)) {
605 env
->mstatus
|= MSTATUS_FS
;
608 env
->frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
609 riscv_cpu_set_fflags(env
, (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
);
610 return RISCV_EXCP_NONE
;
613 static RISCVException
read_vtype(CPURISCVState
*env
, int csrno
,
619 vill
= (uint32_t)env
->vill
<< 31;
622 vill
= (uint64_t)env
->vill
<< 63;
625 g_assert_not_reached();
627 *val
= (target_ulong
)vill
| env
->vtype
;
628 return RISCV_EXCP_NONE
;
631 static RISCVException
read_vl(CPURISCVState
*env
, int csrno
,
635 return RISCV_EXCP_NONE
;
638 static int read_vlenb(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
640 *val
= riscv_cpu_cfg(env
)->vlen
>> 3;
641 return RISCV_EXCP_NONE
;
644 static RISCVException
read_vxrm(CPURISCVState
*env
, int csrno
,
648 return RISCV_EXCP_NONE
;
651 static RISCVException
write_vxrm(CPURISCVState
*env
, int csrno
,
654 #if !defined(CONFIG_USER_ONLY)
655 env
->mstatus
|= MSTATUS_VS
;
658 return RISCV_EXCP_NONE
;
661 static RISCVException
read_vxsat(CPURISCVState
*env
, int csrno
,
665 return RISCV_EXCP_NONE
;
668 static RISCVException
write_vxsat(CPURISCVState
*env
, int csrno
,
671 #if !defined(CONFIG_USER_ONLY)
672 env
->mstatus
|= MSTATUS_VS
;
675 return RISCV_EXCP_NONE
;
678 static RISCVException
read_vstart(CPURISCVState
*env
, int csrno
,
682 return RISCV_EXCP_NONE
;
685 static RISCVException
write_vstart(CPURISCVState
*env
, int csrno
,
688 #if !defined(CONFIG_USER_ONLY)
689 env
->mstatus
|= MSTATUS_VS
;
692 * The vstart CSR is defined to have only enough writable bits
693 * to hold the largest element index, i.e. lg2(VLEN) bits.
695 env
->vstart
= val
& ~(~0ULL << ctzl(riscv_cpu_cfg(env
)->vlen
));
696 return RISCV_EXCP_NONE
;
699 static int read_vcsr(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
701 *val
= (env
->vxrm
<< VCSR_VXRM_SHIFT
) | (env
->vxsat
<< VCSR_VXSAT_SHIFT
);
702 return RISCV_EXCP_NONE
;
705 static int write_vcsr(CPURISCVState
*env
, int csrno
, target_ulong val
)
707 #if !defined(CONFIG_USER_ONLY)
708 env
->mstatus
|= MSTATUS_VS
;
710 env
->vxrm
= (val
& VCSR_VXRM
) >> VCSR_VXRM_SHIFT
;
711 env
->vxsat
= (val
& VCSR_VXSAT
) >> VCSR_VXSAT_SHIFT
;
712 return RISCV_EXCP_NONE
;
715 /* User Timers and Counters */
716 static target_ulong
get_ticks(bool shift
)
721 #if !defined(CONFIG_USER_ONLY)
722 if (icount_enabled()) {
725 val
= cpu_get_host_ticks();
728 val
= cpu_get_host_ticks();
740 #if defined(CONFIG_USER_ONLY)
741 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
744 *val
= cpu_get_host_ticks();
745 return RISCV_EXCP_NONE
;
748 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
751 *val
= cpu_get_host_ticks() >> 32;
752 return RISCV_EXCP_NONE
;
755 static int read_hpmcounter(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
757 *val
= get_ticks(false);
758 return RISCV_EXCP_NONE
;
761 static int read_hpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
763 *val
= get_ticks(true);
764 return RISCV_EXCP_NONE
;
767 #else /* CONFIG_USER_ONLY */
769 static int read_mhpmevent(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
771 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
773 *val
= env
->mhpmevent_val
[evt_index
];
775 return RISCV_EXCP_NONE
;
778 static int write_mhpmevent(CPURISCVState
*env
, int csrno
, target_ulong val
)
780 int evt_index
= csrno
- CSR_MCOUNTINHIBIT
;
781 uint64_t mhpmevt_val
= val
;
783 env
->mhpmevent_val
[evt_index
] = val
;
785 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
786 mhpmevt_val
= mhpmevt_val
|
787 ((uint64_t)env
->mhpmeventh_val
[evt_index
] << 32);
789 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
791 return RISCV_EXCP_NONE
;
794 static int read_mhpmeventh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
796 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
798 *val
= env
->mhpmeventh_val
[evt_index
];
800 return RISCV_EXCP_NONE
;
803 static int write_mhpmeventh(CPURISCVState
*env
, int csrno
, target_ulong val
)
805 int evt_index
= csrno
- CSR_MHPMEVENT3H
+ 3;
806 uint64_t mhpmevth_val
= val
;
807 uint64_t mhpmevt_val
= env
->mhpmevent_val
[evt_index
];
809 mhpmevt_val
= mhpmevt_val
| (mhpmevth_val
<< 32);
810 env
->mhpmeventh_val
[evt_index
] = val
;
812 riscv_pmu_update_event_map(env
, mhpmevt_val
, evt_index
);
814 return RISCV_EXCP_NONE
;
817 static int write_mhpmcounter(CPURISCVState
*env
, int csrno
, target_ulong val
)
819 int ctr_idx
= csrno
- CSR_MCYCLE
;
820 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
821 uint64_t mhpmctr_val
= val
;
823 counter
->mhpmcounter_val
= val
;
824 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
825 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
826 counter
->mhpmcounter_prev
= get_ticks(false);
828 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
829 mhpmctr_val
= mhpmctr_val
|
830 ((uint64_t)counter
->mhpmcounterh_val
<< 32);
832 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
835 /* Other counters can keep incrementing from the given value */
836 counter
->mhpmcounter_prev
= val
;
839 return RISCV_EXCP_NONE
;
842 static int write_mhpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong val
)
844 int ctr_idx
= csrno
- CSR_MCYCLEH
;
845 PMUCTRState
*counter
= &env
->pmu_ctrs
[ctr_idx
];
846 uint64_t mhpmctr_val
= counter
->mhpmcounter_val
;
847 uint64_t mhpmctrh_val
= val
;
849 counter
->mhpmcounterh_val
= val
;
850 mhpmctr_val
= mhpmctr_val
| (mhpmctrh_val
<< 32);
851 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
852 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
853 counter
->mhpmcounterh_prev
= get_ticks(true);
855 riscv_pmu_setup_timer(env
, mhpmctr_val
, ctr_idx
);
858 counter
->mhpmcounterh_prev
= val
;
861 return RISCV_EXCP_NONE
;
864 static RISCVException
riscv_pmu_read_ctr(CPURISCVState
*env
, target_ulong
*val
,
865 bool upper_half
, uint32_t ctr_idx
)
867 PMUCTRState counter
= env
->pmu_ctrs
[ctr_idx
];
868 target_ulong ctr_prev
= upper_half
? counter
.mhpmcounterh_prev
:
869 counter
.mhpmcounter_prev
;
870 target_ulong ctr_val
= upper_half
? counter
.mhpmcounterh_val
:
871 counter
.mhpmcounter_val
;
873 if (get_field(env
->mcountinhibit
, BIT(ctr_idx
))) {
875 * Counter should not increment if inhibit bit is set. We can't really
876 * stop the icount counting. Just return the counter value written by
877 * the supervisor to indicate that counter was not incremented.
879 if (!counter
.started
) {
881 return RISCV_EXCP_NONE
;
883 /* Mark that the counter has been stopped */
884 counter
.started
= false;
889 * The kernel computes the perf delta by subtracting the current value from
890 * the value it initialized previously (ctr_val).
892 if (riscv_pmu_ctr_monitor_cycles(env
, ctr_idx
) ||
893 riscv_pmu_ctr_monitor_instructions(env
, ctr_idx
)) {
894 *val
= get_ticks(upper_half
) - ctr_prev
+ ctr_val
;
899 return RISCV_EXCP_NONE
;
902 static int read_hpmcounter(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
906 if (csrno
>= CSR_MCYCLE
&& csrno
<= CSR_MHPMCOUNTER31
) {
907 ctr_index
= csrno
- CSR_MCYCLE
;
908 } else if (csrno
>= CSR_CYCLE
&& csrno
<= CSR_HPMCOUNTER31
) {
909 ctr_index
= csrno
- CSR_CYCLE
;
911 return RISCV_EXCP_ILLEGAL_INST
;
914 return riscv_pmu_read_ctr(env
, val
, false, ctr_index
);
917 static int read_hpmcounterh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
921 if (csrno
>= CSR_MCYCLEH
&& csrno
<= CSR_MHPMCOUNTER31H
) {
922 ctr_index
= csrno
- CSR_MCYCLEH
;
923 } else if (csrno
>= CSR_CYCLEH
&& csrno
<= CSR_HPMCOUNTER31H
) {
924 ctr_index
= csrno
- CSR_CYCLEH
;
926 return RISCV_EXCP_ILLEGAL_INST
;
929 return riscv_pmu_read_ctr(env
, val
, true, ctr_index
);
932 static int read_scountovf(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
934 int mhpmevt_start
= CSR_MHPMEVENT3
- CSR_MCOUNTINHIBIT
;
937 target_ulong
*mhpm_evt_val
;
938 uint64_t of_bit_mask
;
940 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
941 mhpm_evt_val
= env
->mhpmeventh_val
;
942 of_bit_mask
= MHPMEVENTH_BIT_OF
;
944 mhpm_evt_val
= env
->mhpmevent_val
;
945 of_bit_mask
= MHPMEVENT_BIT_OF
;
948 for (i
= mhpmevt_start
; i
< RV_MAX_MHPMEVENTS
; i
++) {
949 if ((get_field(env
->mcounteren
, BIT(i
))) &&
950 (mhpm_evt_val
[i
] & of_bit_mask
)) {
955 return RISCV_EXCP_NONE
;
958 static RISCVException
read_time(CPURISCVState
*env
, int csrno
,
961 uint64_t delta
= riscv_cpu_virt_enabled(env
) ? env
->htimedelta
: 0;
963 if (!env
->rdtime_fn
) {
964 return RISCV_EXCP_ILLEGAL_INST
;
967 *val
= env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
;
968 return RISCV_EXCP_NONE
;
971 static RISCVException
read_timeh(CPURISCVState
*env
, int csrno
,
974 uint64_t delta
= riscv_cpu_virt_enabled(env
) ? env
->htimedelta
: 0;
976 if (!env
->rdtime_fn
) {
977 return RISCV_EXCP_ILLEGAL_INST
;
980 *val
= (env
->rdtime_fn(env
->rdtime_fn_arg
) + delta
) >> 32;
981 return RISCV_EXCP_NONE
;
984 static RISCVException
read_vstimecmp(CPURISCVState
*env
, int csrno
,
987 *val
= env
->vstimecmp
;
989 return RISCV_EXCP_NONE
;
992 static RISCVException
read_vstimecmph(CPURISCVState
*env
, int csrno
,
995 *val
= env
->vstimecmp
>> 32;
997 return RISCV_EXCP_NONE
;
1000 static RISCVException
write_vstimecmp(CPURISCVState
*env
, int csrno
,
1003 RISCVCPU
*cpu
= env_archcpu(env
);
1005 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1006 env
->vstimecmp
= deposit64(env
->vstimecmp
, 0, 32, (uint64_t)val
);
1008 env
->vstimecmp
= val
;
1011 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
1012 env
->htimedelta
, MIP_VSTIP
);
1014 return RISCV_EXCP_NONE
;
1017 static RISCVException
write_vstimecmph(CPURISCVState
*env
, int csrno
,
1020 RISCVCPU
*cpu
= env_archcpu(env
);
1022 env
->vstimecmp
= deposit64(env
->vstimecmp
, 32, 32, (uint64_t)val
);
1023 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
1024 env
->htimedelta
, MIP_VSTIP
);
1026 return RISCV_EXCP_NONE
;
1029 static RISCVException
read_stimecmp(CPURISCVState
*env
, int csrno
,
1032 if (riscv_cpu_virt_enabled(env
)) {
1033 *val
= env
->vstimecmp
;
1035 *val
= env
->stimecmp
;
1038 return RISCV_EXCP_NONE
;
1041 static RISCVException
read_stimecmph(CPURISCVState
*env
, int csrno
,
1044 if (riscv_cpu_virt_enabled(env
)) {
1045 *val
= env
->vstimecmp
>> 32;
1047 *val
= env
->stimecmp
>> 32;
1050 return RISCV_EXCP_NONE
;
1053 static RISCVException
write_stimecmp(CPURISCVState
*env
, int csrno
,
1056 RISCVCPU
*cpu
= env_archcpu(env
);
1058 if (riscv_cpu_virt_enabled(env
)) {
1059 if (env
->hvictl
& HVICTL_VTI
) {
1060 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1062 return write_vstimecmp(env
, csrno
, val
);
1065 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
1066 env
->stimecmp
= deposit64(env
->stimecmp
, 0, 32, (uint64_t)val
);
1068 env
->stimecmp
= val
;
1071 riscv_timer_write_timecmp(cpu
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1073 return RISCV_EXCP_NONE
;
1076 static RISCVException
write_stimecmph(CPURISCVState
*env
, int csrno
,
1079 RISCVCPU
*cpu
= env_archcpu(env
);
1081 if (riscv_cpu_virt_enabled(env
)) {
1082 if (env
->hvictl
& HVICTL_VTI
) {
1083 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
1085 return write_vstimecmph(env
, csrno
, val
);
1088 env
->stimecmp
= deposit64(env
->stimecmp
, 32, 32, (uint64_t)val
);
1089 riscv_timer_write_timecmp(cpu
, env
->stimer
, env
->stimecmp
, 0, MIP_STIP
);
1091 return RISCV_EXCP_NONE
;
1094 /* Machine constants */
1096 #define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP))
1097 #define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \
1099 #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
1100 #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
1102 #define VSTOPI_NUM_SRCS 5
1104 static const uint64_t delegable_ints
= S_MODE_INTERRUPTS
|
1106 static const uint64_t vs_delegable_ints
= VS_MODE_INTERRUPTS
;
1107 static const uint64_t all_ints
= M_MODE_INTERRUPTS
| S_MODE_INTERRUPTS
|
1109 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
1110 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
1111 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
1112 (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
1113 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
1114 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
1115 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
1116 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
1117 (1ULL << (RISCV_EXCP_U_ECALL)) | \
1118 (1ULL << (RISCV_EXCP_S_ECALL)) | \
1119 (1ULL << (RISCV_EXCP_VS_ECALL)) | \
1120 (1ULL << (RISCV_EXCP_M_ECALL)) | \
1121 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
1122 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
1123 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
1124 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
1125 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
1126 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
1127 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
1128 static const target_ulong vs_delegable_excps
= DELEGABLE_EXCPS
&
1129 ~((1ULL << (RISCV_EXCP_S_ECALL
)) |
1130 (1ULL << (RISCV_EXCP_VS_ECALL
)) |
1131 (1ULL << (RISCV_EXCP_M_ECALL
)) |
1132 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT
)) |
1133 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
)) |
1134 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT
)) |
1135 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
)));
1136 static const target_ulong sstatus_v1_10_mask
= SSTATUS_SIE
| SSTATUS_SPIE
|
1137 SSTATUS_UIE
| SSTATUS_UPIE
| SSTATUS_SPP
| SSTATUS_FS
| SSTATUS_XS
|
1138 SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_VS
;
1139 static const target_ulong sip_writable_mask
= SIP_SSIP
| MIP_USIP
| MIP_UEIP
|
1141 static const target_ulong hip_writable_mask
= MIP_VSSIP
;
1142 static const target_ulong hvip_writable_mask
= MIP_VSSIP
| MIP_VSTIP
| MIP_VSEIP
;
1143 static const target_ulong vsip_writable_mask
= MIP_VSSIP
;
1145 const bool valid_vm_1_10_32
[16] = {
1146 [VM_1_10_MBARE
] = true,
1147 [VM_1_10_SV32
] = true
1150 const bool valid_vm_1_10_64
[16] = {
1151 [VM_1_10_MBARE
] = true,
1152 [VM_1_10_SV39
] = true,
1153 [VM_1_10_SV48
] = true,
1154 [VM_1_10_SV57
] = true
1157 /* Machine Information Registers */
1158 static RISCVException
read_zero(CPURISCVState
*env
, int csrno
,
1162 return RISCV_EXCP_NONE
;
1165 static RISCVException
write_ignore(CPURISCVState
*env
, int csrno
,
1168 return RISCV_EXCP_NONE
;
1171 static RISCVException
read_mvendorid(CPURISCVState
*env
, int csrno
,
1174 RISCVCPU
*cpu
= env_archcpu(env
);
1176 *val
= cpu
->cfg
.mvendorid
;
1177 return RISCV_EXCP_NONE
;
1180 static RISCVException
read_marchid(CPURISCVState
*env
, int csrno
,
1183 RISCVCPU
*cpu
= env_archcpu(env
);
1185 *val
= cpu
->cfg
.marchid
;
1186 return RISCV_EXCP_NONE
;
1189 static RISCVException
read_mimpid(CPURISCVState
*env
, int csrno
,
1192 RISCVCPU
*cpu
= env_archcpu(env
);
1194 *val
= cpu
->cfg
.mimpid
;
1195 return RISCV_EXCP_NONE
;
1198 static RISCVException
read_mhartid(CPURISCVState
*env
, int csrno
,
1201 *val
= env
->mhartid
;
1202 return RISCV_EXCP_NONE
;
1205 /* Machine Trap Setup */
1207 /* We do not store SD explicitly, only compute it on demand. */
1208 static uint64_t add_status_sd(RISCVMXL xl
, uint64_t status
)
1210 if ((status
& MSTATUS_FS
) == MSTATUS_FS
||
1211 (status
& MSTATUS_VS
) == MSTATUS_VS
||
1212 (status
& MSTATUS_XS
) == MSTATUS_XS
) {
1215 return status
| MSTATUS32_SD
;
1217 return status
| MSTATUS64_SD
;
1219 return MSTATUSH128_SD
;
1221 g_assert_not_reached();
1227 static RISCVException
read_mstatus(CPURISCVState
*env
, int csrno
,
1230 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
);
1231 return RISCV_EXCP_NONE
;
1234 static bool validate_vm(CPURISCVState
*env
, target_ulong vm
)
1236 RISCVCPU
*cpu
= RISCV_CPU(env_cpu(env
));
1238 return (vm
& 0xf) <= satp_mode_max_from_map(cpu
->cfg
.satp_mode
.map
);
1241 static RISCVException
write_mstatus(CPURISCVState
*env
, int csrno
,
1244 uint64_t mstatus
= env
->mstatus
;
1246 RISCVMXL xl
= riscv_cpu_mxl(env
);
1248 /* flush tlb on mstatus fields that affect VM */
1249 if ((val
^ mstatus
) & (MSTATUS_MXR
| MSTATUS_MPP
| MSTATUS_MPV
|
1250 MSTATUS_MPRV
| MSTATUS_SUM
)) {
1251 tlb_flush(env_cpu(env
));
1253 mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
|
1254 MSTATUS_SPP
| MSTATUS_MPRV
| MSTATUS_SUM
|
1255 MSTATUS_MPP
| MSTATUS_MXR
| MSTATUS_TVM
| MSTATUS_TSR
|
1256 MSTATUS_TW
| MSTATUS_VS
;
1258 if (riscv_has_ext(env
, RVF
)) {
1262 if (xl
!= MXL_RV32
|| env
->debugger
) {
1264 * RV32: MPV and GVA are not in mstatus. The current plan is to
1265 * add them to mstatush. For now, we just don't support it.
1267 mask
|= MSTATUS_MPV
| MSTATUS_GVA
;
1268 if ((val
& MSTATUS64_UXL
) != 0) {
1269 mask
|= MSTATUS64_UXL
;
1273 mstatus
= (mstatus
& ~mask
) | (val
& mask
);
1275 if (xl
> MXL_RV32
) {
1276 /* SXL field is for now read only */
1277 mstatus
= set_field(mstatus
, MSTATUS64_SXL
, xl
);
1279 env
->mstatus
= mstatus
;
1280 env
->xl
= cpu_recompute_xl(env
);
1282 return RISCV_EXCP_NONE
;
1285 static RISCVException
read_mstatush(CPURISCVState
*env
, int csrno
,
1288 *val
= env
->mstatus
>> 32;
1289 return RISCV_EXCP_NONE
;
1292 static RISCVException
write_mstatush(CPURISCVState
*env
, int csrno
,
1295 uint64_t valh
= (uint64_t)val
<< 32;
1296 uint64_t mask
= MSTATUS_MPV
| MSTATUS_GVA
;
1298 if ((valh
^ env
->mstatus
) & (MSTATUS_MPV
)) {
1299 tlb_flush(env_cpu(env
));
1302 env
->mstatus
= (env
->mstatus
& ~mask
) | (valh
& mask
);
1304 return RISCV_EXCP_NONE
;
1307 static RISCVException
read_mstatus_i128(CPURISCVState
*env
, int csrno
,
1310 *val
= int128_make128(env
->mstatus
, add_status_sd(MXL_RV128
, env
->mstatus
));
1311 return RISCV_EXCP_NONE
;
1314 static RISCVException
read_misa_i128(CPURISCVState
*env
, int csrno
,
1317 *val
= int128_make128(env
->misa_ext
, (uint64_t)MXL_RV128
<< 62);
1318 return RISCV_EXCP_NONE
;
1321 static RISCVException
read_misa(CPURISCVState
*env
, int csrno
,
1326 switch (env
->misa_mxl
) {
1328 misa
= (target_ulong
)MXL_RV32
<< 30;
1330 #ifdef TARGET_RISCV64
1332 misa
= (target_ulong
)MXL_RV64
<< 62;
1336 g_assert_not_reached();
1339 *val
= misa
| env
->misa_ext
;
1340 return RISCV_EXCP_NONE
;
1343 static RISCVException
write_misa(CPURISCVState
*env
, int csrno
,
1346 if (!riscv_cpu_cfg(env
)->misa_w
) {
1347 /* drop write to misa */
1348 return RISCV_EXCP_NONE
;
1351 /* 'I' or 'E' must be present */
1352 if (!(val
& (RVI
| RVE
))) {
1353 /* It is not, drop write to misa */
1354 return RISCV_EXCP_NONE
;
1357 /* 'E' excludes all other extensions */
1360 * when we support 'E' we can do "val = RVE;" however
1361 * for now we just drop writes if 'E' is present.
1363 return RISCV_EXCP_NONE
;
1367 * misa.MXL writes are not supported by QEMU.
1368 * Drop writes to those bits.
1371 /* Mask extensions that are not supported by this hart */
1372 val
&= env
->misa_ext_mask
;
1374 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
1375 if ((val
& RVD
) && !(val
& RVF
)) {
1380 * Suppress 'C' if next instruction is not aligned
1381 * TODO: this should check next_pc
1383 if ((val
& RVC
) && (GETPC() & ~3) != 0) {
1387 /* If nothing changed, do nothing. */
1388 if (val
== env
->misa_ext
) {
1389 return RISCV_EXCP_NONE
;
1393 env
->mstatus
&= ~MSTATUS_FS
;
1396 /* flush translation cache */
1397 tb_flush(env_cpu(env
));
1398 env
->misa_ext
= val
;
1399 env
->xl
= riscv_cpu_mxl(env
);
1400 return RISCV_EXCP_NONE
;
1403 static RISCVException
read_medeleg(CPURISCVState
*env
, int csrno
,
1406 *val
= env
->medeleg
;
1407 return RISCV_EXCP_NONE
;
1410 static RISCVException
write_medeleg(CPURISCVState
*env
, int csrno
,
1413 env
->medeleg
= (env
->medeleg
& ~DELEGABLE_EXCPS
) | (val
& DELEGABLE_EXCPS
);
1414 return RISCV_EXCP_NONE
;
1417 static RISCVException
rmw_mideleg64(CPURISCVState
*env
, int csrno
,
1419 uint64_t new_val
, uint64_t wr_mask
)
1421 uint64_t mask
= wr_mask
& delegable_ints
;
1424 *ret_val
= env
->mideleg
;
1427 env
->mideleg
= (env
->mideleg
& ~mask
) | (new_val
& mask
);
1429 if (riscv_has_ext(env
, RVH
)) {
1430 env
->mideleg
|= HS_MODE_INTERRUPTS
;
1433 return RISCV_EXCP_NONE
;
1436 static RISCVException
rmw_mideleg(CPURISCVState
*env
, int csrno
,
1437 target_ulong
*ret_val
,
1438 target_ulong new_val
, target_ulong wr_mask
)
1443 ret
= rmw_mideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
1451 static RISCVException
rmw_midelegh(CPURISCVState
*env
, int csrno
,
1452 target_ulong
*ret_val
,
1453 target_ulong new_val
,
1454 target_ulong wr_mask
)
1459 ret
= rmw_mideleg64(env
, csrno
, &rval
,
1460 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1462 *ret_val
= rval
>> 32;
1468 static RISCVException
rmw_mie64(CPURISCVState
*env
, int csrno
,
1470 uint64_t new_val
, uint64_t wr_mask
)
1472 uint64_t mask
= wr_mask
& all_ints
;
1475 *ret_val
= env
->mie
;
1478 env
->mie
= (env
->mie
& ~mask
) | (new_val
& mask
);
1480 if (!riscv_has_ext(env
, RVH
)) {
1481 env
->mie
&= ~((uint64_t)MIP_SGEIP
);
1484 return RISCV_EXCP_NONE
;
1487 static RISCVException
rmw_mie(CPURISCVState
*env
, int csrno
,
1488 target_ulong
*ret_val
,
1489 target_ulong new_val
, target_ulong wr_mask
)
1494 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
);
1502 static RISCVException
rmw_mieh(CPURISCVState
*env
, int csrno
,
1503 target_ulong
*ret_val
,
1504 target_ulong new_val
, target_ulong wr_mask
)
1509 ret
= rmw_mie64(env
, csrno
, &rval
,
1510 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
1512 *ret_val
= rval
>> 32;
1518 static int read_mtopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1523 irq
= riscv_cpu_mirq_pending(env
);
1524 if (irq
<= 0 || irq
> 63) {
1527 iprio
= env
->miprio
[irq
];
1529 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_M
) {
1530 iprio
= IPRIO_MMAXIPRIO
;
1533 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
1537 return RISCV_EXCP_NONE
;
1540 static int aia_xlate_vs_csrno(CPURISCVState
*env
, int csrno
)
1542 if (!riscv_cpu_virt_enabled(env
)) {
1548 return CSR_VSISELECT
;
1558 static int rmw_xiselect(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1559 target_ulong new_val
, target_ulong wr_mask
)
1561 target_ulong
*iselect
;
1563 /* Translate CSR number for VS-mode */
1564 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1566 /* Find the iselect CSR based on CSR number */
1569 iselect
= &env
->miselect
;
1572 iselect
= &env
->siselect
;
1575 iselect
= &env
->vsiselect
;
1578 return RISCV_EXCP_ILLEGAL_INST
;
1585 wr_mask
&= ISELECT_MASK
;
1587 *iselect
= (*iselect
& ~wr_mask
) | (new_val
& wr_mask
);
1590 return RISCV_EXCP_NONE
;
1593 static int rmw_iprio(target_ulong xlen
,
1594 target_ulong iselect
, uint8_t *iprio
,
1595 target_ulong
*val
, target_ulong new_val
,
1596 target_ulong wr_mask
, int ext_irq_no
)
1599 target_ulong old_val
;
1601 if (iselect
< ISELECT_IPRIO0
|| ISELECT_IPRIO15
< iselect
) {
1604 if (xlen
!= 32 && iselect
& 0x1) {
1608 nirqs
= 4 * (xlen
/ 32);
1609 firq
= ((iselect
- ISELECT_IPRIO0
) / (xlen
/ 32)) * (nirqs
);
1612 for (i
= 0; i
< nirqs
; i
++) {
1613 old_val
|= ((target_ulong
)iprio
[firq
+ i
]) << (IPRIO_IRQ_BITS
* i
);
1621 new_val
= (old_val
& ~wr_mask
) | (new_val
& wr_mask
);
1622 for (i
= 0; i
< nirqs
; i
++) {
1624 * M-level and S-level external IRQ priority always read-only
1625 * zero. This means default priority order is always preferred
1626 * for M-level and S-level external IRQs.
1628 if ((firq
+ i
) == ext_irq_no
) {
1631 iprio
[firq
+ i
] = (new_val
>> (IPRIO_IRQ_BITS
* i
)) & 0xff;
1638 static int rmw_xireg(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1639 target_ulong new_val
, target_ulong wr_mask
)
1644 target_ulong priv
, isel
, vgein
;
1646 /* Translate CSR number for VS-mode */
1647 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1649 /* Decode register details from CSR number */
1653 iprio
= env
->miprio
;
1654 isel
= env
->miselect
;
1658 iprio
= env
->siprio
;
1659 isel
= env
->siselect
;
1663 iprio
= env
->hviprio
;
1664 isel
= env
->vsiselect
;
1672 /* Find the selected guest interrupt file */
1673 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1675 if (ISELECT_IPRIO0
<= isel
&& isel
<= ISELECT_IPRIO15
) {
1676 /* Local interrupt priority registers not available for VS-mode */
1678 ret
= rmw_iprio(riscv_cpu_mxl_bits(env
),
1679 isel
, iprio
, val
, new_val
, wr_mask
,
1680 (priv
== PRV_M
) ? IRQ_M_EXT
: IRQ_S_EXT
);
1682 } else if (ISELECT_IMSIC_FIRST
<= isel
&& isel
<= ISELECT_IMSIC_LAST
) {
1683 /* IMSIC registers only available when machine implements it. */
1684 if (env
->aia_ireg_rmw_fn
[priv
]) {
1685 /* Selected guest interrupt file should not be zero */
1686 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1689 /* Call machine specific IMSIC register emulation */
1690 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1691 AIA_MAKE_IREG(isel
, priv
, virt
, vgein
,
1692 riscv_cpu_mxl_bits(env
)),
1693 val
, new_val
, wr_mask
);
1699 return (riscv_cpu_virt_enabled(env
) && virt
) ?
1700 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1702 return RISCV_EXCP_NONE
;
1705 static int rmw_xtopei(CPURISCVState
*env
, int csrno
, target_ulong
*val
,
1706 target_ulong new_val
, target_ulong wr_mask
)
1710 target_ulong priv
, vgein
;
1712 /* Translate CSR number for VS-mode */
1713 csrno
= aia_xlate_vs_csrno(env
, csrno
);
1715 /* Decode register details from CSR number */
1732 /* IMSIC CSRs only available when machine implements IMSIC. */
1733 if (!env
->aia_ireg_rmw_fn
[priv
]) {
1737 /* Find the selected guest interrupt file */
1738 vgein
= (virt
) ? get_field(env
->hstatus
, HSTATUS_VGEIN
) : 0;
1740 /* Selected guest interrupt file should be valid */
1741 if (virt
&& (!vgein
|| env
->geilen
< vgein
)) {
1745 /* Call machine specific IMSIC register emulation for TOPEI */
1746 ret
= env
->aia_ireg_rmw_fn
[priv
](env
->aia_ireg_rmw_fn_arg
[priv
],
1747 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, priv
, virt
, vgein
,
1748 riscv_cpu_mxl_bits(env
)),
1749 val
, new_val
, wr_mask
);
1753 return (riscv_cpu_virt_enabled(env
) && virt
) ?
1754 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
1756 return RISCV_EXCP_NONE
;
1759 static RISCVException
read_mtvec(CPURISCVState
*env
, int csrno
,
1763 return RISCV_EXCP_NONE
;
1766 static RISCVException
write_mtvec(CPURISCVState
*env
, int csrno
,
1769 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
1770 if ((val
& 3) < 2) {
1773 qemu_log_mask(LOG_UNIMP
, "CSR_MTVEC: reserved mode not supported\n");
1775 return RISCV_EXCP_NONE
;
1778 static RISCVException
read_mcountinhibit(CPURISCVState
*env
, int csrno
,
1781 *val
= env
->mcountinhibit
;
1782 return RISCV_EXCP_NONE
;
1785 static RISCVException
write_mcountinhibit(CPURISCVState
*env
, int csrno
,
1789 PMUCTRState
*counter
;
1791 env
->mcountinhibit
= val
;
1793 /* Check if any other counter is also monitoring cycles/instructions */
1794 for (cidx
= 0; cidx
< RV_MAX_MHPMCOUNTERS
; cidx
++) {
1795 if (!get_field(env
->mcountinhibit
, BIT(cidx
))) {
1796 counter
= &env
->pmu_ctrs
[cidx
];
1797 counter
->started
= true;
1801 return RISCV_EXCP_NONE
;
1804 static RISCVException
read_mcounteren(CPURISCVState
*env
, int csrno
,
1807 *val
= env
->mcounteren
;
1808 return RISCV_EXCP_NONE
;
1811 static RISCVException
write_mcounteren(CPURISCVState
*env
, int csrno
,
1814 env
->mcounteren
= val
;
1815 return RISCV_EXCP_NONE
;
1818 /* Machine Trap Handling */
1819 static RISCVException
read_mscratch_i128(CPURISCVState
*env
, int csrno
,
1822 *val
= int128_make128(env
->mscratch
, env
->mscratchh
);
1823 return RISCV_EXCP_NONE
;
1826 static RISCVException
write_mscratch_i128(CPURISCVState
*env
, int csrno
,
1829 env
->mscratch
= int128_getlo(val
);
1830 env
->mscratchh
= int128_gethi(val
);
1831 return RISCV_EXCP_NONE
;
1834 static RISCVException
read_mscratch(CPURISCVState
*env
, int csrno
,
1837 *val
= env
->mscratch
;
1838 return RISCV_EXCP_NONE
;
1841 static RISCVException
write_mscratch(CPURISCVState
*env
, int csrno
,
1844 env
->mscratch
= val
;
1845 return RISCV_EXCP_NONE
;
1848 static RISCVException
read_mepc(CPURISCVState
*env
, int csrno
,
1852 return RISCV_EXCP_NONE
;
1855 static RISCVException
write_mepc(CPURISCVState
*env
, int csrno
,
1859 return RISCV_EXCP_NONE
;
1862 static RISCVException
read_mcause(CPURISCVState
*env
, int csrno
,
1866 return RISCV_EXCP_NONE
;
1869 static RISCVException
write_mcause(CPURISCVState
*env
, int csrno
,
1873 return RISCV_EXCP_NONE
;
1876 static RISCVException
read_mtval(CPURISCVState
*env
, int csrno
,
1880 return RISCV_EXCP_NONE
;
1883 static RISCVException
write_mtval(CPURISCVState
*env
, int csrno
,
1887 return RISCV_EXCP_NONE
;
1890 /* Execution environment configuration setup */
1891 static RISCVException
read_menvcfg(CPURISCVState
*env
, int csrno
,
1894 *val
= env
->menvcfg
;
1895 return RISCV_EXCP_NONE
;
1898 static RISCVException
write_menvcfg(CPURISCVState
*env
, int csrno
,
1901 RISCVCPUConfig
*cfg
= &env_archcpu(env
)->cfg
;
1902 uint64_t mask
= MENVCFG_FIOM
| MENVCFG_CBIE
| MENVCFG_CBCFE
| MENVCFG_CBZE
;
1904 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
1905 mask
|= (cfg
->ext_svpbmt
? MENVCFG_PBMTE
: 0) |
1906 (cfg
->ext_sstc
? MENVCFG_STCE
: 0) |
1907 (cfg
->ext_svadu
? MENVCFG_HADE
: 0);
1909 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (val
& mask
);
1911 return RISCV_EXCP_NONE
;
1914 static RISCVException
read_menvcfgh(CPURISCVState
*env
, int csrno
,
1917 *val
= env
->menvcfg
>> 32;
1918 return RISCV_EXCP_NONE
;
1921 static RISCVException
write_menvcfgh(CPURISCVState
*env
, int csrno
,
1924 RISCVCPUConfig
*cfg
= &env_archcpu(env
)->cfg
;
1925 uint64_t mask
= (cfg
->ext_svpbmt
? MENVCFG_PBMTE
: 0) |
1926 (cfg
->ext_sstc
? MENVCFG_STCE
: 0) |
1927 (cfg
->ext_svadu
? MENVCFG_HADE
: 0);
1928 uint64_t valh
= (uint64_t)val
<< 32;
1930 env
->menvcfg
= (env
->menvcfg
& ~mask
) | (valh
& mask
);
1932 return RISCV_EXCP_NONE
;
1935 static RISCVException
read_senvcfg(CPURISCVState
*env
, int csrno
,
1940 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1941 if (ret
!= RISCV_EXCP_NONE
) {
1945 *val
= env
->senvcfg
;
1946 return RISCV_EXCP_NONE
;
1949 static RISCVException
write_senvcfg(CPURISCVState
*env
, int csrno
,
1952 uint64_t mask
= SENVCFG_FIOM
| SENVCFG_CBIE
| SENVCFG_CBCFE
| SENVCFG_CBZE
;
1955 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1956 if (ret
!= RISCV_EXCP_NONE
) {
1960 env
->senvcfg
= (env
->senvcfg
& ~mask
) | (val
& mask
);
1961 return RISCV_EXCP_NONE
;
1964 static RISCVException
read_henvcfg(CPURISCVState
*env
, int csrno
,
1969 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1970 if (ret
!= RISCV_EXCP_NONE
) {
1975 * henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
1976 * henvcfg.stce is read_only 0 when menvcfg.stce = 0
1977 * henvcfg.hade is read_only 0 when menvcfg.hade = 0
1979 *val
= env
->henvcfg
& (~(HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_HADE
) |
1981 return RISCV_EXCP_NONE
;
1984 static RISCVException
write_henvcfg(CPURISCVState
*env
, int csrno
,
1987 uint64_t mask
= HENVCFG_FIOM
| HENVCFG_CBIE
| HENVCFG_CBCFE
| HENVCFG_CBZE
;
1990 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
1991 if (ret
!= RISCV_EXCP_NONE
) {
1995 if (riscv_cpu_mxl(env
) == MXL_RV64
) {
1996 mask
|= env
->menvcfg
& (HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_HADE
);
1999 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (val
& mask
);
2001 return RISCV_EXCP_NONE
;
2004 static RISCVException
read_henvcfgh(CPURISCVState
*env
, int csrno
,
2009 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2010 if (ret
!= RISCV_EXCP_NONE
) {
2014 *val
= (env
->henvcfg
& (~(HENVCFG_PBMTE
| HENVCFG_STCE
| HENVCFG_HADE
) |
2015 env
->menvcfg
)) >> 32;
2016 return RISCV_EXCP_NONE
;
2019 static RISCVException
write_henvcfgh(CPURISCVState
*env
, int csrno
,
2022 uint64_t mask
= env
->menvcfg
& (HENVCFG_PBMTE
| HENVCFG_STCE
|
2024 uint64_t valh
= (uint64_t)val
<< 32;
2027 ret
= smstateen_acc_ok(env
, 0, SMSTATEEN0_HSENVCFG
);
2028 if (ret
!= RISCV_EXCP_NONE
) {
2032 env
->henvcfg
= (env
->henvcfg
& ~mask
) | (valh
& mask
);
2033 return RISCV_EXCP_NONE
;
2036 static RISCVException
read_mstateen(CPURISCVState
*env
, int csrno
,
2039 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2041 return RISCV_EXCP_NONE
;
2044 static RISCVException
write_mstateen(CPURISCVState
*env
, int csrno
,
2045 uint64_t wr_mask
, target_ulong new_val
)
2049 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0
];
2050 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2052 return RISCV_EXCP_NONE
;
2055 static RISCVException
write_mstateen0(CPURISCVState
*env
, int csrno
,
2056 target_ulong new_val
)
2058 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2060 return write_mstateen(env
, csrno
, wr_mask
, new_val
);
2063 static RISCVException
write_mstateen_1_3(CPURISCVState
*env
, int csrno
,
2064 target_ulong new_val
)
2066 return write_mstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2069 static RISCVException
read_mstateenh(CPURISCVState
*env
, int csrno
,
2072 *val
= env
->mstateen
[csrno
- CSR_MSTATEEN0H
] >> 32;
2074 return RISCV_EXCP_NONE
;
2077 static RISCVException
write_mstateenh(CPURISCVState
*env
, int csrno
,
2078 uint64_t wr_mask
, target_ulong new_val
)
2082 reg
= &env
->mstateen
[csrno
- CSR_MSTATEEN0H
];
2083 val
= (uint64_t)new_val
<< 32;
2084 val
|= *reg
& 0xFFFFFFFF;
2085 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2087 return RISCV_EXCP_NONE
;
2090 static RISCVException
write_mstateen0h(CPURISCVState
*env
, int csrno
,
2091 target_ulong new_val
)
2093 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2095 return write_mstateenh(env
, csrno
, wr_mask
, new_val
);
2098 static RISCVException
write_mstateenh_1_3(CPURISCVState
*env
, int csrno
,
2099 target_ulong new_val
)
2101 return write_mstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2104 static RISCVException
read_hstateen(CPURISCVState
*env
, int csrno
,
2107 int index
= csrno
- CSR_HSTATEEN0
;
2109 *val
= env
->hstateen
[index
] & env
->mstateen
[index
];
2111 return RISCV_EXCP_NONE
;
2114 static RISCVException
write_hstateen(CPURISCVState
*env
, int csrno
,
2115 uint64_t mask
, target_ulong new_val
)
2117 int index
= csrno
- CSR_HSTATEEN0
;
2118 uint64_t *reg
, wr_mask
;
2120 reg
= &env
->hstateen
[index
];
2121 wr_mask
= env
->mstateen
[index
] & mask
;
2122 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2124 return RISCV_EXCP_NONE
;
2127 static RISCVException
write_hstateen0(CPURISCVState
*env
, int csrno
,
2128 target_ulong new_val
)
2130 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2132 return write_hstateen(env
, csrno
, wr_mask
, new_val
);
2135 static RISCVException
write_hstateen_1_3(CPURISCVState
*env
, int csrno
,
2136 target_ulong new_val
)
2138 return write_hstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2141 static RISCVException
read_hstateenh(CPURISCVState
*env
, int csrno
,
2144 int index
= csrno
- CSR_HSTATEEN0H
;
2146 *val
= (env
->hstateen
[index
] >> 32) & (env
->mstateen
[index
] >> 32);
2148 return RISCV_EXCP_NONE
;
2151 static RISCVException
write_hstateenh(CPURISCVState
*env
, int csrno
,
2152 uint64_t mask
, target_ulong new_val
)
2154 int index
= csrno
- CSR_HSTATEEN0H
;
2155 uint64_t *reg
, wr_mask
, val
;
2157 reg
= &env
->hstateen
[index
];
2158 val
= (uint64_t)new_val
<< 32;
2159 val
|= *reg
& 0xFFFFFFFF;
2160 wr_mask
= env
->mstateen
[index
] & mask
;
2161 *reg
= (*reg
& ~wr_mask
) | (val
& wr_mask
);
2163 return RISCV_EXCP_NONE
;
2166 static RISCVException
write_hstateen0h(CPURISCVState
*env
, int csrno
,
2167 target_ulong new_val
)
2169 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2171 return write_hstateenh(env
, csrno
, wr_mask
, new_val
);
2174 static RISCVException
write_hstateenh_1_3(CPURISCVState
*env
, int csrno
,
2175 target_ulong new_val
)
2177 return write_hstateenh(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2180 static RISCVException
read_sstateen(CPURISCVState
*env
, int csrno
,
2183 bool virt
= riscv_cpu_virt_enabled(env
);
2184 int index
= csrno
- CSR_SSTATEEN0
;
2186 *val
= env
->sstateen
[index
] & env
->mstateen
[index
];
2188 *val
&= env
->hstateen
[index
];
2191 return RISCV_EXCP_NONE
;
2194 static RISCVException
write_sstateen(CPURISCVState
*env
, int csrno
,
2195 uint64_t mask
, target_ulong new_val
)
2197 bool virt
= riscv_cpu_virt_enabled(env
);
2198 int index
= csrno
- CSR_SSTATEEN0
;
2202 wr_mask
= env
->mstateen
[index
] & mask
;
2204 wr_mask
&= env
->hstateen
[index
];
2207 reg
= &env
->sstateen
[index
];
2208 *reg
= (*reg
& ~wr_mask
) | (new_val
& wr_mask
);
2210 return RISCV_EXCP_NONE
;
2213 static RISCVException
write_sstateen0(CPURISCVState
*env
, int csrno
,
2214 target_ulong new_val
)
2216 uint64_t wr_mask
= SMSTATEEN_STATEEN
| SMSTATEEN0_HSENVCFG
;
2218 return write_sstateen(env
, csrno
, wr_mask
, new_val
);
2221 static RISCVException
write_sstateen_1_3(CPURISCVState
*env
, int csrno
,
2222 target_ulong new_val
)
2224 return write_sstateen(env
, csrno
, SMSTATEEN_STATEEN
, new_val
);
2227 static RISCVException
rmw_mip64(CPURISCVState
*env
, int csrno
,
2229 uint64_t new_val
, uint64_t wr_mask
)
2231 RISCVCPU
*cpu
= env_archcpu(env
);
2232 uint64_t old_mip
, mask
= wr_mask
& delegable_ints
;
2235 if (mask
& MIP_SEIP
) {
2236 env
->software_seip
= new_val
& MIP_SEIP
;
2237 new_val
|= env
->external_seip
* MIP_SEIP
;
2240 if (cpu
->cfg
.ext_sstc
&& (env
->priv
== PRV_M
) &&
2241 get_field(env
->menvcfg
, MENVCFG_STCE
)) {
2242 /* sstc extension forbids STIP & VSTIP to be writeable in mip */
2243 mask
= mask
& ~(MIP_STIP
| MIP_VSTIP
);
2247 old_mip
= riscv_cpu_update_mip(cpu
, mask
, (new_val
& mask
));
2252 if (csrno
!= CSR_HVIP
) {
2253 gin
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
2254 old_mip
|= (env
->hgeip
& ((target_ulong
)1 << gin
)) ? MIP_VSEIP
: 0;
2255 old_mip
|= env
->vstime_irq
? MIP_VSTIP
: 0;
2262 return RISCV_EXCP_NONE
;
2265 static RISCVException
rmw_mip(CPURISCVState
*env
, int csrno
,
2266 target_ulong
*ret_val
,
2267 target_ulong new_val
, target_ulong wr_mask
)
2272 ret
= rmw_mip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2280 static RISCVException
rmw_miph(CPURISCVState
*env
, int csrno
,
2281 target_ulong
*ret_val
,
2282 target_ulong new_val
, target_ulong wr_mask
)
2287 ret
= rmw_mip64(env
, csrno
, &rval
,
2288 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2290 *ret_val
= rval
>> 32;
2296 /* Supervisor Trap Setup */
2297 static RISCVException
read_sstatus_i128(CPURISCVState
*env
, int csrno
,
2300 uint64_t mask
= sstatus_v1_10_mask
;
2301 uint64_t sstatus
= env
->mstatus
& mask
;
2302 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2303 mask
|= SSTATUS64_UXL
;
2306 *val
= int128_make128(sstatus
, add_status_sd(MXL_RV128
, sstatus
));
2307 return RISCV_EXCP_NONE
;
2310 static RISCVException
read_sstatus(CPURISCVState
*env
, int csrno
,
2313 target_ulong mask
= (sstatus_v1_10_mask
);
2314 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2315 mask
|= SSTATUS64_UXL
;
2317 /* TODO: Use SXL not MXL. */
2318 *val
= add_status_sd(riscv_cpu_mxl(env
), env
->mstatus
& mask
);
2319 return RISCV_EXCP_NONE
;
2322 static RISCVException
write_sstatus(CPURISCVState
*env
, int csrno
,
2325 target_ulong mask
= (sstatus_v1_10_mask
);
2327 if (env
->xl
!= MXL_RV32
|| env
->debugger
) {
2328 if ((val
& SSTATUS64_UXL
) != 0) {
2329 mask
|= SSTATUS64_UXL
;
2332 target_ulong newval
= (env
->mstatus
& ~mask
) | (val
& mask
);
2333 return write_mstatus(env
, CSR_MSTATUS
, newval
);
2336 static RISCVException
rmw_vsie64(CPURISCVState
*env
, int csrno
,
2338 uint64_t new_val
, uint64_t wr_mask
)
2341 uint64_t rval
, mask
= env
->hideleg
& VS_MODE_INTERRUPTS
;
2343 /* Bring VS-level bits to correct position */
2344 new_val
= (new_val
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2345 wr_mask
= (wr_mask
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2347 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
& mask
);
2349 *ret_val
= (rval
& mask
) >> 1;
2355 static RISCVException
rmw_vsie(CPURISCVState
*env
, int csrno
,
2356 target_ulong
*ret_val
,
2357 target_ulong new_val
, target_ulong wr_mask
)
2362 ret
= rmw_vsie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2370 static RISCVException
rmw_vsieh(CPURISCVState
*env
, int csrno
,
2371 target_ulong
*ret_val
,
2372 target_ulong new_val
, target_ulong wr_mask
)
2377 ret
= rmw_vsie64(env
, csrno
, &rval
,
2378 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2380 *ret_val
= rval
>> 32;
2386 static RISCVException
rmw_sie64(CPURISCVState
*env
, int csrno
,
2388 uint64_t new_val
, uint64_t wr_mask
)
2391 uint64_t mask
= env
->mideleg
& S_MODE_INTERRUPTS
;
2393 if (riscv_cpu_virt_enabled(env
)) {
2394 if (env
->hvictl
& HVICTL_VTI
) {
2395 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2397 ret
= rmw_vsie64(env
, CSR_VSIE
, ret_val
, new_val
, wr_mask
);
2399 ret
= rmw_mie64(env
, csrno
, ret_val
, new_val
, wr_mask
& mask
);
2409 static RISCVException
rmw_sie(CPURISCVState
*env
, int csrno
,
2410 target_ulong
*ret_val
,
2411 target_ulong new_val
, target_ulong wr_mask
)
2416 ret
= rmw_sie64(env
, csrno
, &rval
, new_val
, wr_mask
);
2417 if (ret
== RISCV_EXCP_NONE
&& ret_val
) {
2424 static RISCVException
rmw_sieh(CPURISCVState
*env
, int csrno
,
2425 target_ulong
*ret_val
,
2426 target_ulong new_val
, target_ulong wr_mask
)
2431 ret
= rmw_sie64(env
, csrno
, &rval
,
2432 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2434 *ret_val
= rval
>> 32;
2440 static RISCVException
read_stvec(CPURISCVState
*env
, int csrno
,
2444 return RISCV_EXCP_NONE
;
2447 static RISCVException
write_stvec(CPURISCVState
*env
, int csrno
,
2450 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
2451 if ((val
& 3) < 2) {
2454 qemu_log_mask(LOG_UNIMP
, "CSR_STVEC: reserved mode not supported\n");
2456 return RISCV_EXCP_NONE
;
2459 static RISCVException
read_scounteren(CPURISCVState
*env
, int csrno
,
2462 *val
= env
->scounteren
;
2463 return RISCV_EXCP_NONE
;
2466 static RISCVException
write_scounteren(CPURISCVState
*env
, int csrno
,
2469 env
->scounteren
= val
;
2470 return RISCV_EXCP_NONE
;
2473 /* Supervisor Trap Handling */
2474 static RISCVException
read_sscratch_i128(CPURISCVState
*env
, int csrno
,
2477 *val
= int128_make128(env
->sscratch
, env
->sscratchh
);
2478 return RISCV_EXCP_NONE
;
2481 static RISCVException
write_sscratch_i128(CPURISCVState
*env
, int csrno
,
2484 env
->sscratch
= int128_getlo(val
);
2485 env
->sscratchh
= int128_gethi(val
);
2486 return RISCV_EXCP_NONE
;
2489 static RISCVException
read_sscratch(CPURISCVState
*env
, int csrno
,
2492 *val
= env
->sscratch
;
2493 return RISCV_EXCP_NONE
;
2496 static RISCVException
write_sscratch(CPURISCVState
*env
, int csrno
,
2499 env
->sscratch
= val
;
2500 return RISCV_EXCP_NONE
;
2503 static RISCVException
read_sepc(CPURISCVState
*env
, int csrno
,
2507 return RISCV_EXCP_NONE
;
2510 static RISCVException
write_sepc(CPURISCVState
*env
, int csrno
,
2514 return RISCV_EXCP_NONE
;
2517 static RISCVException
read_scause(CPURISCVState
*env
, int csrno
,
2521 return RISCV_EXCP_NONE
;
2524 static RISCVException
write_scause(CPURISCVState
*env
, int csrno
,
2528 return RISCV_EXCP_NONE
;
2531 static RISCVException
read_stval(CPURISCVState
*env
, int csrno
,
2535 return RISCV_EXCP_NONE
;
2538 static RISCVException
write_stval(CPURISCVState
*env
, int csrno
,
2542 return RISCV_EXCP_NONE
;
2545 static RISCVException
rmw_vsip64(CPURISCVState
*env
, int csrno
,
2547 uint64_t new_val
, uint64_t wr_mask
)
2550 uint64_t rval
, mask
= env
->hideleg
& VS_MODE_INTERRUPTS
;
2552 /* Bring VS-level bits to correct position */
2553 new_val
= (new_val
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2554 wr_mask
= (wr_mask
& (VS_MODE_INTERRUPTS
>> 1)) << 1;
2556 ret
= rmw_mip64(env
, csrno
, &rval
, new_val
,
2557 wr_mask
& mask
& vsip_writable_mask
);
2559 *ret_val
= (rval
& mask
) >> 1;
2565 static RISCVException
rmw_vsip(CPURISCVState
*env
, int csrno
,
2566 target_ulong
*ret_val
,
2567 target_ulong new_val
, target_ulong wr_mask
)
2572 ret
= rmw_vsip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2580 static RISCVException
rmw_vsiph(CPURISCVState
*env
, int csrno
,
2581 target_ulong
*ret_val
,
2582 target_ulong new_val
, target_ulong wr_mask
)
2587 ret
= rmw_vsip64(env
, csrno
, &rval
,
2588 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2590 *ret_val
= rval
>> 32;
2596 static RISCVException
rmw_sip64(CPURISCVState
*env
, int csrno
,
2598 uint64_t new_val
, uint64_t wr_mask
)
2601 uint64_t mask
= env
->mideleg
& sip_writable_mask
;
2603 if (riscv_cpu_virt_enabled(env
)) {
2604 if (env
->hvictl
& HVICTL_VTI
) {
2605 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
2607 ret
= rmw_vsip64(env
, CSR_VSIP
, ret_val
, new_val
, wr_mask
);
2609 ret
= rmw_mip64(env
, csrno
, ret_val
, new_val
, wr_mask
& mask
);
2613 *ret_val
&= env
->mideleg
& S_MODE_INTERRUPTS
;
2619 static RISCVException
rmw_sip(CPURISCVState
*env
, int csrno
,
2620 target_ulong
*ret_val
,
2621 target_ulong new_val
, target_ulong wr_mask
)
2626 ret
= rmw_sip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2634 static RISCVException
rmw_siph(CPURISCVState
*env
, int csrno
,
2635 target_ulong
*ret_val
,
2636 target_ulong new_val
, target_ulong wr_mask
)
2641 ret
= rmw_sip64(env
, csrno
, &rval
,
2642 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2644 *ret_val
= rval
>> 32;
2650 /* Supervisor Protection and Translation */
2651 static RISCVException
read_satp(CPURISCVState
*env
, int csrno
,
2654 if (!riscv_cpu_cfg(env
)->mmu
) {
2656 return RISCV_EXCP_NONE
;
2659 if (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_TVM
)) {
2660 return RISCV_EXCP_ILLEGAL_INST
;
2665 return RISCV_EXCP_NONE
;
2668 static RISCVException
write_satp(CPURISCVState
*env
, int csrno
,
2674 if (!riscv_cpu_cfg(env
)->mmu
) {
2675 return RISCV_EXCP_NONE
;
2678 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
2679 vm
= validate_vm(env
, get_field(val
, SATP32_MODE
));
2680 mask
= (val
^ env
->satp
) & (SATP32_MODE
| SATP32_ASID
| SATP32_PPN
);
2682 vm
= validate_vm(env
, get_field(val
, SATP64_MODE
));
2683 mask
= (val
^ env
->satp
) & (SATP64_MODE
| SATP64_ASID
| SATP64_PPN
);
2687 if (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_TVM
)) {
2688 return RISCV_EXCP_ILLEGAL_INST
;
2691 * The ISA defines SATP.MODE=Bare as "no translation", but we still
2692 * pass these through QEMU's TLB emulation as it improves
2693 * performance. Flushing the TLB on SATP writes with paging
2694 * enabled avoids leaking those invalid cached mappings.
2696 tlb_flush(env_cpu(env
));
2700 return RISCV_EXCP_NONE
;
2703 static int read_vstopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
2707 uint64_t vseip
, vsgein
;
2708 uint32_t iid
, iprio
, hviid
, hviprio
, gein
;
2709 uint32_t s
, scount
= 0, siid
[VSTOPI_NUM_SRCS
], siprio
[VSTOPI_NUM_SRCS
];
2711 gein
= get_field(env
->hstatus
, HSTATUS_VGEIN
);
2712 hviid
= get_field(env
->hvictl
, HVICTL_IID
);
2713 hviprio
= get_field(env
->hvictl
, HVICTL_IPRIO
);
2716 vsgein
= (env
->hgeip
& (1ULL << gein
)) ? MIP_VSEIP
: 0;
2717 vseip
= env
->mie
& (env
->mip
| vsgein
) & MIP_VSEIP
;
2718 if (gein
<= env
->geilen
&& vseip
) {
2719 siid
[scount
] = IRQ_S_EXT
;
2720 siprio
[scount
] = IPRIO_MMAXIPRIO
+ 1;
2721 if (env
->aia_ireg_rmw_fn
[PRV_S
]) {
2723 * Call machine specific IMSIC register emulation for
2726 ret
= env
->aia_ireg_rmw_fn
[PRV_S
](
2727 env
->aia_ireg_rmw_fn_arg
[PRV_S
],
2728 AIA_MAKE_IREG(ISELECT_IMSIC_TOPEI
, PRV_S
, true, gein
,
2729 riscv_cpu_mxl_bits(env
)),
2731 if (!ret
&& topei
) {
2732 siprio
[scount
] = topei
& IMSIC_TOPEI_IPRIO_MASK
;
2738 if (hviid
== IRQ_S_EXT
&& hviprio
) {
2739 siid
[scount
] = IRQ_S_EXT
;
2740 siprio
[scount
] = hviprio
;
2745 if (env
->hvictl
& HVICTL_VTI
) {
2746 if (hviid
!= IRQ_S_EXT
) {
2747 siid
[scount
] = hviid
;
2748 siprio
[scount
] = hviprio
;
2752 irq
= riscv_cpu_vsirq_pending(env
);
2753 if (irq
!= IRQ_S_EXT
&& 0 < irq
&& irq
<= 63) {
2755 siprio
[scount
] = env
->hviprio
[irq
];
2762 for (s
= 0; s
< scount
; s
++) {
2763 if (siprio
[s
] < iprio
) {
2770 if (env
->hvictl
& HVICTL_IPRIOM
) {
2771 if (iprio
> IPRIO_MMAXIPRIO
) {
2772 iprio
= IPRIO_MMAXIPRIO
;
2775 if (riscv_cpu_default_priority(iid
) > IPRIO_DEFAULT_S
) {
2776 iprio
= IPRIO_MMAXIPRIO
;
2786 *val
= (iid
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
2788 return RISCV_EXCP_NONE
;
2791 static int read_stopi(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
2796 if (riscv_cpu_virt_enabled(env
)) {
2797 return read_vstopi(env
, CSR_VSTOPI
, val
);
2800 irq
= riscv_cpu_sirq_pending(env
);
2801 if (irq
<= 0 || irq
> 63) {
2804 iprio
= env
->siprio
[irq
];
2806 if (riscv_cpu_default_priority(irq
) > IPRIO_DEFAULT_S
) {
2807 iprio
= IPRIO_MMAXIPRIO
;
2810 *val
= (irq
& TOPI_IID_MASK
) << TOPI_IID_SHIFT
;
2814 return RISCV_EXCP_NONE
;
2817 /* Hypervisor Extensions */
2818 static RISCVException
read_hstatus(CPURISCVState
*env
, int csrno
,
2821 *val
= env
->hstatus
;
2822 if (riscv_cpu_mxl(env
) != MXL_RV32
) {
2823 /* We only support 64-bit VSXL */
2824 *val
= set_field(*val
, HSTATUS_VSXL
, 2);
2826 /* We only support little endian */
2827 *val
= set_field(*val
, HSTATUS_VSBE
, 0);
2828 return RISCV_EXCP_NONE
;
2831 static RISCVException
write_hstatus(CPURISCVState
*env
, int csrno
,
2835 if (riscv_cpu_mxl(env
) != MXL_RV32
&& get_field(val
, HSTATUS_VSXL
) != 2) {
2836 qemu_log_mask(LOG_UNIMP
, "QEMU does not support mixed HSXLEN options.");
2838 if (get_field(val
, HSTATUS_VSBE
) != 0) {
2839 qemu_log_mask(LOG_UNIMP
, "QEMU does not support big endian guests.");
2841 return RISCV_EXCP_NONE
;
2844 static RISCVException
read_hedeleg(CPURISCVState
*env
, int csrno
,
2847 *val
= env
->hedeleg
;
2848 return RISCV_EXCP_NONE
;
2851 static RISCVException
write_hedeleg(CPURISCVState
*env
, int csrno
,
2854 env
->hedeleg
= val
& vs_delegable_excps
;
2855 return RISCV_EXCP_NONE
;
2858 static RISCVException
rmw_hideleg64(CPURISCVState
*env
, int csrno
,
2860 uint64_t new_val
, uint64_t wr_mask
)
2862 uint64_t mask
= wr_mask
& vs_delegable_ints
;
2865 *ret_val
= env
->hideleg
& vs_delegable_ints
;
2868 env
->hideleg
= (env
->hideleg
& ~mask
) | (new_val
& mask
);
2869 return RISCV_EXCP_NONE
;
2872 static RISCVException
rmw_hideleg(CPURISCVState
*env
, int csrno
,
2873 target_ulong
*ret_val
,
2874 target_ulong new_val
, target_ulong wr_mask
)
2879 ret
= rmw_hideleg64(env
, csrno
, &rval
, new_val
, wr_mask
);
2887 static RISCVException
rmw_hidelegh(CPURISCVState
*env
, int csrno
,
2888 target_ulong
*ret_val
,
2889 target_ulong new_val
, target_ulong wr_mask
)
2894 ret
= rmw_hideleg64(env
, csrno
, &rval
,
2895 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2897 *ret_val
= rval
>> 32;
2903 static RISCVException
rmw_hvip64(CPURISCVState
*env
, int csrno
,
2905 uint64_t new_val
, uint64_t wr_mask
)
2909 ret
= rmw_mip64(env
, csrno
, ret_val
, new_val
,
2910 wr_mask
& hvip_writable_mask
);
2912 *ret_val
&= VS_MODE_INTERRUPTS
;
2918 static RISCVException
rmw_hvip(CPURISCVState
*env
, int csrno
,
2919 target_ulong
*ret_val
,
2920 target_ulong new_val
, target_ulong wr_mask
)
2925 ret
= rmw_hvip64(env
, csrno
, &rval
, new_val
, wr_mask
);
2933 static RISCVException
rmw_hviph(CPURISCVState
*env
, int csrno
,
2934 target_ulong
*ret_val
,
2935 target_ulong new_val
, target_ulong wr_mask
)
2940 ret
= rmw_hvip64(env
, csrno
, &rval
,
2941 ((uint64_t)new_val
) << 32, ((uint64_t)wr_mask
) << 32);
2943 *ret_val
= rval
>> 32;
2949 static RISCVException
rmw_hip(CPURISCVState
*env
, int csrno
,
2950 target_ulong
*ret_value
,
2951 target_ulong new_value
, target_ulong write_mask
)
2953 int ret
= rmw_mip(env
, csrno
, ret_value
, new_value
,
2954 write_mask
& hip_writable_mask
);
2957 *ret_value
&= HS_MODE_INTERRUPTS
;
2962 static RISCVException
rmw_hie(CPURISCVState
*env
, int csrno
,
2963 target_ulong
*ret_val
,
2964 target_ulong new_val
, target_ulong wr_mask
)
2969 ret
= rmw_mie64(env
, csrno
, &rval
, new_val
, wr_mask
& HS_MODE_INTERRUPTS
);
2971 *ret_val
= rval
& HS_MODE_INTERRUPTS
;
2977 static RISCVException
read_hcounteren(CPURISCVState
*env
, int csrno
,
2980 *val
= env
->hcounteren
;
2981 return RISCV_EXCP_NONE
;
2984 static RISCVException
write_hcounteren(CPURISCVState
*env
, int csrno
,
2987 env
->hcounteren
= val
;
2988 return RISCV_EXCP_NONE
;
2991 static RISCVException
read_hgeie(CPURISCVState
*env
, int csrno
,
2997 return RISCV_EXCP_NONE
;
3000 static RISCVException
write_hgeie(CPURISCVState
*env
, int csrno
,
3003 /* Only GEILEN:1 bits implemented and BIT0 is never implemented */
3004 val
&= ((((target_ulong
)1) << env
->geilen
) - 1) << 1;
3006 /* Update mip.SGEIP bit */
3007 riscv_cpu_update_mip(env_archcpu(env
), MIP_SGEIP
,
3008 BOOL_TO_MASK(!!(env
->hgeie
& env
->hgeip
)));
3009 return RISCV_EXCP_NONE
;
3012 static RISCVException
read_htval(CPURISCVState
*env
, int csrno
,
3016 return RISCV_EXCP_NONE
;
3019 static RISCVException
write_htval(CPURISCVState
*env
, int csrno
,
3023 return RISCV_EXCP_NONE
;
3026 static RISCVException
read_htinst(CPURISCVState
*env
, int csrno
,
3030 return RISCV_EXCP_NONE
;
3033 static RISCVException
write_htinst(CPURISCVState
*env
, int csrno
,
3036 return RISCV_EXCP_NONE
;
3039 static RISCVException
read_hgeip(CPURISCVState
*env
, int csrno
,
3045 return RISCV_EXCP_NONE
;
3048 static RISCVException
read_hgatp(CPURISCVState
*env
, int csrno
,
3052 return RISCV_EXCP_NONE
;
3055 static RISCVException
write_hgatp(CPURISCVState
*env
, int csrno
,
3059 return RISCV_EXCP_NONE
;
3062 static RISCVException
read_htimedelta(CPURISCVState
*env
, int csrno
,
3065 if (!env
->rdtime_fn
) {
3066 return RISCV_EXCP_ILLEGAL_INST
;
3069 *val
= env
->htimedelta
;
3070 return RISCV_EXCP_NONE
;
3073 static RISCVException
write_htimedelta(CPURISCVState
*env
, int csrno
,
3076 RISCVCPU
*cpu
= env_archcpu(env
);
3078 if (!env
->rdtime_fn
) {
3079 return RISCV_EXCP_ILLEGAL_INST
;
3082 if (riscv_cpu_mxl(env
) == MXL_RV32
) {
3083 env
->htimedelta
= deposit64(env
->htimedelta
, 0, 32, (uint64_t)val
);
3085 env
->htimedelta
= val
;
3088 if (cpu
->cfg
.ext_sstc
&& env
->rdtime_fn
) {
3089 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
3090 env
->htimedelta
, MIP_VSTIP
);
3093 return RISCV_EXCP_NONE
;
3096 static RISCVException
read_htimedeltah(CPURISCVState
*env
, int csrno
,
3099 if (!env
->rdtime_fn
) {
3100 return RISCV_EXCP_ILLEGAL_INST
;
3103 *val
= env
->htimedelta
>> 32;
3104 return RISCV_EXCP_NONE
;
3107 static RISCVException
write_htimedeltah(CPURISCVState
*env
, int csrno
,
3110 RISCVCPU
*cpu
= env_archcpu(env
);
3112 if (!env
->rdtime_fn
) {
3113 return RISCV_EXCP_ILLEGAL_INST
;
3116 env
->htimedelta
= deposit64(env
->htimedelta
, 32, 32, (uint64_t)val
);
3118 if (cpu
->cfg
.ext_sstc
&& env
->rdtime_fn
) {
3119 riscv_timer_write_timecmp(cpu
, env
->vstimer
, env
->vstimecmp
,
3120 env
->htimedelta
, MIP_VSTIP
);
3123 return RISCV_EXCP_NONE
;
3126 static int read_hvictl(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3129 return RISCV_EXCP_NONE
;
3132 static int write_hvictl(CPURISCVState
*env
, int csrno
, target_ulong val
)
3134 env
->hvictl
= val
& HVICTL_VALID_MASK
;
3135 return RISCV_EXCP_NONE
;
3138 static int read_hvipriox(CPURISCVState
*env
, int first_index
,
3139 uint8_t *iprio
, target_ulong
*val
)
3141 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3143 /* First index has to be a multiple of number of irqs per register */
3144 if (first_index
% num_irqs
) {
3145 return (riscv_cpu_virt_enabled(env
)) ?
3146 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3149 /* Fill-up return value */
3151 for (i
= 0; i
< num_irqs
; i
++) {
3152 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3158 *val
|= ((target_ulong
)iprio
[irq
]) << (i
* 8);
3161 return RISCV_EXCP_NONE
;
3164 static int write_hvipriox(CPURISCVState
*env
, int first_index
,
3165 uint8_t *iprio
, target_ulong val
)
3167 int i
, irq
, rdzero
, num_irqs
= 4 * (riscv_cpu_mxl_bits(env
) / 32);
3169 /* First index has to be a multiple of number of irqs per register */
3170 if (first_index
% num_irqs
) {
3171 return (riscv_cpu_virt_enabled(env
)) ?
3172 RISCV_EXCP_VIRT_INSTRUCTION_FAULT
: RISCV_EXCP_ILLEGAL_INST
;
3175 /* Fill-up priority arrary */
3176 for (i
= 0; i
< num_irqs
; i
++) {
3177 if (riscv_cpu_hviprio_index2irq(first_index
+ i
, &irq
, &rdzero
)) {
3183 iprio
[irq
] = (val
>> (i
* 8)) & 0xff;
3187 return RISCV_EXCP_NONE
;
3190 static int read_hviprio1(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3192 return read_hvipriox(env
, 0, env
->hviprio
, val
);
3195 static int write_hviprio1(CPURISCVState
*env
, int csrno
, target_ulong val
)
3197 return write_hvipriox(env
, 0, env
->hviprio
, val
);
3200 static int read_hviprio1h(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3202 return read_hvipriox(env
, 4, env
->hviprio
, val
);
3205 static int write_hviprio1h(CPURISCVState
*env
, int csrno
, target_ulong val
)
3207 return write_hvipriox(env
, 4, env
->hviprio
, val
);
3210 static int read_hviprio2(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3212 return read_hvipriox(env
, 8, env
->hviprio
, val
);
3215 static int write_hviprio2(CPURISCVState
*env
, int csrno
, target_ulong val
)
3217 return write_hvipriox(env
, 8, env
->hviprio
, val
);
3220 static int read_hviprio2h(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3222 return read_hvipriox(env
, 12, env
->hviprio
, val
);
3225 static int write_hviprio2h(CPURISCVState
*env
, int csrno
, target_ulong val
)
3227 return write_hvipriox(env
, 12, env
->hviprio
, val
);
3230 /* Virtual CSR Registers */
3231 static RISCVException
read_vsstatus(CPURISCVState
*env
, int csrno
,
3234 *val
= env
->vsstatus
;
3235 return RISCV_EXCP_NONE
;
3238 static RISCVException
write_vsstatus(CPURISCVState
*env
, int csrno
,
3241 uint64_t mask
= (target_ulong
)-1;
3242 if ((val
& VSSTATUS64_UXL
) == 0) {
3243 mask
&= ~VSSTATUS64_UXL
;
3245 env
->vsstatus
= (env
->vsstatus
& ~mask
) | (uint64_t)val
;
3246 return RISCV_EXCP_NONE
;
3249 static int read_vstvec(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
3252 return RISCV_EXCP_NONE
;
3255 static RISCVException
write_vstvec(CPURISCVState
*env
, int csrno
,
3259 return RISCV_EXCP_NONE
;
3262 static RISCVException
read_vsscratch(CPURISCVState
*env
, int csrno
,
3265 *val
= env
->vsscratch
;
3266 return RISCV_EXCP_NONE
;
3269 static RISCVException
write_vsscratch(CPURISCVState
*env
, int csrno
,
3272 env
->vsscratch
= val
;
3273 return RISCV_EXCP_NONE
;
3276 static RISCVException
read_vsepc(CPURISCVState
*env
, int csrno
,
3280 return RISCV_EXCP_NONE
;
3283 static RISCVException
write_vsepc(CPURISCVState
*env
, int csrno
,
3287 return RISCV_EXCP_NONE
;
3290 static RISCVException
read_vscause(CPURISCVState
*env
, int csrno
,
3293 *val
= env
->vscause
;
3294 return RISCV_EXCP_NONE
;
3297 static RISCVException
write_vscause(CPURISCVState
*env
, int csrno
,
3301 return RISCV_EXCP_NONE
;
3304 static RISCVException
read_vstval(CPURISCVState
*env
, int csrno
,
3308 return RISCV_EXCP_NONE
;
3311 static RISCVException
write_vstval(CPURISCVState
*env
, int csrno
,
3315 return RISCV_EXCP_NONE
;
3318 static RISCVException
read_vsatp(CPURISCVState
*env
, int csrno
,
3322 return RISCV_EXCP_NONE
;
3325 static RISCVException
write_vsatp(CPURISCVState
*env
, int csrno
,
3329 return RISCV_EXCP_NONE
;
3332 static RISCVException
read_mtval2(CPURISCVState
*env
, int csrno
,
3336 return RISCV_EXCP_NONE
;
3339 static RISCVException
write_mtval2(CPURISCVState
*env
, int csrno
,
3343 return RISCV_EXCP_NONE
;
3346 static RISCVException
read_mtinst(CPURISCVState
*env
, int csrno
,
3350 return RISCV_EXCP_NONE
;
3353 static RISCVException
write_mtinst(CPURISCVState
*env
, int csrno
,
3357 return RISCV_EXCP_NONE
;
3360 /* Physical Memory Protection */
3361 static RISCVException
read_mseccfg(CPURISCVState
*env
, int csrno
,
3364 *val
= mseccfg_csr_read(env
);
3365 return RISCV_EXCP_NONE
;
3368 static RISCVException
write_mseccfg(CPURISCVState
*env
, int csrno
,
3371 mseccfg_csr_write(env
, val
);
3372 return RISCV_EXCP_NONE
;
3375 static RISCVException
read_pmpcfg(CPURISCVState
*env
, int csrno
,
3378 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3380 *val
= pmpcfg_csr_read(env
, reg_index
);
3381 return RISCV_EXCP_NONE
;
3384 static RISCVException
write_pmpcfg(CPURISCVState
*env
, int csrno
,
3387 uint32_t reg_index
= csrno
- CSR_PMPCFG0
;
3389 pmpcfg_csr_write(env
, reg_index
, val
);
3390 return RISCV_EXCP_NONE
;
3393 static RISCVException
read_pmpaddr(CPURISCVState
*env
, int csrno
,
3396 *val
= pmpaddr_csr_read(env
, csrno
- CSR_PMPADDR0
);
3397 return RISCV_EXCP_NONE
;
3400 static RISCVException
write_pmpaddr(CPURISCVState
*env
, int csrno
,
3403 pmpaddr_csr_write(env
, csrno
- CSR_PMPADDR0
, val
);
3404 return RISCV_EXCP_NONE
;
3407 static RISCVException
read_tselect(CPURISCVState
*env
, int csrno
,
3410 *val
= tselect_csr_read(env
);
3411 return RISCV_EXCP_NONE
;
3414 static RISCVException
write_tselect(CPURISCVState
*env
, int csrno
,
3417 tselect_csr_write(env
, val
);
3418 return RISCV_EXCP_NONE
;
3421 static RISCVException
read_tdata(CPURISCVState
*env
, int csrno
,
3424 /* return 0 in tdata1 to end the trigger enumeration */
3425 if (env
->trigger_cur
>= RV_MAX_TRIGGERS
&& csrno
== CSR_TDATA1
) {
3427 return RISCV_EXCP_NONE
;
3430 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3431 return RISCV_EXCP_ILLEGAL_INST
;
3434 *val
= tdata_csr_read(env
, csrno
- CSR_TDATA1
);
3435 return RISCV_EXCP_NONE
;
3438 static RISCVException
write_tdata(CPURISCVState
*env
, int csrno
,
3441 if (!tdata_available(env
, csrno
- CSR_TDATA1
)) {
3442 return RISCV_EXCP_ILLEGAL_INST
;
3445 tdata_csr_write(env
, csrno
- CSR_TDATA1
, val
);
3446 return RISCV_EXCP_NONE
;
3449 static RISCVException
read_tinfo(CPURISCVState
*env
, int csrno
,
3452 *val
= tinfo_csr_read(env
);
3453 return RISCV_EXCP_NONE
;
3457 * Functions to access Pointer Masking feature registers
3458 * We have to check if current priv lvl could modify
3461 static bool check_pm_current_disabled(CPURISCVState
*env
, int csrno
)
3463 int csr_priv
= get_field(csrno
, 0x300);
3466 if (env
->debugger
) {
3470 * If priv lvls differ that means we're accessing csr from higher priv lvl,
3471 * so allow the access
3473 if (env
->priv
!= csr_priv
) {
3476 switch (env
->priv
) {
3478 pm_current
= get_field(env
->mmte
, M_PM_CURRENT
);
3481 pm_current
= get_field(env
->mmte
, S_PM_CURRENT
);
3484 pm_current
= get_field(env
->mmte
, U_PM_CURRENT
);
3487 g_assert_not_reached();
3489 /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
3493 static RISCVException
read_mmte(CPURISCVState
*env
, int csrno
,
3496 *val
= env
->mmte
& MMTE_MASK
;
3497 return RISCV_EXCP_NONE
;
3500 static RISCVException
write_mmte(CPURISCVState
*env
, int csrno
,
3504 target_ulong wpri_val
= val
& MMTE_MASK
;
3506 if (val
!= wpri_val
) {
3507 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s" TARGET_FMT_lx
"\n",
3508 "MMTE: WPRI violation written 0x", val
,
3509 "vs expected 0x", wpri_val
);
3511 /* for machine mode pm.current is hardwired to 1 */
3512 wpri_val
|= MMTE_M_PM_CURRENT
;
3514 /* hardwiring pm.instruction bit to 0, since it's not supported yet */
3515 wpri_val
&= ~(MMTE_M_PM_INSN
| MMTE_S_PM_INSN
| MMTE_U_PM_INSN
);
3516 env
->mmte
= wpri_val
| PM_EXT_DIRTY
;
3517 riscv_cpu_update_mask(env
);
3519 /* Set XS and SD bits, since PM CSRs are dirty */
3520 mstatus
= env
->mstatus
| MSTATUS_XS
;
3521 write_mstatus(env
, csrno
, mstatus
);
3522 return RISCV_EXCP_NONE
;
3525 static RISCVException
read_smte(CPURISCVState
*env
, int csrno
,
3528 *val
= env
->mmte
& SMTE_MASK
;
3529 return RISCV_EXCP_NONE
;
3532 static RISCVException
write_smte(CPURISCVState
*env
, int csrno
,
3535 target_ulong wpri_val
= val
& SMTE_MASK
;
3537 if (val
!= wpri_val
) {
3538 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s" TARGET_FMT_lx
"\n",
3539 "SMTE: WPRI violation written 0x", val
,
3540 "vs expected 0x", wpri_val
);
3543 /* if pm.current==0 we can't modify current PM CSRs */
3544 if (check_pm_current_disabled(env
, csrno
)) {
3545 return RISCV_EXCP_NONE
;
3548 wpri_val
|= (env
->mmte
& ~SMTE_MASK
);
3549 write_mmte(env
, csrno
, wpri_val
);
3550 return RISCV_EXCP_NONE
;
3553 static RISCVException
read_umte(CPURISCVState
*env
, int csrno
,
3556 *val
= env
->mmte
& UMTE_MASK
;
3557 return RISCV_EXCP_NONE
;
3560 static RISCVException
write_umte(CPURISCVState
*env
, int csrno
,
3563 target_ulong wpri_val
= val
& UMTE_MASK
;
3565 if (val
!= wpri_val
) {
3566 qemu_log_mask(LOG_GUEST_ERROR
, "%s" TARGET_FMT_lx
" %s" TARGET_FMT_lx
"\n",
3567 "UMTE: WPRI violation written 0x", val
,
3568 "vs expected 0x", wpri_val
);
3571 if (check_pm_current_disabled(env
, csrno
)) {
3572 return RISCV_EXCP_NONE
;
3575 wpri_val
|= (env
->mmte
& ~UMTE_MASK
);
3576 write_mmte(env
, csrno
, wpri_val
);
3577 return RISCV_EXCP_NONE
;
3580 static RISCVException
read_mpmmask(CPURISCVState
*env
, int csrno
,
3583 *val
= env
->mpmmask
;
3584 return RISCV_EXCP_NONE
;
3587 static RISCVException
write_mpmmask(CPURISCVState
*env
, int csrno
,
3593 if ((env
->priv
== PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
3594 env
->cur_pmmask
= val
;
3596 env
->mmte
|= PM_EXT_DIRTY
;
3598 /* Set XS and SD bits, since PM CSRs are dirty */
3599 mstatus
= env
->mstatus
| MSTATUS_XS
;
3600 write_mstatus(env
, csrno
, mstatus
);
3601 return RISCV_EXCP_NONE
;
3604 static RISCVException
read_spmmask(CPURISCVState
*env
, int csrno
,
3607 *val
= env
->spmmask
;
3608 return RISCV_EXCP_NONE
;
3611 static RISCVException
write_spmmask(CPURISCVState
*env
, int csrno
,
3616 /* if pm.current==0 we can't modify current PM CSRs */
3617 if (check_pm_current_disabled(env
, csrno
)) {
3618 return RISCV_EXCP_NONE
;
3621 if ((env
->priv
== PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
3622 env
->cur_pmmask
= val
;
3624 env
->mmte
|= PM_EXT_DIRTY
;
3626 /* Set XS and SD bits, since PM CSRs are dirty */
3627 mstatus
= env
->mstatus
| MSTATUS_XS
;
3628 write_mstatus(env
, csrno
, mstatus
);
3629 return RISCV_EXCP_NONE
;
3632 static RISCVException
read_upmmask(CPURISCVState
*env
, int csrno
,
3635 *val
= env
->upmmask
;
3636 return RISCV_EXCP_NONE
;
3639 static RISCVException
write_upmmask(CPURISCVState
*env
, int csrno
,
3644 /* if pm.current==0 we can't modify current PM CSRs */
3645 if (check_pm_current_disabled(env
, csrno
)) {
3646 return RISCV_EXCP_NONE
;
3649 if ((env
->priv
== PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
3650 env
->cur_pmmask
= val
;
3652 env
->mmte
|= PM_EXT_DIRTY
;
3654 /* Set XS and SD bits, since PM CSRs are dirty */
3655 mstatus
= env
->mstatus
| MSTATUS_XS
;
3656 write_mstatus(env
, csrno
, mstatus
);
3657 return RISCV_EXCP_NONE
;
3660 static RISCVException
read_mpmbase(CPURISCVState
*env
, int csrno
,
3663 *val
= env
->mpmbase
;
3664 return RISCV_EXCP_NONE
;
3667 static RISCVException
write_mpmbase(CPURISCVState
*env
, int csrno
,
3673 if ((env
->priv
== PRV_M
) && (env
->mmte
& M_PM_ENABLE
)) {
3674 env
->cur_pmbase
= val
;
3676 env
->mmte
|= PM_EXT_DIRTY
;
3678 /* Set XS and SD bits, since PM CSRs are dirty */
3679 mstatus
= env
->mstatus
| MSTATUS_XS
;
3680 write_mstatus(env
, csrno
, mstatus
);
3681 return RISCV_EXCP_NONE
;
3684 static RISCVException
read_spmbase(CPURISCVState
*env
, int csrno
,
3687 *val
= env
->spmbase
;
3688 return RISCV_EXCP_NONE
;
3691 static RISCVException
write_spmbase(CPURISCVState
*env
, int csrno
,
3696 /* if pm.current==0 we can't modify current PM CSRs */
3697 if (check_pm_current_disabled(env
, csrno
)) {
3698 return RISCV_EXCP_NONE
;
3701 if ((env
->priv
== PRV_S
) && (env
->mmte
& S_PM_ENABLE
)) {
3702 env
->cur_pmbase
= val
;
3704 env
->mmte
|= PM_EXT_DIRTY
;
3706 /* Set XS and SD bits, since PM CSRs are dirty */
3707 mstatus
= env
->mstatus
| MSTATUS_XS
;
3708 write_mstatus(env
, csrno
, mstatus
);
3709 return RISCV_EXCP_NONE
;
3712 static RISCVException
read_upmbase(CPURISCVState
*env
, int csrno
,
3715 *val
= env
->upmbase
;
3716 return RISCV_EXCP_NONE
;
3719 static RISCVException
write_upmbase(CPURISCVState
*env
, int csrno
,
3724 /* if pm.current==0 we can't modify current PM CSRs */
3725 if (check_pm_current_disabled(env
, csrno
)) {
3726 return RISCV_EXCP_NONE
;
3729 if ((env
->priv
== PRV_U
) && (env
->mmte
& U_PM_ENABLE
)) {
3730 env
->cur_pmbase
= val
;
3732 env
->mmte
|= PM_EXT_DIRTY
;
3734 /* Set XS and SD bits, since PM CSRs are dirty */
3735 mstatus
= env
->mstatus
| MSTATUS_XS
;
3736 write_mstatus(env
, csrno
, mstatus
);
3737 return RISCV_EXCP_NONE
;
3742 /* Crypto Extension */
3743 static RISCVException
rmw_seed(CPURISCVState
*env
, int csrno
,
3744 target_ulong
*ret_value
,
3745 target_ulong new_value
,
3746 target_ulong write_mask
)
3749 Error
*random_e
= NULL
;
3753 random_r
= qemu_guest_getrandom(&random_v
, 2, &random_e
);
3754 if (unlikely(random_r
< 0)) {
3756 * Failed, for unknown reasons in the crypto subsystem.
3757 * The best we can do is log the reason and return a
3758 * failure indication to the guest. There is no reason
3759 * we know to expect the failure to be transitory, so
3760 * indicate DEAD to avoid having the guest spin on WAIT.
3762 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
3763 __func__
, error_get_pretty(random_e
));
3764 error_free(random_e
);
3765 rval
= SEED_OPST_DEAD
;
3767 rval
= random_v
| SEED_OPST_ES16
;
3774 return RISCV_EXCP_NONE
;
3778 * riscv_csrrw - read and/or update control and status register
3780 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
3781 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
3782 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
3783 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
3786 static inline RISCVException
riscv_csrrw_check(CPURISCVState
*env
,
3791 /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
3792 bool read_only
= get_field(csrno
, 0xC00) == 3;
3793 int csr_min_priv
= csr_ops
[csrno
].min_priv_ver
;
3795 /* ensure the CSR extension is enabled */
3796 if (!cpu
->cfg
.ext_icsr
) {
3797 return RISCV_EXCP_ILLEGAL_INST
;
3800 /* privileged spec version check */
3801 if (env
->priv_ver
< csr_min_priv
) {
3802 return RISCV_EXCP_ILLEGAL_INST
;
3805 /* read / write check */
3806 if (write_mask
&& read_only
) {
3807 return RISCV_EXCP_ILLEGAL_INST
;
3811 * The predicate() not only does existence check but also does some
3812 * access control check which triggers for example virtual instruction
3813 * exception in some cases. When writing read-only CSRs in those cases
3814 * illegal instruction exception should be triggered instead of virtual
3815 * instruction exception. Hence this comes after the read / write check.
3817 g_assert(csr_ops
[csrno
].predicate
!= NULL
);
3818 RISCVException ret
= csr_ops
[csrno
].predicate(env
, csrno
);
3819 if (ret
!= RISCV_EXCP_NONE
) {
3823 #if !defined(CONFIG_USER_ONLY)
3824 int csr_priv
, effective_priv
= env
->priv
;
3826 if (riscv_has_ext(env
, RVH
) && env
->priv
== PRV_S
&&
3827 !riscv_cpu_virt_enabled(env
)) {
3829 * We are in HS mode. Add 1 to the effective privledge level to
3830 * allow us to access the Hypervisor CSRs.
3835 csr_priv
= get_field(csrno
, 0x300);
3836 if (!env
->debugger
&& (effective_priv
< csr_priv
)) {
3837 if (csr_priv
== (PRV_S
+ 1) && riscv_cpu_virt_enabled(env
)) {
3838 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
3840 return RISCV_EXCP_ILLEGAL_INST
;
3843 return RISCV_EXCP_NONE
;
3846 static RISCVException
riscv_csrrw_do64(CPURISCVState
*env
, int csrno
,
3847 target_ulong
*ret_value
,
3848 target_ulong new_value
,
3849 target_ulong write_mask
)
3852 target_ulong old_value
;
3854 /* execute combined read/write operation if it exists */
3855 if (csr_ops
[csrno
].op
) {
3856 return csr_ops
[csrno
].op(env
, csrno
, ret_value
, new_value
, write_mask
);
3859 /* if no accessor exists then return failure */
3860 if (!csr_ops
[csrno
].read
) {
3861 return RISCV_EXCP_ILLEGAL_INST
;
3863 /* read old value */
3864 ret
= csr_ops
[csrno
].read(env
, csrno
, &old_value
);
3865 if (ret
!= RISCV_EXCP_NONE
) {
3869 /* write value if writable and write mask set, otherwise drop writes */
3871 new_value
= (old_value
& ~write_mask
) | (new_value
& write_mask
);
3872 if (csr_ops
[csrno
].write
) {
3873 ret
= csr_ops
[csrno
].write(env
, csrno
, new_value
);
3874 if (ret
!= RISCV_EXCP_NONE
) {
3880 /* return old value */
3882 *ret_value
= old_value
;
3885 return RISCV_EXCP_NONE
;
3888 RISCVException
riscv_csrrw(CPURISCVState
*env
, int csrno
,
3889 target_ulong
*ret_value
,
3890 target_ulong new_value
, target_ulong write_mask
)
3892 RISCVCPU
*cpu
= env_archcpu(env
);
3894 RISCVException ret
= riscv_csrrw_check(env
, csrno
, write_mask
, cpu
);
3895 if (ret
!= RISCV_EXCP_NONE
) {
3899 return riscv_csrrw_do64(env
, csrno
, ret_value
, new_value
, write_mask
);
3902 static RISCVException
riscv_csrrw_do128(CPURISCVState
*env
, int csrno
,
3910 /* read old value */
3911 ret
= csr_ops
[csrno
].read128(env
, csrno
, &old_value
);
3912 if (ret
!= RISCV_EXCP_NONE
) {
3916 /* write value if writable and write mask set, otherwise drop writes */
3917 if (int128_nz(write_mask
)) {
3918 new_value
= int128_or(int128_and(old_value
, int128_not(write_mask
)),
3919 int128_and(new_value
, write_mask
));
3920 if (csr_ops
[csrno
].write128
) {
3921 ret
= csr_ops
[csrno
].write128(env
, csrno
, new_value
);
3922 if (ret
!= RISCV_EXCP_NONE
) {
3925 } else if (csr_ops
[csrno
].write
) {
3926 /* avoids having to write wrappers for all registers */
3927 ret
= csr_ops
[csrno
].write(env
, csrno
, int128_getlo(new_value
));
3928 if (ret
!= RISCV_EXCP_NONE
) {
3934 /* return old value */
3936 *ret_value
= old_value
;
3939 return RISCV_EXCP_NONE
;
3942 RISCVException
riscv_csrrw_i128(CPURISCVState
*env
, int csrno
,
3944 Int128 new_value
, Int128 write_mask
)
3947 RISCVCPU
*cpu
= env_archcpu(env
);
3949 ret
= riscv_csrrw_check(env
, csrno
, int128_nz(write_mask
), cpu
);
3950 if (ret
!= RISCV_EXCP_NONE
) {
3954 if (csr_ops
[csrno
].read128
) {
3955 return riscv_csrrw_do128(env
, csrno
, ret_value
, new_value
, write_mask
);
3959 * Fall back to 64-bit version for now, if the 128-bit alternative isn't
3961 * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
3962 * significant), for those, this fallback is correctly handling the accesses
3964 target_ulong old_value
;
3965 ret
= riscv_csrrw_do64(env
, csrno
, &old_value
,
3966 int128_getlo(new_value
),
3967 int128_getlo(write_mask
));
3968 if (ret
== RISCV_EXCP_NONE
&& ret_value
) {
3969 *ret_value
= int128_make64(old_value
);
3975 * Debugger support. If not in user mode, set env->debugger before the
3976 * riscv_csrrw call and clear it after the call.
3978 RISCVException
riscv_csrrw_debug(CPURISCVState
*env
, int csrno
,
3979 target_ulong
*ret_value
,
3980 target_ulong new_value
,
3981 target_ulong write_mask
)
3984 #if !defined(CONFIG_USER_ONLY)
3985 env
->debugger
= true;
3987 ret
= riscv_csrrw(env
, csrno
, ret_value
, new_value
, write_mask
);
3988 #if !defined(CONFIG_USER_ONLY)
3989 env
->debugger
= false;
3994 /* Control and Status Register function table */
3995 riscv_csr_operations csr_ops
[CSR_TABLE_SIZE
] = {
3996 /* User Floating-Point CSRs */
3997 [CSR_FFLAGS
] = { "fflags", fs
, read_fflags
, write_fflags
},
3998 [CSR_FRM
] = { "frm", fs
, read_frm
, write_frm
},
3999 [CSR_FCSR
] = { "fcsr", fs
, read_fcsr
, write_fcsr
},
4001 [CSR_VSTART
] = { "vstart", vs
, read_vstart
, write_vstart
},
4002 [CSR_VXSAT
] = { "vxsat", vs
, read_vxsat
, write_vxsat
},
4003 [CSR_VXRM
] = { "vxrm", vs
, read_vxrm
, write_vxrm
},
4004 [CSR_VCSR
] = { "vcsr", vs
, read_vcsr
, write_vcsr
},
4005 [CSR_VL
] = { "vl", vs
, read_vl
},
4006 [CSR_VTYPE
] = { "vtype", vs
, read_vtype
},
4007 [CSR_VLENB
] = { "vlenb", vs
, read_vlenb
},
4008 /* User Timers and Counters */
4009 [CSR_CYCLE
] = { "cycle", ctr
, read_hpmcounter
},
4010 [CSR_INSTRET
] = { "instret", ctr
, read_hpmcounter
},
4011 [CSR_CYCLEH
] = { "cycleh", ctr32
, read_hpmcounterh
},
4012 [CSR_INSTRETH
] = { "instreth", ctr32
, read_hpmcounterh
},
4015 * In privileged mode, the monitor will have to emulate TIME CSRs only if
4016 * rdtime callback is not provided by machine/platform emulation.
4018 [CSR_TIME
] = { "time", ctr
, read_time
},
4019 [CSR_TIMEH
] = { "timeh", ctr32
, read_timeh
},
4021 /* Crypto Extension */
4022 [CSR_SEED
] = { "seed", seed
, NULL
, NULL
, rmw_seed
},
4024 #if !defined(CONFIG_USER_ONLY)
4025 /* Machine Timers and Counters */
4026 [CSR_MCYCLE
] = { "mcycle", any
, read_hpmcounter
,
4027 write_mhpmcounter
},
4028 [CSR_MINSTRET
] = { "minstret", any
, read_hpmcounter
,
4029 write_mhpmcounter
},
4030 [CSR_MCYCLEH
] = { "mcycleh", any32
, read_hpmcounterh
,
4031 write_mhpmcounterh
},
4032 [CSR_MINSTRETH
] = { "minstreth", any32
, read_hpmcounterh
,
4033 write_mhpmcounterh
},
4035 /* Machine Information Registers */
4036 [CSR_MVENDORID
] = { "mvendorid", any
, read_mvendorid
},
4037 [CSR_MARCHID
] = { "marchid", any
, read_marchid
},
4038 [CSR_MIMPID
] = { "mimpid", any
, read_mimpid
},
4039 [CSR_MHARTID
] = { "mhartid", any
, read_mhartid
},
4041 [CSR_MCONFIGPTR
] = { "mconfigptr", any
, read_zero
,
4042 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4043 /* Machine Trap Setup */
4044 [CSR_MSTATUS
] = { "mstatus", any
, read_mstatus
, write_mstatus
,
4045 NULL
, read_mstatus_i128
},
4046 [CSR_MISA
] = { "misa", any
, read_misa
, write_misa
,
4047 NULL
, read_misa_i128
},
4048 [CSR_MIDELEG
] = { "mideleg", any
, NULL
, NULL
, rmw_mideleg
},
4049 [CSR_MEDELEG
] = { "medeleg", any
, read_medeleg
, write_medeleg
},
4050 [CSR_MIE
] = { "mie", any
, NULL
, NULL
, rmw_mie
},
4051 [CSR_MTVEC
] = { "mtvec", any
, read_mtvec
, write_mtvec
},
4052 [CSR_MCOUNTEREN
] = { "mcounteren", umode
, read_mcounteren
,
4055 [CSR_MSTATUSH
] = { "mstatush", any32
, read_mstatush
,
4058 /* Machine Trap Handling */
4059 [CSR_MSCRATCH
] = { "mscratch", any
, read_mscratch
, write_mscratch
,
4060 NULL
, read_mscratch_i128
, write_mscratch_i128
},
4061 [CSR_MEPC
] = { "mepc", any
, read_mepc
, write_mepc
},
4062 [CSR_MCAUSE
] = { "mcause", any
, read_mcause
, write_mcause
},
4063 [CSR_MTVAL
] = { "mtval", any
, read_mtval
, write_mtval
},
4064 [CSR_MIP
] = { "mip", any
, NULL
, NULL
, rmw_mip
},
4066 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
4067 [CSR_MISELECT
] = { "miselect", aia_any
, NULL
, NULL
, rmw_xiselect
},
4068 [CSR_MIREG
] = { "mireg", aia_any
, NULL
, NULL
, rmw_xireg
},
4070 /* Machine-Level Interrupts (AIA) */
4071 [CSR_MTOPEI
] = { "mtopei", aia_any
, NULL
, NULL
, rmw_xtopei
},
4072 [CSR_MTOPI
] = { "mtopi", aia_any
, read_mtopi
},
4074 /* Virtual Interrupts for Supervisor Level (AIA) */
4075 [CSR_MVIEN
] = { "mvien", aia_any
, read_zero
, write_ignore
},
4076 [CSR_MVIP
] = { "mvip", aia_any
, read_zero
, write_ignore
},
4078 /* Machine-Level High-Half CSRs (AIA) */
4079 [CSR_MIDELEGH
] = { "midelegh", aia_any32
, NULL
, NULL
, rmw_midelegh
},
4080 [CSR_MIEH
] = { "mieh", aia_any32
, NULL
, NULL
, rmw_mieh
},
4081 [CSR_MVIENH
] = { "mvienh", aia_any32
, read_zero
, write_ignore
},
4082 [CSR_MVIPH
] = { "mviph", aia_any32
, read_zero
, write_ignore
},
4083 [CSR_MIPH
] = { "miph", aia_any32
, NULL
, NULL
, rmw_miph
},
4085 /* Execution environment configuration */
4086 [CSR_MENVCFG
] = { "menvcfg", umode
, read_menvcfg
, write_menvcfg
,
4087 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4088 [CSR_MENVCFGH
] = { "menvcfgh", umode32
, read_menvcfgh
, write_menvcfgh
,
4089 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4090 [CSR_SENVCFG
] = { "senvcfg", smode
, read_senvcfg
, write_senvcfg
,
4091 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4092 [CSR_HENVCFG
] = { "henvcfg", hmode
, read_henvcfg
, write_henvcfg
,
4093 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4094 [CSR_HENVCFGH
] = { "henvcfgh", hmode32
, read_henvcfgh
, write_henvcfgh
,
4095 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4097 /* Smstateen extension CSRs */
4098 [CSR_MSTATEEN0
] = { "mstateen0", mstateen
, read_mstateen
, write_mstateen0
,
4099 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4100 [CSR_MSTATEEN0H
] = { "mstateen0h", mstateen
, read_mstateenh
,
4102 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4103 [CSR_MSTATEEN1
] = { "mstateen1", mstateen
, read_mstateen
,
4105 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4106 [CSR_MSTATEEN1H
] = { "mstateen1h", mstateen
, read_mstateenh
,
4107 write_mstateenh_1_3
,
4108 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4109 [CSR_MSTATEEN2
] = { "mstateen2", mstateen
, read_mstateen
,
4111 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4112 [CSR_MSTATEEN2H
] = { "mstateen2h", mstateen
, read_mstateenh
,
4113 write_mstateenh_1_3
,
4114 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4115 [CSR_MSTATEEN3
] = { "mstateen3", mstateen
, read_mstateen
,
4117 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4118 [CSR_MSTATEEN3H
] = { "mstateen3h", mstateen
, read_mstateenh
,
4119 write_mstateenh_1_3
,
4120 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4121 [CSR_HSTATEEN0
] = { "hstateen0", hstateen
, read_hstateen
, write_hstateen0
,
4122 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4123 [CSR_HSTATEEN0H
] = { "hstateen0h", hstateenh
, read_hstateenh
,
4125 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4126 [CSR_HSTATEEN1
] = { "hstateen1", hstateen
, read_hstateen
,
4128 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4129 [CSR_HSTATEEN1H
] = { "hstateen1h", hstateenh
, read_hstateenh
,
4130 write_hstateenh_1_3
,
4131 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4132 [CSR_HSTATEEN2
] = { "hstateen2", hstateen
, read_hstateen
,
4134 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4135 [CSR_HSTATEEN2H
] = { "hstateen2h", hstateenh
, read_hstateenh
,
4136 write_hstateenh_1_3
,
4137 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4138 [CSR_HSTATEEN3
] = { "hstateen3", hstateen
, read_hstateen
,
4140 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4141 [CSR_HSTATEEN3H
] = { "hstateen3h", hstateenh
, read_hstateenh
,
4142 write_hstateenh_1_3
,
4143 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4144 [CSR_SSTATEEN0
] = { "sstateen0", sstateen
, read_sstateen
, write_sstateen0
,
4145 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4146 [CSR_SSTATEEN1
] = { "sstateen1", sstateen
, read_sstateen
,
4148 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4149 [CSR_SSTATEEN2
] = { "sstateen2", sstateen
, read_sstateen
,
4151 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4152 [CSR_SSTATEEN3
] = { "sstateen3", sstateen
, read_sstateen
,
4154 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4156 /* Supervisor Trap Setup */
4157 [CSR_SSTATUS
] = { "sstatus", smode
, read_sstatus
, write_sstatus
,
4158 NULL
, read_sstatus_i128
},
4159 [CSR_SIE
] = { "sie", smode
, NULL
, NULL
, rmw_sie
},
4160 [CSR_STVEC
] = { "stvec", smode
, read_stvec
, write_stvec
},
4161 [CSR_SCOUNTEREN
] = { "scounteren", smode
, read_scounteren
,
4164 /* Supervisor Trap Handling */
4165 [CSR_SSCRATCH
] = { "sscratch", smode
, read_sscratch
, write_sscratch
,
4166 NULL
, read_sscratch_i128
, write_sscratch_i128
},
4167 [CSR_SEPC
] = { "sepc", smode
, read_sepc
, write_sepc
},
4168 [CSR_SCAUSE
] = { "scause", smode
, read_scause
, write_scause
},
4169 [CSR_STVAL
] = { "stval", smode
, read_stval
, write_stval
},
4170 [CSR_SIP
] = { "sip", smode
, NULL
, NULL
, rmw_sip
},
4171 [CSR_STIMECMP
] = { "stimecmp", sstc
, read_stimecmp
, write_stimecmp
,
4172 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4173 [CSR_STIMECMPH
] = { "stimecmph", sstc_32
, read_stimecmph
, write_stimecmph
,
4174 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4175 [CSR_VSTIMECMP
] = { "vstimecmp", sstc
, read_vstimecmp
,
4177 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4178 [CSR_VSTIMECMPH
] = { "vstimecmph", sstc_32
, read_vstimecmph
,
4180 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4182 /* Supervisor Protection and Translation */
4183 [CSR_SATP
] = { "satp", smode
, read_satp
, write_satp
},
4185 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
4186 [CSR_SISELECT
] = { "siselect", aia_smode
, NULL
, NULL
, rmw_xiselect
},
4187 [CSR_SIREG
] = { "sireg", aia_smode
, NULL
, NULL
, rmw_xireg
},
4189 /* Supervisor-Level Interrupts (AIA) */
4190 [CSR_STOPEI
] = { "stopei", aia_smode
, NULL
, NULL
, rmw_xtopei
},
4191 [CSR_STOPI
] = { "stopi", aia_smode
, read_stopi
},
4193 /* Supervisor-Level High-Half CSRs (AIA) */
4194 [CSR_SIEH
] = { "sieh", aia_smode32
, NULL
, NULL
, rmw_sieh
},
4195 [CSR_SIPH
] = { "siph", aia_smode32
, NULL
, NULL
, rmw_siph
},
4197 [CSR_HSTATUS
] = { "hstatus", hmode
, read_hstatus
, write_hstatus
,
4198 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4199 [CSR_HEDELEG
] = { "hedeleg", hmode
, read_hedeleg
, write_hedeleg
,
4200 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4201 [CSR_HIDELEG
] = { "hideleg", hmode
, NULL
, NULL
, rmw_hideleg
,
4202 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4203 [CSR_HVIP
] = { "hvip", hmode
, NULL
, NULL
, rmw_hvip
,
4204 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4205 [CSR_HIP
] = { "hip", hmode
, NULL
, NULL
, rmw_hip
,
4206 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4207 [CSR_HIE
] = { "hie", hmode
, NULL
, NULL
, rmw_hie
,
4208 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4209 [CSR_HCOUNTEREN
] = { "hcounteren", hmode
, read_hcounteren
,
4211 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4212 [CSR_HGEIE
] = { "hgeie", hmode
, read_hgeie
, write_hgeie
,
4213 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4214 [CSR_HTVAL
] = { "htval", hmode
, read_htval
, write_htval
,
4215 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4216 [CSR_HTINST
] = { "htinst", hmode
, read_htinst
, write_htinst
,
4217 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4218 [CSR_HGEIP
] = { "hgeip", hmode
, read_hgeip
,
4219 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4220 [CSR_HGATP
] = { "hgatp", hmode
, read_hgatp
, write_hgatp
,
4221 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4222 [CSR_HTIMEDELTA
] = { "htimedelta", hmode
, read_htimedelta
,
4224 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4225 [CSR_HTIMEDELTAH
] = { "htimedeltah", hmode32
, read_htimedeltah
,
4227 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4229 [CSR_VSSTATUS
] = { "vsstatus", hmode
, read_vsstatus
,
4231 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4232 [CSR_VSIP
] = { "vsip", hmode
, NULL
, NULL
, rmw_vsip
,
4233 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4234 [CSR_VSIE
] = { "vsie", hmode
, NULL
, NULL
, rmw_vsie
,
4235 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4236 [CSR_VSTVEC
] = { "vstvec", hmode
, read_vstvec
, write_vstvec
,
4237 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4238 [CSR_VSSCRATCH
] = { "vsscratch", hmode
, read_vsscratch
,
4240 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4241 [CSR_VSEPC
] = { "vsepc", hmode
, read_vsepc
, write_vsepc
,
4242 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4243 [CSR_VSCAUSE
] = { "vscause", hmode
, read_vscause
, write_vscause
,
4244 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4245 [CSR_VSTVAL
] = { "vstval", hmode
, read_vstval
, write_vstval
,
4246 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4247 [CSR_VSATP
] = { "vsatp", hmode
, read_vsatp
, write_vsatp
,
4248 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4250 [CSR_MTVAL2
] = { "mtval2", hmode
, read_mtval2
, write_mtval2
,
4251 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4252 [CSR_MTINST
] = { "mtinst", hmode
, read_mtinst
, write_mtinst
,
4253 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4255 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
4256 [CSR_HVIEN
] = { "hvien", aia_hmode
, read_zero
, write_ignore
},
4257 [CSR_HVICTL
] = { "hvictl", aia_hmode
, read_hvictl
,
4259 [CSR_HVIPRIO1
] = { "hviprio1", aia_hmode
, read_hviprio1
,
4261 [CSR_HVIPRIO2
] = { "hviprio2", aia_hmode
, read_hviprio2
,
4265 * VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
4267 [CSR_VSISELECT
] = { "vsiselect", aia_hmode
, NULL
, NULL
,
4269 [CSR_VSIREG
] = { "vsireg", aia_hmode
, NULL
, NULL
, rmw_xireg
},
4271 /* VS-Level Interrupts (H-extension with AIA) */
4272 [CSR_VSTOPEI
] = { "vstopei", aia_hmode
, NULL
, NULL
, rmw_xtopei
},
4273 [CSR_VSTOPI
] = { "vstopi", aia_hmode
, read_vstopi
},
4275 /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
4276 [CSR_HIDELEGH
] = { "hidelegh", aia_hmode32
, NULL
, NULL
,
4278 [CSR_HVIENH
] = { "hvienh", aia_hmode32
, read_zero
,
4280 [CSR_HVIPH
] = { "hviph", aia_hmode32
, NULL
, NULL
, rmw_hviph
},
4281 [CSR_HVIPRIO1H
] = { "hviprio1h", aia_hmode32
, read_hviprio1h
,
4283 [CSR_HVIPRIO2H
] = { "hviprio2h", aia_hmode32
, read_hviprio2h
,
4285 [CSR_VSIEH
] = { "vsieh", aia_hmode32
, NULL
, NULL
, rmw_vsieh
},
4286 [CSR_VSIPH
] = { "vsiph", aia_hmode32
, NULL
, NULL
, rmw_vsiph
},
4288 /* Physical Memory Protection */
4289 [CSR_MSECCFG
] = { "mseccfg", epmp
, read_mseccfg
, write_mseccfg
,
4290 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4291 [CSR_PMPCFG0
] = { "pmpcfg0", pmp
, read_pmpcfg
, write_pmpcfg
},
4292 [CSR_PMPCFG1
] = { "pmpcfg1", pmp
, read_pmpcfg
, write_pmpcfg
},
4293 [CSR_PMPCFG2
] = { "pmpcfg2", pmp
, read_pmpcfg
, write_pmpcfg
},
4294 [CSR_PMPCFG3
] = { "pmpcfg3", pmp
, read_pmpcfg
, write_pmpcfg
},
4295 [CSR_PMPADDR0
] = { "pmpaddr0", pmp
, read_pmpaddr
, write_pmpaddr
},
4296 [CSR_PMPADDR1
] = { "pmpaddr1", pmp
, read_pmpaddr
, write_pmpaddr
},
4297 [CSR_PMPADDR2
] = { "pmpaddr2", pmp
, read_pmpaddr
, write_pmpaddr
},
4298 [CSR_PMPADDR3
] = { "pmpaddr3", pmp
, read_pmpaddr
, write_pmpaddr
},
4299 [CSR_PMPADDR4
] = { "pmpaddr4", pmp
, read_pmpaddr
, write_pmpaddr
},
4300 [CSR_PMPADDR5
] = { "pmpaddr5", pmp
, read_pmpaddr
, write_pmpaddr
},
4301 [CSR_PMPADDR6
] = { "pmpaddr6", pmp
, read_pmpaddr
, write_pmpaddr
},
4302 [CSR_PMPADDR7
] = { "pmpaddr7", pmp
, read_pmpaddr
, write_pmpaddr
},
4303 [CSR_PMPADDR8
] = { "pmpaddr8", pmp
, read_pmpaddr
, write_pmpaddr
},
4304 [CSR_PMPADDR9
] = { "pmpaddr9", pmp
, read_pmpaddr
, write_pmpaddr
},
4305 [CSR_PMPADDR10
] = { "pmpaddr10", pmp
, read_pmpaddr
, write_pmpaddr
},
4306 [CSR_PMPADDR11
] = { "pmpaddr11", pmp
, read_pmpaddr
, write_pmpaddr
},
4307 [CSR_PMPADDR12
] = { "pmpaddr12", pmp
, read_pmpaddr
, write_pmpaddr
},
4308 [CSR_PMPADDR13
] = { "pmpaddr13", pmp
, read_pmpaddr
, write_pmpaddr
},
4309 [CSR_PMPADDR14
] = { "pmpaddr14", pmp
, read_pmpaddr
, write_pmpaddr
},
4310 [CSR_PMPADDR15
] = { "pmpaddr15", pmp
, read_pmpaddr
, write_pmpaddr
},
4313 [CSR_TSELECT
] = { "tselect", debug
, read_tselect
, write_tselect
},
4314 [CSR_TDATA1
] = { "tdata1", debug
, read_tdata
, write_tdata
},
4315 [CSR_TDATA2
] = { "tdata2", debug
, read_tdata
, write_tdata
},
4316 [CSR_TDATA3
] = { "tdata3", debug
, read_tdata
, write_tdata
},
4317 [CSR_TINFO
] = { "tinfo", debug
, read_tinfo
, write_ignore
},
4319 /* User Pointer Masking */
4320 [CSR_UMTE
] = { "umte", pointer_masking
, read_umte
, write_umte
},
4321 [CSR_UPMMASK
] = { "upmmask", pointer_masking
, read_upmmask
,
4323 [CSR_UPMBASE
] = { "upmbase", pointer_masking
, read_upmbase
,
4325 /* Machine Pointer Masking */
4326 [CSR_MMTE
] = { "mmte", pointer_masking
, read_mmte
, write_mmte
},
4327 [CSR_MPMMASK
] = { "mpmmask", pointer_masking
, read_mpmmask
,
4329 [CSR_MPMBASE
] = { "mpmbase", pointer_masking
, read_mpmbase
,
4331 /* Supervisor Pointer Masking */
4332 [CSR_SMTE
] = { "smte", pointer_masking
, read_smte
, write_smte
},
4333 [CSR_SPMMASK
] = { "spmmask", pointer_masking
, read_spmmask
,
4335 [CSR_SPMBASE
] = { "spmbase", pointer_masking
, read_spmbase
,
4338 /* Performance Counters */
4339 [CSR_HPMCOUNTER3
] = { "hpmcounter3", ctr
, read_hpmcounter
},
4340 [CSR_HPMCOUNTER4
] = { "hpmcounter4", ctr
, read_hpmcounter
},
4341 [CSR_HPMCOUNTER5
] = { "hpmcounter5", ctr
, read_hpmcounter
},
4342 [CSR_HPMCOUNTER6
] = { "hpmcounter6", ctr
, read_hpmcounter
},
4343 [CSR_HPMCOUNTER7
] = { "hpmcounter7", ctr
, read_hpmcounter
},
4344 [CSR_HPMCOUNTER8
] = { "hpmcounter8", ctr
, read_hpmcounter
},
4345 [CSR_HPMCOUNTER9
] = { "hpmcounter9", ctr
, read_hpmcounter
},
4346 [CSR_HPMCOUNTER10
] = { "hpmcounter10", ctr
, read_hpmcounter
},
4347 [CSR_HPMCOUNTER11
] = { "hpmcounter11", ctr
, read_hpmcounter
},
4348 [CSR_HPMCOUNTER12
] = { "hpmcounter12", ctr
, read_hpmcounter
},
4349 [CSR_HPMCOUNTER13
] = { "hpmcounter13", ctr
, read_hpmcounter
},
4350 [CSR_HPMCOUNTER14
] = { "hpmcounter14", ctr
, read_hpmcounter
},
4351 [CSR_HPMCOUNTER15
] = { "hpmcounter15", ctr
, read_hpmcounter
},
4352 [CSR_HPMCOUNTER16
] = { "hpmcounter16", ctr
, read_hpmcounter
},
4353 [CSR_HPMCOUNTER17
] = { "hpmcounter17", ctr
, read_hpmcounter
},
4354 [CSR_HPMCOUNTER18
] = { "hpmcounter18", ctr
, read_hpmcounter
},
4355 [CSR_HPMCOUNTER19
] = { "hpmcounter19", ctr
, read_hpmcounter
},
4356 [CSR_HPMCOUNTER20
] = { "hpmcounter20", ctr
, read_hpmcounter
},
4357 [CSR_HPMCOUNTER21
] = { "hpmcounter21", ctr
, read_hpmcounter
},
4358 [CSR_HPMCOUNTER22
] = { "hpmcounter22", ctr
, read_hpmcounter
},
4359 [CSR_HPMCOUNTER23
] = { "hpmcounter23", ctr
, read_hpmcounter
},
4360 [CSR_HPMCOUNTER24
] = { "hpmcounter24", ctr
, read_hpmcounter
},
4361 [CSR_HPMCOUNTER25
] = { "hpmcounter25", ctr
, read_hpmcounter
},
4362 [CSR_HPMCOUNTER26
] = { "hpmcounter26", ctr
, read_hpmcounter
},
4363 [CSR_HPMCOUNTER27
] = { "hpmcounter27", ctr
, read_hpmcounter
},
4364 [CSR_HPMCOUNTER28
] = { "hpmcounter28", ctr
, read_hpmcounter
},
4365 [CSR_HPMCOUNTER29
] = { "hpmcounter29", ctr
, read_hpmcounter
},
4366 [CSR_HPMCOUNTER30
] = { "hpmcounter30", ctr
, read_hpmcounter
},
4367 [CSR_HPMCOUNTER31
] = { "hpmcounter31", ctr
, read_hpmcounter
},
4369 [CSR_MHPMCOUNTER3
] = { "mhpmcounter3", mctr
, read_hpmcounter
,
4370 write_mhpmcounter
},
4371 [CSR_MHPMCOUNTER4
] = { "mhpmcounter4", mctr
, read_hpmcounter
,
4372 write_mhpmcounter
},
4373 [CSR_MHPMCOUNTER5
] = { "mhpmcounter5", mctr
, read_hpmcounter
,
4374 write_mhpmcounter
},
4375 [CSR_MHPMCOUNTER6
] = { "mhpmcounter6", mctr
, read_hpmcounter
,
4376 write_mhpmcounter
},
4377 [CSR_MHPMCOUNTER7
] = { "mhpmcounter7", mctr
, read_hpmcounter
,
4378 write_mhpmcounter
},
4379 [CSR_MHPMCOUNTER8
] = { "mhpmcounter8", mctr
, read_hpmcounter
,
4380 write_mhpmcounter
},
4381 [CSR_MHPMCOUNTER9
] = { "mhpmcounter9", mctr
, read_hpmcounter
,
4382 write_mhpmcounter
},
4383 [CSR_MHPMCOUNTER10
] = { "mhpmcounter10", mctr
, read_hpmcounter
,
4384 write_mhpmcounter
},
4385 [CSR_MHPMCOUNTER11
] = { "mhpmcounter11", mctr
, read_hpmcounter
,
4386 write_mhpmcounter
},
4387 [CSR_MHPMCOUNTER12
] = { "mhpmcounter12", mctr
, read_hpmcounter
,
4388 write_mhpmcounter
},
4389 [CSR_MHPMCOUNTER13
] = { "mhpmcounter13", mctr
, read_hpmcounter
,
4390 write_mhpmcounter
},
4391 [CSR_MHPMCOUNTER14
] = { "mhpmcounter14", mctr
, read_hpmcounter
,
4392 write_mhpmcounter
},
4393 [CSR_MHPMCOUNTER15
] = { "mhpmcounter15", mctr
, read_hpmcounter
,
4394 write_mhpmcounter
},
4395 [CSR_MHPMCOUNTER16
] = { "mhpmcounter16", mctr
, read_hpmcounter
,
4396 write_mhpmcounter
},
4397 [CSR_MHPMCOUNTER17
] = { "mhpmcounter17", mctr
, read_hpmcounter
,
4398 write_mhpmcounter
},
4399 [CSR_MHPMCOUNTER18
] = { "mhpmcounter18", mctr
, read_hpmcounter
,
4400 write_mhpmcounter
},
4401 [CSR_MHPMCOUNTER19
] = { "mhpmcounter19", mctr
, read_hpmcounter
,
4402 write_mhpmcounter
},
4403 [CSR_MHPMCOUNTER20
] = { "mhpmcounter20", mctr
, read_hpmcounter
,
4404 write_mhpmcounter
},
4405 [CSR_MHPMCOUNTER21
] = { "mhpmcounter21", mctr
, read_hpmcounter
,
4406 write_mhpmcounter
},
4407 [CSR_MHPMCOUNTER22
] = { "mhpmcounter22", mctr
, read_hpmcounter
,
4408 write_mhpmcounter
},
4409 [CSR_MHPMCOUNTER23
] = { "mhpmcounter23", mctr
, read_hpmcounter
,
4410 write_mhpmcounter
},
4411 [CSR_MHPMCOUNTER24
] = { "mhpmcounter24", mctr
, read_hpmcounter
,
4412 write_mhpmcounter
},
4413 [CSR_MHPMCOUNTER25
] = { "mhpmcounter25", mctr
, read_hpmcounter
,
4414 write_mhpmcounter
},
4415 [CSR_MHPMCOUNTER26
] = { "mhpmcounter26", mctr
, read_hpmcounter
,
4416 write_mhpmcounter
},
4417 [CSR_MHPMCOUNTER27
] = { "mhpmcounter27", mctr
, read_hpmcounter
,
4418 write_mhpmcounter
},
4419 [CSR_MHPMCOUNTER28
] = { "mhpmcounter28", mctr
, read_hpmcounter
,
4420 write_mhpmcounter
},
4421 [CSR_MHPMCOUNTER29
] = { "mhpmcounter29", mctr
, read_hpmcounter
,
4422 write_mhpmcounter
},
4423 [CSR_MHPMCOUNTER30
] = { "mhpmcounter30", mctr
, read_hpmcounter
,
4424 write_mhpmcounter
},
4425 [CSR_MHPMCOUNTER31
] = { "mhpmcounter31", mctr
, read_hpmcounter
,
4426 write_mhpmcounter
},
4428 [CSR_MCOUNTINHIBIT
] = { "mcountinhibit", any
, read_mcountinhibit
,
4429 write_mcountinhibit
,
4430 .min_priv_ver
= PRIV_VERSION_1_11_0
},
4432 [CSR_MHPMEVENT3
] = { "mhpmevent3", any
, read_mhpmevent
,
4434 [CSR_MHPMEVENT4
] = { "mhpmevent4", any
, read_mhpmevent
,
4436 [CSR_MHPMEVENT5
] = { "mhpmevent5", any
, read_mhpmevent
,
4438 [CSR_MHPMEVENT6
] = { "mhpmevent6", any
, read_mhpmevent
,
4440 [CSR_MHPMEVENT7
] = { "mhpmevent7", any
, read_mhpmevent
,
4442 [CSR_MHPMEVENT8
] = { "mhpmevent8", any
, read_mhpmevent
,
4444 [CSR_MHPMEVENT9
] = { "mhpmevent9", any
, read_mhpmevent
,
4446 [CSR_MHPMEVENT10
] = { "mhpmevent10", any
, read_mhpmevent
,
4448 [CSR_MHPMEVENT11
] = { "mhpmevent11", any
, read_mhpmevent
,
4450 [CSR_MHPMEVENT12
] = { "mhpmevent12", any
, read_mhpmevent
,
4452 [CSR_MHPMEVENT13
] = { "mhpmevent13", any
, read_mhpmevent
,
4454 [CSR_MHPMEVENT14
] = { "mhpmevent14", any
, read_mhpmevent
,
4456 [CSR_MHPMEVENT15
] = { "mhpmevent15", any
, read_mhpmevent
,
4458 [CSR_MHPMEVENT16
] = { "mhpmevent16", any
, read_mhpmevent
,
4460 [CSR_MHPMEVENT17
] = { "mhpmevent17", any
, read_mhpmevent
,
4462 [CSR_MHPMEVENT18
] = { "mhpmevent18", any
, read_mhpmevent
,
4464 [CSR_MHPMEVENT19
] = { "mhpmevent19", any
, read_mhpmevent
,
4466 [CSR_MHPMEVENT20
] = { "mhpmevent20", any
, read_mhpmevent
,
4468 [CSR_MHPMEVENT21
] = { "mhpmevent21", any
, read_mhpmevent
,
4470 [CSR_MHPMEVENT22
] = { "mhpmevent22", any
, read_mhpmevent
,
4472 [CSR_MHPMEVENT23
] = { "mhpmevent23", any
, read_mhpmevent
,
4474 [CSR_MHPMEVENT24
] = { "mhpmevent24", any
, read_mhpmevent
,
4476 [CSR_MHPMEVENT25
] = { "mhpmevent25", any
, read_mhpmevent
,
4478 [CSR_MHPMEVENT26
] = { "mhpmevent26", any
, read_mhpmevent
,
4480 [CSR_MHPMEVENT27
] = { "mhpmevent27", any
, read_mhpmevent
,
4482 [CSR_MHPMEVENT28
] = { "mhpmevent28", any
, read_mhpmevent
,
4484 [CSR_MHPMEVENT29
] = { "mhpmevent29", any
, read_mhpmevent
,
4486 [CSR_MHPMEVENT30
] = { "mhpmevent30", any
, read_mhpmevent
,
4488 [CSR_MHPMEVENT31
] = { "mhpmevent31", any
, read_mhpmevent
,
4491 [CSR_MHPMEVENT3H
] = { "mhpmevent3h", sscofpmf
, read_mhpmeventh
,
4493 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4494 [CSR_MHPMEVENT4H
] = { "mhpmevent4h", sscofpmf
, read_mhpmeventh
,
4496 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4497 [CSR_MHPMEVENT5H
] = { "mhpmevent5h", sscofpmf
, read_mhpmeventh
,
4499 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4500 [CSR_MHPMEVENT6H
] = { "mhpmevent6h", sscofpmf
, read_mhpmeventh
,
4502 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4503 [CSR_MHPMEVENT7H
] = { "mhpmevent7h", sscofpmf
, read_mhpmeventh
,
4505 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4506 [CSR_MHPMEVENT8H
] = { "mhpmevent8h", sscofpmf
, read_mhpmeventh
,
4508 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4509 [CSR_MHPMEVENT9H
] = { "mhpmevent9h", sscofpmf
, read_mhpmeventh
,
4511 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4512 [CSR_MHPMEVENT10H
] = { "mhpmevent10h", sscofpmf
, read_mhpmeventh
,
4514 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4515 [CSR_MHPMEVENT11H
] = { "mhpmevent11h", sscofpmf
, read_mhpmeventh
,
4517 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4518 [CSR_MHPMEVENT12H
] = { "mhpmevent12h", sscofpmf
, read_mhpmeventh
,
4520 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4521 [CSR_MHPMEVENT13H
] = { "mhpmevent13h", sscofpmf
, read_mhpmeventh
,
4523 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4524 [CSR_MHPMEVENT14H
] = { "mhpmevent14h", sscofpmf
, read_mhpmeventh
,
4526 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4527 [CSR_MHPMEVENT15H
] = { "mhpmevent15h", sscofpmf
, read_mhpmeventh
,
4529 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4530 [CSR_MHPMEVENT16H
] = { "mhpmevent16h", sscofpmf
, read_mhpmeventh
,
4532 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4533 [CSR_MHPMEVENT17H
] = { "mhpmevent17h", sscofpmf
, read_mhpmeventh
,
4535 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4536 [CSR_MHPMEVENT18H
] = { "mhpmevent18h", sscofpmf
, read_mhpmeventh
,
4538 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4539 [CSR_MHPMEVENT19H
] = { "mhpmevent19h", sscofpmf
, read_mhpmeventh
,
4541 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4542 [CSR_MHPMEVENT20H
] = { "mhpmevent20h", sscofpmf
, read_mhpmeventh
,
4544 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4545 [CSR_MHPMEVENT21H
] = { "mhpmevent21h", sscofpmf
, read_mhpmeventh
,
4547 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4548 [CSR_MHPMEVENT22H
] = { "mhpmevent22h", sscofpmf
, read_mhpmeventh
,
4550 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4551 [CSR_MHPMEVENT23H
] = { "mhpmevent23h", sscofpmf
, read_mhpmeventh
,
4553 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4554 [CSR_MHPMEVENT24H
] = { "mhpmevent24h", sscofpmf
, read_mhpmeventh
,
4556 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4557 [CSR_MHPMEVENT25H
] = { "mhpmevent25h", sscofpmf
, read_mhpmeventh
,
4559 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4560 [CSR_MHPMEVENT26H
] = { "mhpmevent26h", sscofpmf
, read_mhpmeventh
,
4562 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4563 [CSR_MHPMEVENT27H
] = { "mhpmevent27h", sscofpmf
, read_mhpmeventh
,
4565 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4566 [CSR_MHPMEVENT28H
] = { "mhpmevent28h", sscofpmf
, read_mhpmeventh
,
4568 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4569 [CSR_MHPMEVENT29H
] = { "mhpmevent29h", sscofpmf
, read_mhpmeventh
,
4571 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4572 [CSR_MHPMEVENT30H
] = { "mhpmevent30h", sscofpmf
, read_mhpmeventh
,
4574 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4575 [CSR_MHPMEVENT31H
] = { "mhpmevent31h", sscofpmf
, read_mhpmeventh
,
4577 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4579 [CSR_HPMCOUNTER3H
] = { "hpmcounter3h", ctr32
, read_hpmcounterh
},
4580 [CSR_HPMCOUNTER4H
] = { "hpmcounter4h", ctr32
, read_hpmcounterh
},
4581 [CSR_HPMCOUNTER5H
] = { "hpmcounter5h", ctr32
, read_hpmcounterh
},
4582 [CSR_HPMCOUNTER6H
] = { "hpmcounter6h", ctr32
, read_hpmcounterh
},
4583 [CSR_HPMCOUNTER7H
] = { "hpmcounter7h", ctr32
, read_hpmcounterh
},
4584 [CSR_HPMCOUNTER8H
] = { "hpmcounter8h", ctr32
, read_hpmcounterh
},
4585 [CSR_HPMCOUNTER9H
] = { "hpmcounter9h", ctr32
, read_hpmcounterh
},
4586 [CSR_HPMCOUNTER10H
] = { "hpmcounter10h", ctr32
, read_hpmcounterh
},
4587 [CSR_HPMCOUNTER11H
] = { "hpmcounter11h", ctr32
, read_hpmcounterh
},
4588 [CSR_HPMCOUNTER12H
] = { "hpmcounter12h", ctr32
, read_hpmcounterh
},
4589 [CSR_HPMCOUNTER13H
] = { "hpmcounter13h", ctr32
, read_hpmcounterh
},
4590 [CSR_HPMCOUNTER14H
] = { "hpmcounter14h", ctr32
, read_hpmcounterh
},
4591 [CSR_HPMCOUNTER15H
] = { "hpmcounter15h", ctr32
, read_hpmcounterh
},
4592 [CSR_HPMCOUNTER16H
] = { "hpmcounter16h", ctr32
, read_hpmcounterh
},
4593 [CSR_HPMCOUNTER17H
] = { "hpmcounter17h", ctr32
, read_hpmcounterh
},
4594 [CSR_HPMCOUNTER18H
] = { "hpmcounter18h", ctr32
, read_hpmcounterh
},
4595 [CSR_HPMCOUNTER19H
] = { "hpmcounter19h", ctr32
, read_hpmcounterh
},
4596 [CSR_HPMCOUNTER20H
] = { "hpmcounter20h", ctr32
, read_hpmcounterh
},
4597 [CSR_HPMCOUNTER21H
] = { "hpmcounter21h", ctr32
, read_hpmcounterh
},
4598 [CSR_HPMCOUNTER22H
] = { "hpmcounter22h", ctr32
, read_hpmcounterh
},
4599 [CSR_HPMCOUNTER23H
] = { "hpmcounter23h", ctr32
, read_hpmcounterh
},
4600 [CSR_HPMCOUNTER24H
] = { "hpmcounter24h", ctr32
, read_hpmcounterh
},
4601 [CSR_HPMCOUNTER25H
] = { "hpmcounter25h", ctr32
, read_hpmcounterh
},
4602 [CSR_HPMCOUNTER26H
] = { "hpmcounter26h", ctr32
, read_hpmcounterh
},
4603 [CSR_HPMCOUNTER27H
] = { "hpmcounter27h", ctr32
, read_hpmcounterh
},
4604 [CSR_HPMCOUNTER28H
] = { "hpmcounter28h", ctr32
, read_hpmcounterh
},
4605 [CSR_HPMCOUNTER29H
] = { "hpmcounter29h", ctr32
, read_hpmcounterh
},
4606 [CSR_HPMCOUNTER30H
] = { "hpmcounter30h", ctr32
, read_hpmcounterh
},
4607 [CSR_HPMCOUNTER31H
] = { "hpmcounter31h", ctr32
, read_hpmcounterh
},
4609 [CSR_MHPMCOUNTER3H
] = { "mhpmcounter3h", mctr32
, read_hpmcounterh
,
4610 write_mhpmcounterh
},
4611 [CSR_MHPMCOUNTER4H
] = { "mhpmcounter4h", mctr32
, read_hpmcounterh
,
4612 write_mhpmcounterh
},
4613 [CSR_MHPMCOUNTER5H
] = { "mhpmcounter5h", mctr32
, read_hpmcounterh
,
4614 write_mhpmcounterh
},
4615 [CSR_MHPMCOUNTER6H
] = { "mhpmcounter6h", mctr32
, read_hpmcounterh
,
4616 write_mhpmcounterh
},
4617 [CSR_MHPMCOUNTER7H
] = { "mhpmcounter7h", mctr32
, read_hpmcounterh
,
4618 write_mhpmcounterh
},
4619 [CSR_MHPMCOUNTER8H
] = { "mhpmcounter8h", mctr32
, read_hpmcounterh
,
4620 write_mhpmcounterh
},
4621 [CSR_MHPMCOUNTER9H
] = { "mhpmcounter9h", mctr32
, read_hpmcounterh
,
4622 write_mhpmcounterh
},
4623 [CSR_MHPMCOUNTER10H
] = { "mhpmcounter10h", mctr32
, read_hpmcounterh
,
4624 write_mhpmcounterh
},
4625 [CSR_MHPMCOUNTER11H
] = { "mhpmcounter11h", mctr32
, read_hpmcounterh
,
4626 write_mhpmcounterh
},
4627 [CSR_MHPMCOUNTER12H
] = { "mhpmcounter12h", mctr32
, read_hpmcounterh
,
4628 write_mhpmcounterh
},
4629 [CSR_MHPMCOUNTER13H
] = { "mhpmcounter13h", mctr32
, read_hpmcounterh
,
4630 write_mhpmcounterh
},
4631 [CSR_MHPMCOUNTER14H
] = { "mhpmcounter14h", mctr32
, read_hpmcounterh
,
4632 write_mhpmcounterh
},
4633 [CSR_MHPMCOUNTER15H
] = { "mhpmcounter15h", mctr32
, read_hpmcounterh
,
4634 write_mhpmcounterh
},
4635 [CSR_MHPMCOUNTER16H
] = { "mhpmcounter16h", mctr32
, read_hpmcounterh
,
4636 write_mhpmcounterh
},
4637 [CSR_MHPMCOUNTER17H
] = { "mhpmcounter17h", mctr32
, read_hpmcounterh
,
4638 write_mhpmcounterh
},
4639 [CSR_MHPMCOUNTER18H
] = { "mhpmcounter18h", mctr32
, read_hpmcounterh
,
4640 write_mhpmcounterh
},
4641 [CSR_MHPMCOUNTER19H
] = { "mhpmcounter19h", mctr32
, read_hpmcounterh
,
4642 write_mhpmcounterh
},
4643 [CSR_MHPMCOUNTER20H
] = { "mhpmcounter20h", mctr32
, read_hpmcounterh
,
4644 write_mhpmcounterh
},
4645 [CSR_MHPMCOUNTER21H
] = { "mhpmcounter21h", mctr32
, read_hpmcounterh
,
4646 write_mhpmcounterh
},
4647 [CSR_MHPMCOUNTER22H
] = { "mhpmcounter22h", mctr32
, read_hpmcounterh
,
4648 write_mhpmcounterh
},
4649 [CSR_MHPMCOUNTER23H
] = { "mhpmcounter23h", mctr32
, read_hpmcounterh
,
4650 write_mhpmcounterh
},
4651 [CSR_MHPMCOUNTER24H
] = { "mhpmcounter24h", mctr32
, read_hpmcounterh
,
4652 write_mhpmcounterh
},
4653 [CSR_MHPMCOUNTER25H
] = { "mhpmcounter25h", mctr32
, read_hpmcounterh
,
4654 write_mhpmcounterh
},
4655 [CSR_MHPMCOUNTER26H
] = { "mhpmcounter26h", mctr32
, read_hpmcounterh
,
4656 write_mhpmcounterh
},
4657 [CSR_MHPMCOUNTER27H
] = { "mhpmcounter27h", mctr32
, read_hpmcounterh
,
4658 write_mhpmcounterh
},
4659 [CSR_MHPMCOUNTER28H
] = { "mhpmcounter28h", mctr32
, read_hpmcounterh
,
4660 write_mhpmcounterh
},
4661 [CSR_MHPMCOUNTER29H
] = { "mhpmcounter29h", mctr32
, read_hpmcounterh
,
4662 write_mhpmcounterh
},
4663 [CSR_MHPMCOUNTER30H
] = { "mhpmcounter30h", mctr32
, read_hpmcounterh
,
4664 write_mhpmcounterh
},
4665 [CSR_MHPMCOUNTER31H
] = { "mhpmcounter31h", mctr32
, read_hpmcounterh
,
4666 write_mhpmcounterh
},
4667 [CSR_SCOUNTOVF
] = { "scountovf", sscofpmf
, read_scountovf
,
4668 .min_priv_ver
= PRIV_VERSION_1_12_0
},
4670 #endif /* !CONFIG_USER_ONLY */