target/riscv/insn32-64.decode

   1 #
   2 # RISC-V translation routines for the RV Instruction Set.
   3 #
   4 # Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
   5 #                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
   6 #
   7 # This program is free software; you can redistribute it and/or modify it
   8 # under the terms and conditions of the GNU General Public License,
   9 # version 2 or later, as published by the Free Software Foundation.
  10 #
  11 # This program is distributed in the hope it will be useful, but WITHOUT
  12 # ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 # FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 # more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along with
  17 # this program.  If not, see <http://www.gnu.org/licenses/>.
  18
  19 # This is concatenated with insn32.decode for risc64 targets.
  20 # Most of the fields and formats are there.
  21
  22 %sh5    20:5
  23
  24 @sh5     .......  ..... .....  ... ..... ....... &shift  shamt=%sh5      %rs1 %rd
  25
  26 # *** RV64I Base Instruction Set (in addition to RV32I) ***
  27 lwu      ............   ..... 110 ..... 0000011 @i
  28 ld       ............   ..... 011 ..... 0000011 @i
  29 sd       ....... .....  ..... 011 ..... 0100011 @s
  30 addiw    ............   ..... 000 ..... 0011011 @i
  31 slliw    0000000 .....  ..... 001 ..... 0011011 @sh5
  32 srliw    0000000 .....  ..... 101 ..... 0011011 @sh5
  33 sraiw    0100000 .....  ..... 101 ..... 0011011 @sh5
  34 addw     0000000 .....  ..... 000 ..... 0111011 @r
  35 subw     0100000 .....  ..... 000 ..... 0111011 @r
  36 sllw     0000000 .....  ..... 001 ..... 0111011 @r
  37 srlw     0000000 .....  ..... 101 ..... 0111011 @r
  38 sraw     0100000 .....  ..... 101 ..... 0111011 @r
  39
  40 # *** RV64M Standard Extension (in addition to RV32M) ***
  41 mulw     0000001 .....  ..... 000 ..... 0111011 @r
  42 divw     0000001 .....  ..... 100 ..... 0111011 @r
  43 divuw    0000001 .....  ..... 101 ..... 0111011 @r
  44 remw     0000001 .....  ..... 110 ..... 0111011 @r
  45 remuw    0000001 .....  ..... 111 ..... 0111011 @r
  46
  47 # *** RV64A Standard Extension (in addition to RV32A) ***
  48 lr_d       00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
  49 sc_d       00011 . . ..... ..... 011 ..... 0101111 @atom_st
  50 amoswap_d  00001 . . ..... ..... 011 ..... 0101111 @atom_st
  51 amoadd_d   00000 . . ..... ..... 011 ..... 0101111 @atom_st
  52 amoxor_d   00100 . . ..... ..... 011 ..... 0101111 @atom_st
  53 amoand_d   01100 . . ..... ..... 011 ..... 0101111 @atom_st
  54 amoor_d    01000 . . ..... ..... 011 ..... 0101111 @atom_st
  55 amomin_d   10000 . . ..... ..... 011 ..... 0101111 @atom_st
  56 amomax_d   10100 . . ..... ..... 011 ..... 0101111 @atom_st
  57 amominu_d  11000 . . ..... ..... 011 ..... 0101111 @atom_st
  58 amomaxu_d  11100 . . ..... ..... 011 ..... 0101111 @atom_st
  59
  60 # *** RV64F Standard Extension (in addition to RV32F) ***
  61 fcvt_l_s   1100000  00010 ..... ... ..... 1010011 @r2_rm
  62 fcvt_lu_s  1100000  00011 ..... ... ..... 1010011 @r2_rm
  63 fcvt_s_l   1101000  00010 ..... ... ..... 1010011 @r2_rm
  64 fcvt_s_lu  1101000  00011 ..... ... ..... 1010011 @r2_rm
  65
  66 # *** RV64D Standard Extension (in addition to RV32D) ***
  67 fcvt_l_d   1100001  00010 ..... ... ..... 1010011 @r2_rm
  68 fcvt_lu_d  1100001  00011 ..... ... ..... 1010011 @r2_rm
  69 fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
  70 fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
  71 fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
  72 fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2