2 * S/390 virtual CPU header
4 * For details on the s390x architecture and used definitions (e.g.,
5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to
6 * the "z/Architecture Principles of Operations" - a.k.a. PoP.
8 * Copyright (c) 2009 Ulrich Hecht
9 * Copyright IBM Corp. 2012, 2018
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
29 #include "cpu_models.h"
30 #include "exec/cpu-defs.h"
31 #include "qemu/cpu-float.h"
32 #include "qapi/qapi-types-machine-common.h"
34 #define ELF_MACHINE_UNAME "S390X"
36 #define TARGET_HAS_PRECISE_SMC
38 #define TARGET_INSN_START_EXTRA_WORDS 2
40 #define MMU_USER_IDX 0
42 #define S390_MAX_CPUS 248
45 #define S390_ADAPTER_SUPPRESSIBLE 0x01
47 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
55 typedef struct CPUArchState
{
56 uint64_t regs
[16]; /* GP registers */
58 * The floating point registers are part of the vector registers.
59 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
61 uint64_t vregs
[32][2] QEMU_ALIGNED(16); /* vector registers */
62 uint32_t aregs
[16]; /* access registers */
63 uint64_t gscb
[4]; /* guarded storage control */
64 uint64_t etoken
; /* etoken */
65 uint64_t etoken_extension
; /* etoken extension */
67 uint64_t diag318_info
;
69 /* Fields up to this point are not cleared by initial CPU reset */
70 struct {} start_initial_reset_fields
;
72 uint32_t fpc
; /* floating-point control register */
74 bool bpbc
; /* branch prediction blocking */
76 float_status fpu_status
; /* passed to softfloat lib */
80 S390CrashReason crash_reason
;
92 uint32_t int_pgm_code
;
93 uint32_t int_pgm_ilen
;
95 uint32_t int_svc_code
;
96 uint32_t int_svc_ilen
;
99 uint16_t per_perc_atmid
;
101 uint64_t cregs
[16]; /* control registers */
107 uint64_t pfault_token
;
108 uint64_t pfault_compare
;
109 uint64_t pfault_select
;
114 /* Fields up to this point are not cleared by normal CPU reset */
115 struct {} start_normal_reset_fields
;
116 uint8_t riccb
[64]; /* runtime instrumentation control */
119 uint16_t external_call_addr
;
120 DECLARE_BITMAP(emergency_signals
, S390_MAX_CPUS
);
122 #if !defined(CONFIG_USER_ONLY)
123 uint64_t tlb_fill_tec
; /* translation exception code during tlb_fill */
124 int tlb_fill_exc
; /* exception number seen during tlb_fill */
127 /* Fields up to this point are cleared by a CPU reset */
128 struct {} end_reset_fields
;
130 #if !defined(CONFIG_USER_ONLY)
131 uint32_t core_id
; /* PoP "CPU address", same as cpu_index */
136 CpuS390Entitlement entitlement
; /* Used only for vertical polarization */
140 QEMUTimer
*tod_timer
;
142 QEMUTimer
*cpu_timer
;
145 * The cpu state represents the logical state of a cpu. In contrast to other
146 * architectures, there is a difference between a halt and a stop on s390.
147 * If all cpus are either stopped (including check stop) or in the disabled
148 * wait state, the vm can be shut down.
149 * The acceptable cpu_state values are defined in the CpuInfoS390State
154 /* currently processed sigp order */
159 static inline uint64_t *get_freg(CPUS390XState
*cs
, int nr
)
161 return &cs
->vregs
[nr
][0];
166 * @env: #CPUS390XState.
175 /* needed for live migration */
177 uint32_t irqstate_saved_size
;
180 typedef enum cpu_reset_type
{
181 S390_CPU_RESET_NORMAL
,
182 S390_CPU_RESET_INITIAL
,
183 S390_CPU_RESET_CLEAR
,
188 * @parent_realize: The parent class' realize handler.
189 * @parent_reset: The parent class' reset handler.
190 * @load_normal: Performs a load normal.
191 * @cpu_reset: Performs a CPU reset.
192 * @initial_cpu_reset: Performs an initial CPU reset.
194 * An S/390 CPU model.
196 struct S390CPUClass
{
197 CPUClass parent_class
;
199 const S390CPUDef
*cpu_def
;
202 bool is_migration_safe
;
205 DeviceRealize parent_realize
;
206 DeviceReset parent_reset
;
207 void (*load_normal
)(CPUState
*cpu
);
208 void (*reset
)(CPUState
*cpu
, cpu_reset_type type
);
211 #ifndef CONFIG_USER_ONLY
212 extern const VMStateDescription vmstate_s390_cpu
;
215 /* distinguish between 24 bit and 31 bit addressing */
216 #define HIGH_ORDER_BIT 0x80000000
218 /* Interrupt Codes */
219 /* Program Interrupts */
220 #define PGM_OPERATION 0x0001
221 #define PGM_PRIVILEGED 0x0002
222 #define PGM_EXECUTE 0x0003
223 #define PGM_PROTECTION 0x0004
224 #define PGM_ADDRESSING 0x0005
225 #define PGM_SPECIFICATION 0x0006
226 #define PGM_DATA 0x0007
227 #define PGM_FIXPT_OVERFLOW 0x0008
228 #define PGM_FIXPT_DIVIDE 0x0009
229 #define PGM_DEC_OVERFLOW 0x000a
230 #define PGM_DEC_DIVIDE 0x000b
231 #define PGM_HFP_EXP_OVERFLOW 0x000c
232 #define PGM_HFP_EXP_UNDERFLOW 0x000d
233 #define PGM_HFP_SIGNIFICANCE 0x000e
234 #define PGM_HFP_DIVIDE 0x000f
235 #define PGM_SEGMENT_TRANS 0x0010
236 #define PGM_PAGE_TRANS 0x0011
237 #define PGM_TRANS_SPEC 0x0012
238 #define PGM_SPECIAL_OP 0x0013
239 #define PGM_OPERAND 0x0015
240 #define PGM_TRACE_TABLE 0x0016
241 #define PGM_VECTOR_PROCESSING 0x001b
242 #define PGM_SPACE_SWITCH 0x001c
243 #define PGM_HFP_SQRT 0x001d
244 #define PGM_PC_TRANS_SPEC 0x001f
245 #define PGM_AFX_TRANS 0x0020
246 #define PGM_ASX_TRANS 0x0021
247 #define PGM_LX_TRANS 0x0022
248 #define PGM_EX_TRANS 0x0023
249 #define PGM_PRIM_AUTH 0x0024
250 #define PGM_SEC_AUTH 0x0025
251 #define PGM_ALET_SPEC 0x0028
252 #define PGM_ALEN_SPEC 0x0029
253 #define PGM_ALE_SEQ 0x002a
254 #define PGM_ASTE_VALID 0x002b
255 #define PGM_ASTE_SEQ 0x002c
256 #define PGM_EXT_AUTH 0x002d
257 #define PGM_STACK_FULL 0x0030
258 #define PGM_STACK_EMPTY 0x0031
259 #define PGM_STACK_SPEC 0x0032
260 #define PGM_STACK_TYPE 0x0033
261 #define PGM_STACK_OP 0x0034
262 #define PGM_ASCE_TYPE 0x0038
263 #define PGM_REG_FIRST_TRANS 0x0039
264 #define PGM_REG_SEC_TRANS 0x003a
265 #define PGM_REG_THIRD_TRANS 0x003b
266 #define PGM_MONITOR 0x0040
267 #define PGM_PER 0x0080
268 #define PGM_CRYPTO 0x0119
270 /* External Interrupts */
271 #define EXT_INTERRUPT_KEY 0x0040
272 #define EXT_CLOCK_COMP 0x1004
273 #define EXT_CPU_TIMER 0x1005
274 #define EXT_MALFUNCTION 0x1200
275 #define EXT_EMERGENCY 0x1201
276 #define EXT_EXTERNAL_CALL 0x1202
277 #define EXT_ETR 0x1406
278 #define EXT_SERVICE 0x2401
279 #define EXT_VIRTIO 0x2603
283 #undef PSW_MASK_UNUSED_2
284 #undef PSW_MASK_UNUSED_3
290 #undef PSW_MASK_MCHECK
292 #undef PSW_MASK_PSTATE
298 #undef PSW_SHIFT_MASK_PM
301 #undef PSW_MASK_ESA_ADDR
303 #define PSW_MASK_PER 0x4000000000000000ULL
304 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL
305 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL
306 #define PSW_MASK_DAT 0x0400000000000000ULL
307 #define PSW_MASK_IO 0x0200000000000000ULL
308 #define PSW_MASK_EXT 0x0100000000000000ULL
309 #define PSW_MASK_KEY 0x00F0000000000000ULL
310 #define PSW_SHIFT_KEY 52
311 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
312 #define PSW_MASK_MCHECK 0x0004000000000000ULL
313 #define PSW_MASK_WAIT 0x0002000000000000ULL
314 #define PSW_MASK_PSTATE 0x0001000000000000ULL
315 #define PSW_MASK_ASC 0x0000C00000000000ULL
316 #define PSW_SHIFT_ASC 46
317 #define PSW_MASK_CC 0x0000300000000000ULL
318 #define PSW_MASK_PM 0x00000F0000000000ULL
319 #define PSW_SHIFT_MASK_PM 40
320 #define PSW_MASK_RI 0x0000008000000000ULL
321 #define PSW_MASK_64 0x0000000100000000ULL
322 #define PSW_MASK_32 0x0000000080000000ULL
323 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
324 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
325 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL
327 #undef PSW_ASC_PRIMARY
328 #undef PSW_ASC_ACCREG
329 #undef PSW_ASC_SECONDARY
332 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
333 #define PSW_ASC_ACCREG 0x0000400000000000ULL
334 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
335 #define PSW_ASC_HOME 0x0000C00000000000ULL
337 /* the address space values shifted */
340 #define AS_SECONDARY 2
345 #define FLAG_MASK_PSW_SHIFT 31
346 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
347 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
348 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
349 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
350 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
351 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
352 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
353 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
355 /* we'll use some unused PSW positions to store CR flags in tb flags */
356 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
357 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
359 /* Control register 0 bits */
360 #define CR0_LOWPROT 0x0000000010000000ULL
361 #define CR0_SECONDARY 0x0000000004000000ULL
362 #define CR0_EDAT 0x0000000000800000ULL
363 #define CR0_AFP 0x0000000000040000ULL
364 #define CR0_VECTOR 0x0000000000020000ULL
365 #define CR0_IEP 0x0000000000100000ULL
366 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
367 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
368 #define CR0_CKC_SC 0x0000000000000800ULL
369 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
370 #define CR0_SERVICE_SC 0x0000000000000200ULL
372 /* Control register 14 bits */
373 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
376 #define MMU_PRIMARY_IDX 0
377 #define MMU_SECONDARY_IDX 1
378 #define MMU_HOME_IDX 2
379 #define MMU_REAL_IDX 3
381 static inline int s390x_env_mmu_index(CPUS390XState
*env
, bool ifetch
)
383 #ifdef CONFIG_USER_ONLY
386 if (!(env
->psw
.mask
& PSW_MASK_DAT
)) {
391 if ((env
->psw
.mask
& PSW_MASK_ASC
) == PSW_ASC_HOME
) {
394 return MMU_PRIMARY_IDX
;
397 switch (env
->psw
.mask
& PSW_MASK_ASC
) {
398 case PSW_ASC_PRIMARY
:
399 return MMU_PRIMARY_IDX
;
400 case PSW_ASC_SECONDARY
:
401 return MMU_SECONDARY_IDX
;
405 /* Fallthrough: access register mode is not yet supported */
414 #include "tcg/tcg_s390x.h"
416 static inline void cpu_get_tb_cpu_state(CPUS390XState
*env
, vaddr
*pc
,
417 uint64_t *cs_base
, uint32_t *flags
)
419 if (env
->psw
.addr
& 1) {
421 * Instructions must be at even addresses.
422 * This needs to be checked before address translation.
424 env
->int_pgm_ilen
= 2; /* see s390_cpu_tlb_fill() */
425 tcg_s390_program_interrupt(env
, PGM_SPECIFICATION
, 0);
428 *cs_base
= env
->ex_value
;
429 *flags
= (env
->psw
.mask
>> FLAG_MASK_PSW_SHIFT
) & FLAG_MASK_PSW
;
430 if (env
->cregs
[0] & CR0_AFP
) {
431 *flags
|= FLAG_MASK_AFP
;
433 if (env
->cregs
[0] & CR0_VECTOR
) {
434 *flags
|= FLAG_MASK_VECTOR
;
438 #endif /* CONFIG_TCG */
440 /* PER bits from control register 9 */
441 #define PER_CR9_EVENT_BRANCH 0x80000000
442 #define PER_CR9_EVENT_IFETCH 0x40000000
443 #define PER_CR9_EVENT_STORE 0x20000000
444 #define PER_CR9_EVENT_STORE_REAL 0x08000000
445 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
446 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
447 #define PER_CR9_CONTROL_ALTERATION 0x00200000
449 /* PER bits from the PER CODE/ATMID/AI in lowcore */
450 #define PER_CODE_EVENT_BRANCH 0x8000
451 #define PER_CODE_EVENT_IFETCH 0x4000
452 #define PER_CODE_EVENT_STORE 0x2000
453 #define PER_CODE_EVENT_STORE_REAL 0x0800
454 #define PER_CODE_EVENT_NULLIFICATION 0x0100
456 #define EXCP_EXT 1 /* external interrupt */
457 #define EXCP_SVC 2 /* supervisor call (syscall) */
458 #define EXCP_PGM 3 /* program interruption */
459 #define EXCP_RESTART 4 /* restart interrupt */
460 #define EXCP_STOP 5 /* stop interrupt */
461 #define EXCP_IO 7 /* I/O interrupt */
462 #define EXCP_MCHK 8 /* machine check */
464 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
465 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
466 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
467 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
468 #define INTERRUPT_RESTART (1 << 7)
469 #define INTERRUPT_STOP (1 << 8)
471 /* Program Status Word. */
472 #define S390_PSWM_REGNUM 0
473 #define S390_PSWA_REGNUM 1
474 /* General Purpose Registers. */
475 #define S390_R0_REGNUM 2
476 #define S390_R1_REGNUM 3
477 #define S390_R2_REGNUM 4
478 #define S390_R3_REGNUM 5
479 #define S390_R4_REGNUM 6
480 #define S390_R5_REGNUM 7
481 #define S390_R6_REGNUM 8
482 #define S390_R7_REGNUM 9
483 #define S390_R8_REGNUM 10
484 #define S390_R9_REGNUM 11
485 #define S390_R10_REGNUM 12
486 #define S390_R11_REGNUM 13
487 #define S390_R12_REGNUM 14
488 #define S390_R13_REGNUM 15
489 #define S390_R14_REGNUM 16
490 #define S390_R15_REGNUM 17
492 static inline void setcc(S390CPU
*cpu
, uint64_t cc
)
494 CPUS390XState
*env
= &cpu
->env
;
496 env
->psw
.mask
&= ~(3ull << 44);
497 env
->psw
.mask
|= (cc
& 3) << 44;
502 #define STSI_R0_FC_MASK 0x00000000f0000000ULL
503 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL
504 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
505 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
506 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
507 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
508 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
509 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
510 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
512 /* Basic Machine Configuration */
513 typedef struct SysIB_111
{
519 uint8_t sequence
[16];
523 QEMU_BUILD_BUG_ON(sizeof(SysIB_111
) != 4096);
525 /* Basic Machine CPU */
526 typedef struct SysIB_121
{
528 uint8_t sequence
[16];
534 QEMU_BUILD_BUG_ON(sizeof(SysIB_121
) != 4096);
536 /* Basic Machine CPUs */
537 typedef struct SysIB_122
{
542 uint16_t standby_cpus
;
543 uint16_t reserved_cpus
;
544 uint16_t adjustments
[2026];
546 QEMU_BUILD_BUG_ON(sizeof(SysIB_122
) != 4096);
549 typedef struct SysIB_221
{
551 uint8_t sequence
[16];
557 QEMU_BUILD_BUG_ON(sizeof(SysIB_221
) != 4096);
560 typedef struct SysIB_222
{
567 uint16_t standby_cpus
;
568 uint16_t reserved_cpus
;
572 uint16_t dedicated_cpus
;
573 uint16_t shared_cpus
;
576 QEMU_BUILD_BUG_ON(sizeof(SysIB_222
) != 4096);
579 typedef struct SysIB_322
{
586 uint16_t standby_cpus
;
587 uint16_t reserved_cpus
;
592 uint8_t ext_name_encoding
;
597 uint8_t ext_names
[8][256];
599 QEMU_BUILD_BUG_ON(sizeof(SysIB_322
) != 4096);
602 * Topology Magnitude fields (MAG) indicates the maximum number of
603 * topology list entries (TLE) at the corresponding nesting level.
605 #define S390_TOPOLOGY_MAG 6
606 #define S390_TOPOLOGY_MAG6 0
607 #define S390_TOPOLOGY_MAG5 1
608 #define S390_TOPOLOGY_MAG4 2
609 #define S390_TOPOLOGY_MAG3 3
610 #define S390_TOPOLOGY_MAG2 4
611 #define S390_TOPOLOGY_MAG1 5
612 /* Configuration topology */
613 typedef struct SysIB_151x
{
614 uint8_t reserved0
[2];
616 uint8_t mag
[S390_TOPOLOGY_MAG
];
622 QEMU_BUILD_BUG_ON(sizeof(SysIB_151x
) != 16);
624 typedef union SysIB
{
631 SysIB_151x sysib_151x
;
633 QEMU_BUILD_BUG_ON(sizeof(SysIB
) != 4096);
636 * CPU Topology List provided by STSI with fc=15 provides a list
637 * of two different Topology List Entries (TLE) types to specify
638 * the topology hierarchy.
640 * - Container Topology List Entry
641 * Defines a container to contain other Topology List Entries
642 * of any type, nested containers or CPU.
643 * - CPU Topology List Entry
644 * Specifies the CPUs position, type, entitlement and polarization
645 * of the CPUs contained in the last container TLE.
647 * There can be theoretically up to five levels of containers, QEMU
648 * uses only three levels, the drawer's, book's and socket's level.
650 * A container with a nesting level (NL) greater than 1 can only
651 * contain another container of nesting level NL-1.
653 * A container of nesting level 1 (socket), contains as many CPU TLE
654 * as needed to describe the position and qualities of all CPUs inside
656 * The qualities of a CPU are polarization, entitlement and type.
658 * The CPU TLE defines the position of the CPUs of identical qualities
659 * using a 64bits mask which first bit has its offset defined by
660 * the CPU address origin field of the CPU TLE like in:
661 * CPU address = origin * 64 + bit position within the mask
663 /* Container type Topology List Entry */
664 typedef struct SYSIBContainerListEntry
{
668 } SYSIBContainerListEntry
;
669 QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry
) != 8);
671 /* CPU type Topology List Entry */
672 typedef struct SysIBCPUListEntry
{
674 uint8_t reserved0
[3];
675 #define SYSIB_TLE_POLARITY_MASK 0x03
676 #define SYSIB_TLE_DEDICATED 0x04
682 QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry
) != 16);
684 void insert_stsi_15_1_x(S390CPU
*cpu
, int sel2
, uint64_t addr
, uint8_t ar
, uintptr_t ra
);
685 void s390_cpu_topology_set_changed(bool changed
);
688 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
689 #define ASCE_SUBSPACE 0x200 /* subspace group control */
690 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */
691 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
692 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */
693 #define ASCE_REAL_SPACE 0x20 /* real space control */
694 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */
695 #define ASCE_TYPE_REGION1 0x0c /* region first table type */
696 #define ASCE_TYPE_REGION2 0x08 /* region second table type */
697 #define ASCE_TYPE_REGION3 0x04 /* region third table type */
698 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
699 #define ASCE_TABLE_LENGTH 0x03 /* region table length */
701 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL
702 #define REGION_ENTRY_P 0x0000000000000200ULL
703 #define REGION_ENTRY_TF 0x00000000000000c0ULL
704 #define REGION_ENTRY_I 0x0000000000000020ULL
705 #define REGION_ENTRY_TT 0x000000000000000cULL
706 #define REGION_ENTRY_TL 0x0000000000000003ULL
708 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL
709 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL
710 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL
712 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL
713 #define REGION3_ENTRY_AV 0x0000000000010000ULL
714 #define REGION3_ENTRY_ACC 0x000000000000f000ULL
715 #define REGION3_ENTRY_F 0x0000000000000800ULL
716 #define REGION3_ENTRY_FC 0x0000000000000400ULL
717 #define REGION3_ENTRY_IEP 0x0000000000000100ULL
718 #define REGION3_ENTRY_CR 0x0000000000000010ULL
720 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL
721 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL
722 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL
723 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL
724 #define SEGMENT_ENTRY_F 0x0000000000000800ULL
725 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL
726 #define SEGMENT_ENTRY_P 0x0000000000000200ULL
727 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL
728 #define SEGMENT_ENTRY_I 0x0000000000000020ULL
729 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL
730 #define SEGMENT_ENTRY_TT 0x000000000000000cULL
732 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL
734 #define PAGE_ENTRY_0 0x0000000000000800ULL
735 #define PAGE_ENTRY_I 0x0000000000000400ULL
736 #define PAGE_ENTRY_P 0x0000000000000200ULL
737 #define PAGE_ENTRY_IEP 0x0000000000000100ULL
739 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL
740 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL
741 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL
742 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL
743 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL
745 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
746 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
747 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
748 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
749 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
751 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62)
752 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51)
753 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40)
754 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29)
756 #define SK_C (0x1 << 1)
757 #define SK_R (0x1 << 2)
758 #define SK_F (0x1 << 3)
759 #define SK_ACC_MASK (0xf << 4)
761 /* SIGP order codes */
762 #define SIGP_SENSE 0x01
763 #define SIGP_EXTERNAL_CALL 0x02
764 #define SIGP_EMERGENCY 0x03
765 #define SIGP_START 0x04
766 #define SIGP_STOP 0x05
767 #define SIGP_RESTART 0x06
768 #define SIGP_STOP_STORE_STATUS 0x09
769 #define SIGP_INITIAL_CPU_RESET 0x0b
770 #define SIGP_CPU_RESET 0x0c
771 #define SIGP_SET_PREFIX 0x0d
772 #define SIGP_STORE_STATUS_ADDR 0x0e
773 #define SIGP_SET_ARCH 0x12
774 #define SIGP_COND_EMERGENCY 0x13
775 #define SIGP_SENSE_RUNNING 0x15
776 #define SIGP_STORE_ADTL_STATUS 0x17
778 /* SIGP condition codes */
779 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
780 #define SIGP_CC_STATUS_STORED 1
781 #define SIGP_CC_BUSY 2
782 #define SIGP_CC_NOT_OPERATIONAL 3
784 /* SIGP status bits */
785 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
786 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
787 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
788 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
789 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
790 #define SIGP_STAT_STOPPED 0x00000040UL
791 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
792 #define SIGP_STAT_CHECK_STOP 0x00000010UL
793 #define SIGP_STAT_INOPERATIVE 0x00000004UL
794 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
795 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
797 /* SIGP order code mask corresponding to bit positions 56-63 */
798 #define SIGP_ORDER_MASK 0x000000ff
800 /* machine check interruption code */
803 #define MCIC_SC_SD 0x8000000000000000ULL
804 #define MCIC_SC_PD 0x4000000000000000ULL
805 #define MCIC_SC_SR 0x2000000000000000ULL
806 #define MCIC_SC_CD 0x0800000000000000ULL
807 #define MCIC_SC_ED 0x0400000000000000ULL
808 #define MCIC_SC_DG 0x0100000000000000ULL
809 #define MCIC_SC_W 0x0080000000000000ULL
810 #define MCIC_SC_CP 0x0040000000000000ULL
811 #define MCIC_SC_SP 0x0020000000000000ULL
812 #define MCIC_SC_CK 0x0010000000000000ULL
814 /* subclass modifiers */
815 #define MCIC_SCM_B 0x0002000000000000ULL
816 #define MCIC_SCM_DA 0x0000000020000000ULL
817 #define MCIC_SCM_AP 0x0000000000080000ULL
820 #define MCIC_SE_SE 0x0000800000000000ULL
821 #define MCIC_SE_SC 0x0000400000000000ULL
822 #define MCIC_SE_KE 0x0000200000000000ULL
823 #define MCIC_SE_DS 0x0000100000000000ULL
824 #define MCIC_SE_IE 0x0000000080000000ULL
827 #define MCIC_VB_WP 0x0000080000000000ULL
828 #define MCIC_VB_MS 0x0000040000000000ULL
829 #define MCIC_VB_PM 0x0000020000000000ULL
830 #define MCIC_VB_IA 0x0000010000000000ULL
831 #define MCIC_VB_FA 0x0000008000000000ULL
832 #define MCIC_VB_VR 0x0000004000000000ULL
833 #define MCIC_VB_EC 0x0000002000000000ULL
834 #define MCIC_VB_FP 0x0000001000000000ULL
835 #define MCIC_VB_GR 0x0000000800000000ULL
836 #define MCIC_VB_CR 0x0000000400000000ULL
837 #define MCIC_VB_ST 0x0000000100000000ULL
838 #define MCIC_VB_AR 0x0000000040000000ULL
839 #define MCIC_VB_GS 0x0000000008000000ULL
840 #define MCIC_VB_PR 0x0000000000200000ULL
841 #define MCIC_VB_FC 0x0000000000100000ULL
842 #define MCIC_VB_CT 0x0000000000020000ULL
843 #define MCIC_VB_CC 0x0000000000010000ULL
845 static inline uint64_t s390_build_validity_mcic(void)
850 * Indicate all validity bits (no damage) only. Other bits have to be
851 * added by the caller. (storage errors, subclasses and subclass modifiers)
853 mcic
= MCIC_VB_WP
| MCIC_VB_MS
| MCIC_VB_PM
| MCIC_VB_IA
| MCIC_VB_FP
|
854 MCIC_VB_GR
| MCIC_VB_CR
| MCIC_VB_ST
| MCIC_VB_AR
| MCIC_VB_PR
|
855 MCIC_VB_FC
| MCIC_VB_CT
| MCIC_VB_CC
;
856 if (s390_has_feat(S390_FEAT_VECTOR
)) {
859 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE
)) {
865 static inline void s390_do_cpu_full_reset(CPUState
*cs
, run_on_cpu_data arg
)
870 static inline void s390_do_cpu_reset(CPUState
*cs
, run_on_cpu_data arg
)
872 S390CPUClass
*scc
= S390_CPU_GET_CLASS(cs
);
874 scc
->reset(cs
, S390_CPU_RESET_NORMAL
);
877 static inline void s390_do_cpu_initial_reset(CPUState
*cs
, run_on_cpu_data arg
)
879 S390CPUClass
*scc
= S390_CPU_GET_CLASS(cs
);
881 scc
->reset(cs
, S390_CPU_RESET_INITIAL
);
884 static inline void s390_do_cpu_load_normal(CPUState
*cs
, run_on_cpu_data arg
)
886 S390CPUClass
*scc
= S390_CPU_GET_CLASS(cs
);
888 scc
->load_normal(cs
);
893 void s390_crypto_reset(void);
894 int s390_set_memory_limit(uint64_t new_limit
, uint64_t *hw_limit
);
895 void s390_set_max_pagesize(uint64_t pagesize
, Error
**errp
);
896 void s390_cmma_reset(void);
897 void s390_enable_css_support(S390CPU
*cpu
);
898 void s390_do_cpu_set_diag318(CPUState
*cs
, run_on_cpu_data arg
);
899 int s390_assign_subch_ioeventfd(EventNotifier
*notifier
, uint32_t sch_id
,
900 int vq
, bool assign
);
901 #ifndef CONFIG_USER_ONLY
902 unsigned int s390_cpu_set_state(uint8_t cpu_state
, S390CPU
*cpu
);
904 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state
, S390CPU
*cpu
)
908 #endif /* CONFIG_USER_ONLY */
909 static inline uint8_t s390_cpu_get_state(S390CPU
*cpu
)
911 return cpu
->env
.cpu_state
;
916 void s390_cpu_list(void);
917 #define cpu_list s390_cpu_list
918 void s390_set_qemu_cpu_model(uint16_t type
, uint8_t gen
, uint8_t ec_ga
,
919 const S390FeatInit feat_init
);
923 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
927 void s390_program_interrupt(CPUS390XState
*env
, uint32_t code
, uintptr_t ra
);
928 /* service interrupts are floating therefore we must not pass an cpustate */
929 void s390_sclp_extint(uint32_t parm
);
932 int s390_cpu_virt_mem_rw(S390CPU
*cpu
, vaddr laddr
, uint8_t ar
, void *hostbuf
,
933 int len
, bool is_write
);
934 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
935 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
936 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
937 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
938 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
939 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
940 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
941 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
942 void s390_cpu_virt_mem_handle_exc(S390CPU
*cpu
, uintptr_t ra
);
943 int s390_cpu_pv_mem_rw(S390CPU
*cpu
, unsigned int offset
, void *hostbuf
,
944 int len
, bool is_write
);
945 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \
946 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
947 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \
948 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
951 int s390_cpu_restart(S390CPU
*cpu
);
952 void s390_init_sigp(void);
955 void s390_cpu_set_psw(CPUS390XState
*env
, uint64_t mask
, uint64_t addr
);
956 uint64_t s390_cpu_get_psw_mask(CPUS390XState
*env
);
958 /* outside of target/s390x/ */
959 S390CPU
*s390_cpu_addr2state(uint16_t cpu_addr
);
961 #include "exec/cpu-all.h"