4 * Copyright (c) 2005 Samuel Tardieu
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat-helpers.h"
31 static void superh_cpu_set_pc(CPUState
*cs
, vaddr value
)
33 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
38 static vaddr
superh_cpu_get_pc(CPUState
*cs
)
40 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
45 static void superh_cpu_synchronize_from_tb(CPUState
*cs
,
46 const TranslationBlock
*tb
)
48 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
50 tcg_debug_assert(!(cs
->tcg_cflags
& CF_PCREL
));
52 cpu
->env
.flags
= tb
->flags
& TB_FLAG_ENVFLAGS_MASK
;
55 static void superh_restore_state_to_opc(CPUState
*cs
,
56 const TranslationBlock
*tb
,
59 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
61 cpu
->env
.pc
= data
[0];
62 cpu
->env
.flags
= data
[1];
64 * Theoretically delayed_pc should also be restored. In practice the
65 * branch instruction is re-executed after exception, so the delayed
66 * branch target will be recomputed.
70 #ifndef CONFIG_USER_ONLY
71 static bool superh_io_recompile_replay_branch(CPUState
*cs
,
72 const TranslationBlock
*tb
)
74 SuperHCPU
*cpu
= SUPERH_CPU(cs
);
75 CPUSH4State
*env
= &cpu
->env
;
77 if ((env
->flags
& (TB_FLAG_DELAY_SLOT
| TB_FLAG_DELAY_SLOT_COND
))
78 && !(cs
->tcg_cflags
& CF_PCREL
) && env
->pc
!= tb
->pc
) {
80 env
->flags
&= ~(TB_FLAG_DELAY_SLOT
| TB_FLAG_DELAY_SLOT_COND
);
87 static bool superh_cpu_has_work(CPUState
*cs
)
89 return cs
->interrupt_request
& CPU_INTERRUPT_HARD
;
92 static void superh_cpu_reset_hold(Object
*obj
)
94 CPUState
*s
= CPU(obj
);
95 SuperHCPU
*cpu
= SUPERH_CPU(s
);
96 SuperHCPUClass
*scc
= SUPERH_CPU_GET_CLASS(cpu
);
97 CPUSH4State
*env
= &cpu
->env
;
99 if (scc
->parent_phases
.hold
) {
100 scc
->parent_phases
.hold(obj
);
103 memset(env
, 0, offsetof(CPUSH4State
, end_reset_fields
));
105 env
->pc
= 0xA0000000;
106 #if defined(CONFIG_USER_ONLY)
107 env
->fpscr
= FPSCR_PR
; /* value for userspace according to the kernel */
108 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
); /* ?! */
110 env
->sr
= (1u << SR_MD
) | (1u << SR_RB
) | (1u << SR_BL
) |
111 (1u << SR_I3
) | (1u << SR_I2
) | (1u << SR_I1
) | (1u << SR_I0
);
112 env
->fpscr
= FPSCR_DN
| FPSCR_RM_ZERO
; /* CPU reset value according to SH4 manual */
113 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
114 set_flush_to_zero(1, &env
->fp_status
);
116 set_default_nan_mode(1, &env
->fp_status
);
119 static void superh_cpu_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
121 info
->mach
= bfd_mach_sh4
;
122 info
->print_insn
= print_insn_sh
;
125 static ObjectClass
*superh_cpu_class_by_name(const char *cpu_model
)
128 char *s
, *typename
= NULL
;
130 s
= g_ascii_strdown(cpu_model
, -1);
131 if (strcmp(s
, "any") == 0) {
132 oc
= object_class_by_name(TYPE_SH7750R_CPU
);
136 typename
= g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s
);
137 oc
= object_class_by_name(typename
);
145 static void sh7750r_cpu_initfn(Object
*obj
)
147 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
148 CPUSH4State
*env
= &cpu
->env
;
150 env
->id
= SH_CPU_SH7750R
;
151 env
->features
= SH_FEATURE_BCR3_AND_BCR4
;
154 static void sh7750r_class_init(ObjectClass
*oc
, void *data
)
156 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
158 scc
->pvr
= 0x00050000;
159 scc
->prr
= 0x00000100;
160 scc
->cvr
= 0x00110000;
163 static void sh7751r_cpu_initfn(Object
*obj
)
165 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
166 CPUSH4State
*env
= &cpu
->env
;
168 env
->id
= SH_CPU_SH7751R
;
169 env
->features
= SH_FEATURE_BCR3_AND_BCR4
;
172 static void sh7751r_class_init(ObjectClass
*oc
, void *data
)
174 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
176 scc
->pvr
= 0x04050005;
177 scc
->prr
= 0x00000113;
178 scc
->cvr
= 0x00110000; /* Neutered caches, should be 0x20480000 */
181 static void sh7785_cpu_initfn(Object
*obj
)
183 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
184 CPUSH4State
*env
= &cpu
->env
;
186 env
->id
= SH_CPU_SH7785
;
187 env
->features
= SH_FEATURE_SH4A
;
190 static void sh7785_class_init(ObjectClass
*oc
, void *data
)
192 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
194 scc
->pvr
= 0x10300700;
195 scc
->prr
= 0x00000200;
196 scc
->cvr
= 0x71440211;
199 static void superh_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
201 CPUState
*cs
= CPU(dev
);
202 SuperHCPUClass
*scc
= SUPERH_CPU_GET_CLASS(dev
);
203 Error
*local_err
= NULL
;
205 cpu_exec_realizefn(cs
, &local_err
);
206 if (local_err
!= NULL
) {
207 error_propagate(errp
, local_err
);
214 scc
->parent_realize(dev
, errp
);
217 static void superh_cpu_initfn(Object
*obj
)
219 SuperHCPU
*cpu
= SUPERH_CPU(obj
);
220 CPUSH4State
*env
= &cpu
->env
;
222 env
->movcal_backup_tail
= &(env
->movcal_backup
);
225 #ifndef CONFIG_USER_ONLY
226 static const VMStateDescription vmstate_sh_cpu
= {
231 #include "hw/core/sysemu-cpu-ops.h"
233 static const struct SysemuCPUOps sh4_sysemu_ops
= {
234 .get_phys_page_debug
= superh_cpu_get_phys_page_debug
,
238 #include "hw/core/tcg-cpu-ops.h"
240 static const struct TCGCPUOps superh_tcg_ops
= {
241 .initialize
= sh4_translate_init
,
242 .synchronize_from_tb
= superh_cpu_synchronize_from_tb
,
243 .restore_state_to_opc
= superh_restore_state_to_opc
,
245 #ifndef CONFIG_USER_ONLY
246 .tlb_fill
= superh_cpu_tlb_fill
,
247 .cpu_exec_interrupt
= superh_cpu_exec_interrupt
,
248 .do_interrupt
= superh_cpu_do_interrupt
,
249 .do_unaligned_access
= superh_cpu_do_unaligned_access
,
250 .io_recompile_replay_branch
= superh_io_recompile_replay_branch
,
251 #endif /* !CONFIG_USER_ONLY */
254 static void superh_cpu_class_init(ObjectClass
*oc
, void *data
)
256 DeviceClass
*dc
= DEVICE_CLASS(oc
);
257 CPUClass
*cc
= CPU_CLASS(oc
);
258 SuperHCPUClass
*scc
= SUPERH_CPU_CLASS(oc
);
259 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
261 device_class_set_parent_realize(dc
, superh_cpu_realizefn
,
262 &scc
->parent_realize
);
264 resettable_class_set_parent_phases(rc
, NULL
, superh_cpu_reset_hold
, NULL
,
265 &scc
->parent_phases
);
267 cc
->class_by_name
= superh_cpu_class_by_name
;
268 cc
->has_work
= superh_cpu_has_work
;
269 cc
->dump_state
= superh_cpu_dump_state
;
270 cc
->set_pc
= superh_cpu_set_pc
;
271 cc
->get_pc
= superh_cpu_get_pc
;
272 cc
->gdb_read_register
= superh_cpu_gdb_read_register
;
273 cc
->gdb_write_register
= superh_cpu_gdb_write_register
;
274 #ifndef CONFIG_USER_ONLY
275 cc
->sysemu_ops
= &sh4_sysemu_ops
;
276 dc
->vmsd
= &vmstate_sh_cpu
;
278 cc
->disas_set_info
= superh_cpu_disas_set_info
;
280 cc
->gdb_num_core_regs
= 59;
281 cc
->tcg_ops
= &superh_tcg_ops
;
284 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
287 .parent = TYPE_SUPERH_CPU, \
288 .class_init = cinit, \
289 .instance_init = initfn, \
291 static const TypeInfo superh_cpu_type_infos
[] = {
293 .name
= TYPE_SUPERH_CPU
,
295 .instance_size
= sizeof(SuperHCPU
),
296 .instance_align
= __alignof(SuperHCPU
),
297 .instance_init
= superh_cpu_initfn
,
299 .class_size
= sizeof(SuperHCPUClass
),
300 .class_init
= superh_cpu_class_init
,
302 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU
, sh7750r_class_init
,
304 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU
, sh7751r_class_init
,
306 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU
, sh7785_class_init
,
311 DEFINE_TYPES(superh_cpu_type_infos
)