4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "qemu/qemu-print.h"
27 /* Sparc MMU emulation */
29 #ifndef TARGET_SPARC64
31 * Sparc V8 Reference MMU (SRMMU)
33 static const int access_table
[8][8] = {
34 { 0, 0, 0, 0, 8, 0, 12, 12 },
35 { 0, 0, 0, 0, 8, 0, 0, 0 },
36 { 8, 8, 0, 0, 0, 8, 12, 12 },
37 { 8, 8, 0, 0, 0, 8, 0, 0 },
38 { 8, 0, 8, 0, 8, 8, 12, 12 },
39 { 8, 0, 8, 0, 8, 0, 8, 0 },
40 { 8, 8, 8, 0, 8, 8, 12, 12 },
41 { 8, 8, 8, 0, 8, 8, 8, 0 }
44 static const int perm_table
[2][8] = {
47 PAGE_READ
| PAGE_WRITE
,
48 PAGE_READ
| PAGE_EXEC
,
49 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
51 PAGE_READ
| PAGE_WRITE
,
52 PAGE_READ
| PAGE_EXEC
,
53 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
57 PAGE_READ
| PAGE_WRITE
,
58 PAGE_READ
| PAGE_EXEC
,
59 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
67 static int get_physical_address(CPUSPARCState
*env
, hwaddr
*physical
,
68 int *prot
, int *access_index
, MemTxAttrs
*attrs
,
69 target_ulong address
, int rw
, int mmu_idx
,
70 target_ulong
*page_size
)
75 int error_code
= 0, is_dirty
, is_user
;
76 unsigned long page_offset
;
77 CPUState
*cs
= env_cpu(env
);
80 is_user
= mmu_idx
== MMU_USER_IDX
;
82 if (mmu_idx
== MMU_PHYS_IDX
) {
83 *page_size
= TARGET_PAGE_SIZE
;
84 /* Boot mode: instruction fetches are taken from PROM */
85 if (rw
== 2 && (env
->mmuregs
[0] & env
->def
.mmu_bm
)) {
86 *physical
= env
->prom_addr
| (address
& 0x7ffffULL
);
87 *prot
= PAGE_READ
| PAGE_EXEC
;
91 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
95 *access_index
= ((rw
& 1) << 2) | (rw
& 2) | (is_user
? 0 : 1);
96 *physical
= 0xffffffffffff0000ULL
;
98 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
99 /* Context base + context number */
100 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
101 pde
= address_space_ldl(cs
->as
, pde_ptr
, MEMTXATTRS_UNSPECIFIED
, &result
);
102 if (result
!= MEMTX_OK
) {
103 return 4 << 2; /* Translation fault, L = 0 */
107 switch (pde
& PTE_ENTRYTYPE_MASK
) {
109 case 0: /* Invalid */
111 case 2: /* L0 PTE, maybe should not happen? */
112 case 3: /* Reserved */
115 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
116 pde
= address_space_ldl(cs
->as
, pde_ptr
,
117 MEMTXATTRS_UNSPECIFIED
, &result
);
118 if (result
!= MEMTX_OK
) {
119 return (1 << 8) | (4 << 2); /* Translation fault, L = 1 */
122 switch (pde
& PTE_ENTRYTYPE_MASK
) {
124 case 0: /* Invalid */
125 return (1 << 8) | (1 << 2);
126 case 3: /* Reserved */
127 return (1 << 8) | (4 << 2);
129 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
130 pde
= address_space_ldl(cs
->as
, pde_ptr
,
131 MEMTXATTRS_UNSPECIFIED
, &result
);
132 if (result
!= MEMTX_OK
) {
133 return (2 << 8) | (4 << 2); /* Translation fault, L = 2 */
136 switch (pde
& PTE_ENTRYTYPE_MASK
) {
138 case 0: /* Invalid */
139 return (2 << 8) | (1 << 2);
140 case 3: /* Reserved */
141 return (2 << 8) | (4 << 2);
143 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
144 pde
= address_space_ldl(cs
->as
, pde_ptr
,
145 MEMTXATTRS_UNSPECIFIED
, &result
);
146 if (result
!= MEMTX_OK
) {
147 return (3 << 8) | (4 << 2); /* Translation fault, L = 3 */
150 switch (pde
& PTE_ENTRYTYPE_MASK
) {
152 case 0: /* Invalid */
153 return (3 << 8) | (1 << 2);
154 case 1: /* PDE, should not happen */
155 case 3: /* Reserved */
156 return (3 << 8) | (4 << 2);
160 *page_size
= TARGET_PAGE_SIZE
;
163 page_offset
= address
& 0x3f000;
164 *page_size
= 0x40000;
168 page_offset
= address
& 0xfff000;
169 *page_size
= 0x1000000;
174 access_perms
= (pde
& PTE_ACCESS_MASK
) >> PTE_ACCESS_SHIFT
;
175 error_code
= access_table
[*access_index
][access_perms
];
176 if (error_code
&& !((env
->mmuregs
[0] & MMU_NF
) && is_user
)) {
180 /* update page modified and dirty bits */
181 is_dirty
= (rw
& 1) && !(pde
& PG_MODIFIED_MASK
);
182 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
183 pde
|= PG_ACCESSED_MASK
;
185 pde
|= PG_MODIFIED_MASK
;
187 stl_phys_notdirty(cs
->as
, pde_ptr
, pde
);
190 /* the page can be put in the TLB */
191 *prot
= perm_table
[is_user
][access_perms
];
192 if (!(pde
& PG_MODIFIED_MASK
)) {
193 /* only set write access if already dirty... otherwise wait
195 *prot
&= ~PAGE_WRITE
;
198 /* Even if large ptes, we map only one 4KB page in the cache to
199 avoid filling it too fast */
200 *physical
= ((hwaddr
)(pde
& PTE_ADDR_MASK
) << 4) + page_offset
;
204 /* Perform address translation */
205 bool sparc_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
206 MMUAccessType access_type
, int mmu_idx
,
207 bool probe
, uintptr_t retaddr
)
209 SPARCCPU
*cpu
= SPARC_CPU(cs
);
210 CPUSPARCState
*env
= &cpu
->env
;
213 target_ulong page_size
;
214 int error_code
= 0, prot
, access_index
;
215 MemTxAttrs attrs
= {};
218 * TODO: If we ever need tlb_vaddr_to_host for this target,
219 * then we must figure out how to manipulate FSR and FAR
220 * when both MMU_NF and probe are set. In the meantime,
221 * do not support this use case.
225 address
&= TARGET_PAGE_MASK
;
226 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
, &attrs
,
227 address
, access_type
,
228 mmu_idx
, &page_size
);
230 if (likely(error_code
== 0)) {
231 qemu_log_mask(CPU_LOG_MMU
,
232 "Translate at %" VADDR_PRIx
" -> "
233 HWADDR_FMT_plx
", vaddr " TARGET_FMT_lx
"\n",
234 address
, paddr
, vaddr
);
235 tlb_set_page(cs
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
239 if (env
->mmuregs
[3]) { /* Fault status register */
240 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
242 env
->mmuregs
[3] |= (access_index
<< 5) | error_code
| 2;
243 env
->mmuregs
[4] = address
; /* Fault address register */
245 if ((env
->mmuregs
[0] & MMU_NF
) || env
->psret
== 0) {
246 /* No fault mode: if a mapping is available, just override
247 permissions. If no mapping is available, redirect accesses to
248 neverland. Fake/overridden mappings will be flushed when
249 switching to normal mode. */
250 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
251 tlb_set_page(cs
, vaddr
, paddr
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
254 if (access_type
== MMU_INST_FETCH
) {
255 cs
->exception_index
= TT_TFAULT
;
257 cs
->exception_index
= TT_DFAULT
;
259 cpu_loop_exit_restore(cs
, retaddr
);
263 target_ulong
mmu_probe(CPUSPARCState
*env
, target_ulong address
, int mmulev
)
265 CPUState
*cs
= env_cpu(env
);
271 * TODO: MMU probe operations are supposed to set the fault
272 * status registers, but we don't do this.
275 /* Context base + context number */
276 pde_ptr
= (hwaddr
)(env
->mmuregs
[1] << 4) +
277 (env
->mmuregs
[2] << 2);
278 pde
= address_space_ldl(cs
->as
, pde_ptr
, MEMTXATTRS_UNSPECIFIED
, &result
);
279 if (result
!= MEMTX_OK
) {
283 switch (pde
& PTE_ENTRYTYPE_MASK
) {
285 case 0: /* Invalid */
286 case 2: /* PTE, maybe should not happen? */
287 case 3: /* Reserved */
293 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
294 pde
= address_space_ldl(cs
->as
, pde_ptr
,
295 MEMTXATTRS_UNSPECIFIED
, &result
);
296 if (result
!= MEMTX_OK
) {
300 switch (pde
& PTE_ENTRYTYPE_MASK
) {
302 case 0: /* Invalid */
303 case 3: /* Reserved */
311 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
312 pde
= address_space_ldl(cs
->as
, pde_ptr
,
313 MEMTXATTRS_UNSPECIFIED
, &result
);
314 if (result
!= MEMTX_OK
) {
318 switch (pde
& PTE_ENTRYTYPE_MASK
) {
320 case 0: /* Invalid */
321 case 3: /* Reserved */
329 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
330 pde
= address_space_ldl(cs
->as
, pde_ptr
,
331 MEMTXATTRS_UNSPECIFIED
, &result
);
332 if (result
!= MEMTX_OK
) {
336 switch (pde
& PTE_ENTRYTYPE_MASK
) {
338 case 0: /* Invalid */
339 case 1: /* PDE, should not happen */
340 case 3: /* Reserved */
351 void dump_mmu(CPUSPARCState
*env
)
353 CPUState
*cs
= env_cpu(env
);
354 target_ulong va
, va1
, va2
;
355 unsigned int n
, m
, o
;
359 qemu_printf("Root ptr: " HWADDR_FMT_plx
", ctx: %d\n",
360 (hwaddr
)env
->mmuregs
[1] << 4, env
->mmuregs
[2]);
361 for (n
= 0, va
= 0; n
< 256; n
++, va
+= 16 * 1024 * 1024) {
362 pde
= mmu_probe(env
, va
, 2);
364 pa
= cpu_get_phys_page_debug(cs
, va
);
365 qemu_printf("VA: " TARGET_FMT_lx
", PA: " HWADDR_FMT_plx
366 " PDE: " TARGET_FMT_lx
"\n", va
, pa
, pde
);
367 for (m
= 0, va1
= va
; m
< 64; m
++, va1
+= 256 * 1024) {
368 pde
= mmu_probe(env
, va1
, 1);
370 pa
= cpu_get_phys_page_debug(cs
, va1
);
371 qemu_printf(" VA: " TARGET_FMT_lx
", PA: "
372 HWADDR_FMT_plx
" PDE: " TARGET_FMT_lx
"\n",
374 for (o
= 0, va2
= va1
; o
< 64; o
++, va2
+= 4 * 1024) {
375 pde
= mmu_probe(env
, va2
, 0);
377 pa
= cpu_get_phys_page_debug(cs
, va2
);
378 qemu_printf(" VA: " TARGET_FMT_lx
", PA: "
379 HWADDR_FMT_plx
" PTE: "
390 /* Gdb expects all registers windows to be flushed in ram. This function handles
391 * reads (and only reads) in stack frames as if windows were flushed. We assume
392 * that the sparc ABI is followed.
394 int sparc_cpu_memory_rw_debug(CPUState
*cs
, vaddr address
,
395 uint8_t *buf
, int len
, bool is_write
)
397 SPARCCPU
*cpu
= SPARC_CPU(cs
);
398 CPUSPARCState
*env
= &cpu
->env
;
399 target_ulong addr
= address
;
405 for (i
= 0; i
< env
->nwindows
; i
++) {
407 target_ulong fp
= env
->regbase
[cwp
* 16 + 22];
409 /* Assume fp == 0 means end of frame. */
414 cwp
= cpu_cwp_inc(env
, cwp
+ 1);
416 /* Invalid window ? */
417 if (env
->wim
& (1 << cwp
)) {
421 /* According to the ABI, the stack is growing downward. */
422 if (addr
+ len
< fp
) {
426 /* Not in this frame. */
427 if (addr
> fp
+ 64) {
431 /* Handle access before this window. */
434 if (cpu_memory_rw_debug(cs
, addr
, buf
, len1
, is_write
) != 0) {
442 /* Access byte per byte to registers. Not very efficient but speed
452 for (; len1
; len1
--) {
453 int reg
= cwp
* 16 + 8 + (off
>> 2);
458 u
.v
= cpu_to_be32(env
->regbase
[reg
]);
459 *buf
++ = u
.c
[off
& 3];
470 return cpu_memory_rw_debug(cs
, addr
, buf
, len
, is_write
);
473 #else /* !TARGET_SPARC64 */
475 /* 41 bit physical address space */
476 static inline hwaddr
ultrasparc_truncate_physical(uint64_t x
)
478 return x
& 0x1ffffffffffULL
;
482 * UltraSparc IIi I/DMMUs
485 /* Returns true if TTE tag is valid and matches virtual address value
486 in context requires virtual address mask value calculated from TTE
488 static inline int ultrasparc_tag_match(SparcTLBEntry
*tlb
,
489 uint64_t address
, uint64_t context
,
492 uint64_t mask
= -(8192ULL << 3 * TTE_PGSIZE(tlb
->tte
));
494 /* valid, context match, virtual address match? */
495 if (TTE_IS_VALID(tlb
->tte
) &&
496 (TTE_IS_GLOBAL(tlb
->tte
) || tlb_compare_context(tlb
, context
))
497 && compare_masked(address
, tlb
->tag
, mask
)) {
498 /* decode physical address */
499 *physical
= ((tlb
->tte
& mask
) | (address
& ~mask
)) & 0x1ffffffe000ULL
;
506 static uint64_t build_sfsr(CPUSPARCState
*env
, int mmu_idx
, int rw
)
508 uint64_t sfsr
= SFSR_VALID_BIT
;
512 sfsr
|= SFSR_CT_NOTRANS
;
516 sfsr
|= SFSR_CT_PRIMARY
;
518 case MMU_USER_SECONDARY_IDX
:
519 case MMU_KERNEL_SECONDARY_IDX
:
520 sfsr
|= SFSR_CT_SECONDARY
;
522 case MMU_NUCLEUS_IDX
:
523 sfsr
|= SFSR_CT_NUCLEUS
;
526 g_assert_not_reached();
530 sfsr
|= SFSR_WRITE_BIT
;
531 } else if (rw
== 4) {
535 if (env
->pstate
& PS_PRIV
) {
539 if (env
->dmmu
.sfsr
& SFSR_VALID_BIT
) { /* Fault status register */
540 sfsr
|= SFSR_OW_BIT
; /* overflow (not read before another fault) */
543 /* FIXME: ASI field in SFSR must be set */
548 static int get_physical_address_data(CPUSPARCState
*env
, hwaddr
*physical
,
549 int *prot
, MemTxAttrs
*attrs
,
550 target_ulong address
, int rw
, int mmu_idx
)
552 CPUState
*cs
= env_cpu(env
);
556 bool is_user
= false;
558 sfsr
= build_sfsr(env
, mmu_idx
, rw
);
562 g_assert_not_reached();
567 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
569 case MMU_USER_SECONDARY_IDX
:
572 case MMU_KERNEL_SECONDARY_IDX
:
573 context
= env
->dmmu
.mmu_secondary_context
& 0x1fff;
580 for (i
= 0; i
< 64; i
++) {
581 /* ctx match, vaddr match, valid? */
582 if (ultrasparc_tag_match(&env
->dtlb
[i
], address
, context
, physical
)) {
585 if (TTE_IS_IE(env
->dtlb
[i
].tte
)) {
586 attrs
->byte_swap
= true;
590 /* multiple bits in SFSR.FT may be set on TT_DFAULT */
591 if (TTE_IS_PRIV(env
->dtlb
[i
].tte
) && is_user
) {
593 sfsr
|= SFSR_FT_PRIV_BIT
; /* privilege violation */
594 trace_mmu_helper_dfault(address
, context
, mmu_idx
, env
->tl
);
597 if (TTE_IS_SIDEEFFECT(env
->dtlb
[i
].tte
)) {
599 sfsr
|= SFSR_FT_NF_E_BIT
;
602 if (TTE_IS_NFO(env
->dtlb
[i
].tte
)) {
604 sfsr
|= SFSR_FT_NFO_BIT
;
609 /* faults above are reported with TT_DFAULT. */
610 cs
->exception_index
= TT_DFAULT
;
611 } else if (!TTE_IS_W_OK(env
->dtlb
[i
].tte
) && (rw
== 1)) {
613 cs
->exception_index
= TT_DPROT
;
615 trace_mmu_helper_dprot(address
, context
, mmu_idx
, env
->tl
);
620 if (TTE_IS_W_OK(env
->dtlb
[i
].tte
)) {
624 TTE_SET_USED(env
->dtlb
[i
].tte
);
629 env
->dmmu
.sfsr
= sfsr
;
630 env
->dmmu
.sfar
= address
; /* Fault address register */
631 env
->dmmu
.tag_access
= (address
& ~0x1fffULL
) | context
;
636 trace_mmu_helper_dmiss(address
, context
);
640 * - UltraSPARC IIi: SFSR and SFAR unmodified
641 * - JPS1: SFAR updated and some fields of SFSR updated
643 env
->dmmu
.tag_access
= (address
& ~0x1fffULL
) | context
;
644 cs
->exception_index
= TT_DMISS
;
648 static int get_physical_address_code(CPUSPARCState
*env
, hwaddr
*physical
,
649 int *prot
, MemTxAttrs
*attrs
,
650 target_ulong address
, int mmu_idx
)
652 CPUState
*cs
= env_cpu(env
);
655 bool is_user
= false;
659 case MMU_USER_SECONDARY_IDX
:
660 case MMU_KERNEL_SECONDARY_IDX
:
661 g_assert_not_reached();
666 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
674 /* PRIMARY context */
675 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
677 /* NUCLEUS context */
681 for (i
= 0; i
< 64; i
++) {
682 /* ctx match, vaddr match, valid? */
683 if (ultrasparc_tag_match(&env
->itlb
[i
],
684 address
, context
, physical
)) {
686 if (TTE_IS_PRIV(env
->itlb
[i
].tte
) && is_user
) {
687 /* Fault status register */
688 if (env
->immu
.sfsr
& SFSR_VALID_BIT
) {
689 env
->immu
.sfsr
= SFSR_OW_BIT
; /* overflow (not read before
694 if (env
->pstate
& PS_PRIV
) {
695 env
->immu
.sfsr
|= SFSR_PR_BIT
;
698 env
->immu
.sfsr
|= SFSR_CT_NUCLEUS
;
701 /* FIXME: ASI field in SFSR must be set */
702 env
->immu
.sfsr
|= SFSR_FT_PRIV_BIT
| SFSR_VALID_BIT
;
703 cs
->exception_index
= TT_TFAULT
;
705 env
->immu
.tag_access
= (address
& ~0x1fffULL
) | context
;
707 trace_mmu_helper_tfault(address
, context
);
712 TTE_SET_USED(env
->itlb
[i
].tte
);
717 trace_mmu_helper_tmiss(address
, context
);
719 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
720 env
->immu
.tag_access
= (address
& ~0x1fffULL
) | context
;
721 cs
->exception_index
= TT_TMISS
;
725 static int get_physical_address(CPUSPARCState
*env
, hwaddr
*physical
,
726 int *prot
, int *access_index
, MemTxAttrs
*attrs
,
727 target_ulong address
, int rw
, int mmu_idx
,
728 target_ulong
*page_size
)
730 /* ??? We treat everything as a small page, then explicitly flush
731 everything when an entry is evicted. */
732 *page_size
= TARGET_PAGE_SIZE
;
734 /* safety net to catch wrong softmmu index use from dynamic code */
735 if (env
->tl
> 0 && mmu_idx
!= MMU_NUCLEUS_IDX
) {
737 trace_mmu_helper_get_phys_addr_code(env
->tl
, mmu_idx
,
738 env
->dmmu
.mmu_primary_context
,
739 env
->dmmu
.mmu_secondary_context
,
742 trace_mmu_helper_get_phys_addr_data(env
->tl
, mmu_idx
,
743 env
->dmmu
.mmu_primary_context
,
744 env
->dmmu
.mmu_secondary_context
,
749 if (mmu_idx
== MMU_PHYS_IDX
) {
750 *physical
= ultrasparc_truncate_physical(address
);
751 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
756 return get_physical_address_code(env
, physical
, prot
, attrs
, address
,
759 return get_physical_address_data(env
, physical
, prot
, attrs
, address
,
764 /* Perform address translation */
765 bool sparc_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
766 MMUAccessType access_type
, int mmu_idx
,
767 bool probe
, uintptr_t retaddr
)
769 SPARCCPU
*cpu
= SPARC_CPU(cs
);
770 CPUSPARCState
*env
= &cpu
->env
;
773 target_ulong page_size
;
774 MemTxAttrs attrs
= {};
775 int error_code
= 0, prot
, access_index
;
777 address
&= TARGET_PAGE_MASK
;
778 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
, &attrs
,
779 address
, access_type
,
780 mmu_idx
, &page_size
);
781 if (likely(error_code
== 0)) {
784 trace_mmu_helper_mmu_fault(address
, paddr
, mmu_idx
, env
->tl
,
785 env
->dmmu
.mmu_primary_context
,
786 env
->dmmu
.mmu_secondary_context
);
788 tlb_set_page_with_attrs(cs
, vaddr
, paddr
, attrs
, prot
, mmu_idx
,
795 cpu_loop_exit_restore(cs
, retaddr
);
798 void dump_mmu(CPUSPARCState
*env
)
803 qemu_printf("MMU contexts: Primary: %" PRId64
", Secondary: %"
805 env
->dmmu
.mmu_primary_context
,
806 env
->dmmu
.mmu_secondary_context
);
807 qemu_printf("DMMU Tag Access: %" PRIx64
", TSB Tag Target: %" PRIx64
808 "\n", env
->dmmu
.tag_access
, env
->dmmu
.tsb_tag_target
);
809 if ((env
->lsu
& DMMU_E
) == 0) {
810 qemu_printf("DMMU disabled\n");
812 qemu_printf("DMMU dump\n");
813 for (i
= 0; i
< 64; i
++) {
814 switch (TTE_PGSIZE(env
->dtlb
[i
].tte
)) {
829 if (TTE_IS_VALID(env
->dtlb
[i
].tte
)) {
830 qemu_printf("[%02u] VA: %" PRIx64
", PA: %llx"
831 ", %s, %s, %s, %s, ie %s, ctx %" PRId64
" %s\n",
833 env
->dtlb
[i
].tag
& (uint64_t)~0x1fffULL
,
834 TTE_PA(env
->dtlb
[i
].tte
),
836 TTE_IS_PRIV(env
->dtlb
[i
].tte
) ? "priv" : "user",
837 TTE_IS_W_OK(env
->dtlb
[i
].tte
) ? "RW" : "RO",
838 TTE_IS_LOCKED(env
->dtlb
[i
].tte
) ?
839 "locked" : "unlocked",
840 TTE_IS_IE(env
->dtlb
[i
].tte
) ?
842 env
->dtlb
[i
].tag
& (uint64_t)0x1fffULL
,
843 TTE_IS_GLOBAL(env
->dtlb
[i
].tte
) ?
848 if ((env
->lsu
& IMMU_E
) == 0) {
849 qemu_printf("IMMU disabled\n");
851 qemu_printf("IMMU dump\n");
852 for (i
= 0; i
< 64; i
++) {
853 switch (TTE_PGSIZE(env
->itlb
[i
].tte
)) {
868 if (TTE_IS_VALID(env
->itlb
[i
].tte
)) {
869 qemu_printf("[%02u] VA: %" PRIx64
", PA: %llx"
870 ", %s, %s, %s, ctx %" PRId64
" %s\n",
872 env
->itlb
[i
].tag
& (uint64_t)~0x1fffULL
,
873 TTE_PA(env
->itlb
[i
].tte
),
875 TTE_IS_PRIV(env
->itlb
[i
].tte
) ? "priv" : "user",
876 TTE_IS_LOCKED(env
->itlb
[i
].tte
) ?
877 "locked" : "unlocked",
878 env
->itlb
[i
].tag
& (uint64_t)0x1fffULL
,
879 TTE_IS_GLOBAL(env
->itlb
[i
].tte
) ?
886 #endif /* TARGET_SPARC64 */
888 static int cpu_sparc_get_phys_page(CPUSPARCState
*env
, hwaddr
*phys
,
889 target_ulong addr
, int rw
, int mmu_idx
)
891 target_ulong page_size
;
892 int prot
, access_index
;
893 MemTxAttrs attrs
= {};
895 return get_physical_address(env
, phys
, &prot
, &access_index
, &attrs
, addr
,
896 rw
, mmu_idx
, &page_size
);
899 #if defined(TARGET_SPARC64)
900 hwaddr
cpu_get_phys_page_nofault(CPUSPARCState
*env
, target_ulong addr
,
905 if (cpu_sparc_get_phys_page(env
, &phys_addr
, addr
, 4, mmu_idx
) != 0) {
912 hwaddr
sparc_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
914 SPARCCPU
*cpu
= SPARC_CPU(cs
);
915 CPUSPARCState
*env
= &cpu
->env
;
917 int mmu_idx
= cpu_mmu_index(env
, false);
919 if (cpu_sparc_get_phys_page(env
, &phys_addr
, addr
, 2, mmu_idx
) != 0) {
920 if (cpu_sparc_get_phys_page(env
, &phys_addr
, addr
, 0, mmu_idx
) != 0) {
927 #ifndef CONFIG_USER_ONLY
928 G_NORETURN
void sparc_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
929 MMUAccessType access_type
,
933 SPARCCPU
*cpu
= SPARC_CPU(cs
);
934 CPUSPARCState
*env
= &cpu
->env
;
936 #ifdef TARGET_SPARC64
937 env
->dmmu
.sfsr
= build_sfsr(env
, mmu_idx
, access_type
);
938 env
->dmmu
.sfar
= addr
;
940 env
->mmuregs
[4] = addr
;
943 cpu_raise_exception_ra(env
, TT_UNALIGNED
, retaddr
);
945 #endif /* !CONFIG_USER_ONLY */