4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "qemu/qemu-print.h"
26 /* Sparc MMU emulation */
28 #if defined(CONFIG_USER_ONLY)
30 bool sparc_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
31 MMUAccessType access_type
, int mmu_idx
,
32 bool probe
, uintptr_t retaddr
)
34 SPARCCPU
*cpu
= SPARC_CPU(cs
);
35 CPUSPARCState
*env
= &cpu
->env
;
37 if (access_type
== MMU_INST_FETCH
) {
38 cs
->exception_index
= TT_TFAULT
;
40 cs
->exception_index
= TT_DFAULT
;
42 env
->dmmu
.mmuregs
[4] = address
;
44 env
->mmuregs
[4] = address
;
47 cpu_loop_exit_restore(cs
, retaddr
);
52 #ifndef TARGET_SPARC64
54 * Sparc V8 Reference MMU (SRMMU)
56 static const int access_table
[8][8] = {
57 { 0, 0, 0, 0, 8, 0, 12, 12 },
58 { 0, 0, 0, 0, 8, 0, 0, 0 },
59 { 8, 8, 0, 0, 0, 8, 12, 12 },
60 { 8, 8, 0, 0, 0, 8, 0, 0 },
61 { 8, 0, 8, 0, 8, 8, 12, 12 },
62 { 8, 0, 8, 0, 8, 0, 8, 0 },
63 { 8, 8, 8, 0, 8, 8, 12, 12 },
64 { 8, 8, 8, 0, 8, 8, 8, 0 }
67 static const int perm_table
[2][8] = {
70 PAGE_READ
| PAGE_WRITE
,
71 PAGE_READ
| PAGE_EXEC
,
72 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
74 PAGE_READ
| PAGE_WRITE
,
75 PAGE_READ
| PAGE_EXEC
,
76 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
80 PAGE_READ
| PAGE_WRITE
,
81 PAGE_READ
| PAGE_EXEC
,
82 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
,
90 static int get_physical_address(CPUSPARCState
*env
, hwaddr
*physical
,
91 int *prot
, int *access_index
, MemTxAttrs
*attrs
,
92 target_ulong address
, int rw
, int mmu_idx
,
93 target_ulong
*page_size
)
98 int error_code
= 0, is_dirty
, is_user
;
99 unsigned long page_offset
;
100 CPUState
*cs
= env_cpu(env
);
102 is_user
= mmu_idx
== MMU_USER_IDX
;
104 if (mmu_idx
== MMU_PHYS_IDX
) {
105 *page_size
= TARGET_PAGE_SIZE
;
106 /* Boot mode: instruction fetches are taken from PROM */
107 if (rw
== 2 && (env
->mmuregs
[0] & env
->def
.mmu_bm
)) {
108 *physical
= env
->prom_addr
| (address
& 0x7ffffULL
);
109 *prot
= PAGE_READ
| PAGE_EXEC
;
113 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
117 *access_index
= ((rw
& 1) << 2) | (rw
& 2) | (is_user
? 0 : 1);
118 *physical
= 0xffffffffffff0000ULL
;
120 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
121 /* Context base + context number */
122 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
123 pde
= ldl_phys(cs
->as
, pde_ptr
);
126 switch (pde
& PTE_ENTRYTYPE_MASK
) {
128 case 0: /* Invalid */
130 case 2: /* L0 PTE, maybe should not happen? */
131 case 3: /* Reserved */
134 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
135 pde
= ldl_phys(cs
->as
, pde_ptr
);
137 switch (pde
& PTE_ENTRYTYPE_MASK
) {
139 case 0: /* Invalid */
140 return (1 << 8) | (1 << 2);
141 case 3: /* Reserved */
142 return (1 << 8) | (4 << 2);
144 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
145 pde
= ldl_phys(cs
->as
, pde_ptr
);
147 switch (pde
& PTE_ENTRYTYPE_MASK
) {
149 case 0: /* Invalid */
150 return (2 << 8) | (1 << 2);
151 case 3: /* Reserved */
152 return (2 << 8) | (4 << 2);
154 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
155 pde
= ldl_phys(cs
->as
, pde_ptr
);
157 switch (pde
& PTE_ENTRYTYPE_MASK
) {
159 case 0: /* Invalid */
160 return (3 << 8) | (1 << 2);
161 case 1: /* PDE, should not happen */
162 case 3: /* Reserved */
163 return (3 << 8) | (4 << 2);
167 *page_size
= TARGET_PAGE_SIZE
;
170 page_offset
= address
& 0x3f000;
171 *page_size
= 0x40000;
175 page_offset
= address
& 0xfff000;
176 *page_size
= 0x1000000;
181 access_perms
= (pde
& PTE_ACCESS_MASK
) >> PTE_ACCESS_SHIFT
;
182 error_code
= access_table
[*access_index
][access_perms
];
183 if (error_code
&& !((env
->mmuregs
[0] & MMU_NF
) && is_user
)) {
187 /* update page modified and dirty bits */
188 is_dirty
= (rw
& 1) && !(pde
& PG_MODIFIED_MASK
);
189 if (!(pde
& PG_ACCESSED_MASK
) || is_dirty
) {
190 pde
|= PG_ACCESSED_MASK
;
192 pde
|= PG_MODIFIED_MASK
;
194 stl_phys_notdirty(cs
->as
, pde_ptr
, pde
);
197 /* the page can be put in the TLB */
198 *prot
= perm_table
[is_user
][access_perms
];
199 if (!(pde
& PG_MODIFIED_MASK
)) {
200 /* only set write access if already dirty... otherwise wait
202 *prot
&= ~PAGE_WRITE
;
205 /* Even if large ptes, we map only one 4KB page in the cache to
206 avoid filling it too fast */
207 *physical
= ((hwaddr
)(pde
& PTE_ADDR_MASK
) << 4) + page_offset
;
211 /* Perform address translation */
212 bool sparc_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
213 MMUAccessType access_type
, int mmu_idx
,
214 bool probe
, uintptr_t retaddr
)
216 SPARCCPU
*cpu
= SPARC_CPU(cs
);
217 CPUSPARCState
*env
= &cpu
->env
;
220 target_ulong page_size
;
221 int error_code
= 0, prot
, access_index
;
222 MemTxAttrs attrs
= {};
225 * TODO: If we ever need tlb_vaddr_to_host for this target,
226 * then we must figure out how to manipulate FSR and FAR
227 * when both MMU_NF and probe are set. In the meantime,
228 * do not support this use case.
232 address
&= TARGET_PAGE_MASK
;
233 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
, &attrs
,
234 address
, access_type
,
235 mmu_idx
, &page_size
);
237 if (likely(error_code
== 0)) {
238 qemu_log_mask(CPU_LOG_MMU
,
239 "Translate at %" VADDR_PRIx
" -> "
240 TARGET_FMT_plx
", vaddr " TARGET_FMT_lx
"\n",
241 address
, paddr
, vaddr
);
242 tlb_set_page(cs
, vaddr
, paddr
, prot
, mmu_idx
, page_size
);
246 if (env
->mmuregs
[3]) { /* Fault status register */
247 env
->mmuregs
[3] = 1; /* overflow (not read before another fault) */
249 env
->mmuregs
[3] |= (access_index
<< 5) | error_code
| 2;
250 env
->mmuregs
[4] = address
; /* Fault address register */
252 if ((env
->mmuregs
[0] & MMU_NF
) || env
->psret
== 0) {
253 /* No fault mode: if a mapping is available, just override
254 permissions. If no mapping is available, redirect accesses to
255 neverland. Fake/overridden mappings will be flushed when
256 switching to normal mode. */
257 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
258 tlb_set_page(cs
, vaddr
, paddr
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
261 if (access_type
== MMU_INST_FETCH
) {
262 cs
->exception_index
= TT_TFAULT
;
264 cs
->exception_index
= TT_DFAULT
;
266 cpu_loop_exit_restore(cs
, retaddr
);
270 target_ulong
mmu_probe(CPUSPARCState
*env
, target_ulong address
, int mmulev
)
272 CPUState
*cs
= env_cpu(env
);
276 /* Context base + context number */
277 pde_ptr
= (hwaddr
)(env
->mmuregs
[1] << 4) +
278 (env
->mmuregs
[2] << 2);
279 pde
= ldl_phys(cs
->as
, pde_ptr
);
281 switch (pde
& PTE_ENTRYTYPE_MASK
) {
283 case 0: /* Invalid */
284 case 2: /* PTE, maybe should not happen? */
285 case 3: /* Reserved */
291 pde_ptr
= ((address
>> 22) & ~3) + ((pde
& ~3) << 4);
292 pde
= ldl_phys(cs
->as
, pde_ptr
);
294 switch (pde
& PTE_ENTRYTYPE_MASK
) {
296 case 0: /* Invalid */
297 case 3: /* Reserved */
305 pde_ptr
= ((address
& 0xfc0000) >> 16) + ((pde
& ~3) << 4);
306 pde
= ldl_phys(cs
->as
, pde_ptr
);
308 switch (pde
& PTE_ENTRYTYPE_MASK
) {
310 case 0: /* Invalid */
311 case 3: /* Reserved */
319 pde_ptr
= ((address
& 0x3f000) >> 10) + ((pde
& ~3) << 4);
320 pde
= ldl_phys(cs
->as
, pde_ptr
);
322 switch (pde
& PTE_ENTRYTYPE_MASK
) {
324 case 0: /* Invalid */
325 case 1: /* PDE, should not happen */
326 case 3: /* Reserved */
337 void dump_mmu(CPUSPARCState
*env
)
339 CPUState
*cs
= env_cpu(env
);
340 target_ulong va
, va1
, va2
;
341 unsigned int n
, m
, o
;
345 pde_ptr
= (env
->mmuregs
[1] << 4) + (env
->mmuregs
[2] << 2);
346 pde
= ldl_phys(cs
->as
, pde_ptr
);
347 qemu_printf("Root ptr: " TARGET_FMT_plx
", ctx: %d\n",
348 (hwaddr
)env
->mmuregs
[1] << 4, env
->mmuregs
[2]);
349 for (n
= 0, va
= 0; n
< 256; n
++, va
+= 16 * 1024 * 1024) {
350 pde
= mmu_probe(env
, va
, 2);
352 pa
= cpu_get_phys_page_debug(cs
, va
);
353 qemu_printf("VA: " TARGET_FMT_lx
", PA: " TARGET_FMT_plx
354 " PDE: " TARGET_FMT_lx
"\n", va
, pa
, pde
);
355 for (m
= 0, va1
= va
; m
< 64; m
++, va1
+= 256 * 1024) {
356 pde
= mmu_probe(env
, va1
, 1);
358 pa
= cpu_get_phys_page_debug(cs
, va1
);
359 qemu_printf(" VA: " TARGET_FMT_lx
", PA: "
360 TARGET_FMT_plx
" PDE: " TARGET_FMT_lx
"\n",
362 for (o
= 0, va2
= va1
; o
< 64; o
++, va2
+= 4 * 1024) {
363 pde
= mmu_probe(env
, va2
, 0);
365 pa
= cpu_get_phys_page_debug(cs
, va2
);
366 qemu_printf(" VA: " TARGET_FMT_lx
", PA: "
367 TARGET_FMT_plx
" PTE: "
378 /* Gdb expects all registers windows to be flushed in ram. This function handles
379 * reads (and only reads) in stack frames as if windows were flushed. We assume
380 * that the sparc ABI is followed.
382 int sparc_cpu_memory_rw_debug(CPUState
*cs
, vaddr address
,
383 uint8_t *buf
, int len
, bool is_write
)
385 SPARCCPU
*cpu
= SPARC_CPU(cs
);
386 CPUSPARCState
*env
= &cpu
->env
;
387 target_ulong addr
= address
;
393 for (i
= 0; i
< env
->nwindows
; i
++) {
395 target_ulong fp
= env
->regbase
[cwp
* 16 + 22];
397 /* Assume fp == 0 means end of frame. */
402 cwp
= cpu_cwp_inc(env
, cwp
+ 1);
404 /* Invalid window ? */
405 if (env
->wim
& (1 << cwp
)) {
409 /* According to the ABI, the stack is growing downward. */
410 if (addr
+ len
< fp
) {
414 /* Not in this frame. */
415 if (addr
> fp
+ 64) {
419 /* Handle access before this window. */
422 if (cpu_memory_rw_debug(cs
, addr
, buf
, len1
, is_write
) != 0) {
430 /* Access byte per byte to registers. Not very efficient but speed
440 for (; len1
; len1
--) {
441 int reg
= cwp
* 16 + 8 + (off
>> 2);
446 u
.v
= cpu_to_be32(env
->regbase
[reg
]);
447 *buf
++ = u
.c
[off
& 3];
458 return cpu_memory_rw_debug(cs
, addr
, buf
, len
, is_write
);
461 #else /* !TARGET_SPARC64 */
463 /* 41 bit physical address space */
464 static inline hwaddr
ultrasparc_truncate_physical(uint64_t x
)
466 return x
& 0x1ffffffffffULL
;
470 * UltraSparc IIi I/DMMUs
473 /* Returns true if TTE tag is valid and matches virtual address value
474 in context requires virtual address mask value calculated from TTE
476 static inline int ultrasparc_tag_match(SparcTLBEntry
*tlb
,
477 uint64_t address
, uint64_t context
,
480 uint64_t mask
= -(8192ULL << 3 * TTE_PGSIZE(tlb
->tte
));
482 /* valid, context match, virtual address match? */
483 if (TTE_IS_VALID(tlb
->tte
) &&
484 (TTE_IS_GLOBAL(tlb
->tte
) || tlb_compare_context(tlb
, context
))
485 && compare_masked(address
, tlb
->tag
, mask
)) {
486 /* decode physical address */
487 *physical
= ((tlb
->tte
& mask
) | (address
& ~mask
)) & 0x1ffffffe000ULL
;
494 static int get_physical_address_data(CPUSPARCState
*env
, hwaddr
*physical
,
495 int *prot
, MemTxAttrs
*attrs
,
496 target_ulong address
, int rw
, int mmu_idx
)
498 CPUState
*cs
= env_cpu(env
);
502 bool is_user
= false;
506 g_assert_not_reached();
511 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
512 sfsr
|= SFSR_CT_PRIMARY
;
514 case MMU_USER_SECONDARY_IDX
:
517 case MMU_KERNEL_SECONDARY_IDX
:
518 context
= env
->dmmu
.mmu_secondary_context
& 0x1fff;
519 sfsr
|= SFSR_CT_SECONDARY
;
521 case MMU_NUCLEUS_IDX
:
522 sfsr
|= SFSR_CT_NUCLEUS
;
530 sfsr
|= SFSR_WRITE_BIT
;
531 } else if (rw
== 4) {
535 for (i
= 0; i
< 64; i
++) {
536 /* ctx match, vaddr match, valid? */
537 if (ultrasparc_tag_match(&env
->dtlb
[i
], address
, context
, physical
)) {
540 if (TTE_IS_IE(env
->dtlb
[i
].tte
)) {
541 attrs
->byte_swap
= true;
545 /* multiple bits in SFSR.FT may be set on TT_DFAULT */
546 if (TTE_IS_PRIV(env
->dtlb
[i
].tte
) && is_user
) {
548 sfsr
|= SFSR_FT_PRIV_BIT
; /* privilege violation */
549 trace_mmu_helper_dfault(address
, context
, mmu_idx
, env
->tl
);
552 if (TTE_IS_SIDEEFFECT(env
->dtlb
[i
].tte
)) {
554 sfsr
|= SFSR_FT_NF_E_BIT
;
557 if (TTE_IS_NFO(env
->dtlb
[i
].tte
)) {
559 sfsr
|= SFSR_FT_NFO_BIT
;
564 /* faults above are reported with TT_DFAULT. */
565 cs
->exception_index
= TT_DFAULT
;
566 } else if (!TTE_IS_W_OK(env
->dtlb
[i
].tte
) && (rw
== 1)) {
568 cs
->exception_index
= TT_DPROT
;
570 trace_mmu_helper_dprot(address
, context
, mmu_idx
, env
->tl
);
575 if (TTE_IS_W_OK(env
->dtlb
[i
].tte
)) {
579 TTE_SET_USED(env
->dtlb
[i
].tte
);
584 if (env
->dmmu
.sfsr
& SFSR_VALID_BIT
) { /* Fault status register */
585 sfsr
|= SFSR_OW_BIT
; /* overflow (not read before
589 if (env
->pstate
& PS_PRIV
) {
593 /* FIXME: ASI field in SFSR must be set */
594 env
->dmmu
.sfsr
= sfsr
| SFSR_VALID_BIT
;
596 env
->dmmu
.sfar
= address
; /* Fault address register */
598 env
->dmmu
.tag_access
= (address
& ~0x1fffULL
) | context
;
604 trace_mmu_helper_dmiss(address
, context
);
608 * - UltraSPARC IIi: SFSR and SFAR unmodified
609 * - JPS1: SFAR updated and some fields of SFSR updated
611 env
->dmmu
.tag_access
= (address
& ~0x1fffULL
) | context
;
612 cs
->exception_index
= TT_DMISS
;
616 static int get_physical_address_code(CPUSPARCState
*env
, hwaddr
*physical
,
617 int *prot
, MemTxAttrs
*attrs
,
618 target_ulong address
, int mmu_idx
)
620 CPUState
*cs
= env_cpu(env
);
623 bool is_user
= false;
627 case MMU_USER_SECONDARY_IDX
:
628 case MMU_KERNEL_SECONDARY_IDX
:
629 g_assert_not_reached();
634 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
642 /* PRIMARY context */
643 context
= env
->dmmu
.mmu_primary_context
& 0x1fff;
645 /* NUCLEUS context */
649 for (i
= 0; i
< 64; i
++) {
650 /* ctx match, vaddr match, valid? */
651 if (ultrasparc_tag_match(&env
->itlb
[i
],
652 address
, context
, physical
)) {
654 if (TTE_IS_PRIV(env
->itlb
[i
].tte
) && is_user
) {
655 /* Fault status register */
656 if (env
->immu
.sfsr
& SFSR_VALID_BIT
) {
657 env
->immu
.sfsr
= SFSR_OW_BIT
; /* overflow (not read before
662 if (env
->pstate
& PS_PRIV
) {
663 env
->immu
.sfsr
|= SFSR_PR_BIT
;
666 env
->immu
.sfsr
|= SFSR_CT_NUCLEUS
;
669 /* FIXME: ASI field in SFSR must be set */
670 env
->immu
.sfsr
|= SFSR_FT_PRIV_BIT
| SFSR_VALID_BIT
;
671 cs
->exception_index
= TT_TFAULT
;
673 env
->immu
.tag_access
= (address
& ~0x1fffULL
) | context
;
675 trace_mmu_helper_tfault(address
, context
);
680 TTE_SET_USED(env
->itlb
[i
].tte
);
685 trace_mmu_helper_tmiss(address
, context
);
687 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
688 env
->immu
.tag_access
= (address
& ~0x1fffULL
) | context
;
689 cs
->exception_index
= TT_TMISS
;
693 static int get_physical_address(CPUSPARCState
*env
, hwaddr
*physical
,
694 int *prot
, int *access_index
, MemTxAttrs
*attrs
,
695 target_ulong address
, int rw
, int mmu_idx
,
696 target_ulong
*page_size
)
698 /* ??? We treat everything as a small page, then explicitly flush
699 everything when an entry is evicted. */
700 *page_size
= TARGET_PAGE_SIZE
;
702 /* safety net to catch wrong softmmu index use from dynamic code */
703 if (env
->tl
> 0 && mmu_idx
!= MMU_NUCLEUS_IDX
) {
705 trace_mmu_helper_get_phys_addr_code(env
->tl
, mmu_idx
,
706 env
->dmmu
.mmu_primary_context
,
707 env
->dmmu
.mmu_secondary_context
,
710 trace_mmu_helper_get_phys_addr_data(env
->tl
, mmu_idx
,
711 env
->dmmu
.mmu_primary_context
,
712 env
->dmmu
.mmu_secondary_context
,
717 if (mmu_idx
== MMU_PHYS_IDX
) {
718 *physical
= ultrasparc_truncate_physical(address
);
719 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
724 return get_physical_address_code(env
, physical
, prot
, attrs
, address
,
727 return get_physical_address_data(env
, physical
, prot
, attrs
, address
,
732 /* Perform address translation */
733 bool sparc_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
734 MMUAccessType access_type
, int mmu_idx
,
735 bool probe
, uintptr_t retaddr
)
737 SPARCCPU
*cpu
= SPARC_CPU(cs
);
738 CPUSPARCState
*env
= &cpu
->env
;
741 target_ulong page_size
;
742 MemTxAttrs attrs
= {};
743 int error_code
= 0, prot
, access_index
;
745 address
&= TARGET_PAGE_MASK
;
746 error_code
= get_physical_address(env
, &paddr
, &prot
, &access_index
, &attrs
,
747 address
, access_type
,
748 mmu_idx
, &page_size
);
749 if (likely(error_code
== 0)) {
752 trace_mmu_helper_mmu_fault(address
, paddr
, mmu_idx
, env
->tl
,
753 env
->dmmu
.mmu_primary_context
,
754 env
->dmmu
.mmu_secondary_context
);
756 tlb_set_page_with_attrs(cs
, vaddr
, paddr
, attrs
, prot
, mmu_idx
,
763 cpu_loop_exit_restore(cs
, retaddr
);
766 void dump_mmu(CPUSPARCState
*env
)
771 qemu_printf("MMU contexts: Primary: %" PRId64
", Secondary: %"
773 env
->dmmu
.mmu_primary_context
,
774 env
->dmmu
.mmu_secondary_context
);
775 qemu_printf("DMMU Tag Access: %" PRIx64
", TSB Tag Target: %" PRIx64
776 "\n", env
->dmmu
.tag_access
, env
->dmmu
.tsb_tag_target
);
777 if ((env
->lsu
& DMMU_E
) == 0) {
778 qemu_printf("DMMU disabled\n");
780 qemu_printf("DMMU dump\n");
781 for (i
= 0; i
< 64; i
++) {
782 switch (TTE_PGSIZE(env
->dtlb
[i
].tte
)) {
797 if (TTE_IS_VALID(env
->dtlb
[i
].tte
)) {
798 qemu_printf("[%02u] VA: %" PRIx64
", PA: %llx"
799 ", %s, %s, %s, %s, ie %s, ctx %" PRId64
" %s\n",
801 env
->dtlb
[i
].tag
& (uint64_t)~0x1fffULL
,
802 TTE_PA(env
->dtlb
[i
].tte
),
804 TTE_IS_PRIV(env
->dtlb
[i
].tte
) ? "priv" : "user",
805 TTE_IS_W_OK(env
->dtlb
[i
].tte
) ? "RW" : "RO",
806 TTE_IS_LOCKED(env
->dtlb
[i
].tte
) ?
807 "locked" : "unlocked",
808 TTE_IS_IE(env
->dtlb
[i
].tte
) ?
810 env
->dtlb
[i
].tag
& (uint64_t)0x1fffULL
,
811 TTE_IS_GLOBAL(env
->dtlb
[i
].tte
) ?
816 if ((env
->lsu
& IMMU_E
) == 0) {
817 qemu_printf("IMMU disabled\n");
819 qemu_printf("IMMU dump\n");
820 for (i
= 0; i
< 64; i
++) {
821 switch (TTE_PGSIZE(env
->itlb
[i
].tte
)) {
836 if (TTE_IS_VALID(env
->itlb
[i
].tte
)) {
837 qemu_printf("[%02u] VA: %" PRIx64
", PA: %llx"
838 ", %s, %s, %s, ctx %" PRId64
" %s\n",
840 env
->itlb
[i
].tag
& (uint64_t)~0x1fffULL
,
841 TTE_PA(env
->itlb
[i
].tte
),
843 TTE_IS_PRIV(env
->itlb
[i
].tte
) ? "priv" : "user",
844 TTE_IS_LOCKED(env
->itlb
[i
].tte
) ?
845 "locked" : "unlocked",
846 env
->itlb
[i
].tag
& (uint64_t)0x1fffULL
,
847 TTE_IS_GLOBAL(env
->itlb
[i
].tte
) ?
854 #endif /* TARGET_SPARC64 */
856 static int cpu_sparc_get_phys_page(CPUSPARCState
*env
, hwaddr
*phys
,
857 target_ulong addr
, int rw
, int mmu_idx
)
859 target_ulong page_size
;
860 int prot
, access_index
;
861 MemTxAttrs attrs
= {};
863 return get_physical_address(env
, phys
, &prot
, &access_index
, &attrs
, addr
,
864 rw
, mmu_idx
, &page_size
);
867 #if defined(TARGET_SPARC64)
868 hwaddr
cpu_get_phys_page_nofault(CPUSPARCState
*env
, target_ulong addr
,
873 if (cpu_sparc_get_phys_page(env
, &phys_addr
, addr
, 4, mmu_idx
) != 0) {
880 hwaddr
sparc_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
882 SPARCCPU
*cpu
= SPARC_CPU(cs
);
883 CPUSPARCState
*env
= &cpu
->env
;
885 int mmu_idx
= cpu_mmu_index(env
, false);
887 if (cpu_sparc_get_phys_page(env
, &phys_addr
, addr
, 2, mmu_idx
) != 0) {
888 if (cpu_sparc_get_phys_page(env
, &phys_addr
, addr
, 0, mmu_idx
) != 0) {