4 #include "host-utils.h"
5 #if !defined(CONFIG_USER_ONLY)
10 static uint32_t cortexa15_cp15_c0_c1
[8] = {
11 0x00001131, 0x00011011, 0x02010555, 0x00000000,
12 0x10201105, 0x20000000, 0x01240000, 0x02102211
15 static uint32_t cortexa15_cp15_c0_c2
[8] = {
16 0x02101110, 0x13112111, 0x21232041, 0x11112131, 0x10011142, 0, 0, 0
19 static uint32_t cortexa9_cp15_c0_c1
[8] =
20 { 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
22 static uint32_t cortexa9_cp15_c0_c2
[8] =
23 { 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };
25 static uint32_t cortexa8_cp15_c0_c1
[8] =
26 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
28 static uint32_t cortexa8_cp15_c0_c2
[8] =
29 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
31 static uint32_t mpcore_cp15_c0_c1
[8] =
32 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
34 static uint32_t mpcore_cp15_c0_c2
[8] =
35 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
37 static uint32_t arm1136_cp15_c0_c1
[8] =
38 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
40 static uint32_t arm1136_cp15_c0_c2
[8] =
41 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
43 static uint32_t arm1176_cp15_c0_c1
[8] =
44 { 0x111, 0x11, 0x33, 0, 0x01130003, 0x10030302, 0x01222100, 0 };
46 static uint32_t arm1176_cp15_c0_c2
[8] =
47 { 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
49 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
52 case ARM_CPUID_ARM926
:
53 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
54 env
->cp15
.c0_cachetype
= 0x1dd20d2;
55 env
->cp15
.c1_sys
= 0x00090078;
57 case ARM_CPUID_ARM946
:
58 env
->cp15
.c0_cachetype
= 0x0f004006;
59 env
->cp15
.c1_sys
= 0x00000078;
61 case ARM_CPUID_ARM1026
:
62 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
63 env
->cp15
.c0_cachetype
= 0x1dd20d2;
64 env
->cp15
.c1_sys
= 0x00090078;
66 case ARM_CPUID_ARM1136
:
67 /* This is the 1136 r1, which is a v6K core */
68 case ARM_CPUID_ARM1136_R2
:
69 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
70 * older core than plain "arm1136". In particular this does not
71 * have the v6K features.
73 /* These ID register values are correct for 1136 but may be wrong
74 * for 1136_r2 (in particular r0p2 does not actually implement most
75 * of the ID registers).
77 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
78 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
79 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
80 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
81 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
82 env
->cp15
.c0_cachetype
= 0x1dd20d2;
83 env
->cp15
.c1_sys
= 0x00050078;
85 case ARM_CPUID_ARM1176
:
86 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b5;
87 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
88 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
89 memcpy(env
->cp15
.c0_c1
, arm1176_cp15_c0_c1
, 8 * sizeof(uint32_t));
90 memcpy(env
->cp15
.c0_c2
, arm1176_cp15_c0_c2
, 8 * sizeof(uint32_t));
91 env
->cp15
.c0_cachetype
= 0x1dd20d2;
92 env
->cp15
.c1_sys
= 0x00050078;
94 case ARM_CPUID_ARM11MPCORE
:
95 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
96 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
97 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
98 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
99 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
100 env
->cp15
.c0_cachetype
= 0x1dd20d2;
102 case ARM_CPUID_CORTEXA8
:
103 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
104 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
105 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
106 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
107 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
108 env
->cp15
.c0_cachetype
= 0x82048004;
109 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
110 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
111 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
112 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
113 env
->cp15
.c1_sys
= 0x00c50078;
115 case ARM_CPUID_CORTEXA9
:
116 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41033090;
117 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
118 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x01111111;
119 memcpy(env
->cp15
.c0_c1
, cortexa9_cp15_c0_c1
, 8 * sizeof(uint32_t));
120 memcpy(env
->cp15
.c0_c2
, cortexa9_cp15_c0_c2
, 8 * sizeof(uint32_t));
121 env
->cp15
.c0_cachetype
= 0x80038003;
122 env
->cp15
.c0_clid
= (1 << 27) | (1 << 24) | 3;
123 env
->cp15
.c0_ccsid
[0] = 0xe00fe015; /* 16k L1 dcache. */
124 env
->cp15
.c0_ccsid
[1] = 0x200fe015; /* 16k L1 icache. */
125 env
->cp15
.c1_sys
= 0x00c50078;
127 case ARM_CPUID_CORTEXA15
:
128 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410430f0;
129 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x10110222;
130 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x11111111;
131 memcpy(env
->cp15
.c0_c1
, cortexa15_cp15_c0_c1
, 8 * sizeof(uint32_t));
132 memcpy(env
->cp15
.c0_c2
, cortexa15_cp15_c0_c2
, 8 * sizeof(uint32_t));
133 env
->cp15
.c0_cachetype
= 0x8444c004;
134 env
->cp15
.c0_clid
= 0x0a200023;
135 env
->cp15
.c0_ccsid
[0] = 0x701fe00a; /* 32K L1 dcache */
136 env
->cp15
.c0_ccsid
[1] = 0x201fe00a; /* 32K L1 icache */
137 env
->cp15
.c0_ccsid
[2] = 0x711fe07a; /* 4096K L2 unified cache */
138 env
->cp15
.c1_sys
= 0x00c50078;
140 case ARM_CPUID_CORTEXM3
:
142 case ARM_CPUID_ANY
: /* For userspace emulation. */
144 case ARM_CPUID_TI915T
:
145 case ARM_CPUID_TI925T
:
146 env
->cp15
.c0_cachetype
= 0x5109149;
147 env
->cp15
.c1_sys
= 0x00000070;
148 env
->cp15
.c15_i_max
= 0x000;
149 env
->cp15
.c15_i_min
= 0xff0;
151 case ARM_CPUID_PXA250
:
152 case ARM_CPUID_PXA255
:
153 case ARM_CPUID_PXA260
:
154 case ARM_CPUID_PXA261
:
155 case ARM_CPUID_PXA262
:
156 /* JTAG_ID is ((id << 28) | 0x09265013) */
157 env
->cp15
.c0_cachetype
= 0xd172172;
158 env
->cp15
.c1_sys
= 0x00000078;
160 case ARM_CPUID_PXA270_A0
:
161 case ARM_CPUID_PXA270_A1
:
162 case ARM_CPUID_PXA270_B0
:
163 case ARM_CPUID_PXA270_B1
:
164 case ARM_CPUID_PXA270_C0
:
165 case ARM_CPUID_PXA270_C5
:
166 /* JTAG_ID is ((id << 28) | 0x09265013) */
167 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
168 env
->cp15
.c0_cachetype
= 0xd172172;
169 env
->cp15
.c1_sys
= 0x00000078;
171 case ARM_CPUID_SA1100
:
172 case ARM_CPUID_SA1110
:
173 env
->cp15
.c1_sys
= 0x00000070;
176 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
182 /* TODO Move contents into arm_cpu_reset() in cpu.c,
183 * once cpu_reset_model_id() is eliminated,
184 * and then forward to cpu_reset() here.
186 void cpu_state_reset(CPUARMState
*env
)
190 ARMCPU
*cpu
= arm_env_get_cpu(env
);
192 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
193 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
194 log_cpu_state(env
, 0);
198 tmp
= env
->cp15
.c15_config_base_address
;
199 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
201 cpu_reset_model_id(env
, id
);
202 env
->cp15
.c15_config_base_address
= tmp
;
203 env
->cp15
.c0_cpuid
= cpu
->midr
;
204 #if defined (CONFIG_USER_ONLY)
205 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
206 /* For user mode we must enable access to coprocessors */
207 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
208 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
209 env
->cp15
.c15_cpar
= 3;
210 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
211 env
->cp15
.c15_cpar
= 1;
214 /* SVC mode with interrupts disabled. */
215 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
216 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
217 clear at reset. Initial SP and PC are loaded from ROM. */
221 env
->uncached_cpsr
&= ~CPSR_I
;
224 /* We should really use ldl_phys here, in case the guest
225 modified flash and reset itself. However images
226 loaded via -kernel have not been copied yet, so load the
227 values directly from there. */
228 env
->regs
[13] = ldl_p(rom
);
231 env
->regs
[15] = pc
& ~1;
234 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
235 env
->cp15
.c2_base_mask
= 0xffffc000u
;
236 /* v7 performance monitor control register: same implementor
237 * field as main ID register, and we implement no event counters.
239 env
->cp15
.c9_pmcr
= (id
& 0xff000000);
241 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
242 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
243 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
244 set_float_detect_tininess(float_tininess_before_rounding
,
245 &env
->vfp
.fp_status
);
246 set_float_detect_tininess(float_tininess_before_rounding
,
247 &env
->vfp
.standard_fp_status
);
249 /* Reset is a state change for some CPUARMState fields which we
250 * bake assumptions about into translated code, so we need to
256 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
260 /* VFP data registers are always little-endian. */
261 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
263 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
266 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
267 /* Aliases for Q regs. */
270 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
271 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
275 switch (reg
- nregs
) {
276 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
277 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
278 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
283 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
287 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
289 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
292 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
295 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
296 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
300 switch (reg
- nregs
) {
301 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
302 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
303 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
308 CPUARMState
*cpu_arm_init(const char *cpu_model
)
312 static int inited
= 0;
314 if (!object_class_by_name(cpu_model
)) {
317 cpu
= ARM_CPU(object_new(cpu_model
));
319 env
->cpu_model_str
= cpu_model
;
320 arm_cpu_realize(cpu
);
322 if (tcg_enabled() && !inited
) {
324 arm_translate_init();
327 cpu_state_reset(env
);
328 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
329 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
330 51, "arm-neon.xml", 0);
331 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
332 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
333 35, "arm-vfp3.xml", 0);
334 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
335 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
336 19, "arm-vfp.xml", 0);
342 typedef struct ARMCPUListState
{
343 fprintf_function cpu_fprintf
;
347 /* Sort alphabetically by type name, except for "any". */
348 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
350 ObjectClass
*class_a
= (ObjectClass
*)a
;
351 ObjectClass
*class_b
= (ObjectClass
*)b
;
352 const char *name_a
, *name_b
;
354 name_a
= object_class_get_name(class_a
);
355 name_b
= object_class_get_name(class_b
);
356 if (strcmp(name_a
, "any") == 0) {
358 } else if (strcmp(name_b
, "any") == 0) {
361 return strcmp(name_a
, name_b
);
365 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
367 ObjectClass
*oc
= data
;
368 ARMCPUListState
*s
= user_data
;
370 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
371 object_class_get_name(oc
));
374 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
376 ARMCPUListState s
= {
378 .cpu_fprintf
= cpu_fprintf
,
382 list
= object_class_get_list(TYPE_ARM_CPU
, false);
383 list
= g_slist_sort(list
, arm_cpu_list_compare
);
384 (*cpu_fprintf
)(f
, "Available CPUs:\n");
385 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
389 static int bad_mode_switch(CPUARMState
*env
, int mode
)
391 /* Return true if it is not valid for us to switch to
392 * this CPU mode (ie all the UNPREDICTABLE cases in
393 * the ARM ARM CPSRWriteByInstr pseudocode).
396 case ARM_CPU_MODE_USR
:
397 case ARM_CPU_MODE_SYS
:
398 case ARM_CPU_MODE_SVC
:
399 case ARM_CPU_MODE_ABT
:
400 case ARM_CPU_MODE_UND
:
401 case ARM_CPU_MODE_IRQ
:
402 case ARM_CPU_MODE_FIQ
:
409 uint32_t cpsr_read(CPUARMState
*env
)
413 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
414 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
415 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
416 | ((env
->condexec_bits
& 0xfc) << 8)
420 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
422 if (mask
& CPSR_NZCV
) {
423 env
->ZF
= (~val
) & CPSR_Z
;
425 env
->CF
= (val
>> 29) & 1;
426 env
->VF
= (val
<< 3) & 0x80000000;
429 env
->QF
= ((val
& CPSR_Q
) != 0);
431 env
->thumb
= ((val
& CPSR_T
) != 0);
432 if (mask
& CPSR_IT_0_1
) {
433 env
->condexec_bits
&= ~3;
434 env
->condexec_bits
|= (val
>> 25) & 3;
436 if (mask
& CPSR_IT_2_7
) {
437 env
->condexec_bits
&= 3;
438 env
->condexec_bits
|= (val
>> 8) & 0xfc;
440 if (mask
& CPSR_GE
) {
441 env
->GE
= (val
>> 16) & 0xf;
444 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
445 if (bad_mode_switch(env
, val
& CPSR_M
)) {
446 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
447 * We choose to ignore the attempt and leave the CPSR M field
452 switch_mode(env
, val
& CPSR_M
);
455 mask
&= ~CACHED_CPSR_BITS
;
456 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
459 /* Sign/zero extend */
460 uint32_t HELPER(sxtb16
)(uint32_t x
)
463 res
= (uint16_t)(int8_t)x
;
464 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
468 uint32_t HELPER(uxtb16
)(uint32_t x
)
471 res
= (uint16_t)(uint8_t)x
;
472 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
476 uint32_t HELPER(clz
)(uint32_t x
)
481 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
485 if (num
== INT_MIN
&& den
== -1)
490 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
497 uint32_t HELPER(rbit
)(uint32_t x
)
499 x
= ((x
& 0xff000000) >> 24)
500 | ((x
& 0x00ff0000) >> 8)
501 | ((x
& 0x0000ff00) << 8)
502 | ((x
& 0x000000ff) << 24);
503 x
= ((x
& 0xf0f0f0f0) >> 4)
504 | ((x
& 0x0f0f0f0f) << 4);
505 x
= ((x
& 0x88888888) >> 3)
506 | ((x
& 0x44444444) >> 1)
507 | ((x
& 0x22222222) << 1)
508 | ((x
& 0x11111111) << 3);
512 uint32_t HELPER(abs
)(uint32_t x
)
514 return ((int32_t)x
< 0) ? -x
: x
;
517 #if defined(CONFIG_USER_ONLY)
519 void do_interrupt (CPUARMState
*env
)
521 env
->exception_index
= -1;
524 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
528 env
->exception_index
= EXCP_PREFETCH_ABORT
;
529 env
->cp15
.c6_insn
= address
;
531 env
->exception_index
= EXCP_DATA_ABORT
;
532 env
->cp15
.c6_data
= address
;
537 /* These should probably raise undefined insn exceptions. */
538 void HELPER(set_cp
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
540 int op1
= (insn
>> 8) & 0xf;
541 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
545 uint32_t HELPER(get_cp
)(CPUARMState
*env
, uint32_t insn
)
547 int op1
= (insn
>> 8) & 0xf;
548 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
552 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
554 cpu_abort(env
, "cp15 insn %08x\n", insn
);
557 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
559 cpu_abort(env
, "cp15 insn %08x\n", insn
);
562 /* These should probably raise undefined insn exceptions. */
563 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
565 cpu_abort(env
, "v7m_mrs %d\n", reg
);
568 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
570 cpu_abort(env
, "v7m_mrs %d\n", reg
);
574 void switch_mode(CPUARMState
*env
, int mode
)
576 if (mode
!= ARM_CPU_MODE_USR
)
577 cpu_abort(env
, "Tried to switch out of user mode\n");
580 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
582 cpu_abort(env
, "banked r13 write\n");
585 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
587 cpu_abort(env
, "banked r13 read\n");
593 /* Map CPU modes onto saved register banks. */
594 static inline int bank_number(CPUARMState
*env
, int mode
)
597 case ARM_CPU_MODE_USR
:
598 case ARM_CPU_MODE_SYS
:
600 case ARM_CPU_MODE_SVC
:
602 case ARM_CPU_MODE_ABT
:
604 case ARM_CPU_MODE_UND
:
606 case ARM_CPU_MODE_IRQ
:
608 case ARM_CPU_MODE_FIQ
:
611 cpu_abort(env
, "Bad mode %x\n", mode
);
615 void switch_mode(CPUARMState
*env
, int mode
)
620 old_mode
= env
->uncached_cpsr
& CPSR_M
;
621 if (mode
== old_mode
)
624 if (old_mode
== ARM_CPU_MODE_FIQ
) {
625 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
626 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
627 } else if (mode
== ARM_CPU_MODE_FIQ
) {
628 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
629 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
632 i
= bank_number(env
, old_mode
);
633 env
->banked_r13
[i
] = env
->regs
[13];
634 env
->banked_r14
[i
] = env
->regs
[14];
635 env
->banked_spsr
[i
] = env
->spsr
;
637 i
= bank_number(env
, mode
);
638 env
->regs
[13] = env
->banked_r13
[i
];
639 env
->regs
[14] = env
->banked_r14
[i
];
640 env
->spsr
= env
->banked_spsr
[i
];
643 static void v7m_push(CPUARMState
*env
, uint32_t val
)
646 stl_phys(env
->regs
[13], val
);
649 static uint32_t v7m_pop(CPUARMState
*env
)
652 val
= ldl_phys(env
->regs
[13]);
657 /* Switch to V7M main or process stack pointer. */
658 static void switch_v7m_sp(CPUARMState
*env
, int process
)
661 if (env
->v7m
.current_sp
!= process
) {
662 tmp
= env
->v7m
.other_sp
;
663 env
->v7m
.other_sp
= env
->regs
[13];
665 env
->v7m
.current_sp
= process
;
669 static void do_v7m_exception_exit(CPUARMState
*env
)
674 type
= env
->regs
[15];
675 if (env
->v7m
.exception
!= 0)
676 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
678 /* Switch to the target stack. */
679 switch_v7m_sp(env
, (type
& 4) != 0);
681 env
->regs
[0] = v7m_pop(env
);
682 env
->regs
[1] = v7m_pop(env
);
683 env
->regs
[2] = v7m_pop(env
);
684 env
->regs
[3] = v7m_pop(env
);
685 env
->regs
[12] = v7m_pop(env
);
686 env
->regs
[14] = v7m_pop(env
);
687 env
->regs
[15] = v7m_pop(env
);
689 xpsr_write(env
, xpsr
, 0xfffffdff);
690 /* Undo stack alignment. */
693 /* ??? The exception return type specifies Thread/Handler mode. However
694 this is also implied by the xPSR value. Not sure what to do
695 if there is a mismatch. */
696 /* ??? Likewise for mismatches between the CONTROL register and the stack
700 static void do_interrupt_v7m(CPUARMState
*env
)
702 uint32_t xpsr
= xpsr_read(env
);
707 if (env
->v7m
.current_sp
)
709 if (env
->v7m
.exception
== 0)
712 /* For exceptions we just mark as pending on the NVIC, and let that
714 /* TODO: Need to escalate if the current priority is higher than the
715 one we're raising. */
716 switch (env
->exception_index
) {
718 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
722 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
724 case EXCP_PREFETCH_ABORT
:
725 case EXCP_DATA_ABORT
:
726 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
729 if (semihosting_enabled
) {
731 nr
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
734 env
->regs
[0] = do_arm_semihosting(env
);
738 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
741 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
743 case EXCP_EXCEPTION_EXIT
:
744 do_v7m_exception_exit(env
);
747 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
748 return; /* Never happens. Keep compiler happy. */
751 /* Align stack pointer. */
752 /* ??? Should only do this if Configuration Control Register
753 STACKALIGN bit is set. */
754 if (env
->regs
[13] & 4) {
758 /* Switch to the handler mode. */
760 v7m_push(env
, env
->regs
[15]);
761 v7m_push(env
, env
->regs
[14]);
762 v7m_push(env
, env
->regs
[12]);
763 v7m_push(env
, env
->regs
[3]);
764 v7m_push(env
, env
->regs
[2]);
765 v7m_push(env
, env
->regs
[1]);
766 v7m_push(env
, env
->regs
[0]);
767 switch_v7m_sp(env
, 0);
769 env
->condexec_bits
= 0;
771 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
772 env
->regs
[15] = addr
& 0xfffffffe;
773 env
->thumb
= addr
& 1;
776 /* Handle a CPU exception. */
777 void do_interrupt(CPUARMState
*env
)
785 do_interrupt_v7m(env
);
788 /* TODO: Vectored interrupt controller. */
789 switch (env
->exception_index
) {
791 new_mode
= ARM_CPU_MODE_UND
;
800 if (semihosting_enabled
) {
801 /* Check for semihosting interrupt. */
803 mask
= arm_lduw_code(env
->regs
[15] - 2, env
->bswap_code
) & 0xff;
805 mask
= arm_ldl_code(env
->regs
[15] - 4, env
->bswap_code
)
808 /* Only intercept calls from privileged modes, to provide some
809 semblance of security. */
810 if (((mask
== 0x123456 && !env
->thumb
)
811 || (mask
== 0xab && env
->thumb
))
812 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
813 env
->regs
[0] = do_arm_semihosting(env
);
817 new_mode
= ARM_CPU_MODE_SVC
;
820 /* The PC already points to the next instruction. */
824 /* See if this is a semihosting syscall. */
825 if (env
->thumb
&& semihosting_enabled
) {
826 mask
= arm_lduw_code(env
->regs
[15], env
->bswap_code
) & 0xff;
828 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
830 env
->regs
[0] = do_arm_semihosting(env
);
834 env
->cp15
.c5_insn
= 2;
835 /* Fall through to prefetch abort. */
836 case EXCP_PREFETCH_ABORT
:
837 new_mode
= ARM_CPU_MODE_ABT
;
839 mask
= CPSR_A
| CPSR_I
;
842 case EXCP_DATA_ABORT
:
843 new_mode
= ARM_CPU_MODE_ABT
;
845 mask
= CPSR_A
| CPSR_I
;
849 new_mode
= ARM_CPU_MODE_IRQ
;
851 /* Disable IRQ and imprecise data aborts. */
852 mask
= CPSR_A
| CPSR_I
;
856 new_mode
= ARM_CPU_MODE_FIQ
;
858 /* Disable FIQ, IRQ and imprecise data aborts. */
859 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
863 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
864 return; /* Never happens. Keep compiler happy. */
867 if (env
->cp15
.c1_sys
& (1 << 13)) {
870 switch_mode (env
, new_mode
);
871 env
->spsr
= cpsr_read(env
);
873 env
->condexec_bits
= 0;
874 /* Switch to the new mode, and to the correct instruction set. */
875 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
876 env
->uncached_cpsr
|= mask
;
877 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
878 * and we should just guard the thumb mode on V4 */
879 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
880 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
882 env
->regs
[14] = env
->regs
[15] + offset
;
883 env
->regs
[15] = addr
;
884 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
887 /* Check section/page access permissions.
888 Returns the page protection flags, or zero if the access is not
890 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
891 int access_type
, int is_user
)
895 if (domain_prot
== 3) {
896 return PAGE_READ
| PAGE_WRITE
;
899 if (access_type
== 1)
906 if (access_type
== 1)
908 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
910 return is_user
? 0 : PAGE_READ
;
917 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
922 return PAGE_READ
| PAGE_WRITE
;
924 return PAGE_READ
| PAGE_WRITE
;
925 case 4: /* Reserved. */
928 return is_user
? 0 : prot_ro
;
932 if (!arm_feature (env
, ARM_FEATURE_V6K
))
940 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
944 if (address
& env
->cp15
.c2_mask
)
945 table
= env
->cp15
.c2_base1
& 0xffffc000;
947 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
949 table
|= (address
>> 18) & 0x3ffc;
953 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
954 int is_user
, uint32_t *phys_ptr
, int *prot
,
955 target_ulong
*page_size
)
966 /* Pagetable walk. */
967 /* Lookup l1 descriptor. */
968 table
= get_level1_table_address(env
, address
);
969 desc
= ldl_phys(table
);
971 domain
= (desc
>> 5) & 0x0f;
972 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
974 /* Section translation fault. */
978 if (domain_prot
== 0 || domain_prot
== 2) {
980 code
= 9; /* Section domain fault. */
982 code
= 11; /* Page domain fault. */
987 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
988 ap
= (desc
>> 10) & 3;
990 *page_size
= 1024 * 1024;
992 /* Lookup l2 entry. */
994 /* Coarse pagetable. */
995 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
997 /* Fine pagetable. */
998 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
1000 desc
= ldl_phys(table
);
1002 case 0: /* Page translation fault. */
1005 case 1: /* 64k page. */
1006 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1007 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1008 *page_size
= 0x10000;
1010 case 2: /* 4k page. */
1011 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1012 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
1013 *page_size
= 0x1000;
1015 case 3: /* 1k page. */
1017 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1018 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1020 /* Page translation fault. */
1025 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1027 ap
= (desc
>> 4) & 3;
1031 /* Never happens, but compiler isn't smart enough to tell. */
1036 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1038 /* Access permission fault. */
1042 *phys_ptr
= phys_addr
;
1045 return code
| (domain
<< 4);
1048 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
1049 int is_user
, uint32_t *phys_ptr
, int *prot
,
1050 target_ulong
*page_size
)
1062 /* Pagetable walk. */
1063 /* Lookup l1 descriptor. */
1064 table
= get_level1_table_address(env
, address
);
1065 desc
= ldl_phys(table
);
1068 /* Section translation fault. */
1072 } else if (type
== 2 && (desc
& (1 << 18))) {
1076 /* Section or page. */
1077 domain
= (desc
>> 5) & 0x0f;
1079 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
1080 if (domain_prot
== 0 || domain_prot
== 2) {
1082 code
= 9; /* Section domain fault. */
1084 code
= 11; /* Page domain fault. */
1088 if (desc
& (1 << 18)) {
1090 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1091 *page_size
= 0x1000000;
1094 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1095 *page_size
= 0x100000;
1097 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1098 xn
= desc
& (1 << 4);
1101 /* Lookup l2 entry. */
1102 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1103 desc
= ldl_phys(table
);
1104 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1106 case 0: /* Page translation fault. */
1109 case 1: /* 64k page. */
1110 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1111 xn
= desc
& (1 << 15);
1112 *page_size
= 0x10000;
1114 case 2: case 3: /* 4k page. */
1115 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1117 *page_size
= 0x1000;
1120 /* Never happens, but compiler isn't smart enough to tell. */
1125 if (domain_prot
== 3) {
1126 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1128 if (xn
&& access_type
== 2)
1131 /* The simplified model uses AP[0] as an access control bit. */
1132 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1133 /* Access flag fault. */
1134 code
= (code
== 15) ? 6 : 3;
1137 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
1139 /* Access permission fault. */
1146 *phys_ptr
= phys_addr
;
1149 return code
| (domain
<< 4);
1152 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
, int access_type
,
1153 int is_user
, uint32_t *phys_ptr
, int *prot
)
1159 *phys_ptr
= address
;
1160 for (n
= 7; n
>= 0; n
--) {
1161 base
= env
->cp15
.c6_region
[n
];
1162 if ((base
& 1) == 0)
1164 mask
= 1 << ((base
>> 1) & 0x1f);
1165 /* Keep this shift separate from the above to avoid an
1166 (undefined) << 32. */
1167 mask
= (mask
<< 1) - 1;
1168 if (((base
^ address
) & ~mask
) == 0)
1174 if (access_type
== 2) {
1175 mask
= env
->cp15
.c5_insn
;
1177 mask
= env
->cp15
.c5_data
;
1179 mask
= (mask
>> (n
* 4)) & 0xf;
1186 *prot
= PAGE_READ
| PAGE_WRITE
;
1191 *prot
|= PAGE_WRITE
;
1194 *prot
= PAGE_READ
| PAGE_WRITE
;
1205 /* Bad permission. */
1212 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
1213 int access_type
, int is_user
,
1214 uint32_t *phys_ptr
, int *prot
,
1215 target_ulong
*page_size
)
1217 /* Fast Context Switch Extension. */
1218 if (address
< 0x02000000)
1219 address
+= env
->cp15
.c13_fcse
;
1221 if ((env
->cp15
.c1_sys
& 1) == 0) {
1222 /* MMU/MPU disabled. */
1223 *phys_ptr
= address
;
1224 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
1225 *page_size
= TARGET_PAGE_SIZE
;
1227 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1228 *page_size
= TARGET_PAGE_SIZE
;
1229 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1231 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1232 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1235 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1240 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
1241 int access_type
, int mmu_idx
)
1244 target_ulong page_size
;
1248 is_user
= mmu_idx
== MMU_USER_IDX
;
1249 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
1252 /* Map a single [sub]page. */
1253 phys_addr
&= ~(uint32_t)0x3ff;
1254 address
&= ~(uint32_t)0x3ff;
1255 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
1259 if (access_type
== 2) {
1260 env
->cp15
.c5_insn
= ret
;
1261 env
->cp15
.c6_insn
= address
;
1262 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1264 env
->cp15
.c5_data
= ret
;
1265 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1266 env
->cp15
.c5_data
|= (1 << 11);
1267 env
->cp15
.c6_data
= address
;
1268 env
->exception_index
= EXCP_DATA_ABORT
;
1273 target_phys_addr_t
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
1276 target_ulong page_size
;
1280 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
1288 void HELPER(set_cp
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1290 int cp_num
= (insn
>> 8) & 0xf;
1291 int cp_info
= (insn
>> 5) & 7;
1292 int src
= (insn
>> 16) & 0xf;
1293 int operand
= insn
& 0xf;
1295 if (env
->cp
[cp_num
].cp_write
)
1296 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1297 cp_info
, src
, operand
, val
);
1300 uint32_t HELPER(get_cp
)(CPUARMState
*env
, uint32_t insn
)
1302 int cp_num
= (insn
>> 8) & 0xf;
1303 int cp_info
= (insn
>> 5) & 7;
1304 int dest
= (insn
>> 16) & 0xf;
1305 int operand
= insn
& 0xf;
1307 if (env
->cp
[cp_num
].cp_read
)
1308 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1309 cp_info
, dest
, operand
);
1313 /* Return basic MPU access permission bits. */
1314 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1321 for (i
= 0; i
< 16; i
+= 2) {
1322 ret
|= (val
>> i
) & mask
;
1328 /* Pad basic MPU access permission bits to extended format. */
1329 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1336 for (i
= 0; i
< 16; i
+= 2) {
1337 ret
|= (val
& mask
) << i
;
1343 void HELPER(set_cp15
)(CPUARMState
*env
, uint32_t insn
, uint32_t val
)
1349 op1
= (insn
>> 21) & 7;
1350 op2
= (insn
>> 5) & 7;
1352 switch ((insn
>> 16) & 0xf) {
1355 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1357 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1359 if (arm_feature(env
, ARM_FEATURE_V7
)
1360 && op1
== 2 && crm
== 0 && op2
== 0) {
1361 env
->cp15
.c0_cssel
= val
& 0xf;
1365 case 1: /* System configuration. */
1366 if (arm_feature(env
, ARM_FEATURE_V7
)
1367 && op1
== 0 && crm
== 1 && op2
== 0) {
1368 env
->cp15
.c1_scr
= val
;
1371 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1375 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1376 env
->cp15
.c1_sys
= val
;
1377 /* ??? Lots of these bits are not implemented. */
1378 /* This may enable/disable the MMU, so do a TLB flush. */
1381 case 1: /* Auxiliary control register. */
1382 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1383 env
->cp15
.c1_xscaleauxcr
= val
;
1386 /* Not implemented. */
1389 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1391 if (env
->cp15
.c1_coproc
!= val
) {
1392 env
->cp15
.c1_coproc
= val
;
1393 /* ??? Is this safe when called from within a TB? */
1401 case 2: /* MMU Page table control / MPU cache control. */
1402 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1405 env
->cp15
.c2_data
= val
;
1408 env
->cp15
.c2_insn
= val
;
1416 env
->cp15
.c2_base0
= val
;
1419 env
->cp15
.c2_base1
= val
;
1423 env
->cp15
.c2_control
= val
;
1424 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1425 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1432 case 3: /* MMU Domain access control / MPU write buffer control. */
1434 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1436 case 4: /* Reserved. */
1438 case 5: /* MMU Fault status / MPU access permission. */
1439 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1443 if (arm_feature(env
, ARM_FEATURE_MPU
))
1444 val
= extended_mpu_ap_bits(val
);
1445 env
->cp15
.c5_data
= val
;
1448 if (arm_feature(env
, ARM_FEATURE_MPU
))
1449 val
= extended_mpu_ap_bits(val
);
1450 env
->cp15
.c5_insn
= val
;
1453 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1455 env
->cp15
.c5_data
= val
;
1458 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1460 env
->cp15
.c5_insn
= val
;
1466 case 6: /* MMU Fault address / MPU base/size. */
1467 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1470 env
->cp15
.c6_region
[crm
] = val
;
1472 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1476 env
->cp15
.c6_data
= val
;
1478 case 1: /* ??? This is WFAR on armv6 */
1480 env
->cp15
.c6_insn
= val
;
1487 case 7: /* Cache control. */
1488 env
->cp15
.c15_i_max
= 0x000;
1489 env
->cp15
.c15_i_min
= 0xff0;
1493 /* No cache, so nothing to do except VA->PA translations. */
1494 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1497 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1498 env
->cp15
.c7_par
= val
& 0xfffff6ff;
1500 env
->cp15
.c7_par
= val
& 0xfffff1ff;
1505 target_ulong page_size
;
1507 int ret
, is_user
= op2
& 2;
1508 int access_type
= op2
& 1;
1511 /* Other states are only available with TrustZone */
1514 ret
= get_phys_addr(env
, val
, access_type
, is_user
,
1515 &phys_addr
, &prot
, &page_size
);
1517 /* We do not set any attribute bits in the PAR */
1518 if (page_size
== (1 << 24)
1519 && arm_feature(env
, ARM_FEATURE_V7
)) {
1520 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1522 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1525 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
1526 ((ret
& (12 << 1)) >> 6) |
1527 ((ret
& 0xf) << 1) | 1;
1534 case 8: /* MMU TLB control. */
1536 case 0: /* Invalidate all (TLBIALL) */
1539 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
1540 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1542 case 2: /* Invalidate by ASID (TLBIASID) */
1543 tlb_flush(env
, val
== 0);
1545 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1546 tlb_flush_page(env
, val
& TARGET_PAGE_MASK
);
1553 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1555 if (arm_feature(env
, ARM_FEATURE_STRONGARM
))
1556 break; /* Ignore ReadBuffer access */
1558 case 0: /* Cache lockdown. */
1560 case 0: /* L1 cache. */
1563 env
->cp15
.c9_data
= val
;
1566 env
->cp15
.c9_insn
= val
;
1572 case 1: /* L2 cache. */
1573 /* Ignore writes to L2 lockdown/auxiliary registers. */
1579 case 1: /* TCM memory region registers. */
1580 /* Not implemented. */
1582 case 12: /* Performance monitor control */
1583 /* Performance monitors are implementation defined in v7,
1584 * but with an ARM recommended set of registers, which we
1585 * follow (although we don't actually implement any counters)
1587 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1591 case 0: /* performance monitor control register */
1592 /* only the DP, X, D and E bits are writable */
1593 env
->cp15
.c9_pmcr
&= ~0x39;
1594 env
->cp15
.c9_pmcr
|= (val
& 0x39);
1596 case 1: /* Count enable set register */
1598 env
->cp15
.c9_pmcnten
|= val
;
1600 case 2: /* Count enable clear */
1602 env
->cp15
.c9_pmcnten
&= ~val
;
1604 case 3: /* Overflow flag status */
1605 env
->cp15
.c9_pmovsr
&= ~val
;
1607 case 4: /* Software increment */
1608 /* RAZ/WI since we don't implement the software-count event */
1610 case 5: /* Event counter selection register */
1611 /* Since we don't implement any events, writing to this register
1612 * is actually UNPREDICTABLE. So we choose to RAZ/WI.
1619 case 13: /* Performance counters */
1620 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1624 case 0: /* Cycle count register: not implemented, so RAZ/WI */
1626 case 1: /* Event type select */
1627 env
->cp15
.c9_pmxevtyper
= val
& 0xff;
1629 case 2: /* Event count register */
1630 /* Unimplemented (we have no events), RAZ/WI */
1636 case 14: /* Performance monitor control */
1637 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
1641 case 0: /* user enable */
1642 env
->cp15
.c9_pmuserenr
= val
& 1;
1643 /* changes access rights for cp registers, so flush tbs */
1646 case 1: /* interrupt enable set */
1647 /* We have no event counters so only the C bit can be changed */
1649 env
->cp15
.c9_pminten
|= val
;
1651 case 2: /* interrupt enable clear */
1653 env
->cp15
.c9_pminten
&= ~val
;
1661 case 10: /* MMU TLB lockdown. */
1662 /* ??? TLB lockdown not implemented. */
1664 case 12: /* Reserved. */
1666 case 13: /* Process ID. */
1669 /* Unlike real hardware the qemu TLB uses virtual addresses,
1670 not modified virtual addresses, so this causes a TLB flush.
1672 if (env
->cp15
.c13_fcse
!= val
)
1674 env
->cp15
.c13_fcse
= val
;
1677 /* This changes the ASID, so do a TLB flush. */
1678 if (env
->cp15
.c13_context
!= val
1679 && !arm_feature(env
, ARM_FEATURE_MPU
))
1681 env
->cp15
.c13_context
= val
;
1687 case 14: /* Generic timer */
1688 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1689 /* Dummy implementation: RAZ/WI for all */
1693 case 15: /* Implementation specific. */
1694 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1695 if (op2
== 0 && crm
== 1) {
1696 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1697 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1699 env
->cp15
.c15_cpar
= val
& 0x3fff;
1705 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1709 case 1: /* Set TI925T configuration. */
1710 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1711 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1712 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1714 case 2: /* Set I_max. */
1715 env
->cp15
.c15_i_max
= val
;
1717 case 3: /* Set I_min. */
1718 env
->cp15
.c15_i_min
= val
;
1720 case 4: /* Set thread-ID. */
1721 env
->cp15
.c15_threadid
= val
& 0xffff;
1723 case 8: /* Wait-for-interrupt (deprecated). */
1724 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1730 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
1733 if ((op1
== 0) && (op2
== 0)) {
1734 env
->cp15
.c15_power_control
= val
;
1735 } else if ((op1
== 0) && (op2
== 1)) {
1736 env
->cp15
.c15_diagnostic
= val
;
1737 } else if ((op1
== 0) && (op2
== 2)) {
1738 env
->cp15
.c15_power_diagnostic
= val
;
1748 /* ??? For debugging only. Should raise illegal instruction exception. */
1749 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1750 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1753 uint32_t HELPER(get_cp15
)(CPUARMState
*env
, uint32_t insn
)
1759 op1
= (insn
>> 21) & 7;
1760 op2
= (insn
>> 5) & 7;
1762 switch ((insn
>> 16) & 0xf) {
1763 case 0: /* ID codes. */
1769 case 0: /* Device ID. */
1770 return env
->cp15
.c0_cpuid
;
1771 case 1: /* Cache Type. */
1772 return env
->cp15
.c0_cachetype
;
1773 case 2: /* TCM status. */
1775 case 3: /* TLB type register. */
1776 return 0; /* No lockable TLB entries. */
1778 /* The MPIDR was standardised in v7; prior to
1779 * this it was implemented only in the 11MPCore.
1780 * For all other pre-v7 cores it does not exist.
1782 if (arm_feature(env
, ARM_FEATURE_V7
) ||
1783 ARM_CPUID(env
) == ARM_CPUID_ARM11MPCORE
) {
1784 int mpidr
= env
->cpu_index
;
1785 /* We don't support setting cluster ID ([8..11])
1786 * so these bits always RAZ.
1788 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1790 /* Cores which are uniprocessor (non-coherent)
1791 * but still implement the MP extensions set
1792 * bit 30. (For instance, A9UP.) However we do
1793 * not currently model any of those cores.
1798 /* otherwise fall through to the unimplemented-reg case */
1803 if (!arm_feature(env
, ARM_FEATURE_V6
))
1805 return env
->cp15
.c0_c1
[op2
];
1807 if (!arm_feature(env
, ARM_FEATURE_V6
))
1809 return env
->cp15
.c0_c2
[op2
];
1810 case 3: case 4: case 5: case 6: case 7:
1816 /* These registers aren't documented on arm11 cores. However
1817 Linux looks at them anyway. */
1818 if (!arm_feature(env
, ARM_FEATURE_V6
))
1822 if (!arm_feature(env
, ARM_FEATURE_V7
))
1827 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1829 return env
->cp15
.c0_clid
;
1835 if (op2
!= 0 || crm
!= 0)
1837 return env
->cp15
.c0_cssel
;
1841 case 1: /* System configuration. */
1842 if (arm_feature(env
, ARM_FEATURE_V7
)
1843 && op1
== 0 && crm
== 1 && op2
== 0) {
1844 return env
->cp15
.c1_scr
;
1846 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1849 case 0: /* Control register. */
1850 return env
->cp15
.c1_sys
;
1851 case 1: /* Auxiliary control register. */
1852 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1853 return env
->cp15
.c1_xscaleauxcr
;
1854 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1856 switch (ARM_CPUID(env
)) {
1857 case ARM_CPUID_ARM1026
:
1859 case ARM_CPUID_ARM1136
:
1860 case ARM_CPUID_ARM1136_R2
:
1861 case ARM_CPUID_ARM1176
:
1863 case ARM_CPUID_ARM11MPCORE
:
1865 case ARM_CPUID_CORTEXA8
:
1867 case ARM_CPUID_CORTEXA9
:
1868 case ARM_CPUID_CORTEXA15
:
1873 case 2: /* Coprocessor access register. */
1874 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1876 return env
->cp15
.c1_coproc
;
1880 case 2: /* MMU Page table control / MPU cache control. */
1881 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1884 return env
->cp15
.c2_data
;
1887 return env
->cp15
.c2_insn
;
1895 return env
->cp15
.c2_base0
;
1897 return env
->cp15
.c2_base1
;
1899 return env
->cp15
.c2_control
;
1904 case 3: /* MMU Domain access control / MPU write buffer control. */
1905 return env
->cp15
.c3
;
1906 case 4: /* Reserved. */
1908 case 5: /* MMU Fault status / MPU access permission. */
1909 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1913 if (arm_feature(env
, ARM_FEATURE_MPU
))
1914 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1915 return env
->cp15
.c5_data
;
1917 if (arm_feature(env
, ARM_FEATURE_MPU
))
1918 return simple_mpu_ap_bits(env
->cp15
.c5_insn
);
1919 return env
->cp15
.c5_insn
;
1921 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1923 return env
->cp15
.c5_data
;
1925 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1927 return env
->cp15
.c5_insn
;
1931 case 6: /* MMU Fault address. */
1932 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1935 return env
->cp15
.c6_region
[crm
];
1937 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1941 return env
->cp15
.c6_data
;
1943 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1944 /* Watchpoint Fault Adrress. */
1945 return 0; /* Not implemented. */
1947 /* Instruction Fault Adrress. */
1948 /* Arm9 doesn't have an IFAR, but implementing it anyway
1949 shouldn't do any harm. */
1950 return env
->cp15
.c6_insn
;
1953 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1954 /* Instruction Fault Adrress. */
1955 return env
->cp15
.c6_insn
;
1963 case 7: /* Cache control. */
1964 if (crm
== 4 && op1
== 0 && op2
== 0) {
1965 return env
->cp15
.c7_par
;
1967 /* FIXME: Should only clear Z flag if destination is r15. */
1970 case 8: /* MMU TLB control. */
1974 case 0: /* Cache lockdown */
1976 case 0: /* L1 cache. */
1977 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1982 return env
->cp15
.c9_data
;
1984 return env
->cp15
.c9_insn
;
1988 case 1: /* L2 cache */
1989 /* L2 Lockdown and Auxiliary control. */
1992 /* L2 cache lockdown (A8 only) */
1995 /* L2 cache auxiliary control (A8) or control (A15) */
1996 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA15
) {
1997 /* Linux wants the number of processors from here.
1998 * Might as well set the interrupt-controller bit too.
2000 return ((smp_cpus
- 1) << 24) | (1 << 23);
2004 /* L2 cache extended control (A15) */
2013 case 12: /* Performance monitor control */
2014 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2018 case 0: /* performance monitor control register */
2019 return env
->cp15
.c9_pmcr
;
2020 case 1: /* count enable set */
2021 case 2: /* count enable clear */
2022 return env
->cp15
.c9_pmcnten
;
2023 case 3: /* overflow flag status */
2024 return env
->cp15
.c9_pmovsr
;
2025 case 4: /* software increment */
2026 case 5: /* event counter selection register */
2027 return 0; /* Unimplemented, RAZ/WI */
2031 case 13: /* Performance counters */
2032 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2036 case 1: /* Event type select */
2037 return env
->cp15
.c9_pmxevtyper
;
2038 case 0: /* Cycle count register */
2039 case 2: /* Event count register */
2040 /* Unimplemented, so RAZ/WI */
2045 case 14: /* Performance monitor control */
2046 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2050 case 0: /* user enable */
2051 return env
->cp15
.c9_pmuserenr
;
2052 case 1: /* interrupt enable set */
2053 case 2: /* interrupt enable clear */
2054 return env
->cp15
.c9_pminten
;
2062 case 10: /* MMU TLB lockdown. */
2063 /* ??? TLB lockdown not implemented. */
2065 case 11: /* TCM DMA control. */
2066 case 12: /* Reserved. */
2068 case 13: /* Process ID. */
2071 return env
->cp15
.c13_fcse
;
2073 return env
->cp15
.c13_context
;
2077 case 14: /* Generic timer */
2078 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
2079 /* Dummy implementation: RAZ/WI for all */
2083 case 15: /* Implementation specific. */
2084 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2085 if (op2
== 0 && crm
== 1)
2086 return env
->cp15
.c15_cpar
;
2090 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2094 case 1: /* Read TI925T configuration. */
2095 return env
->cp15
.c15_ticonfig
;
2096 case 2: /* Read I_max. */
2097 return env
->cp15
.c15_i_max
;
2098 case 3: /* Read I_min. */
2099 return env
->cp15
.c15_i_min
;
2100 case 4: /* Read thread-ID. */
2101 return env
->cp15
.c15_threadid
;
2102 case 8: /* TI925T_status */
2105 /* TODO: Peripheral port remap register:
2106 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2107 * controller base address at $rn & ~0xfff and map size of
2108 * 0x200 << ($rn & 0xfff), when MMU is off. */
2111 if (ARM_CPUID(env
) == ARM_CPUID_CORTEXA9
) {
2114 if ((op1
== 4) && (op2
== 0)) {
2115 /* The config_base_address should hold the value of
2116 * the peripheral base. ARM should get this from a CPU
2117 * object property, but that support isn't available in
2118 * December 2011. Default to 0 for now and board models
2119 * that care can set it by a private hook */
2120 return env
->cp15
.c15_config_base_address
;
2121 } else if ((op1
== 0) && (op2
== 0)) {
2122 /* power_control should be set to maximum latency. Again,
2123 default to 0 and set by private hook */
2124 return env
->cp15
.c15_power_control
;
2125 } else if ((op1
== 0) && (op2
== 1)) {
2126 return env
->cp15
.c15_diagnostic
;
2127 } else if ((op1
== 0) && (op2
== 2)) {
2128 return env
->cp15
.c15_power_diagnostic
;
2131 case 1: /* NEON Busy */
2133 case 5: /* tlb lockdown */
2136 if ((op1
== 5) && (op2
== 2)) {
2148 /* ??? For debugging only. Should raise illegal instruction exception. */
2149 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2150 (insn
>> 16) & 0xf, crm
, op1
, op2
);
2154 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2156 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2157 env
->regs
[13] = val
;
2159 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2163 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2165 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2166 return env
->regs
[13];
2168 return env
->banked_r13
[bank_number(env
, mode
)];
2172 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2176 return xpsr_read(env
) & 0xf8000000;
2178 return xpsr_read(env
) & 0xf80001ff;
2180 return xpsr_read(env
) & 0xff00fc00;
2182 return xpsr_read(env
) & 0xff00fdff;
2184 return xpsr_read(env
) & 0x000001ff;
2186 return xpsr_read(env
) & 0x0700fc00;
2188 return xpsr_read(env
) & 0x0700edff;
2190 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2192 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2193 case 16: /* PRIMASK */
2194 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2195 case 17: /* BASEPRI */
2196 case 18: /* BASEPRI_MAX */
2197 return env
->v7m
.basepri
;
2198 case 19: /* FAULTMASK */
2199 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2200 case 20: /* CONTROL */
2201 return env
->v7m
.control
;
2203 /* ??? For debugging only. */
2204 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2209 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2213 xpsr_write(env
, val
, 0xf8000000);
2216 xpsr_write(env
, val
, 0xf8000000);
2219 xpsr_write(env
, val
, 0xfe00fc00);
2222 xpsr_write(env
, val
, 0xfe00fc00);
2225 /* IPSR bits are readonly. */
2228 xpsr_write(env
, val
, 0x0600fc00);
2231 xpsr_write(env
, val
, 0x0600fc00);
2234 if (env
->v7m
.current_sp
)
2235 env
->v7m
.other_sp
= val
;
2237 env
->regs
[13] = val
;
2240 if (env
->v7m
.current_sp
)
2241 env
->regs
[13] = val
;
2243 env
->v7m
.other_sp
= val
;
2245 case 16: /* PRIMASK */
2247 env
->uncached_cpsr
|= CPSR_I
;
2249 env
->uncached_cpsr
&= ~CPSR_I
;
2251 case 17: /* BASEPRI */
2252 env
->v7m
.basepri
= val
& 0xff;
2254 case 18: /* BASEPRI_MAX */
2256 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2257 env
->v7m
.basepri
= val
;
2259 case 19: /* FAULTMASK */
2261 env
->uncached_cpsr
|= CPSR_F
;
2263 env
->uncached_cpsr
&= ~CPSR_F
;
2265 case 20: /* CONTROL */
2266 env
->v7m
.control
= val
& 3;
2267 switch_v7m_sp(env
, (val
& 2) != 0);
2270 /* ??? For debugging only. */
2271 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2276 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
2277 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
2280 if (cpnum
< 0 || cpnum
> 14) {
2281 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2285 env
->cp
[cpnum
].cp_read
= cp_read
;
2286 env
->cp
[cpnum
].cp_write
= cp_write
;
2287 env
->cp
[cpnum
].opaque
= opaque
;
2292 /* Note that signed overflow is undefined in C. The following routines are
2293 careful to use unsigned types where modulo arithmetic is required.
2294 Failure to do so _will_ break on newer gcc. */
2296 /* Signed saturating arithmetic. */
2298 /* Perform 16-bit signed saturating addition. */
2299 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2304 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2313 /* Perform 8-bit signed saturating addition. */
2314 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2319 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2328 /* Perform 16-bit signed saturating subtraction. */
2329 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2334 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2343 /* Perform 8-bit signed saturating subtraction. */
2344 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2349 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2358 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2359 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2360 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2361 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2364 #include "op_addsub.h"
2366 /* Unsigned saturating arithmetic. */
2367 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2376 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2384 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2393 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2401 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2402 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2403 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2404 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2407 #include "op_addsub.h"
2409 /* Signed modulo arithmetic. */
2410 #define SARITH16(a, b, n, op) do { \
2412 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2413 RESULT(sum, n, 16); \
2415 ge |= 3 << (n * 2); \
2418 #define SARITH8(a, b, n, op) do { \
2420 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2421 RESULT(sum, n, 8); \
2427 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2428 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2429 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2430 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2434 #include "op_addsub.h"
2436 /* Unsigned modulo arithmetic. */
2437 #define ADD16(a, b, n) do { \
2439 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2440 RESULT(sum, n, 16); \
2441 if ((sum >> 16) == 1) \
2442 ge |= 3 << (n * 2); \
2445 #define ADD8(a, b, n) do { \
2447 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2448 RESULT(sum, n, 8); \
2449 if ((sum >> 8) == 1) \
2453 #define SUB16(a, b, n) do { \
2455 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2456 RESULT(sum, n, 16); \
2457 if ((sum >> 16) == 0) \
2458 ge |= 3 << (n * 2); \
2461 #define SUB8(a, b, n) do { \
2463 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2464 RESULT(sum, n, 8); \
2465 if ((sum >> 8) == 0) \
2472 #include "op_addsub.h"
2474 /* Halved signed arithmetic. */
2475 #define ADD16(a, b, n) \
2476 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2477 #define SUB16(a, b, n) \
2478 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2479 #define ADD8(a, b, n) \
2480 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2481 #define SUB8(a, b, n) \
2482 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2485 #include "op_addsub.h"
2487 /* Halved unsigned arithmetic. */
2488 #define ADD16(a, b, n) \
2489 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2490 #define SUB16(a, b, n) \
2491 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2492 #define ADD8(a, b, n) \
2493 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2494 #define SUB8(a, b, n) \
2495 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2498 #include "op_addsub.h"
2500 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2508 /* Unsigned sum of absolute byte differences. */
2509 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2512 sum
= do_usad(a
, b
);
2513 sum
+= do_usad(a
>> 8, b
>> 8);
2514 sum
+= do_usad(a
>> 16, b
>>16);
2515 sum
+= do_usad(a
>> 24, b
>> 24);
2519 /* For ARMv6 SEL instruction. */
2520 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2533 return (a
& mask
) | (b
& ~mask
);
2536 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2538 return (val
>> 32) | (val
!= 0);
2541 /* VFP support. We follow the convention used for VFP instrunctions:
2542 Single precition routines have a "s" suffix, double precision a
2545 /* Convert host exception flags to vfp form. */
2546 static inline int vfp_exceptbits_from_host(int host_bits
)
2548 int target_bits
= 0;
2550 if (host_bits
& float_flag_invalid
)
2552 if (host_bits
& float_flag_divbyzero
)
2554 if (host_bits
& float_flag_overflow
)
2556 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2558 if (host_bits
& float_flag_inexact
)
2559 target_bits
|= 0x10;
2560 if (host_bits
& float_flag_input_denormal
)
2561 target_bits
|= 0x80;
2565 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2570 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2571 | (env
->vfp
.vec_len
<< 16)
2572 | (env
->vfp
.vec_stride
<< 20);
2573 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2574 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2575 fpscr
|= vfp_exceptbits_from_host(i
);
2579 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2581 return HELPER(vfp_get_fpscr
)(env
);
2584 /* Convert vfp exception flags to target form. */
2585 static inline int vfp_exceptbits_to_host(int target_bits
)
2589 if (target_bits
& 1)
2590 host_bits
|= float_flag_invalid
;
2591 if (target_bits
& 2)
2592 host_bits
|= float_flag_divbyzero
;
2593 if (target_bits
& 4)
2594 host_bits
|= float_flag_overflow
;
2595 if (target_bits
& 8)
2596 host_bits
|= float_flag_underflow
;
2597 if (target_bits
& 0x10)
2598 host_bits
|= float_flag_inexact
;
2599 if (target_bits
& 0x80)
2600 host_bits
|= float_flag_input_denormal
;
2604 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2609 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2610 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2611 env
->vfp
.vec_len
= (val
>> 16) & 7;
2612 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2615 if (changed
& (3 << 22)) {
2616 i
= (val
>> 22) & 3;
2619 i
= float_round_nearest_even
;
2625 i
= float_round_down
;
2628 i
= float_round_to_zero
;
2631 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2633 if (changed
& (1 << 24)) {
2634 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2635 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2637 if (changed
& (1 << 25))
2638 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2640 i
= vfp_exceptbits_to_host(val
);
2641 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2642 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
2645 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
2647 HELPER(vfp_set_fpscr
)(env
, val
);
2650 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2652 #define VFP_BINOP(name) \
2653 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
2655 float_status *fpst = fpstp; \
2656 return float32_ ## name(a, b, fpst); \
2658 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
2660 float_status *fpst = fpstp; \
2661 return float64_ ## name(a, b, fpst); \
2669 float32
VFP_HELPER(neg
, s
)(float32 a
)
2671 return float32_chs(a
);
2674 float64
VFP_HELPER(neg
, d
)(float64 a
)
2676 return float64_chs(a
);
2679 float32
VFP_HELPER(abs
, s
)(float32 a
)
2681 return float32_abs(a
);
2684 float64
VFP_HELPER(abs
, d
)(float64 a
)
2686 return float64_abs(a
);
2689 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
2691 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2694 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
2696 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2699 /* XXX: check quiet/signaling case */
2700 #define DO_VFP_cmp(p, type) \
2701 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
2704 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2705 case 0: flags = 0x6; break; \
2706 case -1: flags = 0x8; break; \
2707 case 1: flags = 0x2; break; \
2708 default: case 2: flags = 0x3; break; \
2710 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2711 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2713 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
2716 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2717 case 0: flags = 0x6; break; \
2718 case -1: flags = 0x8; break; \
2719 case 1: flags = 0x2; break; \
2720 default: case 2: flags = 0x3; break; \
2722 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2723 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2725 DO_VFP_cmp(s
, float32
)
2726 DO_VFP_cmp(d
, float64
)
2729 /* Integer to float and float to integer conversions */
2731 #define CONV_ITOF(name, fsz, sign) \
2732 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2734 float_status *fpst = fpstp; \
2735 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
2738 #define CONV_FTOI(name, fsz, sign, round) \
2739 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2741 float_status *fpst = fpstp; \
2742 if (float##fsz##_is_any_nan(x)) { \
2743 float_raise(float_flag_invalid, fpst); \
2746 return float##fsz##_to_##sign##int32##round(x, fpst); \
2749 #define FLOAT_CONVS(name, p, fsz, sign) \
2750 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2751 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2752 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
2754 FLOAT_CONVS(si
, s
, 32, )
2755 FLOAT_CONVS(si
, d
, 64, )
2756 FLOAT_CONVS(ui
, s
, 32, u
)
2757 FLOAT_CONVS(ui
, d
, 64, u
)
2763 /* floating point conversion */
2764 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
2766 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
2767 /* ARM requires that S<->D conversion of any kind of NaN generates
2768 * a quiet NaN by forcing the most significant frac bit to 1.
2770 return float64_maybe_silence_nan(r
);
2773 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
2775 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
2776 /* ARM requires that S<->D conversion of any kind of NaN generates
2777 * a quiet NaN by forcing the most significant frac bit to 1.
2779 return float32_maybe_silence_nan(r
);
2782 /* VFP3 fixed point conversion. */
2783 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
2784 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2787 float_status *fpst = fpstp; \
2789 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2790 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
2792 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2795 float_status *fpst = fpstp; \
2797 if (float##fsz##_is_any_nan(x)) { \
2798 float_raise(float_flag_invalid, fpst); \
2801 tmp = float##fsz##_scalbn(x, shift, fpst); \
2802 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
2805 VFP_CONV_FIX(sh
, d
, 64, int16
, )
2806 VFP_CONV_FIX(sl
, d
, 64, int32
, )
2807 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
2808 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
2809 VFP_CONV_FIX(sh
, s
, 32, int16
, )
2810 VFP_CONV_FIX(sl
, s
, 32, int32
, )
2811 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
2812 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
2815 /* Half precision conversions. */
2816 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
2818 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2819 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
2821 return float32_maybe_silence_nan(r
);
2826 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
2828 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2829 float16 r
= float32_to_float16(a
, ieee
, s
);
2831 r
= float16_maybe_silence_nan(r
);
2833 return float16_val(r
);
2836 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2838 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
2841 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2843 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
2846 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
2848 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
2851 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
2853 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
2856 #define float32_two make_float32(0x40000000)
2857 #define float32_three make_float32(0x40400000)
2858 #define float32_one_point_five make_float32(0x3fc00000)
2860 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2862 float_status
*s
= &env
->vfp
.standard_fp_status
;
2863 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2864 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2865 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2866 float_raise(float_flag_input_denormal
, s
);
2870 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
2873 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
2875 float_status
*s
= &env
->vfp
.standard_fp_status
;
2877 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
2878 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
2879 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
2880 float_raise(float_flag_input_denormal
, s
);
2882 return float32_one_point_five
;
2884 product
= float32_mul(a
, b
, s
);
2885 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
2890 /* Constants 256 and 512 are used in some helpers; we avoid relying on
2891 * int->float conversions at run-time. */
2892 #define float64_256 make_float64(0x4070000000000000LL)
2893 #define float64_512 make_float64(0x4080000000000000LL)
2895 /* The algorithm that must be used to calculate the estimate
2896 * is specified by the ARM ARM.
2898 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
2900 /* These calculations mustn't set any fp exception flags,
2901 * so we use a local copy of the fp_status.
2903 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2904 float_status
*s
= &dummy_status
;
2905 /* q = (int)(a * 512.0) */
2906 float64 q
= float64_mul(float64_512
, a
, s
);
2907 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
2909 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2910 q
= int64_to_float64(q_int
, s
);
2911 q
= float64_add(q
, float64_half
, s
);
2912 q
= float64_div(q
, float64_512
, s
);
2913 q
= float64_div(float64_one
, q
, s
);
2915 /* s = (int)(256.0 * r + 0.5) */
2916 q
= float64_mul(q
, float64_256
, s
);
2917 q
= float64_add(q
, float64_half
, s
);
2918 q_int
= float64_to_int64_round_to_zero(q
, s
);
2920 /* return (double)s / 256.0 */
2921 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
2924 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
2926 float_status
*s
= &env
->vfp
.standard_fp_status
;
2928 uint32_t val32
= float32_val(a
);
2931 int a_exp
= (val32
& 0x7f800000) >> 23;
2932 int sign
= val32
& 0x80000000;
2934 if (float32_is_any_nan(a
)) {
2935 if (float32_is_signaling_nan(a
)) {
2936 float_raise(float_flag_invalid
, s
);
2938 return float32_default_nan
;
2939 } else if (float32_is_infinity(a
)) {
2940 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2941 } else if (float32_is_zero_or_denormal(a
)) {
2942 if (!float32_is_zero(a
)) {
2943 float_raise(float_flag_input_denormal
, s
);
2945 float_raise(float_flag_divbyzero
, s
);
2946 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
2947 } else if (a_exp
>= 253) {
2948 float_raise(float_flag_underflow
, s
);
2949 return float32_set_sign(float32_zero
, float32_is_neg(a
));
2952 f64
= make_float64((0x3feULL
<< 52)
2953 | ((int64_t)(val32
& 0x7fffff) << 29));
2955 result_exp
= 253 - a_exp
;
2957 f64
= recip_estimate(f64
, env
);
2960 | ((result_exp
& 0xff) << 23)
2961 | ((float64_val(f64
) >> 29) & 0x7fffff);
2962 return make_float32(val32
);
2965 /* The algorithm that must be used to calculate the estimate
2966 * is specified by the ARM ARM.
2968 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
2970 /* These calculations mustn't set any fp exception flags,
2971 * so we use a local copy of the fp_status.
2973 float_status dummy_status
= env
->vfp
.standard_fp_status
;
2974 float_status
*s
= &dummy_status
;
2978 if (float64_lt(a
, float64_half
, s
)) {
2979 /* range 0.25 <= a < 0.5 */
2981 /* a in units of 1/512 rounded down */
2982 /* q0 = (int)(a * 512.0); */
2983 q
= float64_mul(float64_512
, a
, s
);
2984 q_int
= float64_to_int64_round_to_zero(q
, s
);
2986 /* reciprocal root r */
2987 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2988 q
= int64_to_float64(q_int
, s
);
2989 q
= float64_add(q
, float64_half
, s
);
2990 q
= float64_div(q
, float64_512
, s
);
2991 q
= float64_sqrt(q
, s
);
2992 q
= float64_div(float64_one
, q
, s
);
2994 /* range 0.5 <= a < 1.0 */
2996 /* a in units of 1/256 rounded down */
2997 /* q1 = (int)(a * 256.0); */
2998 q
= float64_mul(float64_256
, a
, s
);
2999 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3001 /* reciprocal root r */
3002 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3003 q
= int64_to_float64(q_int
, s
);
3004 q
= float64_add(q
, float64_half
, s
);
3005 q
= float64_div(q
, float64_256
, s
);
3006 q
= float64_sqrt(q
, s
);
3007 q
= float64_div(float64_one
, q
, s
);
3009 /* r in units of 1/256 rounded to nearest */
3010 /* s = (int)(256.0 * r + 0.5); */
3012 q
= float64_mul(q
, float64_256
,s
);
3013 q
= float64_add(q
, float64_half
, s
);
3014 q_int
= float64_to_int64_round_to_zero(q
, s
);
3016 /* return (double)s / 256.0;*/
3017 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3020 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3022 float_status
*s
= &env
->vfp
.standard_fp_status
;
3028 val
= float32_val(a
);
3030 if (float32_is_any_nan(a
)) {
3031 if (float32_is_signaling_nan(a
)) {
3032 float_raise(float_flag_invalid
, s
);
3034 return float32_default_nan
;
3035 } else if (float32_is_zero_or_denormal(a
)) {
3036 if (!float32_is_zero(a
)) {
3037 float_raise(float_flag_input_denormal
, s
);
3039 float_raise(float_flag_divbyzero
, s
);
3040 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3041 } else if (float32_is_neg(a
)) {
3042 float_raise(float_flag_invalid
, s
);
3043 return float32_default_nan
;
3044 } else if (float32_is_infinity(a
)) {
3045 return float32_zero
;
3048 /* Normalize to a double-precision value between 0.25 and 1.0,
3049 * preserving the parity of the exponent. */
3050 if ((val
& 0x800000) == 0) {
3051 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3053 | ((uint64_t)(val
& 0x7fffff) << 29));
3055 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3057 | ((uint64_t)(val
& 0x7fffff) << 29));
3060 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3062 f64
= recip_sqrt_estimate(f64
, env
);
3064 val64
= float64_val(f64
);
3066 val
= ((result_exp
& 0xff) << 23)
3067 | ((val64
>> 29) & 0x7fffff);
3068 return make_float32(val
);
3071 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3075 if ((a
& 0x80000000) == 0) {
3079 f64
= make_float64((0x3feULL
<< 52)
3080 | ((int64_t)(a
& 0x7fffffff) << 21));
3082 f64
= recip_estimate (f64
, env
);
3084 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3087 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3091 if ((a
& 0xc0000000) == 0) {
3095 if (a
& 0x80000000) {
3096 f64
= make_float64((0x3feULL
<< 52)
3097 | ((uint64_t)(a
& 0x7fffffff) << 21));
3098 } else { /* bits 31-30 == '01' */
3099 f64
= make_float64((0x3fdULL
<< 52)
3100 | ((uint64_t)(a
& 0x3fffffff) << 22));
3103 f64
= recip_sqrt_estimate(f64
, env
);
3105 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3108 /* VFPv4 fused multiply-accumulate */
3109 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3111 float_status
*fpst
= fpstp
;
3112 return float32_muladd(a
, b
, c
, 0, fpst
);
3115 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3117 float_status
*fpst
= fpstp
;
3118 return float64_muladd(a
, b
, c
, 0, fpst
);
3121 void HELPER(set_teecr
)(CPUARMState
*env
, uint32_t val
)
3124 if (env
->teecr
!= val
) {