]>
git.proxmox.com Git - qemu.git/blob - target-arm/helper.c
9 #include "qemu-common.h"
10 #include "host-utils.h"
12 static uint32_t cortexa8_cp15_c0_c1
[8] =
13 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
15 static uint32_t cortexa8_cp15_c0_c2
[8] =
16 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
18 static uint32_t mpcore_cp15_c0_c1
[8] =
19 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
21 static uint32_t mpcore_cp15_c0_c2
[8] =
22 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
24 static uint32_t arm1136_cp15_c0_c1
[8] =
25 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
27 static uint32_t arm1136_cp15_c0_c2
[8] =
28 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
30 static uint32_t cpu_arm_find_by_name(const char *name
);
32 static inline void set_feature(CPUARMState
*env
, int feature
)
34 env
->features
|= 1u << feature
;
37 static void cpu_reset_model_id(CPUARMState
*env
, uint32_t id
)
39 env
->cp15
.c0_cpuid
= id
;
41 case ARM_CPUID_ARM926
:
42 set_feature(env
, ARM_FEATURE_VFP
);
43 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x41011090;
44 env
->cp15
.c0_cachetype
= 0x1dd20d2;
45 env
->cp15
.c1_sys
= 0x00090078;
47 case ARM_CPUID_ARM946
:
48 set_feature(env
, ARM_FEATURE_MPU
);
49 env
->cp15
.c0_cachetype
= 0x0f004006;
50 env
->cp15
.c1_sys
= 0x00000078;
52 case ARM_CPUID_ARM1026
:
53 set_feature(env
, ARM_FEATURE_VFP
);
54 set_feature(env
, ARM_FEATURE_AUXCR
);
55 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410110a0;
56 env
->cp15
.c0_cachetype
= 0x1dd20d2;
57 env
->cp15
.c1_sys
= 0x00090078;
59 case ARM_CPUID_ARM1136_R2
:
60 case ARM_CPUID_ARM1136
:
61 set_feature(env
, ARM_FEATURE_V6
);
62 set_feature(env
, ARM_FEATURE_VFP
);
63 set_feature(env
, ARM_FEATURE_AUXCR
);
64 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
65 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
66 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
67 memcpy(env
->cp15
.c0_c1
, arm1136_cp15_c0_c1
, 8 * sizeof(uint32_t));
68 memcpy(env
->cp15
.c0_c2
, arm1136_cp15_c0_c2
, 8 * sizeof(uint32_t));
69 env
->cp15
.c0_cachetype
= 0x1dd20d2;
71 case ARM_CPUID_ARM11MPCORE
:
72 set_feature(env
, ARM_FEATURE_V6
);
73 set_feature(env
, ARM_FEATURE_V6K
);
74 set_feature(env
, ARM_FEATURE_VFP
);
75 set_feature(env
, ARM_FEATURE_AUXCR
);
76 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410120b4;
77 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11111111;
78 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00000000;
79 memcpy(env
->cp15
.c0_c1
, mpcore_cp15_c0_c1
, 8 * sizeof(uint32_t));
80 memcpy(env
->cp15
.c0_c2
, mpcore_cp15_c0_c2
, 8 * sizeof(uint32_t));
81 env
->cp15
.c0_cachetype
= 0x1dd20d2;
83 case ARM_CPUID_CORTEXA8
:
84 set_feature(env
, ARM_FEATURE_V6
);
85 set_feature(env
, ARM_FEATURE_V6K
);
86 set_feature(env
, ARM_FEATURE_V7
);
87 set_feature(env
, ARM_FEATURE_AUXCR
);
88 set_feature(env
, ARM_FEATURE_THUMB2
);
89 set_feature(env
, ARM_FEATURE_VFP
);
90 set_feature(env
, ARM_FEATURE_VFP3
);
91 set_feature(env
, ARM_FEATURE_NEON
);
92 set_feature(env
, ARM_FEATURE_THUMB2EE
);
93 env
->vfp
.xregs
[ARM_VFP_FPSID
] = 0x410330c0;
94 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = 0x11110222;
95 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = 0x00011100;
96 memcpy(env
->cp15
.c0_c1
, cortexa8_cp15_c0_c1
, 8 * sizeof(uint32_t));
97 memcpy(env
->cp15
.c0_c2
, cortexa8_cp15_c0_c2
, 8 * sizeof(uint32_t));
98 env
->cp15
.c0_cachetype
= 0x82048004;
99 env
->cp15
.c0_clid
= (1 << 27) | (2 << 24) | 3;
100 env
->cp15
.c0_ccsid
[0] = 0xe007e01a; /* 16k L1 dcache. */
101 env
->cp15
.c0_ccsid
[1] = 0x2007e01a; /* 16k L1 icache. */
102 env
->cp15
.c0_ccsid
[2] = 0xf0000000; /* No L2 icache. */
104 case ARM_CPUID_CORTEXM3
:
105 set_feature(env
, ARM_FEATURE_V6
);
106 set_feature(env
, ARM_FEATURE_THUMB2
);
107 set_feature(env
, ARM_FEATURE_V7
);
108 set_feature(env
, ARM_FEATURE_M
);
109 set_feature(env
, ARM_FEATURE_DIV
);
111 case ARM_CPUID_ANY
: /* For userspace emulation. */
112 set_feature(env
, ARM_FEATURE_V6
);
113 set_feature(env
, ARM_FEATURE_V6K
);
114 set_feature(env
, ARM_FEATURE_V7
);
115 set_feature(env
, ARM_FEATURE_THUMB2
);
116 set_feature(env
, ARM_FEATURE_VFP
);
117 set_feature(env
, ARM_FEATURE_VFP3
);
118 set_feature(env
, ARM_FEATURE_VFP_FP16
);
119 set_feature(env
, ARM_FEATURE_NEON
);
120 set_feature(env
, ARM_FEATURE_THUMB2EE
);
121 set_feature(env
, ARM_FEATURE_DIV
);
123 case ARM_CPUID_TI915T
:
124 case ARM_CPUID_TI925T
:
125 set_feature(env
, ARM_FEATURE_OMAPCP
);
126 env
->cp15
.c0_cpuid
= ARM_CPUID_TI925T
; /* Depends on wiring. */
127 env
->cp15
.c0_cachetype
= 0x5109149;
128 env
->cp15
.c1_sys
= 0x00000070;
129 env
->cp15
.c15_i_max
= 0x000;
130 env
->cp15
.c15_i_min
= 0xff0;
132 case ARM_CPUID_PXA250
:
133 case ARM_CPUID_PXA255
:
134 case ARM_CPUID_PXA260
:
135 case ARM_CPUID_PXA261
:
136 case ARM_CPUID_PXA262
:
137 set_feature(env
, ARM_FEATURE_XSCALE
);
138 /* JTAG_ID is ((id << 28) | 0x09265013) */
139 env
->cp15
.c0_cachetype
= 0xd172172;
140 env
->cp15
.c1_sys
= 0x00000078;
142 case ARM_CPUID_PXA270_A0
:
143 case ARM_CPUID_PXA270_A1
:
144 case ARM_CPUID_PXA270_B0
:
145 case ARM_CPUID_PXA270_B1
:
146 case ARM_CPUID_PXA270_C0
:
147 case ARM_CPUID_PXA270_C5
:
148 set_feature(env
, ARM_FEATURE_XSCALE
);
149 /* JTAG_ID is ((id << 28) | 0x09265013) */
150 set_feature(env
, ARM_FEATURE_IWMMXT
);
151 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
152 env
->cp15
.c0_cachetype
= 0xd172172;
153 env
->cp15
.c1_sys
= 0x00000078;
156 cpu_abort(env
, "Bad CPU ID: %x\n", id
);
161 void cpu_reset(CPUARMState
*env
)
165 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
166 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
167 log_cpu_state(env
, 0);
170 id
= env
->cp15
.c0_cpuid
;
171 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
173 cpu_reset_model_id(env
, id
);
174 #if defined (CONFIG_USER_ONLY)
175 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
176 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
178 /* SVC mode with interrupts disabled. */
179 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
180 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
183 env
->uncached_cpsr
&= ~CPSR_I
;
184 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
185 env
->cp15
.c2_base_mask
= 0xffffc000u
;
191 static int vfp_gdb_get_reg(CPUState
*env
, uint8_t *buf
, int reg
)
195 /* VFP data registers are always little-endian. */
196 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
198 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
201 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
202 /* Aliases for Q regs. */
205 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
206 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
210 switch (reg
- nregs
) {
211 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
212 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
213 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
218 static int vfp_gdb_set_reg(CPUState
*env
, uint8_t *buf
, int reg
)
222 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
224 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
227 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
230 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
231 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
235 switch (reg
- nregs
) {
236 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
237 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
238 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
243 CPUARMState
*cpu_arm_init(const char *cpu_model
)
247 static int inited
= 0;
249 id
= cpu_arm_find_by_name(cpu_model
);
252 env
= qemu_mallocz(sizeof(CPUARMState
));
256 arm_translate_init();
259 env
->cpu_model_str
= cpu_model
;
260 env
->cp15
.c0_cpuid
= id
;
262 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
263 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
264 51, "arm-neon.xml", 0);
265 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
266 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
267 35, "arm-vfp3.xml", 0);
268 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
269 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
270 19, "arm-vfp.xml", 0);
281 static const struct arm_cpu_t arm_cpu_names
[] = {
282 { ARM_CPUID_ARM926
, "arm926"},
283 { ARM_CPUID_ARM946
, "arm946"},
284 { ARM_CPUID_ARM1026
, "arm1026"},
285 { ARM_CPUID_ARM1136
, "arm1136"},
286 { ARM_CPUID_ARM1136_R2
, "arm1136-r2"},
287 { ARM_CPUID_ARM11MPCORE
, "arm11mpcore"},
288 { ARM_CPUID_CORTEXM3
, "cortex-m3"},
289 { ARM_CPUID_CORTEXA8
, "cortex-a8"},
290 { ARM_CPUID_TI925T
, "ti925t" },
291 { ARM_CPUID_PXA250
, "pxa250" },
292 { ARM_CPUID_PXA255
, "pxa255" },
293 { ARM_CPUID_PXA260
, "pxa260" },
294 { ARM_CPUID_PXA261
, "pxa261" },
295 { ARM_CPUID_PXA262
, "pxa262" },
296 { ARM_CPUID_PXA270
, "pxa270" },
297 { ARM_CPUID_PXA270_A0
, "pxa270-a0" },
298 { ARM_CPUID_PXA270_A1
, "pxa270-a1" },
299 { ARM_CPUID_PXA270_B0
, "pxa270-b0" },
300 { ARM_CPUID_PXA270_B1
, "pxa270-b1" },
301 { ARM_CPUID_PXA270_C0
, "pxa270-c0" },
302 { ARM_CPUID_PXA270_C5
, "pxa270-c5" },
303 { ARM_CPUID_ANY
, "any"},
307 void arm_cpu_list(FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...))
311 (*cpu_fprintf
)(f
, "Available CPUs:\n");
312 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
313 (*cpu_fprintf
)(f
, " %s\n", arm_cpu_names
[i
].name
);
317 /* return 0 if not found */
318 static uint32_t cpu_arm_find_by_name(const char *name
)
324 for (i
= 0; arm_cpu_names
[i
].name
; i
++) {
325 if (strcmp(name
, arm_cpu_names
[i
].name
) == 0) {
326 id
= arm_cpu_names
[i
].id
;
333 void cpu_arm_close(CPUARMState
*env
)
338 uint32_t cpsr_read(CPUARMState
*env
)
342 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
343 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
344 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
345 | ((env
->condexec_bits
& 0xfc) << 8)
349 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
351 if (mask
& CPSR_NZCV
) {
352 env
->ZF
= (~val
) & CPSR_Z
;
354 env
->CF
= (val
>> 29) & 1;
355 env
->VF
= (val
<< 3) & 0x80000000;
358 env
->QF
= ((val
& CPSR_Q
) != 0);
360 env
->thumb
= ((val
& CPSR_T
) != 0);
361 if (mask
& CPSR_IT_0_1
) {
362 env
->condexec_bits
&= ~3;
363 env
->condexec_bits
|= (val
>> 25) & 3;
365 if (mask
& CPSR_IT_2_7
) {
366 env
->condexec_bits
&= 3;
367 env
->condexec_bits
|= (val
>> 8) & 0xfc;
369 if (mask
& CPSR_GE
) {
370 env
->GE
= (val
>> 16) & 0xf;
373 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
374 switch_mode(env
, val
& CPSR_M
);
376 mask
&= ~CACHED_CPSR_BITS
;
377 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
380 /* Sign/zero extend */
381 uint32_t HELPER(sxtb16
)(uint32_t x
)
384 res
= (uint16_t)(int8_t)x
;
385 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
389 uint32_t HELPER(uxtb16
)(uint32_t x
)
392 res
= (uint16_t)(uint8_t)x
;
393 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
397 uint32_t HELPER(clz
)(uint32_t x
)
402 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
406 if (num
== INT_MIN
&& den
== -1)
411 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
418 uint32_t HELPER(rbit
)(uint32_t x
)
420 x
= ((x
& 0xff000000) >> 24)
421 | ((x
& 0x00ff0000) >> 8)
422 | ((x
& 0x0000ff00) << 8)
423 | ((x
& 0x000000ff) << 24);
424 x
= ((x
& 0xf0f0f0f0) >> 4)
425 | ((x
& 0x0f0f0f0f) << 4);
426 x
= ((x
& 0x88888888) >> 3)
427 | ((x
& 0x44444444) >> 1)
428 | ((x
& 0x22222222) << 1)
429 | ((x
& 0x11111111) << 3);
433 uint32_t HELPER(abs
)(uint32_t x
)
435 return ((int32_t)x
< 0) ? -x
: x
;
438 #if defined(CONFIG_USER_ONLY)
440 void do_interrupt (CPUState
*env
)
442 env
->exception_index
= -1;
445 /* Structure used to record exclusive memory locations. */
446 typedef struct mmon_state
{
447 struct mmon_state
*next
;
448 CPUARMState
*cpu_env
;
452 /* Chain of current locks. */
453 static mmon_state
* mmon_head
= NULL
;
455 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
456 int mmu_idx
, int is_softmmu
)
459 env
->exception_index
= EXCP_PREFETCH_ABORT
;
460 env
->cp15
.c6_insn
= address
;
462 env
->exception_index
= EXCP_DATA_ABORT
;
463 env
->cp15
.c6_data
= address
;
468 static void allocate_mmon_state(CPUState
*env
)
470 env
->mmon_entry
= malloc(sizeof (mmon_state
));
471 memset (env
->mmon_entry
, 0, sizeof (mmon_state
));
472 env
->mmon_entry
->cpu_env
= env
;
473 mmon_head
= env
->mmon_entry
;
476 /* Flush any monitor locks for the specified address. */
477 static void flush_mmon(uint32_t addr
)
481 for (mon
= mmon_head
; mon
; mon
= mon
->next
)
483 if (mon
->addr
!= addr
)
491 /* Mark an address for exclusive access. */
492 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
494 if (!env
->mmon_entry
)
495 allocate_mmon_state(env
);
496 /* Clear any previous locks. */
498 env
->mmon_entry
->addr
= addr
;
501 /* Test if an exclusive address is still exclusive. Returns zero
502 if the address is still exclusive. */
503 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
507 if (!env
->mmon_entry
)
509 if (env
->mmon_entry
->addr
== addr
)
517 void HELPER(clrex
)(CPUState
*env
)
519 if (!(env
->mmon_entry
&& env
->mmon_entry
->addr
))
521 flush_mmon(env
->mmon_entry
->addr
);
524 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
529 /* These should probably raise undefined insn exceptions. */
530 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
532 int op1
= (insn
>> 8) & 0xf;
533 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
537 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
539 int op1
= (insn
>> 8) & 0xf;
540 cpu_abort(env
, "cp%i insn %08x\n", op1
, insn
);
544 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
546 cpu_abort(env
, "cp15 insn %08x\n", insn
);
549 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
551 cpu_abort(env
, "cp15 insn %08x\n", insn
);
555 /* These should probably raise undefined insn exceptions. */
556 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
558 cpu_abort(env
, "v7m_mrs %d\n", reg
);
561 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
563 cpu_abort(env
, "v7m_mrs %d\n", reg
);
567 void switch_mode(CPUState
*env
, int mode
)
569 if (mode
!= ARM_CPU_MODE_USR
)
570 cpu_abort(env
, "Tried to switch out of user mode\n");
573 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
575 cpu_abort(env
, "banked r13 write\n");
578 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
580 cpu_abort(env
, "banked r13 read\n");
586 extern int semihosting_enabled
;
588 /* Map CPU modes onto saved register banks. */
589 static inline int bank_number (int mode
)
592 case ARM_CPU_MODE_USR
:
593 case ARM_CPU_MODE_SYS
:
595 case ARM_CPU_MODE_SVC
:
597 case ARM_CPU_MODE_ABT
:
599 case ARM_CPU_MODE_UND
:
601 case ARM_CPU_MODE_IRQ
:
603 case ARM_CPU_MODE_FIQ
:
606 cpu_abort(cpu_single_env
, "Bad mode %x\n", mode
);
610 void switch_mode(CPUState
*env
, int mode
)
615 old_mode
= env
->uncached_cpsr
& CPSR_M
;
616 if (mode
== old_mode
)
619 if (old_mode
== ARM_CPU_MODE_FIQ
) {
620 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
621 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
622 } else if (mode
== ARM_CPU_MODE_FIQ
) {
623 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
624 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
627 i
= bank_number(old_mode
);
628 env
->banked_r13
[i
] = env
->regs
[13];
629 env
->banked_r14
[i
] = env
->regs
[14];
630 env
->banked_spsr
[i
] = env
->spsr
;
632 i
= bank_number(mode
);
633 env
->regs
[13] = env
->banked_r13
[i
];
634 env
->regs
[14] = env
->banked_r14
[i
];
635 env
->spsr
= env
->banked_spsr
[i
];
638 static void v7m_push(CPUARMState
*env
, uint32_t val
)
641 stl_phys(env
->regs
[13], val
);
644 static uint32_t v7m_pop(CPUARMState
*env
)
647 val
= ldl_phys(env
->regs
[13]);
652 /* Switch to V7M main or process stack pointer. */
653 static void switch_v7m_sp(CPUARMState
*env
, int process
)
656 if (env
->v7m
.current_sp
!= process
) {
657 tmp
= env
->v7m
.other_sp
;
658 env
->v7m
.other_sp
= env
->regs
[13];
660 env
->v7m
.current_sp
= process
;
664 static void do_v7m_exception_exit(CPUARMState
*env
)
669 type
= env
->regs
[15];
670 if (env
->v7m
.exception
!= 0)
671 armv7m_nvic_complete_irq(env
->v7m
.nvic
, env
->v7m
.exception
);
673 /* Switch to the target stack. */
674 switch_v7m_sp(env
, (type
& 4) != 0);
676 env
->regs
[0] = v7m_pop(env
);
677 env
->regs
[1] = v7m_pop(env
);
678 env
->regs
[2] = v7m_pop(env
);
679 env
->regs
[3] = v7m_pop(env
);
680 env
->regs
[12] = v7m_pop(env
);
681 env
->regs
[14] = v7m_pop(env
);
682 env
->regs
[15] = v7m_pop(env
);
684 xpsr_write(env
, xpsr
, 0xfffffdff);
685 /* Undo stack alignment. */
688 /* ??? The exception return type specifies Thread/Handler mode. However
689 this is also implied by the xPSR value. Not sure what to do
690 if there is a mismatch. */
691 /* ??? Likewise for mismatches between the CONTROL register and the stack
695 static void do_interrupt_v7m(CPUARMState
*env
)
697 uint32_t xpsr
= xpsr_read(env
);
702 if (env
->v7m
.current_sp
)
704 if (env
->v7m
.exception
== 0)
707 /* For exceptions we just mark as pending on the NVIC, and let that
709 /* TODO: Need to escalate if the current priority is higher than the
710 one we're raising. */
711 switch (env
->exception_index
) {
713 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_USAGE
);
717 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_SVC
);
719 case EXCP_PREFETCH_ABORT
:
720 case EXCP_DATA_ABORT
:
721 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_MEM
);
724 if (semihosting_enabled
) {
726 nr
= lduw_code(env
->regs
[15]) & 0xff;
729 env
->regs
[0] = do_arm_semihosting(env
);
733 armv7m_nvic_set_pending(env
->v7m
.nvic
, ARMV7M_EXCP_DEBUG
);
736 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->v7m
.nvic
);
738 case EXCP_EXCEPTION_EXIT
:
739 do_v7m_exception_exit(env
);
742 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
743 return; /* Never happens. Keep compiler happy. */
746 /* Align stack pointer. */
747 /* ??? Should only do this if Configuration Control Register
748 STACKALIGN bit is set. */
749 if (env
->regs
[13] & 4) {
753 /* Switch to the handler mode. */
755 v7m_push(env
, env
->regs
[15]);
756 v7m_push(env
, env
->regs
[14]);
757 v7m_push(env
, env
->regs
[12]);
758 v7m_push(env
, env
->regs
[3]);
759 v7m_push(env
, env
->regs
[2]);
760 v7m_push(env
, env
->regs
[1]);
761 v7m_push(env
, env
->regs
[0]);
762 switch_v7m_sp(env
, 0);
763 env
->uncached_cpsr
&= ~CPSR_IT
;
765 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
766 env
->regs
[15] = addr
& 0xfffffffe;
767 env
->thumb
= addr
& 1;
770 /* Handle a CPU exception. */
771 void do_interrupt(CPUARMState
*env
)
779 do_interrupt_v7m(env
);
782 /* TODO: Vectored interrupt controller. */
783 switch (env
->exception_index
) {
785 new_mode
= ARM_CPU_MODE_UND
;
794 if (semihosting_enabled
) {
795 /* Check for semihosting interrupt. */
797 mask
= lduw_code(env
->regs
[15] - 2) & 0xff;
799 mask
= ldl_code(env
->regs
[15] - 4) & 0xffffff;
801 /* Only intercept calls from privileged modes, to provide some
802 semblance of security. */
803 if (((mask
== 0x123456 && !env
->thumb
)
804 || (mask
== 0xab && env
->thumb
))
805 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
806 env
->regs
[0] = do_arm_semihosting(env
);
810 new_mode
= ARM_CPU_MODE_SVC
;
813 /* The PC already points to the next instruction. */
817 /* See if this is a semihosting syscall. */
818 if (env
->thumb
&& semihosting_enabled
) {
819 mask
= lduw_code(env
->regs
[15]) & 0xff;
821 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
823 env
->regs
[0] = do_arm_semihosting(env
);
827 /* Fall through to prefetch abort. */
828 case EXCP_PREFETCH_ABORT
:
829 new_mode
= ARM_CPU_MODE_ABT
;
831 mask
= CPSR_A
| CPSR_I
;
834 case EXCP_DATA_ABORT
:
835 new_mode
= ARM_CPU_MODE_ABT
;
837 mask
= CPSR_A
| CPSR_I
;
841 new_mode
= ARM_CPU_MODE_IRQ
;
843 /* Disable IRQ and imprecise data aborts. */
844 mask
= CPSR_A
| CPSR_I
;
848 new_mode
= ARM_CPU_MODE_FIQ
;
850 /* Disable FIQ, IRQ and imprecise data aborts. */
851 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
855 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
856 return; /* Never happens. Keep compiler happy. */
859 if (env
->cp15
.c1_sys
& (1 << 13)) {
862 switch_mode (env
, new_mode
);
863 env
->spsr
= cpsr_read(env
);
865 env
->condexec_bits
= 0;
866 /* Switch to the new mode, and switch to Arm mode. */
867 /* ??? Thumb interrupt handlers not implemented. */
868 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
869 env
->uncached_cpsr
|= mask
;
871 env
->regs
[14] = env
->regs
[15] + offset
;
872 env
->regs
[15] = addr
;
873 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
876 /* Check section/page access permissions.
877 Returns the page protection flags, or zero if the access is not
879 static inline int check_ap(CPUState
*env
, int ap
, int domain
, int access_type
,
885 return PAGE_READ
| PAGE_WRITE
;
887 if (access_type
== 1)
894 if (access_type
== 1)
896 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
898 return is_user
? 0 : PAGE_READ
;
905 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
910 return PAGE_READ
| PAGE_WRITE
;
912 return PAGE_READ
| PAGE_WRITE
;
913 case 4: /* Reserved. */
916 return is_user
? 0 : prot_ro
;
920 if (!arm_feature (env
, ARM_FEATURE_V7
))
928 static uint32_t get_level1_table_address(CPUState
*env
, uint32_t address
)
932 if (address
& env
->cp15
.c2_mask
)
933 table
= env
->cp15
.c2_base1
& 0xffffc000;
935 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
937 table
|= (address
>> 18) & 0x3ffc;
941 static int get_phys_addr_v5(CPUState
*env
, uint32_t address
, int access_type
,
942 int is_user
, uint32_t *phys_ptr
, int *prot
)
952 /* Pagetable walk. */
953 /* Lookup l1 descriptor. */
954 table
= get_level1_table_address(env
, address
);
955 desc
= ldl_phys(table
);
957 domain
= (env
->cp15
.c3
>> ((desc
>> 4) & 0x1e)) & 3;
959 /* Section translation fault. */
963 if (domain
== 0 || domain
== 2) {
965 code
= 9; /* Section domain fault. */
967 code
= 11; /* Page domain fault. */
972 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
973 ap
= (desc
>> 10) & 3;
976 /* Lookup l2 entry. */
978 /* Coarse pagetable. */
979 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
981 /* Fine pagetable. */
982 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
984 desc
= ldl_phys(table
);
986 case 0: /* Page translation fault. */
989 case 1: /* 64k page. */
990 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
991 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
993 case 2: /* 4k page. */
994 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
995 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
997 case 3: /* 1k page. */
999 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1000 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1002 /* Page translation fault. */
1007 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
1009 ap
= (desc
>> 4) & 3;
1012 /* Never happens, but compiler isn't smart enough to tell. */
1017 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1019 /* Access permission fault. */
1022 *phys_ptr
= phys_addr
;
1025 return code
| (domain
<< 4);
1028 static int get_phys_addr_v6(CPUState
*env
, uint32_t address
, int access_type
,
1029 int is_user
, uint32_t *phys_ptr
, int *prot
)
1040 /* Pagetable walk. */
1041 /* Lookup l1 descriptor. */
1042 table
= get_level1_table_address(env
, address
);
1043 desc
= ldl_phys(table
);
1046 /* Section translation fault. */
1050 } else if (type
== 2 && (desc
& (1 << 18))) {
1054 /* Section or page. */
1055 domain
= (desc
>> 4) & 0x1e;
1057 domain
= (env
->cp15
.c3
>> domain
) & 3;
1058 if (domain
== 0 || domain
== 2) {
1060 code
= 9; /* Section domain fault. */
1062 code
= 11; /* Page domain fault. */
1066 if (desc
& (1 << 18)) {
1068 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
1071 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
1073 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
1074 xn
= desc
& (1 << 4);
1077 /* Lookup l2 entry. */
1078 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
1079 desc
= ldl_phys(table
);
1080 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
1082 case 0: /* Page translation fault. */
1085 case 1: /* 64k page. */
1086 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
1087 xn
= desc
& (1 << 15);
1089 case 2: case 3: /* 4k page. */
1090 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
1094 /* Never happens, but compiler isn't smart enough to tell. */
1099 if (xn
&& access_type
== 2)
1102 /* The simplified model uses AP[0] as an access control bit. */
1103 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
1104 /* Access flag fault. */
1105 code
= (code
== 15) ? 6 : 3;
1108 *prot
= check_ap(env
, ap
, domain
, access_type
, is_user
);
1110 /* Access permission fault. */
1113 *phys_ptr
= phys_addr
;
1116 return code
| (domain
<< 4);
1119 static int get_phys_addr_mpu(CPUState
*env
, uint32_t address
, int access_type
,
1120 int is_user
, uint32_t *phys_ptr
, int *prot
)
1126 *phys_ptr
= address
;
1127 for (n
= 7; n
>= 0; n
--) {
1128 base
= env
->cp15
.c6_region
[n
];
1129 if ((base
& 1) == 0)
1131 mask
= 1 << ((base
>> 1) & 0x1f);
1132 /* Keep this shift separate from the above to avoid an
1133 (undefined) << 32. */
1134 mask
= (mask
<< 1) - 1;
1135 if (((base
^ address
) & ~mask
) == 0)
1141 if (access_type
== 2) {
1142 mask
= env
->cp15
.c5_insn
;
1144 mask
= env
->cp15
.c5_data
;
1146 mask
= (mask
>> (n
* 4)) & 0xf;
1153 *prot
= PAGE_READ
| PAGE_WRITE
;
1158 *prot
|= PAGE_WRITE
;
1161 *prot
= PAGE_READ
| PAGE_WRITE
;
1172 /* Bad permission. */
1178 static inline int get_phys_addr(CPUState
*env
, uint32_t address
,
1179 int access_type
, int is_user
,
1180 uint32_t *phys_ptr
, int *prot
)
1182 /* Fast Context Switch Extension. */
1183 if (address
< 0x02000000)
1184 address
+= env
->cp15
.c13_fcse
;
1186 if ((env
->cp15
.c1_sys
& 1) == 0) {
1187 /* MMU/MPU disabled. */
1188 *phys_ptr
= address
;
1189 *prot
= PAGE_READ
| PAGE_WRITE
;
1191 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1192 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
1194 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
1195 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
1198 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
1203 int cpu_arm_handle_mmu_fault (CPUState
*env
, target_ulong address
,
1204 int access_type
, int mmu_idx
, int is_softmmu
)
1210 is_user
= mmu_idx
== MMU_USER_IDX
;
1211 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
);
1213 /* Map a single [sub]page. */
1214 phys_addr
&= ~(uint32_t)0x3ff;
1215 address
&= ~(uint32_t)0x3ff;
1216 return tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
,
1220 if (access_type
== 2) {
1221 env
->cp15
.c5_insn
= ret
;
1222 env
->cp15
.c6_insn
= address
;
1223 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1225 env
->cp15
.c5_data
= ret
;
1226 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
1227 env
->cp15
.c5_data
|= (1 << 11);
1228 env
->cp15
.c6_data
= address
;
1229 env
->exception_index
= EXCP_DATA_ABORT
;
1234 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
1240 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
);
1248 /* Not really implemented. Need to figure out a sane way of doing this.
1249 Maybe add generic watchpoint support and use that. */
1251 void HELPER(mark_exclusive
)(CPUState
*env
, uint32_t addr
)
1253 env
->mmon_addr
= addr
;
1256 uint32_t HELPER(test_exclusive
)(CPUState
*env
, uint32_t addr
)
1258 return (env
->mmon_addr
!= addr
);
1261 void HELPER(clrex
)(CPUState
*env
)
1263 env
->mmon_addr
= -1;
1266 void HELPER(set_cp
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1268 int cp_num
= (insn
>> 8) & 0xf;
1269 int cp_info
= (insn
>> 5) & 7;
1270 int src
= (insn
>> 16) & 0xf;
1271 int operand
= insn
& 0xf;
1273 if (env
->cp
[cp_num
].cp_write
)
1274 env
->cp
[cp_num
].cp_write(env
->cp
[cp_num
].opaque
,
1275 cp_info
, src
, operand
, val
);
1278 uint32_t HELPER(get_cp
)(CPUState
*env
, uint32_t insn
)
1280 int cp_num
= (insn
>> 8) & 0xf;
1281 int cp_info
= (insn
>> 5) & 7;
1282 int dest
= (insn
>> 16) & 0xf;
1283 int operand
= insn
& 0xf;
1285 if (env
->cp
[cp_num
].cp_read
)
1286 return env
->cp
[cp_num
].cp_read(env
->cp
[cp_num
].opaque
,
1287 cp_info
, dest
, operand
);
1291 /* Return basic MPU access permission bits. */
1292 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1299 for (i
= 0; i
< 16; i
+= 2) {
1300 ret
|= (val
>> i
) & mask
;
1306 /* Pad basic MPU access permission bits to extended format. */
1307 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1314 for (i
= 0; i
< 16; i
+= 2) {
1315 ret
|= (val
& mask
) << i
;
1321 void HELPER(set_cp15
)(CPUState
*env
, uint32_t insn
, uint32_t val
)
1327 op1
= (insn
>> 21) & 7;
1328 op2
= (insn
>> 5) & 7;
1330 switch ((insn
>> 16) & 0xf) {
1333 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1335 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1337 if (arm_feature(env
, ARM_FEATURE_V7
)
1338 && op1
== 2 && crm
== 0 && op2
== 0) {
1339 env
->cp15
.c0_cssel
= val
& 0xf;
1343 case 1: /* System configuration. */
1344 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1348 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) || crm
== 0)
1349 env
->cp15
.c1_sys
= val
;
1350 /* ??? Lots of these bits are not implemented. */
1351 /* This may enable/disable the MMU, so do a TLB flush. */
1354 case 1: /* Auxiliary cotrol register. */
1355 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1356 env
->cp15
.c1_xscaleauxcr
= val
;
1359 /* Not implemented. */
1362 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1364 if (env
->cp15
.c1_coproc
!= val
) {
1365 env
->cp15
.c1_coproc
= val
;
1366 /* ??? Is this safe when called from within a TB? */
1374 case 2: /* MMU Page table control / MPU cache control. */
1375 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1378 env
->cp15
.c2_data
= val
;
1381 env
->cp15
.c2_insn
= val
;
1389 env
->cp15
.c2_base0
= val
;
1392 env
->cp15
.c2_base1
= val
;
1396 env
->cp15
.c2_control
= val
;
1397 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> val
);
1398 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> val
);
1405 case 3: /* MMU Domain access control / MPU write buffer control. */
1407 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
1409 case 4: /* Reserved. */
1411 case 5: /* MMU Fault status / MPU access permission. */
1412 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1416 if (arm_feature(env
, ARM_FEATURE_MPU
))
1417 val
= extended_mpu_ap_bits(val
);
1418 env
->cp15
.c5_data
= val
;
1421 if (arm_feature(env
, ARM_FEATURE_MPU
))
1422 val
= extended_mpu_ap_bits(val
);
1423 env
->cp15
.c5_insn
= val
;
1426 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1428 env
->cp15
.c5_data
= val
;
1431 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1433 env
->cp15
.c5_insn
= val
;
1439 case 6: /* MMU Fault address / MPU base/size. */
1440 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1443 env
->cp15
.c6_region
[crm
] = val
;
1445 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1449 env
->cp15
.c6_data
= val
;
1451 case 1: /* ??? This is WFAR on armv6 */
1453 env
->cp15
.c6_insn
= val
;
1460 case 7: /* Cache control. */
1461 env
->cp15
.c15_i_max
= 0x000;
1462 env
->cp15
.c15_i_min
= 0xff0;
1463 /* No cache, so nothing to do. */
1464 /* ??? MPCore has VA to PA translation functions. */
1466 case 8: /* MMU TLB control. */
1468 case 0: /* Invalidate all. */
1471 case 1: /* Invalidate single TLB entry. */
1473 /* ??? This is wrong for large pages and sections. */
1474 /* As an ugly hack to make linux work we always flush a 4K
1477 tlb_flush_page(env
, val
);
1478 tlb_flush_page(env
, val
+ 0x400);
1479 tlb_flush_page(env
, val
+ 0x800);
1480 tlb_flush_page(env
, val
+ 0xc00);
1485 case 2: /* Invalidate on ASID. */
1486 tlb_flush(env
, val
== 0);
1488 case 3: /* Invalidate single entry on MVA. */
1489 /* ??? This is like case 1, but ignores ASID. */
1497 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1500 case 0: /* Cache lockdown. */
1502 case 0: /* L1 cache. */
1505 env
->cp15
.c9_data
= val
;
1508 env
->cp15
.c9_insn
= val
;
1514 case 1: /* L2 cache. */
1515 /* Ignore writes to L2 lockdown/auxiliary registers. */
1521 case 1: /* TCM memory region registers. */
1522 /* Not implemented. */
1528 case 10: /* MMU TLB lockdown. */
1529 /* ??? TLB lockdown not implemented. */
1531 case 12: /* Reserved. */
1533 case 13: /* Process ID. */
1536 /* Unlike real hardware the qemu TLB uses virtual addresses,
1537 not modified virtual addresses, so this causes a TLB flush.
1539 if (env
->cp15
.c13_fcse
!= val
)
1541 env
->cp15
.c13_fcse
= val
;
1544 /* This changes the ASID, so do a TLB flush. */
1545 if (env
->cp15
.c13_context
!= val
1546 && !arm_feature(env
, ARM_FEATURE_MPU
))
1548 env
->cp15
.c13_context
= val
;
1551 env
->cp15
.c13_tls1
= val
;
1554 env
->cp15
.c13_tls2
= val
;
1557 env
->cp15
.c13_tls3
= val
;
1563 case 14: /* Reserved. */
1565 case 15: /* Implementation specific. */
1566 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1567 if (op2
== 0 && crm
== 1) {
1568 if (env
->cp15
.c15_cpar
!= (val
& 0x3fff)) {
1569 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1571 env
->cp15
.c15_cpar
= val
& 0x3fff;
1577 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1581 case 1: /* Set TI925T configuration. */
1582 env
->cp15
.c15_ticonfig
= val
& 0xe7;
1583 env
->cp15
.c0_cpuid
= (val
& (1 << 5)) ? /* OS_TYPE bit */
1584 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1586 case 2: /* Set I_max. */
1587 env
->cp15
.c15_i_max
= val
;
1589 case 3: /* Set I_min. */
1590 env
->cp15
.c15_i_min
= val
;
1592 case 4: /* Set thread-ID. */
1593 env
->cp15
.c15_threadid
= val
& 0xffff;
1595 case 8: /* Wait-for-interrupt (deprecated). */
1596 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
1606 /* ??? For debugging only. Should raise illegal instruction exception. */
1607 cpu_abort(env
, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1608 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1611 uint32_t HELPER(get_cp15
)(CPUState
*env
, uint32_t insn
)
1617 op1
= (insn
>> 21) & 7;
1618 op2
= (insn
>> 5) & 7;
1620 switch ((insn
>> 16) & 0xf) {
1621 case 0: /* ID codes. */
1627 case 0: /* Device ID. */
1628 return env
->cp15
.c0_cpuid
;
1629 case 1: /* Cache Type. */
1630 return env
->cp15
.c0_cachetype
;
1631 case 2: /* TCM status. */
1633 case 3: /* TLB type register. */
1634 return 0; /* No lockable TLB entries. */
1635 case 5: /* CPU ID */
1636 return env
->cpu_index
;
1641 if (!arm_feature(env
, ARM_FEATURE_V6
))
1643 return env
->cp15
.c0_c1
[op2
];
1645 if (!arm_feature(env
, ARM_FEATURE_V6
))
1647 return env
->cp15
.c0_c2
[op2
];
1648 case 3: case 4: case 5: case 6: case 7:
1654 /* These registers aren't documented on arm11 cores. However
1655 Linux looks at them anyway. */
1656 if (!arm_feature(env
, ARM_FEATURE_V6
))
1660 if (!arm_feature(env
, ARM_FEATURE_V7
))
1665 return env
->cp15
.c0_ccsid
[env
->cp15
.c0_cssel
];
1667 return env
->cp15
.c0_clid
;
1673 if (op2
!= 0 || crm
!= 0)
1675 return env
->cp15
.c0_cssel
;
1679 case 1: /* System configuration. */
1680 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1683 case 0: /* Control register. */
1684 return env
->cp15
.c1_sys
;
1685 case 1: /* Auxiliary control register. */
1686 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1687 return env
->cp15
.c1_xscaleauxcr
;
1688 if (!arm_feature(env
, ARM_FEATURE_AUXCR
))
1690 switch (ARM_CPUID(env
)) {
1691 case ARM_CPUID_ARM1026
:
1693 case ARM_CPUID_ARM1136
:
1694 case ARM_CPUID_ARM1136_R2
:
1696 case ARM_CPUID_ARM11MPCORE
:
1698 case ARM_CPUID_CORTEXA8
:
1703 case 2: /* Coprocessor access register. */
1704 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
1706 return env
->cp15
.c1_coproc
;
1710 case 2: /* MMU Page table control / MPU cache control. */
1711 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1714 return env
->cp15
.c2_data
;
1717 return env
->cp15
.c2_insn
;
1725 return env
->cp15
.c2_base0
;
1727 return env
->cp15
.c2_base1
;
1729 return env
->cp15
.c2_control
;
1734 case 3: /* MMU Domain access control / MPU write buffer control. */
1735 return env
->cp15
.c3
;
1736 case 4: /* Reserved. */
1738 case 5: /* MMU Fault status / MPU access permission. */
1739 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1743 if (arm_feature(env
, ARM_FEATURE_MPU
))
1744 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1745 return env
->cp15
.c5_data
;
1747 if (arm_feature(env
, ARM_FEATURE_MPU
))
1748 return simple_mpu_ap_bits(env
->cp15
.c5_data
);
1749 return env
->cp15
.c5_insn
;
1751 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1753 return env
->cp15
.c5_data
;
1755 if (!arm_feature(env
, ARM_FEATURE_MPU
))
1757 return env
->cp15
.c5_insn
;
1761 case 6: /* MMU Fault address. */
1762 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1765 return env
->cp15
.c6_region
[crm
];
1767 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1771 return env
->cp15
.c6_data
;
1773 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1774 /* Watchpoint Fault Adrress. */
1775 return 0; /* Not implemented. */
1777 /* Instruction Fault Adrress. */
1778 /* Arm9 doesn't have an IFAR, but implementing it anyway
1779 shouldn't do any harm. */
1780 return env
->cp15
.c6_insn
;
1783 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1784 /* Instruction Fault Adrress. */
1785 return env
->cp15
.c6_insn
;
1793 case 7: /* Cache control. */
1794 /* FIXME: Should only clear Z flag if destination is r15. */
1797 case 8: /* MMU TLB control. */
1799 case 9: /* Cache lockdown. */
1801 case 0: /* L1 cache. */
1802 if (arm_feature(env
, ARM_FEATURE_OMAPCP
))
1806 return env
->cp15
.c9_data
;
1808 return env
->cp15
.c9_insn
;
1812 case 1: /* L2 cache */
1815 /* L2 Lockdown and Auxiliary control. */
1820 case 10: /* MMU TLB lockdown. */
1821 /* ??? TLB lockdown not implemented. */
1823 case 11: /* TCM DMA control. */
1824 case 12: /* Reserved. */
1826 case 13: /* Process ID. */
1829 return env
->cp15
.c13_fcse
;
1831 return env
->cp15
.c13_context
;
1833 return env
->cp15
.c13_tls1
;
1835 return env
->cp15
.c13_tls2
;
1837 return env
->cp15
.c13_tls3
;
1841 case 14: /* Reserved. */
1843 case 15: /* Implementation specific. */
1844 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1845 if (op2
== 0 && crm
== 1)
1846 return env
->cp15
.c15_cpar
;
1850 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1854 case 1: /* Read TI925T configuration. */
1855 return env
->cp15
.c15_ticonfig
;
1856 case 2: /* Read I_max. */
1857 return env
->cp15
.c15_i_max
;
1858 case 3: /* Read I_min. */
1859 return env
->cp15
.c15_i_min
;
1860 case 4: /* Read thread-ID. */
1861 return env
->cp15
.c15_threadid
;
1862 case 8: /* TI925T_status */
1865 /* TODO: Peripheral port remap register:
1866 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1867 * controller base address at $rn & ~0xfff and map size of
1868 * 0x200 << ($rn & 0xfff), when MMU is off. */
1874 /* ??? For debugging only. Should raise illegal instruction exception. */
1875 cpu_abort(env
, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1876 (insn
>> 16) & 0xf, crm
, op1
, op2
);
1880 void HELPER(set_r13_banked
)(CPUState
*env
, uint32_t mode
, uint32_t val
)
1882 env
->banked_r13
[bank_number(mode
)] = val
;
1885 uint32_t HELPER(get_r13_banked
)(CPUState
*env
, uint32_t mode
)
1887 return env
->banked_r13
[bank_number(mode
)];
1890 uint32_t HELPER(v7m_mrs
)(CPUState
*env
, uint32_t reg
)
1894 return xpsr_read(env
) & 0xf8000000;
1896 return xpsr_read(env
) & 0xf80001ff;
1898 return xpsr_read(env
) & 0xff00fc00;
1900 return xpsr_read(env
) & 0xff00fdff;
1902 return xpsr_read(env
) & 0x000001ff;
1904 return xpsr_read(env
) & 0x0700fc00;
1906 return xpsr_read(env
) & 0x0700edff;
1908 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
1910 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
1911 case 16: /* PRIMASK */
1912 return (env
->uncached_cpsr
& CPSR_I
) != 0;
1913 case 17: /* FAULTMASK */
1914 return (env
->uncached_cpsr
& CPSR_F
) != 0;
1915 case 18: /* BASEPRI */
1916 case 19: /* BASEPRI_MAX */
1917 return env
->v7m
.basepri
;
1918 case 20: /* CONTROL */
1919 return env
->v7m
.control
;
1921 /* ??? For debugging only. */
1922 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
1927 void HELPER(v7m_msr
)(CPUState
*env
, uint32_t reg
, uint32_t val
)
1931 xpsr_write(env
, val
, 0xf8000000);
1934 xpsr_write(env
, val
, 0xf8000000);
1937 xpsr_write(env
, val
, 0xfe00fc00);
1940 xpsr_write(env
, val
, 0xfe00fc00);
1943 /* IPSR bits are readonly. */
1946 xpsr_write(env
, val
, 0x0600fc00);
1949 xpsr_write(env
, val
, 0x0600fc00);
1952 if (env
->v7m
.current_sp
)
1953 env
->v7m
.other_sp
= val
;
1955 env
->regs
[13] = val
;
1958 if (env
->v7m
.current_sp
)
1959 env
->regs
[13] = val
;
1961 env
->v7m
.other_sp
= val
;
1963 case 16: /* PRIMASK */
1965 env
->uncached_cpsr
|= CPSR_I
;
1967 env
->uncached_cpsr
&= ~CPSR_I
;
1969 case 17: /* FAULTMASK */
1971 env
->uncached_cpsr
|= CPSR_F
;
1973 env
->uncached_cpsr
&= ~CPSR_F
;
1975 case 18: /* BASEPRI */
1976 env
->v7m
.basepri
= val
& 0xff;
1978 case 19: /* BASEPRI_MAX */
1980 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
1981 env
->v7m
.basepri
= val
;
1983 case 20: /* CONTROL */
1984 env
->v7m
.control
= val
& 3;
1985 switch_v7m_sp(env
, (val
& 2) != 0);
1988 /* ??? For debugging only. */
1989 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
1994 void cpu_arm_set_cp_io(CPUARMState
*env
, int cpnum
,
1995 ARMReadCPFunc
*cp_read
, ARMWriteCPFunc
*cp_write
,
1998 if (cpnum
< 0 || cpnum
> 14) {
1999 cpu_abort(env
, "Bad coprocessor number: %i\n", cpnum
);
2003 env
->cp
[cpnum
].cp_read
= cp_read
;
2004 env
->cp
[cpnum
].cp_write
= cp_write
;
2005 env
->cp
[cpnum
].opaque
= opaque
;
2010 /* Note that signed overflow is undefined in C. The following routines are
2011 careful to use unsigned types where modulo arithmetic is required.
2012 Failure to do so _will_ break on newer gcc. */
2014 /* Signed saturating arithmetic. */
2016 /* Perform 16-bit signed saturating addition. */
2017 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2022 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2031 /* Perform 8-bit signed saturating addition. */
2032 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2037 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2046 /* Perform 16-bit signed saturating subtraction. */
2047 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2052 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2061 /* Perform 8-bit signed saturating subtraction. */
2062 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2067 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2076 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2077 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2078 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2079 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2082 #include "op_addsub.h"
2084 /* Unsigned saturating arithmetic. */
2085 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2094 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2102 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2111 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2119 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2120 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2121 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2122 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2125 #include "op_addsub.h"
2127 /* Signed modulo arithmetic. */
2128 #define SARITH16(a, b, n, op) do { \
2130 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2131 RESULT(sum, n, 16); \
2133 ge |= 3 << (n * 2); \
2136 #define SARITH8(a, b, n, op) do { \
2138 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2139 RESULT(sum, n, 8); \
2145 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2146 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2147 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2148 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2152 #include "op_addsub.h"
2154 /* Unsigned modulo arithmetic. */
2155 #define ADD16(a, b, n) do { \
2157 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2158 RESULT(sum, n, 16); \
2159 if ((sum >> 16) == 1) \
2160 ge |= 3 << (n * 2); \
2163 #define ADD8(a, b, n) do { \
2165 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2166 RESULT(sum, n, 8); \
2167 if ((sum >> 8) == 1) \
2171 #define SUB16(a, b, n) do { \
2173 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2174 RESULT(sum, n, 16); \
2175 if ((sum >> 16) == 0) \
2176 ge |= 3 << (n * 2); \
2179 #define SUB8(a, b, n) do { \
2181 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2182 RESULT(sum, n, 8); \
2183 if ((sum >> 8) == 0) \
2190 #include "op_addsub.h"
2192 /* Halved signed arithmetic. */
2193 #define ADD16(a, b, n) \
2194 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2195 #define SUB16(a, b, n) \
2196 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2197 #define ADD8(a, b, n) \
2198 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2199 #define SUB8(a, b, n) \
2200 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2203 #include "op_addsub.h"
2205 /* Halved unsigned arithmetic. */
2206 #define ADD16(a, b, n) \
2207 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2208 #define SUB16(a, b, n) \
2209 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2210 #define ADD8(a, b, n) \
2211 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2212 #define SUB8(a, b, n) \
2213 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2216 #include "op_addsub.h"
2218 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2226 /* Unsigned sum of absolute byte differences. */
2227 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2230 sum
= do_usad(a
, b
);
2231 sum
+= do_usad(a
>> 8, b
>> 8);
2232 sum
+= do_usad(a
>> 16, b
>>16);
2233 sum
+= do_usad(a
>> 24, b
>> 24);
2237 /* For ARMv6 SEL instruction. */
2238 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2251 return (a
& mask
) | (b
& ~mask
);
2254 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2256 return (val
>> 32) | (val
!= 0);
2259 /* VFP support. We follow the convention used for VFP instrunctions:
2260 Single precition routines have a "s" suffix, double precision a
2263 /* Convert host exception flags to vfp form. */
2264 static inline int vfp_exceptbits_from_host(int host_bits
)
2266 int target_bits
= 0;
2268 if (host_bits
& float_flag_invalid
)
2270 if (host_bits
& float_flag_divbyzero
)
2272 if (host_bits
& float_flag_overflow
)
2274 if (host_bits
& float_flag_underflow
)
2276 if (host_bits
& float_flag_inexact
)
2277 target_bits
|= 0x10;
2281 uint32_t HELPER(vfp_get_fpscr
)(CPUState
*env
)
2286 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2287 | (env
->vfp
.vec_len
<< 16)
2288 | (env
->vfp
.vec_stride
<< 20);
2289 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2290 fpscr
|= vfp_exceptbits_from_host(i
);
2294 /* Convert vfp exception flags to target form. */
2295 static inline int vfp_exceptbits_to_host(int target_bits
)
2299 if (target_bits
& 1)
2300 host_bits
|= float_flag_invalid
;
2301 if (target_bits
& 2)
2302 host_bits
|= float_flag_divbyzero
;
2303 if (target_bits
& 4)
2304 host_bits
|= float_flag_overflow
;
2305 if (target_bits
& 8)
2306 host_bits
|= float_flag_underflow
;
2307 if (target_bits
& 0x10)
2308 host_bits
|= float_flag_inexact
;
2312 void HELPER(vfp_set_fpscr
)(CPUState
*env
, uint32_t val
)
2317 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2318 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2319 env
->vfp
.vec_len
= (val
>> 16) & 7;
2320 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2323 if (changed
& (3 << 22)) {
2324 i
= (val
>> 22) & 3;
2327 i
= float_round_nearest_even
;
2333 i
= float_round_down
;
2336 i
= float_round_to_zero
;
2339 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2341 if (changed
& (1 << 24))
2342 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
2343 if (changed
& (1 << 25))
2344 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
2346 i
= vfp_exceptbits_to_host((val
>> 8) & 0x1f);
2347 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
2350 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2352 #define VFP_BINOP(name) \
2353 float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2355 return float32_ ## name (a, b, &env->vfp.fp_status); \
2357 float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2359 return float64_ ## name (a, b, &env->vfp.fp_status); \
2367 float32
VFP_HELPER(neg
, s
)(float32 a
)
2369 return float32_chs(a
);
2372 float64
VFP_HELPER(neg
, d
)(float64 a
)
2374 return float64_chs(a
);
2377 float32
VFP_HELPER(abs
, s
)(float32 a
)
2379 return float32_abs(a
);
2382 float64
VFP_HELPER(abs
, d
)(float64 a
)
2384 return float64_abs(a
);
2387 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUState
*env
)
2389 return float32_sqrt(a
, &env
->vfp
.fp_status
);
2392 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUState
*env
)
2394 return float64_sqrt(a
, &env
->vfp
.fp_status
);
2397 /* XXX: check quiet/signaling case */
2398 #define DO_VFP_cmp(p, type) \
2399 void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2402 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2403 case 0: flags = 0x6; break; \
2404 case -1: flags = 0x8; break; \
2405 case 1: flags = 0x2; break; \
2406 default: case 2: flags = 0x3; break; \
2408 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2409 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2411 void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2414 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2415 case 0: flags = 0x6; break; \
2416 case -1: flags = 0x8; break; \
2417 case 1: flags = 0x2; break; \
2418 default: case 2: flags = 0x3; break; \
2420 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2421 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2423 DO_VFP_cmp(s
, float32
)
2424 DO_VFP_cmp(d
, float64
)
2427 /* Helper routines to perform bitwise copies between float and int. */
2428 static inline float32
vfp_itos(uint32_t i
)
2439 static inline uint32_t vfp_stoi(float32 s
)
2450 static inline float64
vfp_itod(uint64_t i
)
2461 static inline uint64_t vfp_dtoi(float64 d
)
2472 /* Integer to float conversion. */
2473 float32
VFP_HELPER(uito
, s
)(float32 x
, CPUState
*env
)
2475 return uint32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2478 float64
VFP_HELPER(uito
, d
)(float32 x
, CPUState
*env
)
2480 return uint32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2483 float32
VFP_HELPER(sito
, s
)(float32 x
, CPUState
*env
)
2485 return int32_to_float32(vfp_stoi(x
), &env
->vfp
.fp_status
);
2488 float64
VFP_HELPER(sito
, d
)(float32 x
, CPUState
*env
)
2490 return int32_to_float64(vfp_stoi(x
), &env
->vfp
.fp_status
);
2493 /* Float to integer conversion. */
2494 float32
VFP_HELPER(toui
, s
)(float32 x
, CPUState
*env
)
2496 return vfp_itos(float32_to_uint32(x
, &env
->vfp
.fp_status
));
2499 float32
VFP_HELPER(toui
, d
)(float64 x
, CPUState
*env
)
2501 return vfp_itos(float64_to_uint32(x
, &env
->vfp
.fp_status
));
2504 float32
VFP_HELPER(tosi
, s
)(float32 x
, CPUState
*env
)
2506 return vfp_itos(float32_to_int32(x
, &env
->vfp
.fp_status
));
2509 float32
VFP_HELPER(tosi
, d
)(float64 x
, CPUState
*env
)
2511 return vfp_itos(float64_to_int32(x
, &env
->vfp
.fp_status
));
2514 float32
VFP_HELPER(touiz
, s
)(float32 x
, CPUState
*env
)
2516 return vfp_itos(float32_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2519 float32
VFP_HELPER(touiz
, d
)(float64 x
, CPUState
*env
)
2521 return vfp_itos(float64_to_uint32_round_to_zero(x
, &env
->vfp
.fp_status
));
2524 float32
VFP_HELPER(tosiz
, s
)(float32 x
, CPUState
*env
)
2526 return vfp_itos(float32_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2529 float32
VFP_HELPER(tosiz
, d
)(float64 x
, CPUState
*env
)
2531 return vfp_itos(float64_to_int32_round_to_zero(x
, &env
->vfp
.fp_status
));
2534 /* floating point conversion */
2535 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUState
*env
)
2537 return float32_to_float64(x
, &env
->vfp
.fp_status
);
2540 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUState
*env
)
2542 return float64_to_float32(x
, &env
->vfp
.fp_status
);
2545 /* VFP3 fixed point conversion. */
2546 #define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2547 ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2550 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2551 &env->vfp.fp_status); \
2552 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
2554 ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2557 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2558 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2559 &env->vfp.fp_status)); \
2562 VFP_CONV_FIX(sh
, d
, float64
, int16
, )
2563 VFP_CONV_FIX(sl
, d
, float64
, int32
, )
2564 VFP_CONV_FIX(uh
, d
, float64
, uint16
, u
)
2565 VFP_CONV_FIX(ul
, d
, float64
, uint32
, u
)
2566 VFP_CONV_FIX(sh
, s
, float32
, int16
, )
2567 VFP_CONV_FIX(sl
, s
, float32
, int32
, )
2568 VFP_CONV_FIX(uh
, s
, float32
, uint16
, u
)
2569 VFP_CONV_FIX(ul
, s
, float32
, uint32
, u
)
2572 /* Half precision conversions. */
2573 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUState
*env
)
2575 float_status
*s
= &env
->vfp
.fp_status
;
2576 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2577 return float16_to_float32(a
, ieee
, s
);
2580 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUState
*env
)
2582 float_status
*s
= &env
->vfp
.fp_status
;
2583 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
2584 return float32_to_float16(a
, ieee
, s
);
2587 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUState
*env
)
2589 float_status
*s
= &env
->vfp
.fp_status
;
2590 float32 two
= int32_to_float32(2, s
);
2591 return float32_sub(two
, float32_mul(a
, b
, s
), s
);
2594 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUState
*env
)
2596 float_status
*s
= &env
->vfp
.fp_status
;
2597 float32 three
= int32_to_float32(3, s
);
2598 return float32_sub(three
, float32_mul(a
, b
, s
), s
);
2603 /* TODO: The architecture specifies the value that the estimate functions
2604 should return. We return the exact reciprocal/root instead. */
2605 float32
HELPER(recpe_f32
)(float32 a
, CPUState
*env
)
2607 float_status
*s
= &env
->vfp
.fp_status
;
2608 float32 one
= int32_to_float32(1, s
);
2609 return float32_div(one
, a
, s
);
2612 float32
HELPER(rsqrte_f32
)(float32 a
, CPUState
*env
)
2614 float_status
*s
= &env
->vfp
.fp_status
;
2615 float32 one
= int32_to_float32(1, s
);
2616 return float32_div(one
, float32_sqrt(a
, s
), s
);
2619 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUState
*env
)
2621 float_status
*s
= &env
->vfp
.fp_status
;
2623 tmp
= int32_to_float32(a
, s
);
2624 tmp
= float32_scalbn(tmp
, -32, s
);
2625 tmp
= helper_recpe_f32(tmp
, env
);
2626 tmp
= float32_scalbn(tmp
, 31, s
);
2627 return float32_to_int32(tmp
, s
);
2630 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUState
*env
)
2632 float_status
*s
= &env
->vfp
.fp_status
;
2634 tmp
= int32_to_float32(a
, s
);
2635 tmp
= float32_scalbn(tmp
, -32, s
);
2636 tmp
= helper_rsqrte_f32(tmp
, env
);
2637 tmp
= float32_scalbn(tmp
, 31, s
);
2638 return float32_to_int32(tmp
, s
);
2641 void HELPER(set_teecr
)(CPUState
*env
, uint32_t val
)
2644 if (env
->teecr
!= val
) {