2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * The condition code translation is in need of attention.
39 #include "crisv32-decode.h"
40 #include "qemu-common.h"
50 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51 #define BUG_ON(x) ({if (x) BUG();})
55 /* Used by the decoder. */
56 #define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
59 #define CC_MASK_NZ 0xc
60 #define CC_MASK_NZV 0xe
61 #define CC_MASK_NZVC 0xf
62 #define CC_MASK_RNZV 0x10e
78 /* This is the state at translation time. */
79 typedef struct DisasContext
{
88 unsigned int zsize
, zzsize
;
96 int flags_live
; /* Wether or not $ccs is uptodate. */
97 int flagx_live
; /* Wether or not flags_x has the x flag known at
100 int clear_x
; /* Clear x after this insn? */
102 int user
; /* user or kernel mode. */
107 struct TranslationBlock
*tb
;
108 int singlestep_enabled
;
111 static void gen_BUG(DisasContext
*dc
, char *file
, int line
)
113 printf ("BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
114 fprintf (logfile
, "BUG: pc=%x %s %d\n", dc
->pc
, file
, line
);
115 cpu_abort(dc
->env
, "%s:%d\n", file
, line
);
118 const char *regnames
[] =
120 "$r0", "$r1", "$r2", "$r3",
121 "$r4", "$r5", "$r6", "$r7",
122 "$r8", "$r9", "$r10", "$r11",
123 "$r12", "$r13", "$sp", "$acr",
125 const char *pregnames
[] =
127 "$bz", "$vr", "$pid", "$srs",
128 "$wz", "$exs", "$eda", "$mof",
129 "$dz", "$ebp", "$erp", "$srp",
130 "$nrp", "$ccs", "$usp", "$spc",
133 /* We need this table to handle preg-moves with implicit width. */
145 #define t_gen_mov_TN_env(tn, member) \
146 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
147 #define t_gen_mov_env_TN(member, tn) \
148 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
150 static inline void t_gen_mov_TN_reg(TCGv tn
, int r
)
153 fprintf(stderr
, "wrong register read $r%d\n", r
);
154 tcg_gen_mov_tl(tn
, cpu_R
[r
]);
156 static inline void t_gen_mov_reg_TN(int r
, TCGv tn
)
159 fprintf(stderr
, "wrong register write $r%d\n", r
);
160 tcg_gen_mov_tl(cpu_R
[r
], tn
);
163 static inline void _t_gen_mov_TN_env(TCGv tn
, int offset
)
165 if (offset
> sizeof (CPUState
))
166 fprintf(stderr
, "wrong load from env from off=%d\n", offset
);
167 tcg_gen_ld_tl(tn
, cpu_env
, offset
);
169 static inline void _t_gen_mov_env_TN(int offset
, TCGv tn
)
171 if (offset
> sizeof (CPUState
))
172 fprintf(stderr
, "wrong store to env at off=%d\n", offset
);
173 tcg_gen_st_tl(tn
, cpu_env
, offset
);
176 static inline void t_gen_mov_TN_preg(TCGv tn
, int r
)
179 fprintf(stderr
, "wrong register read $p%d\n", r
);
180 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
)
181 tcg_gen_mov_tl(tn
, tcg_const_tl(0));
183 tcg_gen_mov_tl(tn
, tcg_const_tl(32));
184 else if (r
== PR_EXS
) {
185 printf("read from EXS!\n");
186 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
188 else if (r
== PR_EDA
) {
189 printf("read from EDA!\n");
190 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
193 tcg_gen_mov_tl(tn
, cpu_PR
[r
]);
195 static inline void t_gen_mov_preg_TN(DisasContext
*dc
, int r
, TCGv tn
)
198 fprintf(stderr
, "wrong register write $p%d\n", r
);
199 if (r
== PR_BZ
|| r
== PR_WZ
|| r
== PR_DZ
)
201 else if (r
== PR_SRS
)
202 tcg_gen_andi_tl(cpu_PR
[r
], tn
, 3);
204 tcg_gen_mov_tl(cpu_PR
[r
], tn
);
206 tcg_gen_helper_0_1(helper_tlb_flush_pid
, tn
);
210 static inline void t_gen_raise_exception(uint32_t index
)
212 tcg_gen_helper_0_1(helper_raise_exception
, tcg_const_tl(index
));
215 static void t_gen_lsl(TCGv d
, TCGv a
, TCGv b
)
219 l1
= gen_new_label();
220 /* Speculative shift. */
221 tcg_gen_shl_tl(d
, a
, b
);
222 tcg_gen_brcond_tl(TCG_COND_LEU
, b
, tcg_const_tl(31), l1
);
223 /* Clear dst if shift operands were to large. */
224 tcg_gen_movi_tl(d
, 0);
228 static void t_gen_lsr(TCGv d
, TCGv a
, TCGv b
)
232 l1
= gen_new_label();
233 /* Speculative shift. */
234 tcg_gen_shr_tl(d
, a
, b
);
235 tcg_gen_brcond_tl(TCG_COND_LEU
, b
, tcg_const_tl(31), l1
);
236 /* Clear dst if shift operands were to large. */
237 tcg_gen_movi_tl(d
, 0);
241 static void t_gen_asr(TCGv d
, TCGv a
, TCGv b
)
245 l1
= gen_new_label();
246 /* Speculative shift. */
247 tcg_gen_sar_tl(d
, a
, b
);
248 tcg_gen_brcond_tl(TCG_COND_LEU
, b
, tcg_const_tl(31), l1
);
249 /* Clear dst if shift operands were to large. */
250 tcg_gen_sar_tl(d
, a
, tcg_const_tl(30));
254 /* 64-bit signed mul, lower result in d and upper in d2. */
255 static void t_gen_muls(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
259 t0
= tcg_temp_new(TCG_TYPE_I64
);
260 t1
= tcg_temp_new(TCG_TYPE_I64
);
262 tcg_gen_ext32s_i64(t0
, a
);
263 tcg_gen_ext32s_i64(t1
, b
);
264 tcg_gen_mul_i64(t0
, t0
, t1
);
266 tcg_gen_trunc_i64_i32(d
, t0
);
267 tcg_gen_shri_i64(t0
, t0
, 32);
268 tcg_gen_trunc_i64_i32(d2
, t0
);
270 tcg_gen_discard_i64(t0
);
271 tcg_gen_discard_i64(t1
);
274 /* 64-bit unsigned muls, lower result in d and upper in d2. */
275 static void t_gen_mulu(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
279 t0
= tcg_temp_new(TCG_TYPE_I64
);
280 t1
= tcg_temp_new(TCG_TYPE_I64
);
282 tcg_gen_extu_i32_i64(t0
, a
);
283 tcg_gen_extu_i32_i64(t1
, b
);
284 tcg_gen_mul_i64(t0
, t0
, t1
);
286 tcg_gen_trunc_i64_i32(d
, t0
);
287 tcg_gen_shri_i64(t0
, t0
, 32);
288 tcg_gen_trunc_i64_i32(d2
, t0
);
290 tcg_gen_discard_i64(t0
);
291 tcg_gen_discard_i64(t1
);
294 /* 32bit branch-free binary search for counting leading zeros. */
295 static void t_gen_lz_i32(TCGv d
, TCGv x
)
299 y
= tcg_temp_new(TCG_TYPE_I32
);
300 m
= tcg_temp_new(TCG_TYPE_I32
);
301 n
= tcg_temp_new(TCG_TYPE_I32
);
304 tcg_gen_shri_i32(y
, x
, 16);
305 tcg_gen_neg_i32(y
, y
);
307 /* m = (y >> 16) & 16 */
308 tcg_gen_sari_i32(m
, y
, 16);
309 tcg_gen_andi_i32(m
, m
, 16);
312 tcg_gen_sub_i32(n
, tcg_const_i32(16), m
);
314 tcg_gen_shr_i32(x
, x
, m
);
317 tcg_gen_subi_i32(y
, x
, 0x100);
318 /* m = (y >> 16) & 8 */
319 tcg_gen_sari_i32(m
, y
, 16);
320 tcg_gen_andi_i32(m
, m
, 8);
322 tcg_gen_add_i32(n
, n
, m
);
324 tcg_gen_shl_i32(x
, x
, m
);
327 tcg_gen_subi_i32(y
, x
, 0x1000);
328 /* m = (y >> 16) & 4 */
329 tcg_gen_sari_i32(m
, y
, 16);
330 tcg_gen_andi_i32(m
, m
, 4);
332 tcg_gen_add_i32(n
, n
, m
);
334 tcg_gen_shl_i32(x
, x
, m
);
337 tcg_gen_subi_i32(y
, x
, 0x4000);
338 /* m = (y >> 16) & 2 */
339 tcg_gen_sari_i32(m
, y
, 16);
340 tcg_gen_andi_i32(m
, m
, 2);
342 tcg_gen_add_i32(n
, n
, m
);
344 tcg_gen_shl_i32(x
, x
, m
);
347 tcg_gen_shri_i32(y
, x
, 14);
348 /* m = y & ~(y >> 1) */
349 tcg_gen_sari_i32(m
, y
, 1);
350 tcg_gen_not_i32(m
, m
);
351 tcg_gen_and_i32(m
, m
, y
);
354 tcg_gen_addi_i32(d
, n
, 2);
355 tcg_gen_sub_i32(d
, d
, m
);
357 tcg_gen_discard_i32(y
);
358 tcg_gen_discard_i32(m
);
359 tcg_gen_discard_i32(n
);
362 static void t_gen_btst(TCGv d
, TCGv s
)
369 The N flag is set according to the selected bit in the dest reg.
370 The Z flag is set if the selected bit and all bits to the right are
372 The X flag is cleared.
373 Other flags are left untouched.
374 The destination reg is not affected.
376 unsigned int fz, sbit, bset, mask, masked_t0;
379 bset = !!(T0 & (1 << sbit));
380 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
381 masked_t0 = T0 & mask;
382 fz = !(masked_t0 | bset);
384 // Clear the X, N and Z flags.
385 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
386 // Set the N and Z flags accordingly.
387 T0 |= (bset << 3) | (fz << 2);
390 l1
= gen_new_label();
391 sbit
= tcg_temp_new(TCG_TYPE_TL
);
392 bset
= tcg_temp_new(TCG_TYPE_TL
);
394 /* Compute bset and sbit. */
395 tcg_gen_andi_tl(sbit
, s
, 31);
396 tcg_gen_shl_tl(s
, tcg_const_tl(1), sbit
);
397 tcg_gen_and_tl(bset
, d
, s
);
398 tcg_gen_shr_tl(bset
, bset
, sbit
);
399 /* Displace to N_FLAG. */
400 tcg_gen_shli_tl(bset
, bset
, 3);
402 tcg_gen_shl_tl(sbit
, tcg_const_tl(2), sbit
);
403 tcg_gen_subi_tl(sbit
, sbit
, 1);
404 tcg_gen_and_tl(sbit
, d
, sbit
);
406 tcg_gen_andi_tl(d
, cpu_PR
[PR_CCS
], ~(X_FLAG
| N_FLAG
| Z_FLAG
));
407 /* or in the N_FLAG. */
408 tcg_gen_or_tl(d
, d
, bset
);
409 tcg_gen_brcond_tl(TCG_COND_NE
, sbit
, tcg_const_tl(0), l1
);
410 /* or in the Z_FLAG. */
411 tcg_gen_ori_tl(d
, d
, Z_FLAG
);
414 tcg_gen_discard_tl(sbit
);
415 tcg_gen_discard_tl(bset
);
418 static void t_gen_cris_dstep(TCGv d
, TCGv s
)
422 l1
= gen_new_label();
429 tcg_gen_shli_tl(d
, d
, 1);
430 tcg_gen_brcond_tl(TCG_COND_LTU
, d
, s
, l1
);
431 tcg_gen_sub_tl(d
, d
, s
);
435 /* Extended arithmetics on CRIS. */
436 static inline void t_gen_add_flag(TCGv d
, int flag
)
440 c
= tcg_temp_new(TCG_TYPE_TL
);
441 t_gen_mov_TN_preg(c
, PR_CCS
);
442 /* Propagate carry into d. */
443 tcg_gen_andi_tl(c
, c
, 1 << flag
);
445 tcg_gen_shri_tl(c
, c
, flag
);
446 tcg_gen_add_tl(d
, d
, c
);
447 tcg_gen_discard_tl(c
);
450 static inline void t_gen_addx_carry(TCGv d
)
454 x
= tcg_temp_new(TCG_TYPE_TL
);
455 c
= tcg_temp_new(TCG_TYPE_TL
);
456 t_gen_mov_TN_preg(x
, PR_CCS
);
457 tcg_gen_mov_tl(c
, x
);
459 /* Propagate carry into d if X is set. Branch free. */
460 tcg_gen_andi_tl(c
, c
, C_FLAG
);
461 tcg_gen_andi_tl(x
, x
, X_FLAG
);
462 tcg_gen_shri_tl(x
, x
, 4);
464 tcg_gen_and_tl(x
, x
, c
);
465 tcg_gen_add_tl(d
, d
, x
);
466 tcg_gen_discard_tl(x
);
467 tcg_gen_discard_tl(c
);
470 static inline void t_gen_subx_carry(DisasContext
*dc
, TCGv d
)
472 if (dc
->flagx_live
) {
475 x
= tcg_temp_new(TCG_TYPE_TL
);
476 c
= tcg_temp_new(TCG_TYPE_TL
);
477 t_gen_mov_TN_preg(x
, PR_CCS
);
478 tcg_gen_mov_tl(c
, x
);
480 /* Propagate carry into d if X is set. Branch free. */
481 tcg_gen_andi_tl(c
, c
, C_FLAG
);
482 tcg_gen_andi_tl(x
, x
, X_FLAG
);
483 tcg_gen_shri_tl(x
, x
, 4);
485 tcg_gen_and_tl(x
, x
, c
);
486 tcg_gen_sub_tl(d
, d
, x
);
487 tcg_gen_discard_tl(x
);
488 tcg_gen_discard_tl(c
);
493 c
= tcg_temp_new(TCG_TYPE_TL
);
494 /* C flag is already at bit 0. */
495 tcg_gen_andi_tl(c
, c
, C_FLAG
);
496 tcg_gen_add_tl(d
, d
, c
);
497 tcg_gen_discard_tl(c
);
502 /* Swap the two bytes within each half word of the s operand.
503 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
504 static inline void t_gen_swapb(TCGv d
, TCGv s
)
508 t
= tcg_temp_new(TCG_TYPE_TL
);
509 org_s
= tcg_temp_new(TCG_TYPE_TL
);
511 /* d and s may refer to the same object. */
512 tcg_gen_mov_tl(org_s
, s
);
513 tcg_gen_shli_tl(t
, org_s
, 8);
514 tcg_gen_andi_tl(d
, t
, 0xff00ff00);
515 tcg_gen_shri_tl(t
, org_s
, 8);
516 tcg_gen_andi_tl(t
, t
, 0x00ff00ff);
517 tcg_gen_or_tl(d
, d
, t
);
518 tcg_gen_discard_tl(t
);
519 tcg_gen_discard_tl(org_s
);
522 /* Swap the halfwords of the s operand. */
523 static inline void t_gen_swapw(TCGv d
, TCGv s
)
526 /* d and s refer the same object. */
527 t
= tcg_temp_new(TCG_TYPE_TL
);
528 tcg_gen_mov_tl(t
, s
);
529 tcg_gen_shli_tl(d
, t
, 16);
530 tcg_gen_shri_tl(t
, t
, 16);
531 tcg_gen_or_tl(d
, d
, t
);
532 tcg_gen_discard_tl(t
);
535 /* Reverse the within each byte.
536 T0 = (((T0 << 7) & 0x80808080) |
537 ((T0 << 5) & 0x40404040) |
538 ((T0 << 3) & 0x20202020) |
539 ((T0 << 1) & 0x10101010) |
540 ((T0 >> 1) & 0x08080808) |
541 ((T0 >> 3) & 0x04040404) |
542 ((T0 >> 5) & 0x02020202) |
543 ((T0 >> 7) & 0x01010101));
545 static inline void t_gen_swapr(TCGv d
, TCGv s
)
548 int shift
; /* LSL when positive, LSR when negative. */
563 /* d and s refer the same object. */
564 t
= tcg_temp_new(TCG_TYPE_TL
);
565 org_s
= tcg_temp_new(TCG_TYPE_TL
);
566 tcg_gen_mov_tl(org_s
, s
);
568 tcg_gen_shli_tl(t
, org_s
, bitrev
[0].shift
);
569 tcg_gen_andi_tl(d
, t
, bitrev
[0].mask
);
570 for (i
= 1; i
< sizeof bitrev
/ sizeof bitrev
[0]; i
++) {
571 if (bitrev
[i
].shift
>= 0) {
572 tcg_gen_shli_tl(t
, org_s
, bitrev
[i
].shift
);
574 tcg_gen_shri_tl(t
, org_s
, -bitrev
[i
].shift
);
576 tcg_gen_andi_tl(t
, t
, bitrev
[i
].mask
);
577 tcg_gen_or_tl(d
, d
, t
);
579 tcg_gen_discard_tl(t
);
580 tcg_gen_discard_tl(org_s
);
583 static void t_gen_cc_jmp(TCGv pc_true
, TCGv pc_false
)
588 l1
= gen_new_label();
589 btaken
= tcg_temp_new(TCG_TYPE_TL
);
591 /* Conditional jmp. */
592 t_gen_mov_TN_env(btaken
, btaken
);
593 tcg_gen_mov_tl(env_pc
, pc_false
);
594 tcg_gen_brcond_tl(TCG_COND_EQ
, btaken
, tcg_const_tl(0), l1
);
595 tcg_gen_mov_tl(env_pc
, pc_true
);
598 tcg_gen_discard_tl(btaken
);
601 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
603 TranslationBlock
*tb
;
605 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
607 tcg_gen_movi_tl(env_pc
, dest
);
608 tcg_gen_exit_tb((long)tb
+ n
);
610 tcg_gen_mov_tl(env_pc
, cpu_T
[0]);
615 /* Sign extend at translation time. */
616 static int sign_extend(unsigned int val
, unsigned int width
)
628 static inline void cris_clear_x_flag(DisasContext
*dc
)
631 || (dc
->flagx_live
&& dc
->flags_x
)
632 || dc
->cc_op
== CC_OP_FLAGS
)
633 tcg_gen_andi_i32(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~X_FLAG
);
638 static void cris_evaluate_flags(DisasContext
*dc
)
640 if (!dc
->flags_live
) {
641 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
642 tcg_gen_movi_tl(cc_size
, dc
->cc_size
);
643 tcg_gen_movi_tl(cc_mask
, dc
->cc_mask
);
648 tcg_gen_helper_0_0(helper_evaluate_flags_mcp
);
651 tcg_gen_helper_0_0(helper_evaluate_flags_muls
);
654 tcg_gen_helper_0_0(helper_evaluate_flags_mulu
);
660 tcg_gen_helper_0_0(helper_evaluate_flags_move_4
);
663 tcg_gen_helper_0_0(helper_evaluate_flags_move_2
);
666 tcg_gen_helper_0_0(helper_evaluate_flags
);
678 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4
);
681 tcg_gen_helper_0_0(helper_evaluate_flags
);
691 static void cris_cc_mask(DisasContext
*dc
, unsigned int mask
)
695 /* Check if we need to evaluate the condition codes due to
697 ovl
= (dc
->cc_mask
^ mask
) & ~mask
;
699 /* TODO: optimize this case. It trigs all the time. */
700 cris_evaluate_flags (dc
);
711 static void cris_update_cc_op(DisasContext
*dc
, int op
, int size
)
718 /* op is the operation.
719 T0, T1 are the operands.
720 dst is the destination reg.
722 static void crisv32_alu_op(DisasContext
*dc
, int op
, int rd
, int size
)
726 cris_update_cc_op(dc
, op
, size
);
727 if (op
!= CC_OP_MOVE
)
728 tcg_gen_mov_tl(cc_dest
, cpu_T
[0]);
730 /* FIXME: This shouldn't be needed. But we don't pass the
731 tests without it. Investigate. */
732 t_gen_mov_env_TN(cc_x_live
, tcg_const_tl(dc
->flagx_live
));
733 t_gen_mov_env_TN(cc_x
, tcg_const_tl(dc
->flags_x
));
736 /* Emit the ALU insns. */
740 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
741 /* Extended arithmetics. */
742 t_gen_addx_carry(cpu_T
[0]);
745 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
746 t_gen_add_flag(cpu_T
[0], 0); /* C_FLAG. */
749 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
750 t_gen_add_flag(cpu_T
[0], 8); /* R_FLAG. */
753 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[1]);
754 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
755 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[1]);
756 /* CRIS flag evaluation needs ~src. */
757 tcg_gen_not_tl(cpu_T
[1], cpu_T
[1]);
759 /* Extended arithmetics. */
760 t_gen_subx_carry(dc
, cpu_T
[0]);
763 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
766 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
769 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
772 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
775 t_gen_lsl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
778 t_gen_lsr(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
781 t_gen_asr(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
784 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[1]);
785 /* Extended arithmetics. */
786 t_gen_subx_carry(dc
, cpu_T
[0]);
789 t_gen_lz_i32(cpu_T
[0], cpu_T
[1]);
792 t_gen_btst(cpu_T
[0], cpu_T
[1]);
798 mof
= tcg_temp_new(TCG_TYPE_TL
);
799 t_gen_muls(cpu_T
[0], mof
, cpu_T
[0], cpu_T
[1]);
800 t_gen_mov_preg_TN(dc
, PR_MOF
, mof
);
801 tcg_gen_discard_tl(mof
);
807 mof
= tcg_temp_new(TCG_TYPE_TL
);
808 t_gen_mulu(cpu_T
[0], mof
, cpu_T
[0], cpu_T
[1]);
809 t_gen_mov_preg_TN(dc
, PR_MOF
, mof
);
810 tcg_gen_discard_tl(mof
);
814 t_gen_cris_dstep(cpu_T
[0], cpu_T
[1]);
819 l1
= gen_new_label();
820 tcg_gen_brcond_tl(TCG_COND_LEU
,
821 cpu_T
[0], cpu_T
[1], l1
);
822 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
827 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
828 /* CRIS flag evaluation needs ~src. */
829 tcg_gen_not_tl(cpu_T
[1], cpu_T
[1]);
831 /* Extended arithmetics. */
832 t_gen_subx_carry(dc
, cpu_T
[0]);
836 fprintf (logfile
, "illegal ALU op.\n");
842 tcg_gen_mov_tl(cc_src
, cpu_T
[1]);
845 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
847 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
852 tcg_gen_mov_tl(cpu_R
[rd
], cpu_T
[0]);
855 tcg_gen_andi_tl(cpu_R
[rd
], cpu_R
[rd
], ~0xff);
857 tcg_gen_andi_tl(cpu_R
[rd
], cpu_R
[rd
], ~0xffff);
858 tcg_gen_or_tl(cpu_R
[rd
], cpu_R
[rd
], cpu_T
[0]);
862 tcg_gen_mov_tl(cc_result
, cpu_T
[0]);
865 static int arith_cc(DisasContext
*dc
)
869 case CC_OP_ADD
: return 1;
870 case CC_OP_SUB
: return 1;
871 case CC_OP_LSL
: return 1;
872 case CC_OP_LSR
: return 1;
873 case CC_OP_ASR
: return 1;
874 case CC_OP_CMP
: return 1;
882 static void gen_tst_cc (DisasContext
*dc
, int cond
)
886 /* TODO: optimize more condition codes. */
889 * If the flags are live, we've gotta look into the bits of CCS.
890 * Otherwise, if we just did an arithmetic operation we try to
891 * evaluate the condition code faster.
893 * When this function is done, T0 should be non-zero if the condition
896 arith_opt
= arith_cc(dc
) && !dc
->flags_live
;
900 /* If cc_result is zero, T0 should be
901 non-zero otherwise T0 should be zero. */
903 l1
= gen_new_label();
904 tcg_gen_movi_tl(cpu_T
[0], 0);
905 tcg_gen_brcond_tl(TCG_COND_NE
, cc_result
,
906 tcg_const_tl(0), l1
);
907 tcg_gen_movi_tl(cpu_T
[0], 1);
911 cris_evaluate_flags(dc
);
912 tcg_gen_andi_tl(cpu_T
[0],
913 cpu_PR
[PR_CCS
], Z_FLAG
);
918 tcg_gen_mov_tl(cpu_T
[0], cc_result
);
920 cris_evaluate_flags(dc
);
921 tcg_gen_xori_tl(cpu_T
[0], cpu_PR
[PR_CCS
],
923 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], Z_FLAG
);
927 cris_evaluate_flags(dc
);
928 tcg_gen_andi_tl(cpu_T
[0], cpu_PR
[PR_CCS
], C_FLAG
);
931 cris_evaluate_flags(dc
);
932 tcg_gen_xori_tl(cpu_T
[0], cpu_PR
[PR_CCS
],
934 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], C_FLAG
);
937 cris_evaluate_flags(dc
);
938 tcg_gen_andi_tl(cpu_T
[0], cpu_PR
[PR_CCS
], V_FLAG
);
941 cris_evaluate_flags(dc
);
942 tcg_gen_xori_tl(cpu_T
[0], cpu_PR
[PR_CCS
],
944 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], V_FLAG
);
948 tcg_gen_shli_tl(cpu_T
[0], cc_result
, 31);
950 cris_evaluate_flags(dc
);
951 tcg_gen_xori_tl(cpu_T
[0], cpu_PR
[PR_CCS
],
953 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], N_FLAG
);
958 tcg_gen_shli_tl(cpu_T
[0], cc_result
, 31);
959 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], 1);
962 cris_evaluate_flags(dc
);
963 tcg_gen_andi_tl(cpu_T
[0], cpu_PR
[PR_CCS
],
968 cris_evaluate_flags(dc
);
969 tcg_gen_andi_tl(cpu_T
[0], cpu_PR
[PR_CCS
],
973 cris_evaluate_flags(dc
);
977 tmp
= tcg_temp_new(TCG_TYPE_TL
);
978 tcg_gen_xori_tl(tmp
, cpu_PR
[PR_CCS
],
980 /* Overlay the C flag on top of the Z. */
981 tcg_gen_shli_tl(cpu_T
[0], tmp
, 2);
982 tcg_gen_and_tl(cpu_T
[0], tmp
, cpu_T
[0]);
983 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], Z_FLAG
);
985 tcg_gen_discard_tl(tmp
);
989 cris_evaluate_flags(dc
);
990 /* Overlay the V flag on top of the N. */
991 tcg_gen_shli_tl(cpu_T
[0], cpu_PR
[PR_CCS
], 2);
992 tcg_gen_xor_tl(cpu_T
[0],
993 cpu_PR
[PR_CCS
], cpu_T
[0]);
994 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], N_FLAG
);
995 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], N_FLAG
);
998 cris_evaluate_flags(dc
);
999 /* Overlay the V flag on top of the N. */
1000 tcg_gen_shli_tl(cpu_T
[0], cpu_PR
[PR_CCS
], 2);
1001 tcg_gen_xor_tl(cpu_T
[0],
1002 cpu_PR
[PR_CCS
], cpu_T
[0]);
1003 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], N_FLAG
);
1006 cris_evaluate_flags(dc
);
1010 n
= tcg_temp_new(TCG_TYPE_TL
);
1011 z
= tcg_temp_new(TCG_TYPE_TL
);
1013 /* To avoid a shift we overlay everything on
1015 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1016 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1018 tcg_gen_xori_tl(z
, z
, 2);
1020 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1021 tcg_gen_xori_tl(n
, n
, 2);
1022 tcg_gen_and_tl(cpu_T
[0], z
, n
);
1023 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 2);
1025 tcg_gen_discard_tl(n
);
1026 tcg_gen_discard_tl(z
);
1030 cris_evaluate_flags(dc
);
1034 n
= tcg_temp_new(TCG_TYPE_TL
);
1035 z
= tcg_temp_new(TCG_TYPE_TL
);
1037 /* To avoid a shift we overlay everything on
1039 tcg_gen_shri_tl(n
, cpu_PR
[PR_CCS
], 2);
1040 tcg_gen_shri_tl(z
, cpu_PR
[PR_CCS
], 1);
1042 tcg_gen_xor_tl(n
, n
, cpu_PR
[PR_CCS
]);
1043 tcg_gen_or_tl(cpu_T
[0], z
, n
);
1044 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 2);
1046 tcg_gen_discard_tl(n
);
1047 tcg_gen_discard_tl(z
);
1051 cris_evaluate_flags(dc
);
1052 tcg_gen_andi_tl(cpu_T
[0], cpu_PR
[PR_CCS
], P_FLAG
);
1055 tcg_gen_movi_tl(cpu_T
[0], 1);
1063 static void cris_prepare_cc_branch (DisasContext
*dc
, int offset
, int cond
)
1065 /* This helps us re-schedule the micro-code to insns in delay-slots
1066 before the actual jump. */
1067 dc
->delayed_branch
= 2;
1070 gen_tst_cc (dc
, cond
);
1071 t_gen_mov_env_TN(btaken
, cpu_T
[0]);
1073 t_gen_mov_env_TN(btaken
, tcg_const_tl(1));
1074 tcg_gen_movi_tl(env_btarget
, dc
->pc
+ offset
);
1078 /* Dynamic jumps, when the dest is in a live reg for example. */
1079 void cris_prepare_dyn_jmp (DisasContext
*dc
)
1081 /* This helps us re-schedule the micro-code to insns in delay-slots
1082 before the actual jump. */
1083 dc
->delayed_branch
= 2;
1084 t_gen_mov_env_TN(btaken
, tcg_const_tl(1));
1087 void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
1088 unsigned int size
, int sign
)
1090 int mem_index
= cpu_mmu_index(dc
->env
);
1092 cris_evaluate_flags(dc
);
1095 tcg_gen_qemu_ld8s(dst
, addr
, mem_index
);
1097 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
1099 else if (size
== 2) {
1101 tcg_gen_qemu_ld16s(dst
, addr
, mem_index
);
1103 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
1106 tcg_gen_qemu_ld32s(dst
, addr
, mem_index
);
1110 void gen_store (DisasContext
*dc
, TCGv addr
, TCGv val
,
1113 int mem_index
= cpu_mmu_index(dc
->env
);
1115 cris_evaluate_flags(dc
);
1117 /* Remember, operands are flipped. CRIS has reversed order. */
1119 tcg_gen_qemu_st8(val
, addr
, mem_index
);
1121 tcg_gen_qemu_st16(val
, addr
, mem_index
);
1123 tcg_gen_qemu_st32(val
, addr
, mem_index
);
1126 static inline void t_gen_sext(TCGv d
, TCGv s
, int size
)
1129 tcg_gen_ext8s_i32(d
, s
);
1131 tcg_gen_ext16s_i32(d
, s
);
1133 tcg_gen_mov_tl(d
, s
);
1136 static inline void t_gen_zext(TCGv d
, TCGv s
, int size
)
1139 tcg_gen_ext8u_i32(d
, s
);
1141 tcg_gen_ext16u_i32(d
, s
);
1143 tcg_gen_mov_tl(d
, s
);
1147 static char memsize_char(int size
)
1151 case 1: return 'b'; break;
1152 case 2: return 'w'; break;
1153 case 4: return 'd'; break;
1161 static unsigned int memsize_z(DisasContext
*dc
)
1163 return dc
->zsize
+ 1;
1166 static unsigned int memsize_zz(DisasContext
*dc
)
1177 static inline void do_postinc (DisasContext
*dc
, int size
)
1180 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], size
);
1183 static void dec_prep_move_r(DisasContext
*dc
, int rs
, int rd
,
1184 int size
, int s_ext
)
1187 t_gen_sext(cpu_T
[1], cpu_R
[rs
], size
);
1189 t_gen_zext(cpu_T
[1], cpu_R
[rs
], size
);
1192 /* Prepare T0 and T1 for a register alu operation.
1193 s_ext decides if the operand1 should be sign-extended or zero-extended when
1195 static void dec_prep_alu_r(DisasContext
*dc
, int rs
, int rd
,
1196 int size
, int s_ext
)
1198 dec_prep_move_r(dc
, rs
, rd
, size
, s_ext
);
1201 t_gen_sext(cpu_T
[0], cpu_R
[rd
], size
);
1203 t_gen_zext(cpu_T
[0], cpu_R
[rd
], size
);
1206 static int dec_prep_move_m(DisasContext
*dc
, int s_ext
, int memsize
)
1208 unsigned int rs
, rd
;
1215 is_imm
= rs
== 15 && dc
->postinc
;
1217 /* Load [$rs] onto T1. */
1219 insn_len
= 2 + memsize
;
1226 imm
= ldsb_code(dc
->pc
+ 2);
1228 imm
= ldsw_code(dc
->pc
+ 2);
1231 imm
= ldub_code(dc
->pc
+ 2);
1233 imm
= lduw_code(dc
->pc
+ 2);
1236 imm
= ldl_code(dc
->pc
+ 2);
1238 DIS(fprintf (logfile
, "imm=%x rd=%d sext=%d ms=%d\n",
1239 imm
, rd
, s_ext
, memsize
));
1240 tcg_gen_movi_tl(cpu_T
[1], imm
);
1243 gen_load(dc
, cpu_T
[1], cpu_R
[rs
], memsize
, 0);
1245 t_gen_sext(cpu_T
[1], cpu_T
[1], memsize
);
1247 t_gen_zext(cpu_T
[1], cpu_T
[1], memsize
);
1252 /* Prepare T0 and T1 for a memory + alu operation.
1253 s_ext decides if the operand1 should be sign-extended or zero-extended when
1255 static int dec_prep_alu_m(DisasContext
*dc
, int s_ext
, int memsize
)
1259 insn_len
= dec_prep_move_m(dc
, s_ext
, memsize
);
1261 /* put dest in T0. */
1262 tcg_gen_mov_tl(cpu_T
[0], cpu_R
[dc
->op2
]);
1267 static const char *cc_name(int cc
)
1269 static char *cc_names
[16] = {
1270 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1271 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1274 return cc_names
[cc
];
1278 /* Start of insn decoders. */
1280 static unsigned int dec_bccq(DisasContext
*dc
)
1284 uint32_t cond
= dc
->op2
;
1287 offset
= EXTRACT_FIELD (dc
->ir
, 1, 7);
1288 sign
= EXTRACT_FIELD(dc
->ir
, 0, 0);
1291 offset
|= sign
<< 8;
1293 offset
= sign_extend(offset
, 8);
1295 /* op2 holds the condition-code. */
1296 cris_cc_mask(dc
, 0);
1297 cris_prepare_cc_branch (dc
, offset
, cond
);
1300 static unsigned int dec_addoq(DisasContext
*dc
)
1304 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 7);
1305 imm
= sign_extend(dc
->op1
, 7);
1307 DIS(fprintf (logfile
, "addoq %d, $r%u\n", imm
, dc
->op2
));
1308 cris_cc_mask(dc
, 0);
1309 /* Fetch register operand, */
1310 tcg_gen_addi_tl(cpu_R
[R_ACR
], cpu_R
[dc
->op2
], imm
);
1313 static unsigned int dec_addq(DisasContext
*dc
)
1315 DIS(fprintf (logfile
, "addq %u, $r%u\n", dc
->op1
, dc
->op2
));
1317 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1319 cris_cc_mask(dc
, CC_MASK_NZVC
);
1320 /* Fetch register operand, */
1321 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1322 tcg_gen_movi_tl(cpu_T
[1], dc
->op1
);
1323 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1326 static unsigned int dec_moveq(DisasContext
*dc
)
1330 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1331 imm
= sign_extend(dc
->op1
, 5);
1332 DIS(fprintf (logfile
, "moveq %d, $r%u\n", imm
, dc
->op2
));
1334 tcg_gen_mov_tl(cpu_R
[dc
->op2
], tcg_const_tl(imm
));
1337 static unsigned int dec_subq(DisasContext
*dc
)
1339 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1341 DIS(fprintf (logfile
, "subq %u, $r%u\n", dc
->op1
, dc
->op2
));
1343 cris_cc_mask(dc
, CC_MASK_NZVC
);
1344 /* Fetch register operand, */
1345 tcg_gen_mov_tl(cpu_T
[0], cpu_R
[dc
->op2
]);
1346 tcg_gen_movi_tl(cpu_T
[1], dc
->op1
);
1347 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1350 static unsigned int dec_cmpq(DisasContext
*dc
)
1353 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1354 imm
= sign_extend(dc
->op1
, 5);
1356 DIS(fprintf (logfile
, "cmpq %d, $r%d\n", imm
, dc
->op2
));
1357 cris_cc_mask(dc
, CC_MASK_NZVC
);
1358 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1359 tcg_gen_movi_tl(cpu_T
[1], imm
);
1360 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, 4);
1363 static unsigned int dec_andq(DisasContext
*dc
)
1366 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1367 imm
= sign_extend(dc
->op1
, 5);
1369 DIS(fprintf (logfile
, "andq %d, $r%d\n", imm
, dc
->op2
));
1370 cris_cc_mask(dc
, CC_MASK_NZ
);
1371 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1372 tcg_gen_movi_tl(cpu_T
[1], imm
);
1373 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, 4);
1376 static unsigned int dec_orq(DisasContext
*dc
)
1379 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 5);
1380 imm
= sign_extend(dc
->op1
, 5);
1381 DIS(fprintf (logfile
, "orq %d, $r%d\n", imm
, dc
->op2
));
1382 cris_cc_mask(dc
, CC_MASK_NZ
);
1383 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1384 tcg_gen_movi_tl(cpu_T
[1], imm
);
1385 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, 4);
1388 static unsigned int dec_btstq(DisasContext
*dc
)
1390 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1391 DIS(fprintf (logfile
, "btstq %u, $r%d\n", dc
->op1
, dc
->op2
));
1393 cris_cc_mask(dc
, CC_MASK_NZ
);
1394 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1395 tcg_gen_movi_tl(cpu_T
[1], dc
->op1
);
1396 crisv32_alu_op(dc
, CC_OP_BTST
, dc
->op2
, 4);
1398 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1399 t_gen_mov_preg_TN(dc
, PR_CCS
, cpu_T
[0]);
1403 static unsigned int dec_asrq(DisasContext
*dc
)
1405 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1406 DIS(fprintf (logfile
, "asrq %u, $r%d\n", dc
->op1
, dc
->op2
));
1407 cris_cc_mask(dc
, CC_MASK_NZ
);
1408 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1409 tcg_gen_movi_tl(cpu_T
[1], dc
->op1
);
1410 crisv32_alu_op(dc
, CC_OP_ASR
, dc
->op2
, 4);
1413 static unsigned int dec_lslq(DisasContext
*dc
)
1415 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1416 DIS(fprintf (logfile
, "lslq %u, $r%d\n", dc
->op1
, dc
->op2
));
1418 cris_cc_mask(dc
, CC_MASK_NZ
);
1419 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1420 tcg_gen_movi_tl(cpu_T
[1], dc
->op1
);
1421 crisv32_alu_op(dc
, CC_OP_LSL
, dc
->op2
, 4);
1424 static unsigned int dec_lsrq(DisasContext
*dc
)
1426 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 4);
1427 DIS(fprintf (logfile
, "lsrq %u, $r%d\n", dc
->op1
, dc
->op2
));
1429 cris_cc_mask(dc
, CC_MASK_NZ
);
1430 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1431 tcg_gen_movi_tl(cpu_T
[1], dc
->op1
);
1432 crisv32_alu_op(dc
, CC_OP_LSR
, dc
->op2
, 4);
1436 static unsigned int dec_move_r(DisasContext
*dc
)
1438 int size
= memsize_zz(dc
);
1440 DIS(fprintf (logfile
, "move.%c $r%u, $r%u\n",
1441 memsize_char(size
), dc
->op1
, dc
->op2
));
1443 cris_cc_mask(dc
, CC_MASK_NZ
);
1444 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1445 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, size
);
1449 static unsigned int dec_scc_r(DisasContext
*dc
)
1453 DIS(fprintf (logfile
, "s%s $r%u\n",
1454 cc_name(cond
), dc
->op1
));
1460 gen_tst_cc (dc
, cond
);
1462 l1
= gen_new_label();
1463 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 0);
1464 tcg_gen_brcond_tl(TCG_COND_EQ
, cpu_T
[0], tcg_const_tl(0), l1
);
1465 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 1);
1469 tcg_gen_movi_tl(cpu_R
[dc
->op1
], 1);
1471 cris_cc_mask(dc
, 0);
1475 static unsigned int dec_and_r(DisasContext
*dc
)
1477 int size
= memsize_zz(dc
);
1479 DIS(fprintf (logfile
, "and.%c $r%u, $r%u\n",
1480 memsize_char(size
), dc
->op1
, dc
->op2
));
1481 cris_cc_mask(dc
, CC_MASK_NZ
);
1482 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1483 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, size
);
1487 static unsigned int dec_lz_r(DisasContext
*dc
)
1489 DIS(fprintf (logfile
, "lz $r%u, $r%u\n",
1491 cris_cc_mask(dc
, CC_MASK_NZ
);
1492 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1493 crisv32_alu_op(dc
, CC_OP_LZ
, dc
->op2
, 4);
1497 static unsigned int dec_lsl_r(DisasContext
*dc
)
1499 int size
= memsize_zz(dc
);
1501 DIS(fprintf (logfile
, "lsl.%c $r%u, $r%u\n",
1502 memsize_char(size
), dc
->op1
, dc
->op2
));
1503 cris_cc_mask(dc
, CC_MASK_NZ
);
1504 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1505 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], 63);
1506 crisv32_alu_op(dc
, CC_OP_LSL
, dc
->op2
, size
);
1510 static unsigned int dec_lsr_r(DisasContext
*dc
)
1512 int size
= memsize_zz(dc
);
1514 DIS(fprintf (logfile
, "lsr.%c $r%u, $r%u\n",
1515 memsize_char(size
), dc
->op1
, dc
->op2
));
1516 cris_cc_mask(dc
, CC_MASK_NZ
);
1517 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1518 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], 63);
1519 crisv32_alu_op(dc
, CC_OP_LSR
, dc
->op2
, size
);
1523 static unsigned int dec_asr_r(DisasContext
*dc
)
1525 int size
= memsize_zz(dc
);
1527 DIS(fprintf (logfile
, "asr.%c $r%u, $r%u\n",
1528 memsize_char(size
), dc
->op1
, dc
->op2
));
1529 cris_cc_mask(dc
, CC_MASK_NZ
);
1530 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1);
1531 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], 63);
1532 crisv32_alu_op(dc
, CC_OP_ASR
, dc
->op2
, size
);
1536 static unsigned int dec_muls_r(DisasContext
*dc
)
1538 int size
= memsize_zz(dc
);
1540 DIS(fprintf (logfile
, "muls.%c $r%u, $r%u\n",
1541 memsize_char(size
), dc
->op1
, dc
->op2
));
1542 cris_cc_mask(dc
, CC_MASK_NZV
);
1543 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 1);
1544 t_gen_sext(cpu_T
[0], cpu_T
[0], size
);
1545 crisv32_alu_op(dc
, CC_OP_MULS
, dc
->op2
, 4);
1549 static unsigned int dec_mulu_r(DisasContext
*dc
)
1551 int size
= memsize_zz(dc
);
1553 DIS(fprintf (logfile
, "mulu.%c $r%u, $r%u\n",
1554 memsize_char(size
), dc
->op1
, dc
->op2
));
1555 cris_cc_mask(dc
, CC_MASK_NZV
);
1556 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1557 t_gen_zext(cpu_T
[0], cpu_T
[0], size
);
1558 crisv32_alu_op(dc
, CC_OP_MULU
, dc
->op2
, 4);
1563 static unsigned int dec_dstep_r(DisasContext
*dc
)
1565 DIS(fprintf (logfile
, "dstep $r%u, $r%u\n", dc
->op1
, dc
->op2
));
1566 cris_cc_mask(dc
, CC_MASK_NZ
);
1567 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1568 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1569 crisv32_alu_op(dc
, CC_OP_DSTEP
, dc
->op2
, 4);
1573 static unsigned int dec_xor_r(DisasContext
*dc
)
1575 int size
= memsize_zz(dc
);
1576 DIS(fprintf (logfile
, "xor.%c $r%u, $r%u\n",
1577 memsize_char(size
), dc
->op1
, dc
->op2
));
1578 BUG_ON(size
!= 4); /* xor is dword. */
1579 cris_cc_mask(dc
, CC_MASK_NZ
);
1580 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1581 crisv32_alu_op(dc
, CC_OP_XOR
, dc
->op2
, 4);
1585 static unsigned int dec_bound_r(DisasContext
*dc
)
1587 int size
= memsize_zz(dc
);
1588 DIS(fprintf (logfile
, "bound.%c $r%u, $r%u\n",
1589 memsize_char(size
), dc
->op1
, dc
->op2
));
1590 cris_cc_mask(dc
, CC_MASK_NZ
);
1591 /* TODO: needs optmimization. */
1592 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1593 /* rd should be 4. */
1594 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1595 crisv32_alu_op(dc
, CC_OP_BOUND
, dc
->op2
, 4);
1599 static unsigned int dec_cmp_r(DisasContext
*dc
)
1601 int size
= memsize_zz(dc
);
1602 DIS(fprintf (logfile
, "cmp.%c $r%u, $r%u\n",
1603 memsize_char(size
), dc
->op1
, dc
->op2
));
1604 cris_cc_mask(dc
, CC_MASK_NZVC
);
1605 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1606 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, size
);
1610 static unsigned int dec_abs_r(DisasContext
*dc
)
1614 DIS(fprintf (logfile
, "abs $r%u, $r%u\n",
1616 cris_cc_mask(dc
, CC_MASK_NZ
);
1617 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1619 /* TODO: consider a branch free approach. */
1620 l1
= gen_new_label();
1621 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_T
[1], tcg_const_tl(0), l1
);
1622 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[1]);
1624 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1628 static unsigned int dec_add_r(DisasContext
*dc
)
1630 int size
= memsize_zz(dc
);
1631 DIS(fprintf (logfile
, "add.%c $r%u, $r%u\n",
1632 memsize_char(size
), dc
->op1
, dc
->op2
));
1633 cris_cc_mask(dc
, CC_MASK_NZVC
);
1634 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1635 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, size
);
1639 static unsigned int dec_addc_r(DisasContext
*dc
)
1641 DIS(fprintf (logfile
, "addc $r%u, $r%u\n",
1643 cris_evaluate_flags(dc
);
1644 cris_cc_mask(dc
, CC_MASK_NZVC
);
1645 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1646 crisv32_alu_op(dc
, CC_OP_ADDC
, dc
->op2
, 4);
1650 static unsigned int dec_mcp_r(DisasContext
*dc
)
1652 DIS(fprintf (logfile
, "mcp $p%u, $r%u\n",
1654 cris_evaluate_flags(dc
);
1655 cris_cc_mask(dc
, CC_MASK_RNZV
);
1656 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1657 t_gen_mov_TN_preg(cpu_T
[1], dc
->op2
);
1658 crisv32_alu_op(dc
, CC_OP_MCP
, dc
->op1
, 4);
1663 static char * swapmode_name(int mode
, char *modename
) {
1666 modename
[i
++] = 'n';
1668 modename
[i
++] = 'w';
1670 modename
[i
++] = 'b';
1672 modename
[i
++] = 'r';
1678 static unsigned int dec_swap_r(DisasContext
*dc
)
1683 DIS(fprintf (logfile
, "swap%s $r%u\n",
1684 swapmode_name(dc
->op2
, modename
), dc
->op1
));
1686 cris_cc_mask(dc
, CC_MASK_NZ
);
1687 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1689 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
1691 t_gen_swapw(cpu_T
[0], cpu_T
[0]);
1693 t_gen_swapb(cpu_T
[0], cpu_T
[0]);
1695 t_gen_swapr(cpu_T
[0], cpu_T
[0]);
1696 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1697 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, 4);
1701 static unsigned int dec_or_r(DisasContext
*dc
)
1703 int size
= memsize_zz(dc
);
1704 DIS(fprintf (logfile
, "or.%c $r%u, $r%u\n",
1705 memsize_char(size
), dc
->op1
, dc
->op2
));
1706 cris_cc_mask(dc
, CC_MASK_NZ
);
1707 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1708 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, size
);
1712 static unsigned int dec_addi_r(DisasContext
*dc
)
1714 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u\n",
1715 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1716 cris_cc_mask(dc
, 0);
1717 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1718 t_gen_lsl(cpu_T
[0], cpu_T
[0], tcg_const_tl(dc
->zzsize
));
1719 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1720 t_gen_mov_reg_TN(dc
->op1
, cpu_T
[0]);
1724 static unsigned int dec_addi_acr(DisasContext
*dc
)
1726 DIS(fprintf (logfile
, "addi.%c $r%u, $r%u, $acr\n",
1727 memsize_char(memsize_zz(dc
)), dc
->op2
, dc
->op1
));
1728 cris_cc_mask(dc
, 0);
1729 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1730 t_gen_lsl(cpu_T
[0], cpu_T
[0], tcg_const_tl(dc
->zzsize
));
1732 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1733 t_gen_mov_reg_TN(R_ACR
, cpu_T
[0]);
1737 static unsigned int dec_neg_r(DisasContext
*dc
)
1739 int size
= memsize_zz(dc
);
1740 DIS(fprintf (logfile
, "neg.%c $r%u, $r%u\n",
1741 memsize_char(size
), dc
->op1
, dc
->op2
));
1742 cris_cc_mask(dc
, CC_MASK_NZVC
);
1743 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1744 crisv32_alu_op(dc
, CC_OP_NEG
, dc
->op2
, size
);
1748 static unsigned int dec_btst_r(DisasContext
*dc
)
1750 DIS(fprintf (logfile
, "btst $r%u, $r%u\n",
1752 cris_cc_mask(dc
, CC_MASK_NZ
);
1753 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, 4, 0);
1754 crisv32_alu_op(dc
, CC_OP_BTST
, dc
->op2
, 4);
1756 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1757 t_gen_mov_preg_TN(dc
, PR_CCS
, cpu_T
[0]);
1762 static unsigned int dec_sub_r(DisasContext
*dc
)
1764 int size
= memsize_zz(dc
);
1765 DIS(fprintf (logfile
, "sub.%c $r%u, $r%u\n",
1766 memsize_char(size
), dc
->op1
, dc
->op2
));
1767 cris_cc_mask(dc
, CC_MASK_NZVC
);
1768 dec_prep_alu_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1769 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, size
);
1773 /* Zero extension. From size to dword. */
1774 static unsigned int dec_movu_r(DisasContext
*dc
)
1776 int size
= memsize_z(dc
);
1777 DIS(fprintf (logfile
, "movu.%c $r%u, $r%u\n",
1781 cris_cc_mask(dc
, CC_MASK_NZ
);
1782 dec_prep_move_r(dc
, dc
->op1
, dc
->op2
, size
, 0);
1783 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1787 /* Sign extension. From size to dword. */
1788 static unsigned int dec_movs_r(DisasContext
*dc
)
1790 int size
= memsize_z(dc
);
1791 DIS(fprintf (logfile
, "movs.%c $r%u, $r%u\n",
1795 cris_cc_mask(dc
, CC_MASK_NZ
);
1796 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1797 /* Size can only be qi or hi. */
1798 t_gen_sext(cpu_T
[1], cpu_T
[0], size
);
1799 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
1803 /* zero extension. From size to dword. */
1804 static unsigned int dec_addu_r(DisasContext
*dc
)
1806 int size
= memsize_z(dc
);
1807 DIS(fprintf (logfile
, "addu.%c $r%u, $r%u\n",
1811 cris_cc_mask(dc
, CC_MASK_NZVC
);
1812 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1813 /* Size can only be qi or hi. */
1814 t_gen_zext(cpu_T
[1], cpu_T
[1], size
);
1815 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1816 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1820 /* Sign extension. From size to dword. */
1821 static unsigned int dec_adds_r(DisasContext
*dc
)
1823 int size
= memsize_z(dc
);
1824 DIS(fprintf (logfile
, "adds.%c $r%u, $r%u\n",
1828 cris_cc_mask(dc
, CC_MASK_NZVC
);
1829 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1830 /* Size can only be qi or hi. */
1831 t_gen_sext(cpu_T
[1], cpu_T
[1], size
);
1832 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1834 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
1838 /* Zero extension. From size to dword. */
1839 static unsigned int dec_subu_r(DisasContext
*dc
)
1841 int size
= memsize_z(dc
);
1842 DIS(fprintf (logfile
, "subu.%c $r%u, $r%u\n",
1846 cris_cc_mask(dc
, CC_MASK_NZVC
);
1847 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1848 /* Size can only be qi or hi. */
1849 t_gen_zext(cpu_T
[1], cpu_T
[1], size
);
1850 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1851 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1855 /* Sign extension. From size to dword. */
1856 static unsigned int dec_subs_r(DisasContext
*dc
)
1858 int size
= memsize_z(dc
);
1859 DIS(fprintf (logfile
, "subs.%c $r%u, $r%u\n",
1863 cris_cc_mask(dc
, CC_MASK_NZVC
);
1864 t_gen_mov_TN_reg(cpu_T
[1], dc
->op1
);
1865 /* Size can only be qi or hi. */
1866 t_gen_sext(cpu_T
[1], cpu_T
[1], size
);
1867 t_gen_mov_TN_reg(cpu_T
[0], dc
->op2
);
1868 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
1872 static unsigned int dec_setclrf(DisasContext
*dc
)
1875 int set
= (~dc
->opcode
>> 2) & 1;
1877 flags
= (EXTRACT_FIELD(dc
->ir
, 12, 15) << 4)
1878 | EXTRACT_FIELD(dc
->ir
, 0, 3);
1879 DIS(fprintf (logfile
, "set=%d flags=%x\n", set
, flags
));
1880 if (set
&& flags
== 0) {
1881 DIS(fprintf (logfile
, "nop\n"));
1882 } else if (!set
&& (flags
& 0x20)) {
1883 DIS(fprintf (logfile
, "di\n"));
1886 DIS(fprintf (logfile
, "%sf %x\n",
1887 set
? "set" : "clr",
1891 if (set
&& (flags
& X_FLAG
)) {
1896 /* Simply decode the flags. */
1897 cris_evaluate_flags (dc
);
1898 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1899 tcg_gen_movi_tl(cc_op
, dc
->cc_op
);
1902 if (!dc
->user
&& (flags
& U_FLAG
)) {
1903 /* Enter user mode. */
1904 t_gen_mov_env_TN(ksp
, cpu_R
[R_SP
]);
1905 tcg_gen_mov_tl(cpu_R
[R_SP
], cpu_PR
[PR_USP
]);
1906 dc
->is_jmp
= DISAS_NEXT
;
1908 tcg_gen_ori_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], flags
);
1911 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~flags
);
1918 static unsigned int dec_move_rs(DisasContext
*dc
)
1920 DIS(fprintf (logfile
, "move $r%u, $s%u\n", dc
->op1
, dc
->op2
));
1921 cris_cc_mask(dc
, 0);
1922 tcg_gen_helper_0_2(helper_movl_sreg_reg
,
1923 tcg_const_tl(dc
->op2
), tcg_const_tl(dc
->op1
));
1926 static unsigned int dec_move_sr(DisasContext
*dc
)
1928 DIS(fprintf (logfile
, "move $s%u, $r%u\n", dc
->op2
, dc
->op1
));
1929 cris_cc_mask(dc
, 0);
1930 tcg_gen_helper_0_2(helper_movl_reg_sreg
,
1931 tcg_const_tl(dc
->op1
), tcg_const_tl(dc
->op2
));
1935 static unsigned int dec_move_rp(DisasContext
*dc
)
1937 DIS(fprintf (logfile
, "move $r%u, $p%u\n", dc
->op1
, dc
->op2
));
1938 cris_cc_mask(dc
, 0);
1940 if (dc
->op2
== PR_CCS
) {
1941 cris_evaluate_flags(dc
);
1942 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1944 /* User space is not allowed to touch all flags. */
1945 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0x39f);
1946 tcg_gen_andi_tl(cpu_T
[1], cpu_PR
[PR_CCS
], ~0x39f);
1947 tcg_gen_or_tl(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1951 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
1953 t_gen_mov_preg_TN(dc
, dc
->op2
, cpu_T
[0]);
1954 if (dc
->op2
== PR_CCS
) {
1955 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
1960 static unsigned int dec_move_pr(DisasContext
*dc
)
1962 DIS(fprintf (logfile
, "move $p%u, $r%u\n", dc
->op1
, dc
->op2
));
1963 cris_cc_mask(dc
, 0);
1964 /* Support register 0 is hardwired to zero.
1965 Treat it specially. */
1967 tcg_gen_movi_tl(cpu_T
[1], 0);
1968 else if (dc
->op2
== PR_CCS
) {
1969 cris_evaluate_flags(dc
);
1970 t_gen_mov_TN_preg(cpu_T
[1], dc
->op2
);
1972 t_gen_mov_TN_preg(cpu_T
[1], dc
->op2
);
1973 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op1
, preg_sizes
[dc
->op2
]);
1977 static unsigned int dec_move_mr(DisasContext
*dc
)
1979 int memsize
= memsize_zz(dc
);
1981 DIS(fprintf (logfile
, "move.%c [$r%u%s, $r%u\n",
1982 memsize_char(memsize
),
1983 dc
->op1
, dc
->postinc
? "+]" : "]",
1986 insn_len
= dec_prep_move_m(dc
, 0, memsize
);
1987 cris_cc_mask(dc
, CC_MASK_NZ
);
1988 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, memsize
);
1989 do_postinc(dc
, memsize
);
1993 static unsigned int dec_movs_m(DisasContext
*dc
)
1995 int memsize
= memsize_z(dc
);
1997 DIS(fprintf (logfile
, "movs.%c [$r%u%s, $r%u\n",
1998 memsize_char(memsize
),
1999 dc
->op1
, dc
->postinc
? "+]" : "]",
2003 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
2004 cris_cc_mask(dc
, CC_MASK_NZ
);
2005 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
2006 do_postinc(dc
, memsize
);
2010 static unsigned int dec_addu_m(DisasContext
*dc
)
2012 int memsize
= memsize_z(dc
);
2014 DIS(fprintf (logfile
, "addu.%c [$r%u%s, $r%u\n",
2015 memsize_char(memsize
),
2016 dc
->op1
, dc
->postinc
? "+]" : "]",
2020 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2021 cris_cc_mask(dc
, CC_MASK_NZVC
);
2022 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
2023 do_postinc(dc
, memsize
);
2027 static unsigned int dec_adds_m(DisasContext
*dc
)
2029 int memsize
= memsize_z(dc
);
2031 DIS(fprintf (logfile
, "adds.%c [$r%u%s, $r%u\n",
2032 memsize_char(memsize
),
2033 dc
->op1
, dc
->postinc
? "+]" : "]",
2037 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
2038 cris_cc_mask(dc
, CC_MASK_NZVC
);
2039 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, 4);
2040 do_postinc(dc
, memsize
);
2044 static unsigned int dec_subu_m(DisasContext
*dc
)
2046 int memsize
= memsize_z(dc
);
2048 DIS(fprintf (logfile
, "subu.%c [$r%u%s, $r%u\n",
2049 memsize_char(memsize
),
2050 dc
->op1
, dc
->postinc
? "+]" : "]",
2054 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2055 cris_cc_mask(dc
, CC_MASK_NZVC
);
2056 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
2057 do_postinc(dc
, memsize
);
2061 static unsigned int dec_subs_m(DisasContext
*dc
)
2063 int memsize
= memsize_z(dc
);
2065 DIS(fprintf (logfile
, "subs.%c [$r%u%s, $r%u\n",
2066 memsize_char(memsize
),
2067 dc
->op1
, dc
->postinc
? "+]" : "]",
2071 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
2072 cris_cc_mask(dc
, CC_MASK_NZVC
);
2073 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, 4);
2074 do_postinc(dc
, memsize
);
2078 static unsigned int dec_movu_m(DisasContext
*dc
)
2080 int memsize
= memsize_z(dc
);
2083 DIS(fprintf (logfile
, "movu.%c [$r%u%s, $r%u\n",
2084 memsize_char(memsize
),
2085 dc
->op1
, dc
->postinc
? "+]" : "]",
2088 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2089 cris_cc_mask(dc
, CC_MASK_NZ
);
2090 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
2091 do_postinc(dc
, memsize
);
2095 static unsigned int dec_cmpu_m(DisasContext
*dc
)
2097 int memsize
= memsize_z(dc
);
2099 DIS(fprintf (logfile
, "cmpu.%c [$r%u%s, $r%u\n",
2100 memsize_char(memsize
),
2101 dc
->op1
, dc
->postinc
? "+]" : "]",
2104 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2105 cris_cc_mask(dc
, CC_MASK_NZVC
);
2106 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, 4);
2107 do_postinc(dc
, memsize
);
2111 static unsigned int dec_cmps_m(DisasContext
*dc
)
2113 int memsize
= memsize_z(dc
);
2115 DIS(fprintf (logfile
, "cmps.%c [$r%u%s, $r%u\n",
2116 memsize_char(memsize
),
2117 dc
->op1
, dc
->postinc
? "+]" : "]",
2120 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
2121 cris_cc_mask(dc
, CC_MASK_NZVC
);
2122 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
2123 do_postinc(dc
, memsize
);
2127 static unsigned int dec_cmp_m(DisasContext
*dc
)
2129 int memsize
= memsize_zz(dc
);
2131 DIS(fprintf (logfile
, "cmp.%c [$r%u%s, $r%u\n",
2132 memsize_char(memsize
),
2133 dc
->op1
, dc
->postinc
? "+]" : "]",
2136 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2137 cris_cc_mask(dc
, CC_MASK_NZVC
);
2138 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
2139 do_postinc(dc
, memsize
);
2143 static unsigned int dec_test_m(DisasContext
*dc
)
2145 int memsize
= memsize_zz(dc
);
2147 DIS(fprintf (logfile
, "test.%d [$r%u%s] op2=%x\n",
2148 memsize_char(memsize
),
2149 dc
->op1
, dc
->postinc
? "+]" : "]",
2152 cris_evaluate_flags(dc
);
2154 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2155 cris_cc_mask(dc
, CC_MASK_NZ
);
2156 tcg_gen_andi_tl(cpu_PR
[PR_CCS
], cpu_PR
[PR_CCS
], ~3);
2158 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
2159 tcg_gen_movi_tl(cpu_T
[1], 0);
2160 crisv32_alu_op(dc
, CC_OP_CMP
, dc
->op2
, memsize_zz(dc
));
2161 do_postinc(dc
, memsize
);
2165 static unsigned int dec_and_m(DisasContext
*dc
)
2167 int memsize
= memsize_zz(dc
);
2169 DIS(fprintf (logfile
, "and.%d [$r%u%s, $r%u\n",
2170 memsize_char(memsize
),
2171 dc
->op1
, dc
->postinc
? "+]" : "]",
2174 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2175 cris_cc_mask(dc
, CC_MASK_NZ
);
2176 crisv32_alu_op(dc
, CC_OP_AND
, dc
->op2
, memsize_zz(dc
));
2177 do_postinc(dc
, memsize
);
2181 static unsigned int dec_add_m(DisasContext
*dc
)
2183 int memsize
= memsize_zz(dc
);
2185 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
2186 memsize_char(memsize
),
2187 dc
->op1
, dc
->postinc
? "+]" : "]",
2190 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2191 cris_cc_mask(dc
, CC_MASK_NZVC
);
2192 crisv32_alu_op(dc
, CC_OP_ADD
, dc
->op2
, memsize_zz(dc
));
2193 do_postinc(dc
, memsize
);
2197 static unsigned int dec_addo_m(DisasContext
*dc
)
2199 int memsize
= memsize_zz(dc
);
2201 DIS(fprintf (logfile
, "add.%d [$r%u%s, $r%u\n",
2202 memsize_char(memsize
),
2203 dc
->op1
, dc
->postinc
? "+]" : "]",
2206 insn_len
= dec_prep_alu_m(dc
, 1, memsize
);
2207 cris_cc_mask(dc
, 0);
2208 crisv32_alu_op(dc
, CC_OP_ADD
, R_ACR
, 4);
2209 do_postinc(dc
, memsize
);
2213 static unsigned int dec_bound_m(DisasContext
*dc
)
2215 int memsize
= memsize_zz(dc
);
2217 DIS(fprintf (logfile
, "bound.%d [$r%u%s, $r%u\n",
2218 memsize_char(memsize
),
2219 dc
->op1
, dc
->postinc
? "+]" : "]",
2222 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2223 cris_cc_mask(dc
, CC_MASK_NZ
);
2224 crisv32_alu_op(dc
, CC_OP_BOUND
, dc
->op2
, 4);
2225 do_postinc(dc
, memsize
);
2229 static unsigned int dec_addc_mr(DisasContext
*dc
)
2232 DIS(fprintf (logfile
, "addc [$r%u%s, $r%u\n",
2233 dc
->op1
, dc
->postinc
? "+]" : "]",
2236 cris_evaluate_flags(dc
);
2237 insn_len
= dec_prep_alu_m(dc
, 0, 4);
2238 cris_cc_mask(dc
, CC_MASK_NZVC
);
2239 crisv32_alu_op(dc
, CC_OP_ADDC
, dc
->op2
, 4);
2244 static unsigned int dec_sub_m(DisasContext
*dc
)
2246 int memsize
= memsize_zz(dc
);
2248 DIS(fprintf (logfile
, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2249 memsize_char(memsize
),
2250 dc
->op1
, dc
->postinc
? "+]" : "]",
2251 dc
->op2
, dc
->ir
, dc
->zzsize
));
2253 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2254 cris_cc_mask(dc
, CC_MASK_NZVC
);
2255 crisv32_alu_op(dc
, CC_OP_SUB
, dc
->op2
, memsize
);
2256 do_postinc(dc
, memsize
);
2260 static unsigned int dec_or_m(DisasContext
*dc
)
2262 int memsize
= memsize_zz(dc
);
2264 DIS(fprintf (logfile
, "or.%d [$r%u%s, $r%u pc=%x\n",
2265 memsize_char(memsize
),
2266 dc
->op1
, dc
->postinc
? "+]" : "]",
2269 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2270 cris_cc_mask(dc
, CC_MASK_NZ
);
2271 crisv32_alu_op(dc
, CC_OP_OR
, dc
->op2
, memsize_zz(dc
));
2272 do_postinc(dc
, memsize
);
2276 static unsigned int dec_move_mp(DisasContext
*dc
)
2278 int memsize
= memsize_zz(dc
);
2281 DIS(fprintf (logfile
, "move.%c [$r%u%s, $p%u\n",
2282 memsize_char(memsize
),
2284 dc
->postinc
? "+]" : "]",
2287 insn_len
= dec_prep_alu_m(dc
, 0, memsize
);
2288 cris_cc_mask(dc
, 0);
2289 if (dc
->op2
== PR_CCS
) {
2290 cris_evaluate_flags(dc
);
2292 /* User space is not allowed to touch all flags. */
2293 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], 0x39f);
2294 tcg_gen_andi_tl(cpu_T
[0], cpu_PR
[PR_CCS
], ~0x39f);
2295 tcg_gen_or_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1]);
2299 t_gen_mov_preg_TN(dc
, dc
->op2
, cpu_T
[1]);
2301 do_postinc(dc
, memsize
);
2305 static unsigned int dec_move_pm(DisasContext
*dc
)
2309 memsize
= preg_sizes
[dc
->op2
];
2311 DIS(fprintf (logfile
, "move.%c $p%u, [$r%u%s\n",
2312 memsize_char(memsize
),
2313 dc
->op2
, dc
->op1
, dc
->postinc
? "+]" : "]"));
2315 /* prepare store. Address in T0, value in T1. */
2316 if (dc
->op2
== PR_CCS
)
2317 cris_evaluate_flags(dc
);
2318 t_gen_mov_TN_preg(cpu_T
[1], dc
->op2
);
2319 gen_store(dc
, cpu_R
[dc
->op1
], cpu_T
[1], memsize
);
2321 cris_cc_mask(dc
, 0);
2323 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2327 static unsigned int dec_movem_mr(DisasContext
*dc
)
2332 DIS(fprintf (logfile
, "movem [$r%u%s, $r%u\n", dc
->op1
,
2333 dc
->postinc
? "+]" : "]", dc
->op2
));
2335 /* fetch the address into T0 and T1. */
2336 for (i
= 0; i
<= dc
->op2
; i
++) {
2337 tmp
[i
] = tcg_temp_new(TCG_TYPE_TL
);
2338 /* Perform the load onto regnum i. Always dword wide. */
2339 tcg_gen_addi_tl(cpu_T
[0], cpu_R
[dc
->op1
], i
* 4);
2340 gen_load(dc
, tmp
[i
], cpu_T
[0], 4, 0);
2343 for (i
= 0; i
<= dc
->op2
; i
++) {
2344 tcg_gen_mov_tl(cpu_R
[i
], tmp
[i
]);
2345 tcg_gen_discard_tl(tmp
[i
]);
2348 /* writeback the updated pointer value. */
2350 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], i
* 4);
2352 /* gen_load might want to evaluate the previous insns flags. */
2353 cris_cc_mask(dc
, 0);
2357 static unsigned int dec_movem_rm(DisasContext
*dc
)
2361 DIS(fprintf (logfile
, "movem $r%u, [$r%u%s\n", dc
->op2
, dc
->op1
,
2362 dc
->postinc
? "+]" : "]"));
2364 for (i
= 0; i
<= dc
->op2
; i
++) {
2365 /* Displace addr. */
2366 tcg_gen_addi_tl(cpu_T
[0], cpu_R
[dc
->op1
], i
* 4);
2367 /* Perform the store. */
2368 gen_store(dc
, cpu_T
[0], cpu_R
[i
], 4);
2371 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], i
* 4);
2372 cris_cc_mask(dc
, 0);
2376 static unsigned int dec_move_rm(DisasContext
*dc
)
2380 memsize
= memsize_zz(dc
);
2382 DIS(fprintf (logfile
, "move.%d $r%u, [$r%u]\n",
2383 memsize
, dc
->op2
, dc
->op1
));
2385 /* prepare store. */
2386 gen_store(dc
, cpu_R
[dc
->op1
], cpu_R
[dc
->op2
], memsize
);
2389 tcg_gen_addi_tl(cpu_R
[dc
->op1
], cpu_R
[dc
->op1
], memsize
);
2390 cris_cc_mask(dc
, 0);
2394 static unsigned int dec_lapcq(DisasContext
*dc
)
2396 DIS(fprintf (logfile
, "lapcq %x, $r%u\n",
2397 dc
->pc
+ dc
->op1
*2, dc
->op2
));
2398 cris_cc_mask(dc
, 0);
2399 tcg_gen_movi_tl(cpu_T
[1], dc
->pc
+ dc
->op1
* 2);
2400 crisv32_alu_op(dc
, CC_OP_MOVE
, dc
->op2
, 4);
2404 static unsigned int dec_lapc_im(DisasContext
*dc
)
2412 cris_cc_mask(dc
, 0);
2413 imm
= ldl_code(dc
->pc
+ 2);
2414 DIS(fprintf (logfile
, "lapc 0x%x, $r%u\n", imm
+ dc
->pc
, dc
->op2
));
2418 t_gen_mov_reg_TN(rd
, tcg_const_tl(pc
));
2422 /* Jump to special reg. */
2423 static unsigned int dec_jump_p(DisasContext
*dc
)
2425 DIS(fprintf (logfile
, "jump $p%u\n", dc
->op2
));
2427 if (dc
->op2
== PR_CCS
)
2428 cris_evaluate_flags(dc
);
2429 t_gen_mov_TN_preg(cpu_T
[0], dc
->op2
);
2430 /* rete will often have low bit set to indicate delayslot. */
2431 tcg_gen_andi_tl(env_btarget
, cpu_T
[0], ~1);
2432 cris_cc_mask(dc
, 0);
2433 cris_prepare_dyn_jmp(dc
);
2437 /* Jump and save. */
2438 static unsigned int dec_jas_r(DisasContext
*dc
)
2440 DIS(fprintf (logfile
, "jas $r%u, $p%u\n", dc
->op1
, dc
->op2
));
2441 cris_cc_mask(dc
, 0);
2442 /* Store the return address in Pd. */
2443 tcg_gen_mov_tl(env_btarget
, cpu_R
[dc
->op1
]);
2446 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 4);
2447 tcg_gen_mov_tl(cpu_PR
[dc
->op2
], cpu_T
[0]);
2449 cris_prepare_dyn_jmp(dc
);
2453 static unsigned int dec_jas_im(DisasContext
*dc
)
2457 imm
= ldl_code(dc
->pc
+ 2);
2459 DIS(fprintf (logfile
, "jas 0x%x\n", imm
));
2460 cris_cc_mask(dc
, 0);
2461 /* Store the return address in Pd. */
2462 tcg_gen_movi_tl(env_btarget
, imm
);
2463 t_gen_mov_preg_TN(dc
, dc
->op2
, tcg_const_tl(dc
->pc
+ 8));
2464 cris_prepare_dyn_jmp(dc
);
2468 static unsigned int dec_jasc_im(DisasContext
*dc
)
2472 imm
= ldl_code(dc
->pc
+ 2);
2474 DIS(fprintf (logfile
, "jasc 0x%x\n", imm
));
2475 cris_cc_mask(dc
, 0);
2476 /* Store the return address in Pd. */
2477 tcg_gen_movi_tl(cpu_T
[0], imm
);
2478 tcg_gen_mov_tl(env_btarget
, cpu_T
[0]);
2479 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 8 + 4);
2480 t_gen_mov_preg_TN(dc
, dc
->op2
, cpu_T
[0]);
2481 cris_prepare_dyn_jmp(dc
);
2485 static unsigned int dec_jasc_r(DisasContext
*dc
)
2487 DIS(fprintf (logfile
, "jasc_r $r%u, $p%u\n", dc
->op1
, dc
->op2
));
2488 cris_cc_mask(dc
, 0);
2489 /* Store the return address in Pd. */
2490 t_gen_mov_TN_reg(cpu_T
[0], dc
->op1
);
2491 tcg_gen_mov_tl(env_btarget
, cpu_T
[0]);
2492 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 4 + 4);
2493 t_gen_mov_preg_TN(dc
, dc
->op2
, cpu_T
[0]);
2494 cris_prepare_dyn_jmp(dc
);
2498 static unsigned int dec_bcc_im(DisasContext
*dc
)
2501 uint32_t cond
= dc
->op2
;
2503 offset
= ldsw_code(dc
->pc
+ 2);
2505 DIS(fprintf (logfile
, "b%s %d pc=%x dst=%x\n",
2506 cc_name(cond
), offset
,
2507 dc
->pc
, dc
->pc
+ offset
));
2509 cris_cc_mask(dc
, 0);
2510 /* op2 holds the condition-code. */
2511 cris_prepare_cc_branch (dc
, offset
, cond
);
2515 static unsigned int dec_bas_im(DisasContext
*dc
)
2520 simm
= ldl_code(dc
->pc
+ 2);
2522 DIS(fprintf (logfile
, "bas 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2523 cris_cc_mask(dc
, 0);
2524 /* Stor the return address in Pd. */
2525 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ simm
);
2526 tcg_gen_mov_tl(env_btarget
, cpu_T
[0]);
2527 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 8);
2528 t_gen_mov_preg_TN(dc
, dc
->op2
, cpu_T
[0]);
2529 cris_prepare_dyn_jmp(dc
);
2533 static unsigned int dec_basc_im(DisasContext
*dc
)
2536 simm
= ldl_code(dc
->pc
+ 2);
2538 DIS(fprintf (logfile
, "basc 0x%x, $p%u\n", dc
->pc
+ simm
, dc
->op2
));
2539 cris_cc_mask(dc
, 0);
2540 /* Stor the return address in Pd. */
2541 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ simm
);
2542 tcg_gen_mov_tl(env_btarget
, cpu_T
[0]);
2543 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
+ 12);
2544 t_gen_mov_preg_TN(dc
, dc
->op2
, cpu_T
[0]);
2545 cris_prepare_dyn_jmp(dc
);
2549 static unsigned int dec_rfe_etc(DisasContext
*dc
)
2551 DIS(fprintf (logfile
, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2552 dc
->opcode
, dc
->pc
, dc
->op1
, dc
->op2
));
2554 cris_cc_mask(dc
, 0);
2556 if (dc
->op2
== 15) /* ignore halt. */
2559 switch (dc
->op2
& 7) {
2562 cris_evaluate_flags(dc
);
2563 tcg_gen_helper_0_0(helper_rfe
);
2564 dc
->is_jmp
= DISAS_UPDATE
;
2572 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
);
2573 t_gen_mov_env_TN(pc
, cpu_T
[0]);
2574 /* Breaks start at 16 in the exception vector. */
2575 t_gen_mov_env_TN(trap_vector
,
2576 tcg_const_tl(dc
->op1
+ 16));
2577 t_gen_raise_exception(EXCP_BREAK
);
2578 dc
->is_jmp
= DISAS_UPDATE
;
2581 printf ("op2=%x\n", dc
->op2
);
2589 static unsigned int dec_ftag_fidx_d_m(DisasContext
*dc
)
2591 /* Ignore D-cache flushes. */
2595 static unsigned int dec_ftag_fidx_i_m(DisasContext
*dc
)
2597 /* Ignore I-cache flushes. */
2601 static unsigned int dec_null(DisasContext
*dc
)
2603 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2604 dc
->pc
, dc
->opcode
, dc
->op1
, dc
->op2
);
2610 struct decoder_info
{
2615 unsigned int (*dec
)(DisasContext
*dc
);
2617 /* Order matters here. */
2618 {DEC_MOVEQ
, dec_moveq
},
2619 {DEC_BTSTQ
, dec_btstq
},
2620 {DEC_CMPQ
, dec_cmpq
},
2621 {DEC_ADDOQ
, dec_addoq
},
2622 {DEC_ADDQ
, dec_addq
},
2623 {DEC_SUBQ
, dec_subq
},
2624 {DEC_ANDQ
, dec_andq
},
2626 {DEC_ASRQ
, dec_asrq
},
2627 {DEC_LSLQ
, dec_lslq
},
2628 {DEC_LSRQ
, dec_lsrq
},
2629 {DEC_BCCQ
, dec_bccq
},
2631 {DEC_BCC_IM
, dec_bcc_im
},
2632 {DEC_JAS_IM
, dec_jas_im
},
2633 {DEC_JAS_R
, dec_jas_r
},
2634 {DEC_JASC_IM
, dec_jasc_im
},
2635 {DEC_JASC_R
, dec_jasc_r
},
2636 {DEC_BAS_IM
, dec_bas_im
},
2637 {DEC_BASC_IM
, dec_basc_im
},
2638 {DEC_JUMP_P
, dec_jump_p
},
2639 {DEC_LAPC_IM
, dec_lapc_im
},
2640 {DEC_LAPCQ
, dec_lapcq
},
2642 {DEC_RFE_ETC
, dec_rfe_etc
},
2643 {DEC_ADDC_MR
, dec_addc_mr
},
2645 {DEC_MOVE_MP
, dec_move_mp
},
2646 {DEC_MOVE_PM
, dec_move_pm
},
2647 {DEC_MOVEM_MR
, dec_movem_mr
},
2648 {DEC_MOVEM_RM
, dec_movem_rm
},
2649 {DEC_MOVE_PR
, dec_move_pr
},
2650 {DEC_SCC_R
, dec_scc_r
},
2651 {DEC_SETF
, dec_setclrf
},
2652 {DEC_CLEARF
, dec_setclrf
},
2654 {DEC_MOVE_SR
, dec_move_sr
},
2655 {DEC_MOVE_RP
, dec_move_rp
},
2656 {DEC_SWAP_R
, dec_swap_r
},
2657 {DEC_ABS_R
, dec_abs_r
},
2658 {DEC_LZ_R
, dec_lz_r
},
2659 {DEC_MOVE_RS
, dec_move_rs
},
2660 {DEC_BTST_R
, dec_btst_r
},
2661 {DEC_ADDC_R
, dec_addc_r
},
2663 {DEC_DSTEP_R
, dec_dstep_r
},
2664 {DEC_XOR_R
, dec_xor_r
},
2665 {DEC_MCP_R
, dec_mcp_r
},
2666 {DEC_CMP_R
, dec_cmp_r
},
2668 {DEC_ADDI_R
, dec_addi_r
},
2669 {DEC_ADDI_ACR
, dec_addi_acr
},
2671 {DEC_ADD_R
, dec_add_r
},
2672 {DEC_SUB_R
, dec_sub_r
},
2674 {DEC_ADDU_R
, dec_addu_r
},
2675 {DEC_ADDS_R
, dec_adds_r
},
2676 {DEC_SUBU_R
, dec_subu_r
},
2677 {DEC_SUBS_R
, dec_subs_r
},
2678 {DEC_LSL_R
, dec_lsl_r
},
2680 {DEC_AND_R
, dec_and_r
},
2681 {DEC_OR_R
, dec_or_r
},
2682 {DEC_BOUND_R
, dec_bound_r
},
2683 {DEC_ASR_R
, dec_asr_r
},
2684 {DEC_LSR_R
, dec_lsr_r
},
2686 {DEC_MOVU_R
, dec_movu_r
},
2687 {DEC_MOVS_R
, dec_movs_r
},
2688 {DEC_NEG_R
, dec_neg_r
},
2689 {DEC_MOVE_R
, dec_move_r
},
2691 {DEC_FTAG_FIDX_I_M
, dec_ftag_fidx_i_m
},
2692 {DEC_FTAG_FIDX_D_M
, dec_ftag_fidx_d_m
},
2694 {DEC_MULS_R
, dec_muls_r
},
2695 {DEC_MULU_R
, dec_mulu_r
},
2697 {DEC_ADDU_M
, dec_addu_m
},
2698 {DEC_ADDS_M
, dec_adds_m
},
2699 {DEC_SUBU_M
, dec_subu_m
},
2700 {DEC_SUBS_M
, dec_subs_m
},
2702 {DEC_CMPU_M
, dec_cmpu_m
},
2703 {DEC_CMPS_M
, dec_cmps_m
},
2704 {DEC_MOVU_M
, dec_movu_m
},
2705 {DEC_MOVS_M
, dec_movs_m
},
2707 {DEC_CMP_M
, dec_cmp_m
},
2708 {DEC_ADDO_M
, dec_addo_m
},
2709 {DEC_BOUND_M
, dec_bound_m
},
2710 {DEC_ADD_M
, dec_add_m
},
2711 {DEC_SUB_M
, dec_sub_m
},
2712 {DEC_AND_M
, dec_and_m
},
2713 {DEC_OR_M
, dec_or_m
},
2714 {DEC_MOVE_RM
, dec_move_rm
},
2715 {DEC_TEST_M
, dec_test_m
},
2716 {DEC_MOVE_MR
, dec_move_mr
},
2721 static inline unsigned int
2722 cris_decoder(DisasContext
*dc
)
2724 unsigned int insn_len
= 2;
2727 /* Load a halfword onto the instruction register. */
2728 dc
->ir
= lduw_code(dc
->pc
);
2730 /* Now decode it. */
2731 dc
->opcode
= EXTRACT_FIELD(dc
->ir
, 4, 11);
2732 dc
->op1
= EXTRACT_FIELD(dc
->ir
, 0, 3);
2733 dc
->op2
= EXTRACT_FIELD(dc
->ir
, 12, 15);
2734 dc
->zsize
= EXTRACT_FIELD(dc
->ir
, 4, 4);
2735 dc
->zzsize
= EXTRACT_FIELD(dc
->ir
, 4, 5);
2736 dc
->postinc
= EXTRACT_FIELD(dc
->ir
, 10, 10);
2738 /* Large switch for all insns. */
2739 for (i
= 0; i
< sizeof decinfo
/ sizeof decinfo
[0]; i
++) {
2740 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
)
2742 insn_len
= decinfo
[i
].dec(dc
);
2750 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
2753 if (env
->nb_breakpoints
> 0) {
2754 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2755 if (env
->breakpoints
[j
] == dc
->pc
) {
2756 cris_evaluate_flags (dc
);
2757 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
);
2758 t_gen_mov_env_TN(pc
, cpu_T
[0]);
2759 t_gen_raise_exception(EXCP_DEBUG
);
2760 dc
->is_jmp
= DISAS_UPDATE
;
2768 * Delay slots on QEMU/CRIS.
2770 * If an exception hits on a delayslot, the core will let ERP (the Exception
2771 * Return Pointer) point to the branch (the previous) insn and set the lsb to
2772 * to give SW a hint that the exception actually hit on the dslot.
2774 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
2775 * the core and any jmp to an odd addresses will mask off that lsb. It is
2776 * simply there to let sw know there was an exception on a dslot.
2778 * When the software returns from an exception, the branch will re-execute.
2779 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
2780 * and the branch and delayslot dont share pages.
2782 * The TB contaning the branch insn will set up env->btarget and evaluate
2783 * env->btaken. When the translation loop exits we will note that the branch
2784 * sequence is broken and let env->dslot be the size of the branch insn (those
2787 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
2788 * set). It will also expect to have env->dslot setup with the size of the
2789 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
2790 * will execute the dslot and take the branch, either to btarget or just one
2793 * When exceptions occur, we check for env->dslot in do_interrupt to detect
2794 * broken branch sequences and setup $erp accordingly (i.e let it point to the
2795 * branch and set lsb). Then env->dslot gets cleared so that the exception
2796 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
2797 * masked off and we will reexecute the branch insn.
2801 /* generate intermediate code for basic block 'tb'. */
2803 gen_intermediate_code_internal(CPUState
*env
, TranslationBlock
*tb
,
2806 uint16_t *gen_opc_end
;
2808 unsigned int insn_len
;
2810 struct DisasContext ctx
;
2811 struct DisasContext
*dc
= &ctx
;
2812 uint32_t next_page_start
;
2817 /* Odd PC indicates that branch is rexecuting due to exception in the
2818 * delayslot, like in real hw.
2820 pc_start
= tb
->pc
& ~1;
2824 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2826 dc
->is_jmp
= DISAS_NEXT
;
2829 dc
->singlestep_enabled
= env
->singlestep_enabled
;
2835 cris_update_cc_op(dc
, CC_OP_FLAGS
, 4);
2837 /* Decode TB flags. */
2838 dc
->user
= tb
->flags
& U_FLAG
;
2839 dc
->delayed_branch
= !!(tb
->flags
& 7);
2841 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2843 "srch=%d pc=%x %x bt=%x ds=%lld ccs=%x\n"
2844 "pid=%x usp=%x dbg=%x %x %x\n"
2849 search_pc
, dc
->pc
, dc
->ppc
,
2850 env
->btarget
, tb
->flags
& 7,
2852 env
->pregs
[PR_PID
], env
->pregs
[PR_USP
],
2853 env
->debug1
, env
->debug2
, env
->debug3
,
2854 env
->regs
[0], env
->regs
[1], env
->regs
[2], env
->regs
[3],
2855 env
->regs
[4], env
->regs
[5], env
->regs
[6], env
->regs
[7],
2856 env
->regs
[8], env
->regs
[9],
2857 env
->regs
[10], env
->regs
[11],
2858 env
->regs
[12], env
->regs
[13],
2859 env
->regs
[14], env
->regs
[15]);
2863 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
2867 check_breakpoint(env
, dc
);
2868 if (dc
->is_jmp
== DISAS_JUMP
2869 || dc
->is_jmp
== DISAS_SWI
)
2873 j
= gen_opc_ptr
- gen_opc_buf
;
2877 gen_opc_instr_start
[lj
++] = 0;
2879 if (dc
->delayed_branch
== 1)
2880 gen_opc_pc
[lj
] = dc
->ppc
| 1;
2882 gen_opc_pc
[lj
] = dc
->pc
;
2883 gen_opc_instr_start
[lj
] = 1;
2887 DIS(fprintf(logfile
, "%x ", dc
->pc
));
2889 DIS(fprintf(logfile
, "%x ", dc
->pc
));
2893 insn_len
= cris_decoder(dc
);
2897 cris_clear_x_flag(dc
);
2899 /* Check for delayed branches here. If we do it before
2900 actually genereating any host code, the simulator will just
2901 loop doing nothing for on this program location. */
2902 if (dc
->delayed_branch
) {
2903 t_gen_mov_env_TN(dslot
, tcg_const_tl(0));
2904 dc
->delayed_branch
--;
2905 if (dc
->delayed_branch
== 0)
2907 t_gen_cc_jmp(env_btarget
,
2908 tcg_const_tl(dc
->pc
));
2909 dc
->is_jmp
= DISAS_JUMP
;
2913 /* If we are rexecuting a branch due to exceptions on
2914 delay slots dont break. */
2915 if (!(tb
->pc
& 1) && env
->singlestep_enabled
)
2917 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
2918 && (dc
->pc
< next_page_start
));
2920 /* Broken branch+delayslot sequence. */
2921 if (dc
->delayed_branch
== 1) {
2922 /* Set env->dslot to the size of the branch insn. */
2923 t_gen_mov_env_TN(dslot
, tcg_const_tl(dc
->pc
- dc
->ppc
));
2927 D(fprintf(logfile
, "!jmp pc=%x jmp=%d db=%d\n", dc
->pc
,
2928 dc
->is_jmp
, dc
->delayed_branch
));
2929 /* T0 and env_pc should hold the new pc. */
2930 tcg_gen_movi_tl(cpu_T
[0], dc
->pc
);
2931 tcg_gen_mov_tl(env_pc
, cpu_T
[0]);
2934 cris_evaluate_flags (dc
);
2936 if (__builtin_expect(env
->singlestep_enabled
, 0)) {
2937 t_gen_raise_exception(EXCP_DEBUG
);
2939 switch(dc
->is_jmp
) {
2941 gen_goto_tb(dc
, 1, dc
->pc
);
2946 /* indicate that the hash table must be used
2947 to find the next TB */
2952 /* nothing more to generate */
2956 *gen_opc_ptr
= INDEX_op_end
;
2958 j
= gen_opc_ptr
- gen_opc_buf
;
2961 gen_opc_instr_start
[lj
++] = 0;
2963 tb
->size
= dc
->pc
- pc_start
;
2967 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2968 fprintf(logfile
, "--------------\n");
2969 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2970 target_disas(logfile
, pc_start
, dc
->pc
- pc_start
, 0);
2971 fprintf(logfile
, "\nisize=%d osize=%d\n",
2972 dc
->pc
- pc_start
, gen_opc_ptr
- gen_opc_buf
);
2978 int gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2980 return gen_intermediate_code_internal(env
, tb
, 0);
2983 int gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2985 return gen_intermediate_code_internal(env
, tb
, 1);
2988 void cpu_dump_state (CPUState
*env
, FILE *f
,
2989 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
2998 cpu_fprintf(f
, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2999 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
3001 env
->pc
, env
->pregs
[PR_CCS
], env
->btaken
, env
->btarget
,
3003 env
->cc_src
, env
->cc_dest
, env
->cc_result
, env
->cc_mask
,
3004 env
->debug1
, env
->debug2
, env
->debug3
);
3006 for (i
= 0; i
< 16; i
++) {
3007 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
3008 if ((i
+ 1) % 4 == 0)
3009 cpu_fprintf(f
, "\n");
3011 cpu_fprintf(f
, "\nspecial regs:\n");
3012 for (i
= 0; i
< 16; i
++) {
3013 cpu_fprintf(f
, "p%2.2d=%8.8x ", i
, env
->pregs
[i
]);
3014 if ((i
+ 1) % 4 == 0)
3015 cpu_fprintf(f
, "\n");
3017 srs
= env
->pregs
[PR_SRS
];
3018 cpu_fprintf(f
, "\nsupport function regs bank %x:\n", srs
);
3020 for (i
= 0; i
< 16; i
++) {
3021 cpu_fprintf(f
, "s%2.2d=%8.8x ",
3022 i
, env
->sregs
[srs
][i
]);
3023 if ((i
+ 1) % 4 == 0)
3024 cpu_fprintf(f
, "\n");
3027 cpu_fprintf(f
, "\n\n");
3031 static void tcg_macro_func(TCGContext
*s
, int macro_id
, const int *dead_args
)
3035 CPUCRISState
*cpu_cris_init (const char *cpu_model
)
3040 env
= qemu_mallocz(sizeof(CPUCRISState
));
3045 tcg_set_macro_func(&tcg_ctx
, tcg_macro_func
);
3046 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
3047 #if TARGET_LONG_BITS > HOST_LONG_BITS
3048 cpu_T
[0] = tcg_global_mem_new(TCG_TYPE_TL
,
3049 TCG_AREG0
, offsetof(CPUState
, t0
), "T0");
3050 cpu_T
[1] = tcg_global_mem_new(TCG_TYPE_TL
,
3051 TCG_AREG0
, offsetof(CPUState
, t1
), "T1");
3053 cpu_T
[0] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG1
, "T0");
3054 cpu_T
[1] = tcg_global_reg_new(TCG_TYPE_TL
, TCG_AREG2
, "T1");
3057 cc_src
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3058 offsetof(CPUState
, cc_src
), "cc_src");
3059 cc_dest
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3060 offsetof(CPUState
, cc_dest
),
3062 cc_result
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3063 offsetof(CPUState
, cc_result
),
3065 cc_op
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3066 offsetof(CPUState
, cc_op
), "cc_op");
3067 cc_size
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3068 offsetof(CPUState
, cc_size
),
3070 cc_mask
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3071 offsetof(CPUState
, cc_mask
),
3074 env_pc
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3075 offsetof(CPUState
, pc
),
3077 env_btarget
= tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3078 offsetof(CPUState
, btarget
),
3081 for (i
= 0; i
< 16; i
++) {
3082 cpu_R
[i
] = tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3083 offsetof(CPUState
, regs
[i
]),
3086 for (i
= 0; i
< 16; i
++) {
3087 cpu_PR
[i
] = tcg_global_mem_new(TCG_TYPE_PTR
, TCG_AREG0
,
3088 offsetof(CPUState
, pregs
[i
]),
3092 TCG_HELPER(helper_raise_exception
);
3093 TCG_HELPER(helper_store
);
3094 TCG_HELPER(helper_dump
);
3095 TCG_HELPER(helper_dummy
);
3097 TCG_HELPER(helper_tlb_flush
);
3098 TCG_HELPER(helper_tlb_flush_pid
);
3099 TCG_HELPER(helper_movl_sreg_reg
);
3100 TCG_HELPER(helper_movl_reg_sreg
);
3101 TCG_HELPER(helper_rfe
);
3103 TCG_HELPER(helper_evaluate_flags_muls
);
3104 TCG_HELPER(helper_evaluate_flags_mulu
);
3105 TCG_HELPER(helper_evaluate_flags_mcp
);
3106 TCG_HELPER(helper_evaluate_flags_alu_4
);
3107 TCG_HELPER(helper_evaluate_flags_move_4
);
3108 TCG_HELPER(helper_evaluate_flags_move_2
);
3109 TCG_HELPER(helper_evaluate_flags
);
3115 void cpu_reset (CPUCRISState
*env
)
3117 memset(env
, 0, offsetof(CPUCRISState
, breakpoints
));
3120 #if defined(CONFIG_USER_ONLY)
3121 /* start in user mode with interrupts enabled. */
3122 env
->pregs
[PR_CCS
] |= U_FLAG
| I_FLAG
;
3124 env
->pregs
[PR_CCS
] = 0;
3128 void gen_pc_load(CPUState
*env
, struct TranslationBlock
*tb
,
3129 unsigned long searched_pc
, int pc_pos
, void *puc
)
3131 env
->pc
= gen_opc_pc
[pc_pos
];