2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "qemu-option.h"
28 #include "qemu-config.h"
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
40 /* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
44 static const char *feature_name
[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL
, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
54 static const char *ext_feature_name
[] = {
55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
56 "ds_cpl", "vmx", "smx", "est",
57 "tm2", "ssse3", "cid", NULL
,
58 "fma", "cx16", "xtpr", "pdcm",
59 NULL
, "pcid", "dca", "sse4.1|sse4_1",
60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
61 "tsc-deadline", "aes", "xsave", "osxsave",
62 "avx", NULL
, NULL
, "hypervisor",
64 static const char *ext2_feature_name
[] = {
65 "fpu", "vme", "de", "pse",
66 "tsc", "msr", "pae", "mce",
67 "cx8" /* AMD CMPXCHG8B */, "apic", NULL
, "syscall",
68 "mtrr", "pge", "mca", "cmov",
69 "pat", "pse36", NULL
, NULL
/* Linux mp */,
70 "nx|xd", NULL
, "mmxext", "mmx",
71 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
72 NULL
, "lm|i64", "3dnowext", "3dnow",
74 static const char *ext3_feature_name
[] = {
75 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
76 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
77 "3dnowprefetch", "osvw", "ibs", "xop",
78 "skinit", "wdt", NULL
, NULL
,
79 "fma4", NULL
, "cvt16", "nodeid_msr",
80 NULL
, NULL
, NULL
, NULL
,
81 NULL
, NULL
, NULL
, NULL
,
82 NULL
, NULL
, NULL
, NULL
,
85 static const char *kvm_feature_name
[] = {
86 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL
, "kvm_pv_eoi", NULL
,
87 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
88 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
89 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
92 static const char *svm_feature_name
[] = {
93 "npt", "lbrv", "svm_lock", "nrip_save",
94 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
95 NULL
, NULL
, "pause_filter", NULL
,
96 "pfthreshold", NULL
, NULL
, NULL
,
97 NULL
, NULL
, NULL
, NULL
,
98 NULL
, NULL
, NULL
, NULL
,
99 NULL
, NULL
, NULL
, NULL
,
100 NULL
, NULL
, NULL
, NULL
,
103 /* collects per-function cpuid data
105 typedef struct model_features_t
{
106 uint32_t *guest_feat
;
109 const char **flag_names
;
114 int enforce_cpuid
= 0;
116 void host_cpuid(uint32_t function
, uint32_t count
,
117 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
119 #if defined(CONFIG_KVM)
124 : "=a"(vec
[0]), "=b"(vec
[1]),
125 "=c"(vec
[2]), "=d"(vec
[3])
126 : "0"(function
), "c"(count
) : "cc");
128 asm volatile("pusha \n\t"
130 "mov %%eax, 0(%2) \n\t"
131 "mov %%ebx, 4(%2) \n\t"
132 "mov %%ecx, 8(%2) \n\t"
133 "mov %%edx, 12(%2) \n\t"
135 : : "a"(function
), "c"(count
), "S"(vec
)
150 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
152 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
153 * a substring. ex if !NULL points to the first char after a substring,
154 * otherwise the string is assumed to sized by a terminating nul.
155 * Return lexical ordering of *s1:*s2.
157 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
161 if (!*s1
|| !*s2
|| *s1
!= *s2
)
164 if (s1
== e1
&& s2
== e2
)
173 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
174 * '|' delimited (possibly empty) strings in which case search for a match
175 * within the alternatives proceeds left to right. Return 0 for success,
176 * non-zero otherwise.
178 static int altcmp(const char *s
, const char *e
, const char *altstr
)
182 for (q
= p
= altstr
; ; ) {
183 while (*p
&& *p
!= '|')
185 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
194 /* search featureset for flag *[s..e), if found set corresponding bit in
195 * *pval and return true, otherwise return false
197 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
198 const char **featureset
)
204 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
205 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
213 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
,
214 uint32_t *ext_features
,
215 uint32_t *ext2_features
,
216 uint32_t *ext3_features
,
217 uint32_t *kvm_features
,
218 uint32_t *svm_features
)
220 if (!lookup_feature(features
, flagname
, NULL
, feature_name
) &&
221 !lookup_feature(ext_features
, flagname
, NULL
, ext_feature_name
) &&
222 !lookup_feature(ext2_features
, flagname
, NULL
, ext2_feature_name
) &&
223 !lookup_feature(ext3_features
, flagname
, NULL
, ext3_feature_name
) &&
224 !lookup_feature(kvm_features
, flagname
, NULL
, kvm_feature_name
) &&
225 !lookup_feature(svm_features
, flagname
, NULL
, svm_feature_name
))
226 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
229 typedef struct x86_def_t
{
230 struct x86_def_t
*next
;
233 uint32_t vendor1
, vendor2
, vendor3
;
238 uint32_t features
, ext_features
, ext2_features
, ext3_features
;
239 uint32_t kvm_features
, svm_features
;
244 /* Store the results of Centaur's CPUID instructions */
245 uint32_t ext4_features
;
247 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
248 uint32_t cpuid_7_0_ebx_features
;
251 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
252 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
253 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
254 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
255 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
256 CPUID_PSE36 | CPUID_FXSR)
257 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
258 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
259 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
260 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
261 CPUID_PAE | CPUID_SEP | CPUID_APIC)
262 #define EXT2_FEATURE_MASK 0x0183F3FF
264 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
265 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
266 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
267 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
268 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
269 /* partly implemented:
270 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
271 CPUID_PSE36 (needed for Solaris) */
273 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
274 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
275 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
276 CPUID_EXT_HYPERVISOR)
278 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
279 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
280 #define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
281 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
282 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
284 CPUID_EXT2_PDPE1GB */
285 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
286 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
287 #define TCG_SVM_FEATURES 0
289 /* maintains list of cpu model definitions
291 static x86_def_t
*x86_defs
= {NULL
};
293 /* built-in cpu model definitions (deprecated)
295 static x86_def_t builtin_x86_defs
[] = {
299 .vendor1
= CPUID_VENDOR_AMD_1
,
300 .vendor2
= CPUID_VENDOR_AMD_2
,
301 .vendor3
= CPUID_VENDOR_AMD_3
,
305 .features
= PPRO_FEATURES
|
306 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
308 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
309 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
310 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
311 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
312 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
313 .xlevel
= 0x8000000A,
318 .vendor1
= CPUID_VENDOR_AMD_1
,
319 .vendor2
= CPUID_VENDOR_AMD_2
,
320 .vendor3
= CPUID_VENDOR_AMD_3
,
324 .features
= PPRO_FEATURES
|
325 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
326 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
327 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
329 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
330 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
331 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
332 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
333 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
335 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
336 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
337 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
338 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
339 .svm_features
= CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
340 .xlevel
= 0x8000001A,
341 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
349 .features
= PPRO_FEATURES
|
350 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
351 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
352 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
353 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
354 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
355 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
356 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
357 .ext3_features
= CPUID_EXT3_LAHF_LM
,
358 .xlevel
= 0x80000008,
359 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
364 .vendor1
= CPUID_VENDOR_INTEL_1
,
365 .vendor2
= CPUID_VENDOR_INTEL_2
,
366 .vendor3
= CPUID_VENDOR_INTEL_3
,
370 /* Missing: CPUID_VME, CPUID_HT */
371 .features
= PPRO_FEATURES
|
372 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
374 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
375 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
376 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
377 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
378 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
379 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
380 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
381 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
382 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
384 .xlevel
= 0x80000008,
385 .model_id
= "Common KVM processor"
393 .features
= PPRO_FEATURES
,
394 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
395 .xlevel
= 0x80000004,
403 .features
= PPRO_FEATURES
|
404 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
405 .ext_features
= CPUID_EXT_SSE3
,
406 .ext2_features
= PPRO_FEATURES
& EXT2_FEATURE_MASK
,
408 .xlevel
= 0x80000008,
409 .model_id
= "Common 32-bit KVM processor"
417 .features
= PPRO_FEATURES
| CPUID_VME
|
418 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
419 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
420 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
421 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
422 .ext2_features
= CPUID_EXT2_NX
,
423 .xlevel
= 0x80000008,
424 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
432 .features
= I486_FEATURES
,
441 .features
= PENTIUM_FEATURES
,
450 .features
= PENTIUM2_FEATURES
,
459 .features
= PENTIUM3_FEATURES
,
465 .vendor1
= CPUID_VENDOR_AMD_1
,
466 .vendor2
= CPUID_VENDOR_AMD_2
,
467 .vendor3
= CPUID_VENDOR_AMD_3
,
471 .features
= PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
| CPUID_MCA
,
472 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
473 .xlevel
= 0x80000008,
477 /* original is on level 10 */
482 .features
= PPRO_FEATURES
|
483 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
484 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
485 /* Some CPUs got no CPUID_SEP */
486 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
487 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
,
488 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_NX
,
489 .ext3_features
= CPUID_EXT3_LAHF_LM
,
490 .xlevel
= 0x8000000A,
491 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
496 .vendor1
= CPUID_VENDOR_INTEL_1
,
497 .vendor2
= CPUID_VENDOR_INTEL_2
,
498 .vendor3
= CPUID_VENDOR_INTEL_3
,
502 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
503 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
504 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
505 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
506 CPUID_DE
| CPUID_FP87
,
507 .ext_features
= CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
508 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
509 .ext3_features
= CPUID_EXT3_LAHF_LM
,
510 .xlevel
= 0x8000000A,
511 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
516 .vendor1
= CPUID_VENDOR_INTEL_1
,
517 .vendor2
= CPUID_VENDOR_INTEL_2
,
518 .vendor3
= CPUID_VENDOR_INTEL_3
,
522 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
523 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
524 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
525 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
526 CPUID_DE
| CPUID_FP87
,
527 .ext_features
= CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
529 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
530 .ext3_features
= CPUID_EXT3_LAHF_LM
,
531 .xlevel
= 0x8000000A,
532 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
537 .vendor1
= CPUID_VENDOR_INTEL_1
,
538 .vendor2
= CPUID_VENDOR_INTEL_2
,
539 .vendor3
= CPUID_VENDOR_INTEL_3
,
543 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
544 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
545 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
546 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
547 CPUID_DE
| CPUID_FP87
,
548 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
549 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
550 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
551 .ext3_features
= CPUID_EXT3_LAHF_LM
,
552 .xlevel
= 0x8000000A,
553 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
558 .vendor1
= CPUID_VENDOR_INTEL_1
,
559 .vendor2
= CPUID_VENDOR_INTEL_2
,
560 .vendor3
= CPUID_VENDOR_INTEL_3
,
564 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
565 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
566 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
567 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
568 CPUID_DE
| CPUID_FP87
,
569 .ext_features
= CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
570 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
572 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
573 .ext3_features
= CPUID_EXT3_LAHF_LM
,
574 .xlevel
= 0x8000000A,
575 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
578 .name
= "SandyBridge",
580 .vendor1
= CPUID_VENDOR_INTEL_1
,
581 .vendor2
= CPUID_VENDOR_INTEL_2
,
582 .vendor3
= CPUID_VENDOR_INTEL_3
,
586 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
587 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
588 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
589 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
590 CPUID_DE
| CPUID_FP87
,
591 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
592 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
593 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
594 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
596 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
598 .ext3_features
= CPUID_EXT3_LAHF_LM
,
599 .xlevel
= 0x8000000A,
600 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
603 .name
= "Opteron_G1",
605 .vendor1
= CPUID_VENDOR_AMD_1
,
606 .vendor2
= CPUID_VENDOR_AMD_2
,
607 .vendor3
= CPUID_VENDOR_AMD_3
,
611 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
612 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
613 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
614 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
615 CPUID_DE
| CPUID_FP87
,
616 .ext_features
= CPUID_EXT_SSE3
,
617 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
618 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
619 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
620 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
621 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
622 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
623 .xlevel
= 0x80000008,
624 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
627 .name
= "Opteron_G2",
629 .vendor1
= CPUID_VENDOR_AMD_1
,
630 .vendor2
= CPUID_VENDOR_AMD_2
,
631 .vendor3
= CPUID_VENDOR_AMD_3
,
635 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
636 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
637 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
638 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
639 CPUID_DE
| CPUID_FP87
,
640 .ext_features
= CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
641 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
642 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
643 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
644 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
645 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
646 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
647 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
648 .ext3_features
= CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
649 .xlevel
= 0x80000008,
650 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
653 .name
= "Opteron_G3",
655 .vendor1
= CPUID_VENDOR_AMD_1
,
656 .vendor2
= CPUID_VENDOR_AMD_2
,
657 .vendor3
= CPUID_VENDOR_AMD_3
,
661 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
662 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
663 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
664 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
665 CPUID_DE
| CPUID_FP87
,
666 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
668 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
669 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
670 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
671 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
672 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
673 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
674 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
675 .ext3_features
= CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
676 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
677 .xlevel
= 0x80000008,
678 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
681 .name
= "Opteron_G4",
683 .vendor1
= CPUID_VENDOR_AMD_1
,
684 .vendor2
= CPUID_VENDOR_AMD_2
,
685 .vendor3
= CPUID_VENDOR_AMD_3
,
689 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
690 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
691 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
692 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
693 CPUID_DE
| CPUID_FP87
,
694 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
695 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
696 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
698 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
699 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
700 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
701 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
702 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
703 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
704 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
705 .ext3_features
= CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
706 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
707 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
709 .xlevel
= 0x8000001A,
710 .model_id
= "AMD Opteron 62xx class CPU",
714 static int cpu_x86_fill_model_id(char *str
)
716 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
719 for (i
= 0; i
< 3; i
++) {
720 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
721 memcpy(str
+ i
* 16 + 0, &eax
, 4);
722 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
723 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
724 memcpy(str
+ i
* 16 + 12, &edx
, 4);
729 static int cpu_x86_fill_host(x86_def_t
*x86_cpu_def
)
731 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
733 x86_cpu_def
->name
= "host";
734 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
735 x86_cpu_def
->level
= eax
;
736 x86_cpu_def
->vendor1
= ebx
;
737 x86_cpu_def
->vendor2
= edx
;
738 x86_cpu_def
->vendor3
= ecx
;
740 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
741 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
742 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
743 x86_cpu_def
->stepping
= eax
& 0x0F;
744 x86_cpu_def
->ext_features
= ecx
;
745 x86_cpu_def
->features
= edx
;
747 if (kvm_enabled() && x86_cpu_def
->level
>= 7) {
748 x86_cpu_def
->cpuid_7_0_ebx_features
= kvm_arch_get_supported_cpuid(kvm_state
, 0x7, 0, R_EBX
);
750 x86_cpu_def
->cpuid_7_0_ebx_features
= 0;
753 host_cpuid(0x80000000, 0, &eax
, &ebx
, &ecx
, &edx
);
754 x86_cpu_def
->xlevel
= eax
;
756 host_cpuid(0x80000001, 0, &eax
, &ebx
, &ecx
, &edx
);
757 x86_cpu_def
->ext2_features
= edx
;
758 x86_cpu_def
->ext3_features
= ecx
;
759 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
760 x86_cpu_def
->vendor_override
= 0;
762 /* Call Centaur's CPUID instruction. */
763 if (x86_cpu_def
->vendor1
== CPUID_VENDOR_VIA_1
&&
764 x86_cpu_def
->vendor2
== CPUID_VENDOR_VIA_2
&&
765 x86_cpu_def
->vendor3
== CPUID_VENDOR_VIA_3
) {
766 host_cpuid(0xC0000000, 0, &eax
, &ebx
, &ecx
, &edx
);
767 if (eax
>= 0xC0000001) {
768 /* Support VIA max extended level */
769 x86_cpu_def
->xlevel2
= eax
;
770 host_cpuid(0xC0000001, 0, &eax
, &ebx
, &ecx
, &edx
);
771 x86_cpu_def
->ext4_features
= edx
;
776 * Every SVM feature requires emulation support in KVM - so we can't just
777 * read the host features here. KVM might even support SVM features not
778 * available on the host hardware. Just set all bits and mask out the
779 * unsupported ones later.
781 x86_cpu_def
->svm_features
= -1;
786 static int unavailable_host_feature(struct model_features_t
*f
, uint32_t mask
)
790 for (i
= 0; i
< 32; ++i
)
792 fprintf(stderr
, "warning: host cpuid %04x_%04x lacks requested"
793 " flag '%s' [0x%08x]\n",
794 f
->cpuid
>> 16, f
->cpuid
& 0xffff,
795 f
->flag_names
[i
] ? f
->flag_names
[i
] : "[reserved]", mask
);
801 /* best effort attempt to inform user requested cpu flags aren't making
802 * their way to the guest. Note: ft[].check_feat ideally should be
803 * specified via a guest_def field to suppress report of extraneous flags.
805 static int check_features_against_host(x86_def_t
*guest_def
)
810 struct model_features_t ft
[] = {
811 {&guest_def
->features
, &host_def
.features
,
812 ~0, feature_name
, 0x00000000},
813 {&guest_def
->ext_features
, &host_def
.ext_features
,
814 ~CPUID_EXT_HYPERVISOR
, ext_feature_name
, 0x00000001},
815 {&guest_def
->ext2_features
, &host_def
.ext2_features
,
816 ~PPRO_FEATURES
, ext2_feature_name
, 0x80000000},
817 {&guest_def
->ext3_features
, &host_def
.ext3_features
,
818 ~CPUID_EXT3_SVM
, ext3_feature_name
, 0x80000001}};
820 cpu_x86_fill_host(&host_def
);
821 for (rv
= 0, i
= 0; i
< ARRAY_SIZE(ft
); ++i
)
822 for (mask
= 1; mask
; mask
<<= 1)
823 if (ft
[i
].check_feat
& mask
&& *ft
[i
].guest_feat
& mask
&&
824 !(*ft
[i
].host_feat
& mask
)) {
825 unavailable_host_feature(&ft
[i
], mask
);
831 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
832 const char *name
, Error
**errp
)
834 X86CPU
*cpu
= X86_CPU(obj
);
835 CPUX86State
*env
= &cpu
->env
;
838 value
= (env
->cpuid_version
>> 8) & 0xf;
840 value
+= (env
->cpuid_version
>> 20) & 0xff;
842 visit_type_int(v
, &value
, name
, errp
);
845 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
846 const char *name
, Error
**errp
)
848 X86CPU
*cpu
= X86_CPU(obj
);
849 CPUX86State
*env
= &cpu
->env
;
850 const int64_t min
= 0;
851 const int64_t max
= 0xff + 0xf;
854 visit_type_int(v
, &value
, name
, errp
);
855 if (error_is_set(errp
)) {
858 if (value
< min
|| value
> max
) {
859 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
860 name
? name
: "null", value
, min
, max
);
864 env
->cpuid_version
&= ~0xff00f00;
866 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
868 env
->cpuid_version
|= value
<< 8;
872 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
873 const char *name
, Error
**errp
)
875 X86CPU
*cpu
= X86_CPU(obj
);
876 CPUX86State
*env
= &cpu
->env
;
879 value
= (env
->cpuid_version
>> 4) & 0xf;
880 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
881 visit_type_int(v
, &value
, name
, errp
);
884 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
885 const char *name
, Error
**errp
)
887 X86CPU
*cpu
= X86_CPU(obj
);
888 CPUX86State
*env
= &cpu
->env
;
889 const int64_t min
= 0;
890 const int64_t max
= 0xff;
893 visit_type_int(v
, &value
, name
, errp
);
894 if (error_is_set(errp
)) {
897 if (value
< min
|| value
> max
) {
898 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
899 name
? name
: "null", value
, min
, max
);
903 env
->cpuid_version
&= ~0xf00f0;
904 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
907 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
908 void *opaque
, const char *name
,
911 X86CPU
*cpu
= X86_CPU(obj
);
912 CPUX86State
*env
= &cpu
->env
;
915 value
= env
->cpuid_version
& 0xf;
916 visit_type_int(v
, &value
, name
, errp
);
919 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
920 void *opaque
, const char *name
,
923 X86CPU
*cpu
= X86_CPU(obj
);
924 CPUX86State
*env
= &cpu
->env
;
925 const int64_t min
= 0;
926 const int64_t max
= 0xf;
929 visit_type_int(v
, &value
, name
, errp
);
930 if (error_is_set(errp
)) {
933 if (value
< min
|| value
> max
) {
934 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
935 name
? name
: "null", value
, min
, max
);
939 env
->cpuid_version
&= ~0xf;
940 env
->cpuid_version
|= value
& 0xf;
943 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
944 const char *name
, Error
**errp
)
946 X86CPU
*cpu
= X86_CPU(obj
);
948 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
951 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
952 const char *name
, Error
**errp
)
954 X86CPU
*cpu
= X86_CPU(obj
);
956 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
959 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
960 const char *name
, Error
**errp
)
962 X86CPU
*cpu
= X86_CPU(obj
);
964 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
967 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
968 const char *name
, Error
**errp
)
970 X86CPU
*cpu
= X86_CPU(obj
);
972 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
975 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
977 X86CPU
*cpu
= X86_CPU(obj
);
978 CPUX86State
*env
= &cpu
->env
;
982 value
= (char *)g_malloc(12 + 1);
983 for (i
= 0; i
< 4; i
++) {
984 value
[i
] = env
->cpuid_vendor1
>> (8 * i
);
985 value
[i
+ 4] = env
->cpuid_vendor2
>> (8 * i
);
986 value
[i
+ 8] = env
->cpuid_vendor3
>> (8 * i
);
992 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
995 X86CPU
*cpu
= X86_CPU(obj
);
996 CPUX86State
*env
= &cpu
->env
;
999 if (strlen(value
) != 12) {
1000 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1005 env
->cpuid_vendor1
= 0;
1006 env
->cpuid_vendor2
= 0;
1007 env
->cpuid_vendor3
= 0;
1008 for (i
= 0; i
< 4; i
++) {
1009 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1010 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1011 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1013 env
->cpuid_vendor_override
= 1;
1016 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1018 X86CPU
*cpu
= X86_CPU(obj
);
1019 CPUX86State
*env
= &cpu
->env
;
1023 value
= g_malloc(48 + 1);
1024 for (i
= 0; i
< 48; i
++) {
1025 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1031 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1034 X86CPU
*cpu
= X86_CPU(obj
);
1035 CPUX86State
*env
= &cpu
->env
;
1038 if (model_id
== NULL
) {
1041 len
= strlen(model_id
);
1042 memset(env
->cpuid_model
, 0, 48);
1043 for (i
= 0; i
< 48; i
++) {
1047 c
= (uint8_t)model_id
[i
];
1049 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1053 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1054 const char *name
, Error
**errp
)
1056 X86CPU
*cpu
= X86_CPU(obj
);
1059 value
= cpu
->env
.tsc_khz
* 1000;
1060 visit_type_int(v
, &value
, name
, errp
);
1063 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1064 const char *name
, Error
**errp
)
1066 X86CPU
*cpu
= X86_CPU(obj
);
1067 const int64_t min
= 0;
1068 const int64_t max
= INT_MAX
;
1071 visit_type_int(v
, &value
, name
, errp
);
1072 if (error_is_set(errp
)) {
1075 if (value
< min
|| value
> max
) {
1076 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1077 name
? name
: "null", value
, min
, max
);
1081 cpu
->env
.tsc_khz
= value
/ 1000;
1084 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *cpu_model
)
1089 char *s
= g_strdup(cpu_model
);
1090 char *featurestr
, *name
= strtok(s
, ",");
1091 /* Features to be added*/
1092 uint32_t plus_features
= 0, plus_ext_features
= 0;
1093 uint32_t plus_ext2_features
= 0, plus_ext3_features
= 0;
1094 uint32_t plus_kvm_features
= 0, plus_svm_features
= 0;
1095 /* Features to be removed */
1096 uint32_t minus_features
= 0, minus_ext_features
= 0;
1097 uint32_t minus_ext2_features
= 0, minus_ext3_features
= 0;
1098 uint32_t minus_kvm_features
= 0, minus_svm_features
= 0;
1101 for (def
= x86_defs
; def
; def
= def
->next
)
1102 if (name
&& !strcmp(name
, def
->name
))
1104 if (kvm_enabled() && name
&& strcmp(name
, "host") == 0) {
1105 cpu_x86_fill_host(x86_cpu_def
);
1109 memcpy(x86_cpu_def
, def
, sizeof(*def
));
1112 #if defined(CONFIG_KVM)
1113 plus_kvm_features
= (1 << KVM_FEATURE_CLOCKSOURCE
) |
1114 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
1115 (1 << KVM_FEATURE_MMU_OP
) |
1116 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
1117 (1 << KVM_FEATURE_ASYNC_PF
) |
1118 (1 << KVM_FEATURE_STEAL_TIME
) |
1119 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
);
1121 plus_kvm_features
= 0;
1124 add_flagname_to_bitmaps("hypervisor", &plus_features
,
1125 &plus_ext_features
, &plus_ext2_features
, &plus_ext3_features
,
1126 &plus_kvm_features
, &plus_svm_features
);
1128 featurestr
= strtok(NULL
, ",");
1130 while (featurestr
) {
1132 if (featurestr
[0] == '+') {
1133 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
,
1134 &plus_ext_features
, &plus_ext2_features
,
1135 &plus_ext3_features
, &plus_kvm_features
,
1136 &plus_svm_features
);
1137 } else if (featurestr
[0] == '-') {
1138 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
,
1139 &minus_ext_features
, &minus_ext2_features
,
1140 &minus_ext3_features
, &minus_kvm_features
,
1141 &minus_svm_features
);
1142 } else if ((val
= strchr(featurestr
, '='))) {
1144 if (!strcmp(featurestr
, "family")) {
1146 numvalue
= strtoul(val
, &err
, 0);
1147 if (!*val
|| *err
|| numvalue
> 0xff + 0xf) {
1148 fprintf(stderr
, "bad numerical value %s\n", val
);
1151 x86_cpu_def
->family
= numvalue
;
1152 } else if (!strcmp(featurestr
, "model")) {
1154 numvalue
= strtoul(val
, &err
, 0);
1155 if (!*val
|| *err
|| numvalue
> 0xff) {
1156 fprintf(stderr
, "bad numerical value %s\n", val
);
1159 x86_cpu_def
->model
= numvalue
;
1160 } else if (!strcmp(featurestr
, "stepping")) {
1162 numvalue
= strtoul(val
, &err
, 0);
1163 if (!*val
|| *err
|| numvalue
> 0xf) {
1164 fprintf(stderr
, "bad numerical value %s\n", val
);
1167 x86_cpu_def
->stepping
= numvalue
;
1168 } else if (!strcmp(featurestr
, "level")) {
1170 numvalue
= strtoul(val
, &err
, 0);
1171 if (!*val
|| *err
) {
1172 fprintf(stderr
, "bad numerical value %s\n", val
);
1175 x86_cpu_def
->level
= numvalue
;
1176 } else if (!strcmp(featurestr
, "xlevel")) {
1178 numvalue
= strtoul(val
, &err
, 0);
1179 if (!*val
|| *err
) {
1180 fprintf(stderr
, "bad numerical value %s\n", val
);
1183 if (numvalue
< 0x80000000) {
1184 numvalue
+= 0x80000000;
1186 x86_cpu_def
->xlevel
= numvalue
;
1187 } else if (!strcmp(featurestr
, "vendor")) {
1188 if (strlen(val
) != 12) {
1189 fprintf(stderr
, "vendor string must be 12 chars long\n");
1192 x86_cpu_def
->vendor1
= 0;
1193 x86_cpu_def
->vendor2
= 0;
1194 x86_cpu_def
->vendor3
= 0;
1195 for(i
= 0; i
< 4; i
++) {
1196 x86_cpu_def
->vendor1
|= ((uint8_t)val
[i
]) << (8 * i
);
1197 x86_cpu_def
->vendor2
|= ((uint8_t)val
[i
+ 4]) << (8 * i
);
1198 x86_cpu_def
->vendor3
|= ((uint8_t)val
[i
+ 8]) << (8 * i
);
1200 x86_cpu_def
->vendor_override
= 1;
1201 } else if (!strcmp(featurestr
, "model_id")) {
1202 pstrcpy(x86_cpu_def
->model_id
, sizeof(x86_cpu_def
->model_id
),
1204 } else if (!strcmp(featurestr
, "tsc_freq")) {
1208 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1209 STRTOSZ_DEFSUFFIX_B
, 1000);
1210 if (tsc_freq
< 0 || *err
) {
1211 fprintf(stderr
, "bad numerical value %s\n", val
);
1214 x86_cpu_def
->tsc_khz
= tsc_freq
/ 1000;
1215 } else if (!strcmp(featurestr
, "hv_spinlocks")) {
1217 numvalue
= strtoul(val
, &err
, 0);
1218 if (!*val
|| *err
) {
1219 fprintf(stderr
, "bad numerical value %s\n", val
);
1222 hyperv_set_spinlock_retries(numvalue
);
1224 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1227 } else if (!strcmp(featurestr
, "check")) {
1229 } else if (!strcmp(featurestr
, "enforce")) {
1230 check_cpuid
= enforce_cpuid
= 1;
1231 } else if (!strcmp(featurestr
, "hv_relaxed")) {
1232 hyperv_enable_relaxed_timing(true);
1233 } else if (!strcmp(featurestr
, "hv_vapic")) {
1234 hyperv_enable_vapic_recommended(true);
1236 fprintf(stderr
, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr
);
1239 featurestr
= strtok(NULL
, ",");
1241 x86_cpu_def
->features
|= plus_features
;
1242 x86_cpu_def
->ext_features
|= plus_ext_features
;
1243 x86_cpu_def
->ext2_features
|= plus_ext2_features
;
1244 x86_cpu_def
->ext3_features
|= plus_ext3_features
;
1245 x86_cpu_def
->kvm_features
|= plus_kvm_features
;
1246 x86_cpu_def
->svm_features
|= plus_svm_features
;
1247 x86_cpu_def
->features
&= ~minus_features
;
1248 x86_cpu_def
->ext_features
&= ~minus_ext_features
;
1249 x86_cpu_def
->ext2_features
&= ~minus_ext2_features
;
1250 x86_cpu_def
->ext3_features
&= ~minus_ext3_features
;
1251 x86_cpu_def
->kvm_features
&= ~minus_kvm_features
;
1252 x86_cpu_def
->svm_features
&= ~minus_svm_features
;
1254 if (check_features_against_host(x86_cpu_def
) && enforce_cpuid
)
1265 /* generate a composite string into buf of all cpuid names in featureset
1266 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1267 * if flags, suppress names undefined in featureset.
1269 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1270 const char **featureset
, uint32_t flags
)
1272 const char **p
= &featureset
[31];
1276 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1278 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1279 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1281 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1283 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1284 if (bufsize
<= nc
) {
1286 memcpy(b
, "...", sizeof("..."));
1295 /* generate CPU information. */
1296 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1301 for (def
= x86_defs
; def
; def
= def
->next
) {
1302 snprintf(buf
, sizeof (buf
), def
->flags
? "[%s]": "%s", def
->name
);
1303 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1305 if (kvm_enabled()) {
1306 (*cpu_fprintf
)(f
, "x86 %16s\n", "[host]");
1308 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1309 listflags(buf
, sizeof(buf
), (uint32_t)~0, feature_name
, 1);
1310 (*cpu_fprintf
)(f
, " f_edx: %s\n", buf
);
1311 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext_feature_name
, 1);
1312 (*cpu_fprintf
)(f
, " f_ecx: %s\n", buf
);
1313 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext2_feature_name
, 1);
1314 (*cpu_fprintf
)(f
, " extf_edx: %s\n", buf
);
1315 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext3_feature_name
, 1);
1316 (*cpu_fprintf
)(f
, " extf_ecx: %s\n", buf
);
1319 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1321 CpuDefinitionInfoList
*cpu_list
= NULL
;
1324 for (def
= x86_defs
; def
; def
= def
->next
) {
1325 CpuDefinitionInfoList
*entry
;
1326 CpuDefinitionInfo
*info
;
1328 info
= g_malloc0(sizeof(*info
));
1329 info
->name
= g_strdup(def
->name
);
1331 entry
= g_malloc0(sizeof(*entry
));
1332 entry
->value
= info
;
1333 entry
->next
= cpu_list
;
1340 int cpu_x86_register(X86CPU
*cpu
, const char *cpu_model
)
1342 CPUX86State
*env
= &cpu
->env
;
1343 x86_def_t def1
, *def
= &def1
;
1344 Error
*error
= NULL
;
1346 memset(def
, 0, sizeof(*def
));
1348 if (cpu_x86_find_by_name(def
, cpu_model
) < 0)
1351 env
->cpuid_vendor1
= def
->vendor1
;
1352 env
->cpuid_vendor2
= def
->vendor2
;
1353 env
->cpuid_vendor3
= def
->vendor3
;
1355 env
->cpuid_vendor1
= CPUID_VENDOR_INTEL_1
;
1356 env
->cpuid_vendor2
= CPUID_VENDOR_INTEL_2
;
1357 env
->cpuid_vendor3
= CPUID_VENDOR_INTEL_3
;
1359 env
->cpuid_vendor_override
= def
->vendor_override
;
1360 object_property_set_int(OBJECT(cpu
), def
->level
, "level", &error
);
1361 object_property_set_int(OBJECT(cpu
), def
->family
, "family", &error
);
1362 object_property_set_int(OBJECT(cpu
), def
->model
, "model", &error
);
1363 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", &error
);
1364 env
->cpuid_features
= def
->features
;
1365 env
->cpuid_ext_features
= def
->ext_features
;
1366 env
->cpuid_ext2_features
= def
->ext2_features
;
1367 env
->cpuid_ext3_features
= def
->ext3_features
;
1368 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", &error
);
1369 env
->cpuid_kvm_features
= def
->kvm_features
;
1370 env
->cpuid_svm_features
= def
->svm_features
;
1371 env
->cpuid_ext4_features
= def
->ext4_features
;
1372 env
->cpuid_7_0_ebx
= def
->cpuid_7_0_ebx_features
;
1373 env
->cpuid_xlevel2
= def
->xlevel2
;
1374 object_property_set_int(OBJECT(cpu
), (int64_t)def
->tsc_khz
* 1000,
1375 "tsc-frequency", &error
);
1376 if (!kvm_enabled()) {
1377 env
->cpuid_features
&= TCG_FEATURES
;
1378 env
->cpuid_ext_features
&= TCG_EXT_FEATURES
;
1379 env
->cpuid_ext2_features
&= (TCG_EXT2_FEATURES
1380 #ifdef TARGET_X86_64
1381 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
1384 env
->cpuid_ext3_features
&= TCG_EXT3_FEATURES
;
1385 env
->cpuid_svm_features
&= TCG_SVM_FEATURES
;
1387 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", &error
);
1388 if (error_is_set(&error
)) {
1395 #if !defined(CONFIG_USER_ONLY)
1396 /* copy vendor id string to 32 bit register, nul pad as needed
1398 static void cpyid(const char *s
, uint32_t *id
)
1400 char *d
= (char *)id
;
1403 for (i
= sizeof (*id
); i
--; )
1404 *d
++ = *s
? *s
++ : '\0';
1407 /* interpret radix and convert from string to arbitrary scalar,
1408 * otherwise flag failure
1410 #define setscalar(pval, str, perr) \
1415 ul = strtoul(str, &pend, 0); \
1416 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1419 /* map cpuid options to feature bits, otherwise return failure
1420 * (option tags in *str are delimited by whitespace)
1422 static void setfeatures(uint32_t *pval
, const char *str
,
1423 const char **featureset
, int *perr
)
1427 for (q
= p
= str
; *p
|| *q
; q
= p
) {
1430 while (*p
&& !iswhite(*p
))
1434 if (!lookup_feature(pval
, q
, p
, featureset
)) {
1435 fprintf(stderr
, "error: feature \"%.*s\" not available in set\n",
1443 /* map config file options to x86_def_t form
1445 static int cpudef_setfield(const char *name
, const char *str
, void *opaque
)
1447 x86_def_t
*def
= opaque
;
1450 if (!strcmp(name
, "name")) {
1451 g_free((void *)def
->name
);
1452 def
->name
= g_strdup(str
);
1453 } else if (!strcmp(name
, "model_id")) {
1454 strncpy(def
->model_id
, str
, sizeof (def
->model_id
));
1455 } else if (!strcmp(name
, "level")) {
1456 setscalar(&def
->level
, str
, &err
)
1457 } else if (!strcmp(name
, "vendor")) {
1458 cpyid(&str
[0], &def
->vendor1
);
1459 cpyid(&str
[4], &def
->vendor2
);
1460 cpyid(&str
[8], &def
->vendor3
);
1461 } else if (!strcmp(name
, "family")) {
1462 setscalar(&def
->family
, str
, &err
)
1463 } else if (!strcmp(name
, "model")) {
1464 setscalar(&def
->model
, str
, &err
)
1465 } else if (!strcmp(name
, "stepping")) {
1466 setscalar(&def
->stepping
, str
, &err
)
1467 } else if (!strcmp(name
, "feature_edx")) {
1468 setfeatures(&def
->features
, str
, feature_name
, &err
);
1469 } else if (!strcmp(name
, "feature_ecx")) {
1470 setfeatures(&def
->ext_features
, str
, ext_feature_name
, &err
);
1471 } else if (!strcmp(name
, "extfeature_edx")) {
1472 setfeatures(&def
->ext2_features
, str
, ext2_feature_name
, &err
);
1473 } else if (!strcmp(name
, "extfeature_ecx")) {
1474 setfeatures(&def
->ext3_features
, str
, ext3_feature_name
, &err
);
1475 } else if (!strcmp(name
, "xlevel")) {
1476 setscalar(&def
->xlevel
, str
, &err
)
1478 fprintf(stderr
, "error: unknown option [%s = %s]\n", name
, str
);
1482 fprintf(stderr
, "error: bad option value [%s = %s]\n", name
, str
);
1488 /* register config file entry as x86_def_t
1490 static int cpudef_register(QemuOpts
*opts
, void *opaque
)
1492 x86_def_t
*def
= g_malloc0(sizeof (x86_def_t
));
1494 qemu_opt_foreach(opts
, cpudef_setfield
, def
, 1);
1495 def
->next
= x86_defs
;
1500 void cpu_clear_apic_feature(CPUX86State
*env
)
1502 env
->cpuid_features
&= ~CPUID_APIC
;
1505 #endif /* !CONFIG_USER_ONLY */
1507 /* register "cpudef" models defined in configuration file. Here we first
1508 * preload any built-in definitions
1510 void x86_cpudef_setup(void)
1513 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1515 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1516 x86_def_t
*def
= &builtin_x86_defs
[i
];
1517 def
->next
= x86_defs
;
1520 /* Look for specific "cpudef" models that */
1521 /* have the QEMU version in .model_id */
1522 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1523 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
1524 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
1525 "QEMU Virtual CPU version ");
1526 pstrcat(def
->model_id
, sizeof(def
->model_id
),
1527 qemu_get_version());
1534 #if !defined(CONFIG_USER_ONLY)
1535 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register
, NULL
, 0);
1539 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1540 uint32_t *ecx
, uint32_t *edx
)
1542 *ebx
= env
->cpuid_vendor1
;
1543 *edx
= env
->cpuid_vendor2
;
1544 *ecx
= env
->cpuid_vendor3
;
1546 /* sysenter isn't supported on compatibility mode on AMD, syscall
1547 * isn't supported in compatibility mode on Intel.
1548 * Normally we advertise the actual cpu vendor, but you can override
1549 * this if you want to use KVM's sysenter/syscall emulation
1550 * in compatibility mode and when doing cross vendor migration
1552 if (kvm_enabled() && ! env
->cpuid_vendor_override
) {
1553 host_cpuid(0, 0, NULL
, ebx
, ecx
, edx
);
1557 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1558 uint32_t *eax
, uint32_t *ebx
,
1559 uint32_t *ecx
, uint32_t *edx
)
1561 /* test if maximum index reached */
1562 if (index
& 0x80000000) {
1563 if (index
> env
->cpuid_xlevel
) {
1564 if (env
->cpuid_xlevel2
> 0) {
1565 /* Handle the Centaur's CPUID instruction. */
1566 if (index
> env
->cpuid_xlevel2
) {
1567 index
= env
->cpuid_xlevel2
;
1568 } else if (index
< 0xC0000000) {
1569 index
= env
->cpuid_xlevel
;
1572 index
= env
->cpuid_xlevel
;
1576 if (index
> env
->cpuid_level
)
1577 index
= env
->cpuid_level
;
1582 *eax
= env
->cpuid_level
;
1583 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
1586 *eax
= env
->cpuid_version
;
1587 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1588 *ecx
= env
->cpuid_ext_features
;
1589 *edx
= env
->cpuid_features
;
1590 if (env
->nr_cores
* env
->nr_threads
> 1) {
1591 *ebx
|= (env
->nr_cores
* env
->nr_threads
) << 16;
1592 *edx
|= 1 << 28; /* HTT bit */
1596 /* cache info: needed for Pentium Pro compatibility */
1603 /* cache info: needed for Core compatibility */
1604 if (env
->nr_cores
> 1) {
1605 *eax
= (env
->nr_cores
- 1) << 26;
1610 case 0: /* L1 dcache info */
1616 case 1: /* L1 icache info */
1622 case 2: /* L2 cache info */
1624 if (env
->nr_threads
> 1) {
1625 *eax
|= (env
->nr_threads
- 1) << 14;
1631 default: /* end of info */
1640 /* mwait info: needed for Core compatibility */
1641 *eax
= 0; /* Smallest monitor-line size in bytes */
1642 *ebx
= 0; /* Largest monitor-line size in bytes */
1643 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
1647 /* Thermal and Power Leaf */
1654 /* Structured Extended Feature Flags Enumeration Leaf */
1656 *eax
= 0; /* Maximum ECX value for sub-leaves */
1657 *ebx
= env
->cpuid_7_0_ebx
; /* Feature flags */
1658 *ecx
= 0; /* Reserved */
1659 *edx
= 0; /* Reserved */
1668 /* Direct Cache Access Information Leaf */
1669 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
1675 /* Architectural Performance Monitoring Leaf */
1676 if (kvm_enabled()) {
1677 KVMState
*s
= env
->kvm_state
;
1679 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
1680 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
1681 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
1682 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
1691 /* Processor Extended State */
1692 if (!(env
->cpuid_ext_features
& CPUID_EXT_XSAVE
)) {
1699 if (kvm_enabled()) {
1700 KVMState
*s
= env
->kvm_state
;
1702 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EAX
);
1703 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EBX
);
1704 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_ECX
);
1705 *edx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EDX
);
1714 *eax
= env
->cpuid_xlevel
;
1715 *ebx
= env
->cpuid_vendor1
;
1716 *edx
= env
->cpuid_vendor2
;
1717 *ecx
= env
->cpuid_vendor3
;
1720 *eax
= env
->cpuid_version
;
1722 *ecx
= env
->cpuid_ext3_features
;
1723 *edx
= env
->cpuid_ext2_features
;
1725 /* The Linux kernel checks for the CMPLegacy bit and
1726 * discards multiple thread information if it is set.
1727 * So dont set it here for Intel to make Linux guests happy.
1729 if (env
->nr_cores
* env
->nr_threads
> 1) {
1730 uint32_t tebx
, tecx
, tedx
;
1731 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
1732 if (tebx
!= CPUID_VENDOR_INTEL_1
||
1733 tedx
!= CPUID_VENDOR_INTEL_2
||
1734 tecx
!= CPUID_VENDOR_INTEL_3
) {
1735 *ecx
|= 1 << 1; /* CmpLegacy bit */
1742 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
1743 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
1744 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
1745 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
1748 /* cache info (L1 cache) */
1755 /* cache info (L2 cache) */
1762 /* virtual & phys address size in low 2 bytes. */
1763 /* XXX: This value must match the one used in the MMU code. */
1764 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
1765 /* 64 bit processor */
1766 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1767 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
1769 if (env
->cpuid_features
& CPUID_PSE36
)
1770 *eax
= 0x00000024; /* 36 bits physical */
1772 *eax
= 0x00000020; /* 32 bits physical */
1777 if (env
->nr_cores
* env
->nr_threads
> 1) {
1778 *ecx
|= (env
->nr_cores
* env
->nr_threads
) - 1;
1782 if (env
->cpuid_ext3_features
& CPUID_EXT3_SVM
) {
1783 *eax
= 0x00000001; /* SVM Revision */
1784 *ebx
= 0x00000010; /* nr of ASIDs */
1786 *edx
= env
->cpuid_svm_features
; /* optional features */
1795 *eax
= env
->cpuid_xlevel2
;
1801 /* Support for VIA CPU's CPUID instruction */
1802 *eax
= env
->cpuid_version
;
1805 *edx
= env
->cpuid_ext4_features
;
1810 /* Reserved for the future, and now filled with zero */
1817 /* reserved values: zero */
1826 /* CPUClass::reset() */
1827 static void x86_cpu_reset(CPUState
*s
)
1829 X86CPU
*cpu
= X86_CPU(s
);
1830 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
1831 CPUX86State
*env
= &cpu
->env
;
1834 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1835 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1836 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
1839 xcc
->parent_reset(s
);
1842 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
1846 env
->old_exception
= -1;
1848 /* init to reset state */
1850 #ifdef CONFIG_SOFTMMU
1851 env
->hflags
|= HF_SOFTMMU_MASK
;
1853 env
->hflags2
|= HF2_GIF_MASK
;
1855 cpu_x86_update_cr0(env
, 0x60000010);
1856 env
->a20_mask
= ~0x0;
1857 env
->smbase
= 0x30000;
1859 env
->idt
.limit
= 0xffff;
1860 env
->gdt
.limit
= 0xffff;
1861 env
->ldt
.limit
= 0xffff;
1862 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
1863 env
->tr
.limit
= 0xffff;
1864 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
1866 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
1867 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
1868 DESC_R_MASK
| DESC_A_MASK
);
1869 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
1870 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1872 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
1873 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1875 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
1876 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1878 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
1879 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1881 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
1882 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1886 env
->regs
[R_EDX
] = env
->cpuid_version
;
1891 for (i
= 0; i
< 8; i
++) {
1896 env
->mxcsr
= 0x1f80;
1898 env
->pat
= 0x0007040600070406ULL
;
1899 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
1901 memset(env
->dr
, 0, sizeof(env
->dr
));
1902 env
->dr
[6] = DR6_FIXED_1
;
1903 env
->dr
[7] = DR7_FIXED_1
;
1904 cpu_breakpoint_remove_all(env
, BP_CPU
);
1905 cpu_watchpoint_remove_all(env
, BP_CPU
);
1907 #if !defined(CONFIG_USER_ONLY)
1908 /* We hard-wire the BSP to the first CPU. */
1909 if (env
->cpu_index
== 0) {
1910 apic_designate_bsp(env
->apic_state
);
1913 env
->halted
= !cpu_is_bsp(cpu
);
1917 #ifndef CONFIG_USER_ONLY
1918 bool cpu_is_bsp(X86CPU
*cpu
)
1920 return cpu_get_apic_base(cpu
->env
.apic_state
) & MSR_IA32_APICBASE_BSP
;
1923 /* TODO: remove me, when reset over QOM tree is implemented */
1924 static void x86_cpu_machine_reset_cb(void *opaque
)
1926 X86CPU
*cpu
= opaque
;
1927 cpu_reset(CPU(cpu
));
1931 static void mce_init(X86CPU
*cpu
)
1933 CPUX86State
*cenv
= &cpu
->env
;
1936 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
1937 && (cenv
->cpuid_features
& (CPUID_MCE
| CPUID_MCA
)) ==
1938 (CPUID_MCE
| CPUID_MCA
)) {
1939 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
1940 cenv
->mcg_ctl
= ~(uint64_t)0;
1941 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
1942 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
1947 void x86_cpu_realize(Object
*obj
, Error
**errp
)
1949 X86CPU
*cpu
= X86_CPU(obj
);
1951 #ifndef CONFIG_USER_ONLY
1952 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
1956 qemu_init_vcpu(&cpu
->env
);
1957 cpu_reset(CPU(cpu
));
1960 static void x86_cpu_initfn(Object
*obj
)
1962 X86CPU
*cpu
= X86_CPU(obj
);
1963 CPUX86State
*env
= &cpu
->env
;
1968 object_property_add(obj
, "family", "int",
1969 x86_cpuid_version_get_family
,
1970 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
1971 object_property_add(obj
, "model", "int",
1972 x86_cpuid_version_get_model
,
1973 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
1974 object_property_add(obj
, "stepping", "int",
1975 x86_cpuid_version_get_stepping
,
1976 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
1977 object_property_add(obj
, "level", "int",
1978 x86_cpuid_get_level
,
1979 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
1980 object_property_add(obj
, "xlevel", "int",
1981 x86_cpuid_get_xlevel
,
1982 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
1983 object_property_add_str(obj
, "vendor",
1984 x86_cpuid_get_vendor
,
1985 x86_cpuid_set_vendor
, NULL
);
1986 object_property_add_str(obj
, "model-id",
1987 x86_cpuid_get_model_id
,
1988 x86_cpuid_set_model_id
, NULL
);
1989 object_property_add(obj
, "tsc-frequency", "int",
1990 x86_cpuid_get_tsc_freq
,
1991 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
1993 env
->cpuid_apic_id
= env
->cpu_index
;
1995 /* init various static tables used in TCG mode */
1996 if (tcg_enabled() && !inited
) {
1998 optimize_flags_init();
1999 #ifndef CONFIG_USER_ONLY
2000 cpu_set_debug_excp_handler(breakpoint_handler
);
2005 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
2007 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2008 CPUClass
*cc
= CPU_CLASS(oc
);
2010 xcc
->parent_reset
= cc
->reset
;
2011 cc
->reset
= x86_cpu_reset
;
2014 static const TypeInfo x86_cpu_type_info
= {
2015 .name
= TYPE_X86_CPU
,
2017 .instance_size
= sizeof(X86CPU
),
2018 .instance_init
= x86_cpu_initfn
,
2020 .class_size
= sizeof(X86CPUClass
),
2021 .class_init
= x86_cpu_common_class_init
,
2024 static void x86_cpu_register_types(void)
2026 type_register_static(&x86_cpu_type_info
);
2029 type_init(x86_cpu_register_types
)