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target-i386: Drop redundant list of CPU definitions
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "topology.h"
28
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi/visitor.h"
34 #include "sysemu/arch_init.h"
35
36 #include "hyperv.h"
37
38 #include "hw/hw.h"
39 #if defined(CONFIG_KVM)
40 #include <linux/kvm_para.h>
41 #endif
42
43 #include "sysemu/sysemu.h"
44 #ifndef CONFIG_USER_ONLY
45 #include "hw/xen.h"
46 #include "hw/sysbus.h"
47 #include "hw/apic_internal.h"
48 #endif
49
50 /* feature flags taken from "Intel Processor Identification and the CPUID
51 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
52 * between feature naming conventions, aliases may be added.
53 */
54 static const char *feature_name[] = {
55 "fpu", "vme", "de", "pse",
56 "tsc", "msr", "pae", "mce",
57 "cx8", "apic", NULL, "sep",
58 "mtrr", "pge", "mca", "cmov",
59 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
60 NULL, "ds" /* Intel dts */, "acpi", "mmx",
61 "fxsr", "sse", "sse2", "ss",
62 "ht" /* Intel htt */, "tm", "ia64", "pbe",
63 };
64 static const char *ext_feature_name[] = {
65 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
66 "ds_cpl", "vmx", "smx", "est",
67 "tm2", "ssse3", "cid", NULL,
68 "fma", "cx16", "xtpr", "pdcm",
69 NULL, "pcid", "dca", "sse4.1|sse4_1",
70 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
71 "tsc-deadline", "aes", "xsave", "osxsave",
72 "avx", "f16c", "rdrand", "hypervisor",
73 };
74 /* Feature names that are already defined on feature_name[] but are set on
75 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
76 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
77 * if and only if CPU vendor is AMD.
78 */
79 static const char *ext2_feature_name[] = {
80 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
81 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
82 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
83 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
84 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
85 "nx|xd", NULL, "mmxext", NULL /* mmx */,
86 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
87 NULL, "lm|i64", "3dnowext", "3dnow",
88 };
89 static const char *ext3_feature_name[] = {
90 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
91 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
92 "3dnowprefetch", "osvw", "ibs", "xop",
93 "skinit", "wdt", NULL, "lwp",
94 "fma4", "tce", NULL, "nodeid_msr",
95 NULL, "tbm", "topoext", "perfctr_core",
96 "perfctr_nb", NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98 };
99
100 static const char *ext4_feature_name[] = {
101 NULL, NULL, "xstore", "xstore-en",
102 NULL, NULL, "xcrypt", "xcrypt-en",
103 "ace2", "ace2-en", "phe", "phe-en",
104 "pmm", "pmm-en", NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 NULL, NULL, NULL, NULL,
108 NULL, NULL, NULL, NULL,
109 };
110
111 static const char *kvm_feature_name[] = {
112 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
113 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 NULL, NULL, NULL, NULL,
119 NULL, NULL, NULL, NULL,
120 };
121
122 static const char *svm_feature_name[] = {
123 "npt", "lbrv", "svm_lock", "nrip_save",
124 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
125 NULL, NULL, "pause_filter", NULL,
126 "pfthreshold", NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 NULL, NULL, NULL, NULL,
130 NULL, NULL, NULL, NULL,
131 };
132
133 static const char *cpuid_7_0_ebx_feature_name[] = {
134 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
135 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
136 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
137 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
138 };
139
140 typedef struct FeatureWordInfo {
141 const char **feat_names;
142 uint32_t cpuid_eax; /* Input EAX for CPUID */
143 int cpuid_reg; /* R_* register constant */
144 } FeatureWordInfo;
145
146 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
147 [FEAT_1_EDX] = {
148 .feat_names = feature_name,
149 .cpuid_eax = 1, .cpuid_reg = R_EDX,
150 },
151 [FEAT_1_ECX] = {
152 .feat_names = ext_feature_name,
153 .cpuid_eax = 1, .cpuid_reg = R_ECX,
154 },
155 [FEAT_8000_0001_EDX] = {
156 .feat_names = ext2_feature_name,
157 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
158 },
159 [FEAT_8000_0001_ECX] = {
160 .feat_names = ext3_feature_name,
161 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
162 },
163 [FEAT_C000_0001_EDX] = {
164 .feat_names = ext4_feature_name,
165 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
166 },
167 [FEAT_KVM] = {
168 .feat_names = kvm_feature_name,
169 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
170 },
171 [FEAT_SVM] = {
172 .feat_names = svm_feature_name,
173 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
174 },
175 [FEAT_7_0_EBX] = {
176 .feat_names = cpuid_7_0_ebx_feature_name,
177 .cpuid_eax = 7, .cpuid_reg = R_EBX,
178 },
179 };
180
181 const char *get_register_name_32(unsigned int reg)
182 {
183 static const char *reg_names[CPU_NB_REGS32] = {
184 [R_EAX] = "EAX",
185 [R_ECX] = "ECX",
186 [R_EDX] = "EDX",
187 [R_EBX] = "EBX",
188 [R_ESP] = "ESP",
189 [R_EBP] = "EBP",
190 [R_ESI] = "ESI",
191 [R_EDI] = "EDI",
192 };
193
194 if (reg > CPU_NB_REGS32) {
195 return NULL;
196 }
197 return reg_names[reg];
198 }
199
200 /* collects per-function cpuid data
201 */
202 typedef struct model_features_t {
203 uint32_t *guest_feat;
204 uint32_t *host_feat;
205 FeatureWord feat_word;
206 } model_features_t;
207
208 int check_cpuid = 0;
209 int enforce_cpuid = 0;
210
211 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
212 (1 << KVM_FEATURE_NOP_IO_DELAY) |
213 (1 << KVM_FEATURE_CLOCKSOURCE2) |
214 (1 << KVM_FEATURE_ASYNC_PF) |
215 (1 << KVM_FEATURE_STEAL_TIME) |
216 (1 << KVM_FEATURE_PV_EOI) |
217 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
218
219 void disable_kvm_pv_eoi(void)
220 {
221 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
222 }
223
224 void host_cpuid(uint32_t function, uint32_t count,
225 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
226 {
227 #if defined(CONFIG_KVM)
228 uint32_t vec[4];
229
230 #ifdef __x86_64__
231 asm volatile("cpuid"
232 : "=a"(vec[0]), "=b"(vec[1]),
233 "=c"(vec[2]), "=d"(vec[3])
234 : "0"(function), "c"(count) : "cc");
235 #else
236 asm volatile("pusha \n\t"
237 "cpuid \n\t"
238 "mov %%eax, 0(%2) \n\t"
239 "mov %%ebx, 4(%2) \n\t"
240 "mov %%ecx, 8(%2) \n\t"
241 "mov %%edx, 12(%2) \n\t"
242 "popa"
243 : : "a"(function), "c"(count), "S"(vec)
244 : "memory", "cc");
245 #endif
246
247 if (eax)
248 *eax = vec[0];
249 if (ebx)
250 *ebx = vec[1];
251 if (ecx)
252 *ecx = vec[2];
253 if (edx)
254 *edx = vec[3];
255 #endif
256 }
257
258 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
259
260 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
261 * a substring. ex if !NULL points to the first char after a substring,
262 * otherwise the string is assumed to sized by a terminating nul.
263 * Return lexical ordering of *s1:*s2.
264 */
265 static int sstrcmp(const char *s1, const char *e1, const char *s2,
266 const char *e2)
267 {
268 for (;;) {
269 if (!*s1 || !*s2 || *s1 != *s2)
270 return (*s1 - *s2);
271 ++s1, ++s2;
272 if (s1 == e1 && s2 == e2)
273 return (0);
274 else if (s1 == e1)
275 return (*s2);
276 else if (s2 == e2)
277 return (*s1);
278 }
279 }
280
281 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
282 * '|' delimited (possibly empty) strings in which case search for a match
283 * within the alternatives proceeds left to right. Return 0 for success,
284 * non-zero otherwise.
285 */
286 static int altcmp(const char *s, const char *e, const char *altstr)
287 {
288 const char *p, *q;
289
290 for (q = p = altstr; ; ) {
291 while (*p && *p != '|')
292 ++p;
293 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
294 return (0);
295 if (!*p)
296 return (1);
297 else
298 q = ++p;
299 }
300 }
301
302 /* search featureset for flag *[s..e), if found set corresponding bit in
303 * *pval and return true, otherwise return false
304 */
305 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
306 const char **featureset)
307 {
308 uint32_t mask;
309 const char **ppc;
310 bool found = false;
311
312 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
313 if (*ppc && !altcmp(s, e, *ppc)) {
314 *pval |= mask;
315 found = true;
316 }
317 }
318 return found;
319 }
320
321 static void add_flagname_to_bitmaps(const char *flagname,
322 FeatureWordArray words)
323 {
324 FeatureWord w;
325 for (w = 0; w < FEATURE_WORDS; w++) {
326 FeatureWordInfo *wi = &feature_word_info[w];
327 if (wi->feat_names &&
328 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
329 break;
330 }
331 }
332 if (w == FEATURE_WORDS) {
333 fprintf(stderr, "CPU feature %s not found\n", flagname);
334 }
335 }
336
337 typedef struct x86_def_t {
338 const char *name;
339 uint32_t level;
340 uint32_t vendor1, vendor2, vendor3;
341 int family;
342 int model;
343 int stepping;
344 int tsc_khz;
345 uint32_t features, ext_features, ext2_features, ext3_features;
346 uint32_t kvm_features, svm_features;
347 uint32_t xlevel;
348 char model_id[48];
349 int vendor_override;
350 /* Store the results of Centaur's CPUID instructions */
351 uint32_t ext4_features;
352 uint32_t xlevel2;
353 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
354 uint32_t cpuid_7_0_ebx_features;
355 } x86_def_t;
356
357 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
358 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
359 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
360 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
361 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
362 CPUID_PSE36 | CPUID_FXSR)
363 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
364 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
365 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
366 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
367 CPUID_PAE | CPUID_SEP | CPUID_APIC)
368
369 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
370 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
371 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
372 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
373 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
374 /* partly implemented:
375 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
376 CPUID_PSE36 (needed for Solaris) */
377 /* missing:
378 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
379 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
380 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
381 CPUID_EXT_HYPERVISOR)
382 /* missing:
383 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
384 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
385 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
386 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
387 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
388 /* missing:
389 CPUID_EXT2_PDPE1GB */
390 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
391 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
392 #define TCG_SVM_FEATURES 0
393 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
394
395 /* built-in CPU model definitions
396 */
397 static x86_def_t builtin_x86_defs[] = {
398 {
399 .name = "qemu64",
400 .level = 4,
401 .vendor1 = CPUID_VENDOR_AMD_1,
402 .vendor2 = CPUID_VENDOR_AMD_2,
403 .vendor3 = CPUID_VENDOR_AMD_3,
404 .family = 6,
405 .model = 2,
406 .stepping = 3,
407 .features = PPRO_FEATURES |
408 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
409 CPUID_PSE36,
410 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
411 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
412 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
413 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
414 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
415 .xlevel = 0x8000000A,
416 },
417 {
418 .name = "phenom",
419 .level = 5,
420 .vendor1 = CPUID_VENDOR_AMD_1,
421 .vendor2 = CPUID_VENDOR_AMD_2,
422 .vendor3 = CPUID_VENDOR_AMD_3,
423 .family = 16,
424 .model = 2,
425 .stepping = 3,
426 .features = PPRO_FEATURES |
427 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
428 CPUID_PSE36 | CPUID_VME | CPUID_HT,
429 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
430 CPUID_EXT_POPCNT,
431 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
432 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
433 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
434 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
435 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
436 CPUID_EXT3_CR8LEG,
437 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
438 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
439 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
440 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
441 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
442 .xlevel = 0x8000001A,
443 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
444 },
445 {
446 .name = "core2duo",
447 .level = 10,
448 .vendor1 = CPUID_VENDOR_INTEL_1,
449 .vendor2 = CPUID_VENDOR_INTEL_2,
450 .vendor3 = CPUID_VENDOR_INTEL_3,
451 .family = 6,
452 .model = 15,
453 .stepping = 11,
454 .features = PPRO_FEATURES |
455 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
456 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
457 CPUID_HT | CPUID_TM | CPUID_PBE,
458 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
459 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
460 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
461 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
462 .ext3_features = CPUID_EXT3_LAHF_LM,
463 .xlevel = 0x80000008,
464 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
465 },
466 {
467 .name = "kvm64",
468 .level = 5,
469 .vendor1 = CPUID_VENDOR_INTEL_1,
470 .vendor2 = CPUID_VENDOR_INTEL_2,
471 .vendor3 = CPUID_VENDOR_INTEL_3,
472 .family = 15,
473 .model = 6,
474 .stepping = 1,
475 /* Missing: CPUID_VME, CPUID_HT */
476 .features = PPRO_FEATURES |
477 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
478 CPUID_PSE36,
479 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
480 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
481 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
482 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
483 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
484 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
485 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
486 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
487 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
488 .ext3_features = 0,
489 .xlevel = 0x80000008,
490 .model_id = "Common KVM processor"
491 },
492 {
493 .name = "qemu32",
494 .level = 4,
495 .vendor1 = CPUID_VENDOR_INTEL_1,
496 .vendor2 = CPUID_VENDOR_INTEL_2,
497 .vendor3 = CPUID_VENDOR_INTEL_3,
498 .family = 6,
499 .model = 3,
500 .stepping = 3,
501 .features = PPRO_FEATURES,
502 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
503 .xlevel = 0x80000004,
504 },
505 {
506 .name = "kvm32",
507 .level = 5,
508 .vendor1 = CPUID_VENDOR_INTEL_1,
509 .vendor2 = CPUID_VENDOR_INTEL_2,
510 .vendor3 = CPUID_VENDOR_INTEL_3,
511 .family = 15,
512 .model = 6,
513 .stepping = 1,
514 .features = PPRO_FEATURES |
515 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
516 .ext_features = CPUID_EXT_SSE3,
517 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
518 .ext3_features = 0,
519 .xlevel = 0x80000008,
520 .model_id = "Common 32-bit KVM processor"
521 },
522 {
523 .name = "coreduo",
524 .level = 10,
525 .vendor1 = CPUID_VENDOR_INTEL_1,
526 .vendor2 = CPUID_VENDOR_INTEL_2,
527 .vendor3 = CPUID_VENDOR_INTEL_3,
528 .family = 6,
529 .model = 14,
530 .stepping = 8,
531 .features = PPRO_FEATURES | CPUID_VME |
532 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
533 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
534 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
535 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
536 .ext2_features = CPUID_EXT2_NX,
537 .xlevel = 0x80000008,
538 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
539 },
540 {
541 .name = "486",
542 .level = 1,
543 .vendor1 = CPUID_VENDOR_INTEL_1,
544 .vendor2 = CPUID_VENDOR_INTEL_2,
545 .vendor3 = CPUID_VENDOR_INTEL_3,
546 .family = 4,
547 .model = 0,
548 .stepping = 0,
549 .features = I486_FEATURES,
550 .xlevel = 0,
551 },
552 {
553 .name = "pentium",
554 .level = 1,
555 .vendor1 = CPUID_VENDOR_INTEL_1,
556 .vendor2 = CPUID_VENDOR_INTEL_2,
557 .vendor3 = CPUID_VENDOR_INTEL_3,
558 .family = 5,
559 .model = 4,
560 .stepping = 3,
561 .features = PENTIUM_FEATURES,
562 .xlevel = 0,
563 },
564 {
565 .name = "pentium2",
566 .level = 2,
567 .vendor1 = CPUID_VENDOR_INTEL_1,
568 .vendor2 = CPUID_VENDOR_INTEL_2,
569 .vendor3 = CPUID_VENDOR_INTEL_3,
570 .family = 6,
571 .model = 5,
572 .stepping = 2,
573 .features = PENTIUM2_FEATURES,
574 .xlevel = 0,
575 },
576 {
577 .name = "pentium3",
578 .level = 2,
579 .vendor1 = CPUID_VENDOR_INTEL_1,
580 .vendor2 = CPUID_VENDOR_INTEL_2,
581 .vendor3 = CPUID_VENDOR_INTEL_3,
582 .family = 6,
583 .model = 7,
584 .stepping = 3,
585 .features = PENTIUM3_FEATURES,
586 .xlevel = 0,
587 },
588 {
589 .name = "athlon",
590 .level = 2,
591 .vendor1 = CPUID_VENDOR_AMD_1,
592 .vendor2 = CPUID_VENDOR_AMD_2,
593 .vendor3 = CPUID_VENDOR_AMD_3,
594 .family = 6,
595 .model = 2,
596 .stepping = 3,
597 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
598 CPUID_MCA,
599 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
600 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
601 .xlevel = 0x80000008,
602 },
603 {
604 .name = "n270",
605 /* original is on level 10 */
606 .level = 5,
607 .vendor1 = CPUID_VENDOR_INTEL_1,
608 .vendor2 = CPUID_VENDOR_INTEL_2,
609 .vendor3 = CPUID_VENDOR_INTEL_3,
610 .family = 6,
611 .model = 28,
612 .stepping = 2,
613 .features = PPRO_FEATURES |
614 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
615 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
616 /* Some CPUs got no CPUID_SEP */
617 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
618 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
619 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
620 CPUID_EXT2_NX,
621 .ext3_features = CPUID_EXT3_LAHF_LM,
622 .xlevel = 0x8000000A,
623 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
624 },
625 {
626 .name = "Conroe",
627 .level = 2,
628 .vendor1 = CPUID_VENDOR_INTEL_1,
629 .vendor2 = CPUID_VENDOR_INTEL_2,
630 .vendor3 = CPUID_VENDOR_INTEL_3,
631 .family = 6,
632 .model = 2,
633 .stepping = 3,
634 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
635 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
636 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
637 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
638 CPUID_DE | CPUID_FP87,
639 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
640 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
641 .ext3_features = CPUID_EXT3_LAHF_LM,
642 .xlevel = 0x8000000A,
643 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
644 },
645 {
646 .name = "Penryn",
647 .level = 2,
648 .vendor1 = CPUID_VENDOR_INTEL_1,
649 .vendor2 = CPUID_VENDOR_INTEL_2,
650 .vendor3 = CPUID_VENDOR_INTEL_3,
651 .family = 6,
652 .model = 2,
653 .stepping = 3,
654 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
655 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
656 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
657 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
658 CPUID_DE | CPUID_FP87,
659 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
660 CPUID_EXT_SSE3,
661 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
662 .ext3_features = CPUID_EXT3_LAHF_LM,
663 .xlevel = 0x8000000A,
664 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
665 },
666 {
667 .name = "Nehalem",
668 .level = 2,
669 .vendor1 = CPUID_VENDOR_INTEL_1,
670 .vendor2 = CPUID_VENDOR_INTEL_2,
671 .vendor3 = CPUID_VENDOR_INTEL_3,
672 .family = 6,
673 .model = 2,
674 .stepping = 3,
675 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
676 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
677 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
678 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
679 CPUID_DE | CPUID_FP87,
680 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
681 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
682 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
683 .ext3_features = CPUID_EXT3_LAHF_LM,
684 .xlevel = 0x8000000A,
685 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
686 },
687 {
688 .name = "Westmere",
689 .level = 11,
690 .vendor1 = CPUID_VENDOR_INTEL_1,
691 .vendor2 = CPUID_VENDOR_INTEL_2,
692 .vendor3 = CPUID_VENDOR_INTEL_3,
693 .family = 6,
694 .model = 44,
695 .stepping = 1,
696 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
697 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
698 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
699 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
700 CPUID_DE | CPUID_FP87,
701 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
702 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
703 CPUID_EXT_SSE3,
704 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
705 .ext3_features = CPUID_EXT3_LAHF_LM,
706 .xlevel = 0x8000000A,
707 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
708 },
709 {
710 .name = "SandyBridge",
711 .level = 0xd,
712 .vendor1 = CPUID_VENDOR_INTEL_1,
713 .vendor2 = CPUID_VENDOR_INTEL_2,
714 .vendor3 = CPUID_VENDOR_INTEL_3,
715 .family = 6,
716 .model = 42,
717 .stepping = 1,
718 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
722 CPUID_DE | CPUID_FP87,
723 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
724 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
725 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
726 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
727 CPUID_EXT_SSE3,
728 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
729 CPUID_EXT2_SYSCALL,
730 .ext3_features = CPUID_EXT3_LAHF_LM,
731 .xlevel = 0x8000000A,
732 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
733 },
734 {
735 .name = "Haswell",
736 .level = 0xd,
737 .vendor1 = CPUID_VENDOR_INTEL_1,
738 .vendor2 = CPUID_VENDOR_INTEL_2,
739 .vendor3 = CPUID_VENDOR_INTEL_3,
740 .family = 6,
741 .model = 60,
742 .stepping = 1,
743 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
744 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
745 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
746 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
747 CPUID_DE | CPUID_FP87,
748 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
749 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
750 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
751 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
752 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
753 CPUID_EXT_PCID,
754 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
755 CPUID_EXT2_SYSCALL,
756 .ext3_features = CPUID_EXT3_LAHF_LM,
757 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
758 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
759 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
760 CPUID_7_0_EBX_RTM,
761 .xlevel = 0x8000000A,
762 .model_id = "Intel Core Processor (Haswell)",
763 },
764 {
765 .name = "Opteron_G1",
766 .level = 5,
767 .vendor1 = CPUID_VENDOR_AMD_1,
768 .vendor2 = CPUID_VENDOR_AMD_2,
769 .vendor3 = CPUID_VENDOR_AMD_3,
770 .family = 15,
771 .model = 6,
772 .stepping = 1,
773 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
774 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
775 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
776 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
777 CPUID_DE | CPUID_FP87,
778 .ext_features = CPUID_EXT_SSE3,
779 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
780 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
781 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
782 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
783 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
784 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
785 .xlevel = 0x80000008,
786 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
787 },
788 {
789 .name = "Opteron_G2",
790 .level = 5,
791 .vendor1 = CPUID_VENDOR_AMD_1,
792 .vendor2 = CPUID_VENDOR_AMD_2,
793 .vendor3 = CPUID_VENDOR_AMD_3,
794 .family = 15,
795 .model = 6,
796 .stepping = 1,
797 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
801 CPUID_DE | CPUID_FP87,
802 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
803 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
804 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
805 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
806 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
807 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
808 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
809 CPUID_EXT2_DE | CPUID_EXT2_FPU,
810 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
811 .xlevel = 0x80000008,
812 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
813 },
814 {
815 .name = "Opteron_G3",
816 .level = 5,
817 .vendor1 = CPUID_VENDOR_AMD_1,
818 .vendor2 = CPUID_VENDOR_AMD_2,
819 .vendor3 = CPUID_VENDOR_AMD_3,
820 .family = 15,
821 .model = 6,
822 .stepping = 1,
823 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
824 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
825 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
826 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
827 CPUID_DE | CPUID_FP87,
828 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
829 CPUID_EXT_SSE3,
830 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
831 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
832 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
833 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
834 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
835 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
836 CPUID_EXT2_DE | CPUID_EXT2_FPU,
837 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
838 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
839 .xlevel = 0x80000008,
840 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
841 },
842 {
843 .name = "Opteron_G4",
844 .level = 0xd,
845 .vendor1 = CPUID_VENDOR_AMD_1,
846 .vendor2 = CPUID_VENDOR_AMD_2,
847 .vendor3 = CPUID_VENDOR_AMD_3,
848 .family = 21,
849 .model = 1,
850 .stepping = 2,
851 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
852 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
853 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
854 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
855 CPUID_DE | CPUID_FP87,
856 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
857 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
858 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
859 CPUID_EXT_SSE3,
860 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
861 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
862 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
863 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
864 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
865 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
866 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
867 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
868 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
869 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
870 CPUID_EXT3_LAHF_LM,
871 .xlevel = 0x8000001A,
872 .model_id = "AMD Opteron 62xx class CPU",
873 },
874 {
875 .name = "Opteron_G5",
876 .level = 0xd,
877 .vendor1 = CPUID_VENDOR_AMD_1,
878 .vendor2 = CPUID_VENDOR_AMD_2,
879 .vendor3 = CPUID_VENDOR_AMD_3,
880 .family = 21,
881 .model = 2,
882 .stepping = 0,
883 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
887 CPUID_DE | CPUID_FP87,
888 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
889 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
890 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
891 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
892 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
893 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
894 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
895 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
896 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
897 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
898 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
899 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
900 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
901 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
902 CPUID_EXT3_LAHF_LM,
903 .xlevel = 0x8000001A,
904 .model_id = "AMD Opteron 63xx class CPU",
905 },
906 };
907
908 #ifdef CONFIG_KVM
909 static int cpu_x86_fill_model_id(char *str)
910 {
911 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
912 int i;
913
914 for (i = 0; i < 3; i++) {
915 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
916 memcpy(str + i * 16 + 0, &eax, 4);
917 memcpy(str + i * 16 + 4, &ebx, 4);
918 memcpy(str + i * 16 + 8, &ecx, 4);
919 memcpy(str + i * 16 + 12, &edx, 4);
920 }
921 return 0;
922 }
923 #endif
924
925 /* Fill a x86_def_t struct with information about the host CPU, and
926 * the CPU features supported by the host hardware + host kernel
927 *
928 * This function may be called only if KVM is enabled.
929 */
930 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
931 {
932 #ifdef CONFIG_KVM
933 KVMState *s = kvm_state;
934 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
935
936 assert(kvm_enabled());
937
938 x86_cpu_def->name = "host";
939 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
940 x86_cpu_def->vendor1 = ebx;
941 x86_cpu_def->vendor2 = edx;
942 x86_cpu_def->vendor3 = ecx;
943
944 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
945 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
946 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
947 x86_cpu_def->stepping = eax & 0x0F;
948
949 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
950 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
951 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
952
953 if (x86_cpu_def->level >= 7) {
954 x86_cpu_def->cpuid_7_0_ebx_features =
955 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
956 } else {
957 x86_cpu_def->cpuid_7_0_ebx_features = 0;
958 }
959
960 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
961 x86_cpu_def->ext2_features =
962 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
963 x86_cpu_def->ext3_features =
964 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
965
966 cpu_x86_fill_model_id(x86_cpu_def->model_id);
967 x86_cpu_def->vendor_override = 0;
968
969 /* Call Centaur's CPUID instruction. */
970 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
971 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
972 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
973 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
974 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
975 if (eax >= 0xC0000001) {
976 /* Support VIA max extended level */
977 x86_cpu_def->xlevel2 = eax;
978 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
979 x86_cpu_def->ext4_features =
980 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
981 }
982 }
983
984 /* Other KVM-specific feature fields: */
985 x86_cpu_def->svm_features =
986 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
987 x86_cpu_def->kvm_features =
988 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
989
990 #endif /* CONFIG_KVM */
991 }
992
993 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
994 {
995 int i;
996
997 for (i = 0; i < 32; ++i)
998 if (1 << i & mask) {
999 const char *reg = get_register_name_32(f->cpuid_reg);
1000 assert(reg);
1001 fprintf(stderr, "warning: host doesn't support requested feature: "
1002 "CPUID.%02XH:%s%s%s [bit %d]\n",
1003 f->cpuid_eax, reg,
1004 f->feat_names[i] ? "." : "",
1005 f->feat_names[i] ? f->feat_names[i] : "", i);
1006 break;
1007 }
1008 return 0;
1009 }
1010
1011 /* Check if all requested cpu flags are making their way to the guest
1012 *
1013 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1014 *
1015 * This function may be called only if KVM is enabled.
1016 */
1017 static int kvm_check_features_against_host(X86CPU *cpu)
1018 {
1019 CPUX86State *env = &cpu->env;
1020 x86_def_t host_def;
1021 uint32_t mask;
1022 int rv, i;
1023 struct model_features_t ft[] = {
1024 {&env->cpuid_features, &host_def.features,
1025 FEAT_1_EDX },
1026 {&env->cpuid_ext_features, &host_def.ext_features,
1027 FEAT_1_ECX },
1028 {&env->cpuid_ext2_features, &host_def.ext2_features,
1029 FEAT_8000_0001_EDX },
1030 {&env->cpuid_ext3_features, &host_def.ext3_features,
1031 FEAT_8000_0001_ECX },
1032 {&env->cpuid_ext4_features, &host_def.ext4_features,
1033 FEAT_C000_0001_EDX },
1034 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
1035 FEAT_7_0_EBX },
1036 {&env->cpuid_svm_features, &host_def.svm_features,
1037 FEAT_SVM },
1038 {&env->cpuid_kvm_features, &host_def.kvm_features,
1039 FEAT_KVM },
1040 };
1041
1042 assert(kvm_enabled());
1043
1044 kvm_cpu_fill_host(&host_def);
1045 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1046 FeatureWord w = ft[i].feat_word;
1047 FeatureWordInfo *wi = &feature_word_info[w];
1048 for (mask = 1; mask; mask <<= 1) {
1049 if (*ft[i].guest_feat & mask &&
1050 !(*ft[i].host_feat & mask)) {
1051 unavailable_host_feature(wi, mask);
1052 rv = 1;
1053 }
1054 }
1055 }
1056 return rv;
1057 }
1058
1059 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1060 const char *name, Error **errp)
1061 {
1062 X86CPU *cpu = X86_CPU(obj);
1063 CPUX86State *env = &cpu->env;
1064 int64_t value;
1065
1066 value = (env->cpuid_version >> 8) & 0xf;
1067 if (value == 0xf) {
1068 value += (env->cpuid_version >> 20) & 0xff;
1069 }
1070 visit_type_int(v, &value, name, errp);
1071 }
1072
1073 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1074 const char *name, Error **errp)
1075 {
1076 X86CPU *cpu = X86_CPU(obj);
1077 CPUX86State *env = &cpu->env;
1078 const int64_t min = 0;
1079 const int64_t max = 0xff + 0xf;
1080 int64_t value;
1081
1082 visit_type_int(v, &value, name, errp);
1083 if (error_is_set(errp)) {
1084 return;
1085 }
1086 if (value < min || value > max) {
1087 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1088 name ? name : "null", value, min, max);
1089 return;
1090 }
1091
1092 env->cpuid_version &= ~0xff00f00;
1093 if (value > 0x0f) {
1094 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1095 } else {
1096 env->cpuid_version |= value << 8;
1097 }
1098 }
1099
1100 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1101 const char *name, Error **errp)
1102 {
1103 X86CPU *cpu = X86_CPU(obj);
1104 CPUX86State *env = &cpu->env;
1105 int64_t value;
1106
1107 value = (env->cpuid_version >> 4) & 0xf;
1108 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1109 visit_type_int(v, &value, name, errp);
1110 }
1111
1112 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1113 const char *name, Error **errp)
1114 {
1115 X86CPU *cpu = X86_CPU(obj);
1116 CPUX86State *env = &cpu->env;
1117 const int64_t min = 0;
1118 const int64_t max = 0xff;
1119 int64_t value;
1120
1121 visit_type_int(v, &value, name, errp);
1122 if (error_is_set(errp)) {
1123 return;
1124 }
1125 if (value < min || value > max) {
1126 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1127 name ? name : "null", value, min, max);
1128 return;
1129 }
1130
1131 env->cpuid_version &= ~0xf00f0;
1132 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1133 }
1134
1135 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1136 void *opaque, const char *name,
1137 Error **errp)
1138 {
1139 X86CPU *cpu = X86_CPU(obj);
1140 CPUX86State *env = &cpu->env;
1141 int64_t value;
1142
1143 value = env->cpuid_version & 0xf;
1144 visit_type_int(v, &value, name, errp);
1145 }
1146
1147 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1148 void *opaque, const char *name,
1149 Error **errp)
1150 {
1151 X86CPU *cpu = X86_CPU(obj);
1152 CPUX86State *env = &cpu->env;
1153 const int64_t min = 0;
1154 const int64_t max = 0xf;
1155 int64_t value;
1156
1157 visit_type_int(v, &value, name, errp);
1158 if (error_is_set(errp)) {
1159 return;
1160 }
1161 if (value < min || value > max) {
1162 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1163 name ? name : "null", value, min, max);
1164 return;
1165 }
1166
1167 env->cpuid_version &= ~0xf;
1168 env->cpuid_version |= value & 0xf;
1169 }
1170
1171 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1172 const char *name, Error **errp)
1173 {
1174 X86CPU *cpu = X86_CPU(obj);
1175
1176 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1177 }
1178
1179 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1180 const char *name, Error **errp)
1181 {
1182 X86CPU *cpu = X86_CPU(obj);
1183
1184 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1185 }
1186
1187 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1188 const char *name, Error **errp)
1189 {
1190 X86CPU *cpu = X86_CPU(obj);
1191
1192 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1193 }
1194
1195 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1196 const char *name, Error **errp)
1197 {
1198 X86CPU *cpu = X86_CPU(obj);
1199
1200 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1201 }
1202
1203 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1204 {
1205 X86CPU *cpu = X86_CPU(obj);
1206 CPUX86State *env = &cpu->env;
1207 char *value;
1208 int i;
1209
1210 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1211 for (i = 0; i < 4; i++) {
1212 value[i ] = env->cpuid_vendor1 >> (8 * i);
1213 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1214 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1215 }
1216 value[CPUID_VENDOR_SZ] = '\0';
1217 return value;
1218 }
1219
1220 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1221 Error **errp)
1222 {
1223 X86CPU *cpu = X86_CPU(obj);
1224 CPUX86State *env = &cpu->env;
1225 int i;
1226
1227 if (strlen(value) != CPUID_VENDOR_SZ) {
1228 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1229 "vendor", value);
1230 return;
1231 }
1232
1233 env->cpuid_vendor1 = 0;
1234 env->cpuid_vendor2 = 0;
1235 env->cpuid_vendor3 = 0;
1236 for (i = 0; i < 4; i++) {
1237 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1238 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1239 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1240 }
1241 env->cpuid_vendor_override = 1;
1242 }
1243
1244 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1245 {
1246 X86CPU *cpu = X86_CPU(obj);
1247 CPUX86State *env = &cpu->env;
1248 char *value;
1249 int i;
1250
1251 value = g_malloc(48 + 1);
1252 for (i = 0; i < 48; i++) {
1253 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1254 }
1255 value[48] = '\0';
1256 return value;
1257 }
1258
1259 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1260 Error **errp)
1261 {
1262 X86CPU *cpu = X86_CPU(obj);
1263 CPUX86State *env = &cpu->env;
1264 int c, len, i;
1265
1266 if (model_id == NULL) {
1267 model_id = "";
1268 }
1269 len = strlen(model_id);
1270 memset(env->cpuid_model, 0, 48);
1271 for (i = 0; i < 48; i++) {
1272 if (i >= len) {
1273 c = '\0';
1274 } else {
1275 c = (uint8_t)model_id[i];
1276 }
1277 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1278 }
1279 }
1280
1281 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1282 const char *name, Error **errp)
1283 {
1284 X86CPU *cpu = X86_CPU(obj);
1285 int64_t value;
1286
1287 value = cpu->env.tsc_khz * 1000;
1288 visit_type_int(v, &value, name, errp);
1289 }
1290
1291 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1292 const char *name, Error **errp)
1293 {
1294 X86CPU *cpu = X86_CPU(obj);
1295 const int64_t min = 0;
1296 const int64_t max = INT64_MAX;
1297 int64_t value;
1298
1299 visit_type_int(v, &value, name, errp);
1300 if (error_is_set(errp)) {
1301 return;
1302 }
1303 if (value < min || value > max) {
1304 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1305 name ? name : "null", value, min, max);
1306 return;
1307 }
1308
1309 cpu->env.tsc_khz = value / 1000;
1310 }
1311
1312 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1313 {
1314 x86_def_t *def;
1315 int i;
1316
1317 if (name == NULL) {
1318 return -1;
1319 }
1320 if (kvm_enabled() && strcmp(name, "host") == 0) {
1321 kvm_cpu_fill_host(x86_cpu_def);
1322 return 0;
1323 }
1324
1325 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1326 def = &builtin_x86_defs[i];
1327 if (strcmp(name, def->name) == 0) {
1328 memcpy(x86_cpu_def, def, sizeof(*def));
1329 return 0;
1330 }
1331 }
1332
1333 return -1;
1334 }
1335
1336 /* Parse "+feature,-feature,feature=foo" CPU feature string
1337 */
1338 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1339 {
1340 unsigned int i;
1341 char *featurestr; /* Single 'key=value" string being parsed */
1342 /* Features to be added */
1343 FeatureWordArray plus_features = { 0 };
1344 /* Features to be removed */
1345 FeatureWordArray minus_features = { 0 };
1346 uint32_t numvalue;
1347
1348 featurestr = features ? strtok(features, ",") : NULL;
1349
1350 while (featurestr) {
1351 char *val;
1352 if (featurestr[0] == '+') {
1353 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1354 } else if (featurestr[0] == '-') {
1355 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1356 } else if ((val = strchr(featurestr, '='))) {
1357 *val = 0; val++;
1358 if (!strcmp(featurestr, "family")) {
1359 char *err;
1360 numvalue = strtoul(val, &err, 0);
1361 if (!*val || *err || numvalue > 0xff + 0xf) {
1362 fprintf(stderr, "bad numerical value %s\n", val);
1363 goto error;
1364 }
1365 x86_cpu_def->family = numvalue;
1366 } else if (!strcmp(featurestr, "model")) {
1367 char *err;
1368 numvalue = strtoul(val, &err, 0);
1369 if (!*val || *err || numvalue > 0xff) {
1370 fprintf(stderr, "bad numerical value %s\n", val);
1371 goto error;
1372 }
1373 x86_cpu_def->model = numvalue;
1374 } else if (!strcmp(featurestr, "stepping")) {
1375 char *err;
1376 numvalue = strtoul(val, &err, 0);
1377 if (!*val || *err || numvalue > 0xf) {
1378 fprintf(stderr, "bad numerical value %s\n", val);
1379 goto error;
1380 }
1381 x86_cpu_def->stepping = numvalue ;
1382 } else if (!strcmp(featurestr, "level")) {
1383 char *err;
1384 numvalue = strtoul(val, &err, 0);
1385 if (!*val || *err) {
1386 fprintf(stderr, "bad numerical value %s\n", val);
1387 goto error;
1388 }
1389 x86_cpu_def->level = numvalue;
1390 } else if (!strcmp(featurestr, "xlevel")) {
1391 char *err;
1392 numvalue = strtoul(val, &err, 0);
1393 if (!*val || *err) {
1394 fprintf(stderr, "bad numerical value %s\n", val);
1395 goto error;
1396 }
1397 if (numvalue < 0x80000000) {
1398 numvalue += 0x80000000;
1399 }
1400 x86_cpu_def->xlevel = numvalue;
1401 } else if (!strcmp(featurestr, "vendor")) {
1402 if (strlen(val) != 12) {
1403 fprintf(stderr, "vendor string must be 12 chars long\n");
1404 goto error;
1405 }
1406 x86_cpu_def->vendor1 = 0;
1407 x86_cpu_def->vendor2 = 0;
1408 x86_cpu_def->vendor3 = 0;
1409 for(i = 0; i < 4; i++) {
1410 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1411 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1412 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1413 }
1414 x86_cpu_def->vendor_override = 1;
1415 } else if (!strcmp(featurestr, "model_id")) {
1416 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1417 val);
1418 } else if (!strcmp(featurestr, "tsc_freq")) {
1419 int64_t tsc_freq;
1420 char *err;
1421
1422 tsc_freq = strtosz_suffix_unit(val, &err,
1423 STRTOSZ_DEFSUFFIX_B, 1000);
1424 if (tsc_freq < 0 || *err) {
1425 fprintf(stderr, "bad numerical value %s\n", val);
1426 goto error;
1427 }
1428 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1429 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1430 char *err;
1431 numvalue = strtoul(val, &err, 0);
1432 if (!*val || *err) {
1433 fprintf(stderr, "bad numerical value %s\n", val);
1434 goto error;
1435 }
1436 hyperv_set_spinlock_retries(numvalue);
1437 } else {
1438 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1439 goto error;
1440 }
1441 } else if (!strcmp(featurestr, "check")) {
1442 check_cpuid = 1;
1443 } else if (!strcmp(featurestr, "enforce")) {
1444 check_cpuid = enforce_cpuid = 1;
1445 } else if (!strcmp(featurestr, "hv_relaxed")) {
1446 hyperv_enable_relaxed_timing(true);
1447 } else if (!strcmp(featurestr, "hv_vapic")) {
1448 hyperv_enable_vapic_recommended(true);
1449 } else {
1450 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1451 goto error;
1452 }
1453 featurestr = strtok(NULL, ",");
1454 }
1455 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1456 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1457 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1458 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
1459 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
1460 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1461 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1462 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1463 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1464 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1465 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1466 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1467 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1468 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1469 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1470 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1471 return 0;
1472
1473 error:
1474 return -1;
1475 }
1476
1477 /* generate a composite string into buf of all cpuid names in featureset
1478 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1479 * if flags, suppress names undefined in featureset.
1480 */
1481 static void listflags(char *buf, int bufsize, uint32_t fbits,
1482 const char **featureset, uint32_t flags)
1483 {
1484 const char **p = &featureset[31];
1485 char *q, *b, bit;
1486 int nc;
1487
1488 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1489 *buf = '\0';
1490 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1491 if (fbits & 1 << bit && (*p || !flags)) {
1492 if (*p)
1493 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1494 else
1495 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1496 if (bufsize <= nc) {
1497 if (b) {
1498 memcpy(b, "...", sizeof("..."));
1499 }
1500 return;
1501 }
1502 q += nc;
1503 bufsize -= nc;
1504 }
1505 }
1506
1507 /* generate CPU information. */
1508 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1509 {
1510 x86_def_t *def;
1511 char buf[256];
1512 int i;
1513
1514 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1515 def = &builtin_x86_defs[i];
1516 snprintf(buf, sizeof(buf), "%s", def->name);
1517 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1518 }
1519 if (kvm_enabled()) {
1520 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1521 }
1522 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1523 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1524 (*cpu_fprintf)(f, " %s\n", buf);
1525 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1526 (*cpu_fprintf)(f, " %s\n", buf);
1527 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1528 (*cpu_fprintf)(f, " %s\n", buf);
1529 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1530 (*cpu_fprintf)(f, " %s\n", buf);
1531 }
1532
1533 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1534 {
1535 CpuDefinitionInfoList *cpu_list = NULL;
1536 x86_def_t *def;
1537 int i;
1538
1539 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1540 CpuDefinitionInfoList *entry;
1541 CpuDefinitionInfo *info;
1542
1543 def = &builtin_x86_defs[i];
1544 info = g_malloc0(sizeof(*info));
1545 info->name = g_strdup(def->name);
1546
1547 entry = g_malloc0(sizeof(*entry));
1548 entry->value = info;
1549 entry->next = cpu_list;
1550 cpu_list = entry;
1551 }
1552
1553 return cpu_list;
1554 }
1555
1556 #ifdef CONFIG_KVM
1557 static void filter_features_for_kvm(X86CPU *cpu)
1558 {
1559 CPUX86State *env = &cpu->env;
1560 KVMState *s = kvm_state;
1561
1562 env->cpuid_features &=
1563 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1564 env->cpuid_ext_features &=
1565 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1566 env->cpuid_ext2_features &=
1567 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1568 env->cpuid_ext3_features &=
1569 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1570 env->cpuid_svm_features &=
1571 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1572 env->cpuid_7_0_ebx_features &=
1573 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1574 env->cpuid_kvm_features &=
1575 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1576 env->cpuid_ext4_features &=
1577 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1578
1579 }
1580 #endif
1581
1582 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1583 {
1584 CPUX86State *env = &cpu->env;
1585 x86_def_t def1, *def = &def1;
1586 Error *error = NULL;
1587 char *name, *features;
1588 gchar **model_pieces;
1589
1590 memset(def, 0, sizeof(*def));
1591
1592 model_pieces = g_strsplit(cpu_model, ",", 2);
1593 if (!model_pieces[0]) {
1594 error_setg(&error, "Invalid/empty CPU model name");
1595 goto out;
1596 }
1597 name = model_pieces[0];
1598 features = model_pieces[1];
1599
1600 if (cpu_x86_find_by_name(def, name) < 0) {
1601 error_setg(&error, "Unable to find CPU definition: %s", name);
1602 goto out;
1603 }
1604
1605 if (kvm_enabled()) {
1606 def->kvm_features |= kvm_default_features;
1607 }
1608 def->ext_features |= CPUID_EXT_HYPERVISOR;
1609
1610 if (cpu_x86_parse_featurestr(def, features) < 0) {
1611 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1612 goto out;
1613 }
1614 assert(def->vendor1);
1615 env->cpuid_vendor1 = def->vendor1;
1616 env->cpuid_vendor2 = def->vendor2;
1617 env->cpuid_vendor3 = def->vendor3;
1618 env->cpuid_vendor_override = def->vendor_override;
1619 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1620 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1621 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1622 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1623 env->cpuid_features = def->features;
1624 env->cpuid_ext_features = def->ext_features;
1625 env->cpuid_ext2_features = def->ext2_features;
1626 env->cpuid_ext3_features = def->ext3_features;
1627 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1628 env->cpuid_kvm_features = def->kvm_features;
1629 env->cpuid_svm_features = def->svm_features;
1630 env->cpuid_ext4_features = def->ext4_features;
1631 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1632 env->cpuid_xlevel2 = def->xlevel2;
1633 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1634 "tsc-frequency", &error);
1635
1636 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1637
1638 out:
1639 g_strfreev(model_pieces);
1640 if (error) {
1641 fprintf(stderr, "%s\n", error_get_pretty(error));
1642 error_free(error);
1643 return -1;
1644 }
1645 return 0;
1646 }
1647
1648 #if !defined(CONFIG_USER_ONLY)
1649
1650 void cpu_clear_apic_feature(CPUX86State *env)
1651 {
1652 env->cpuid_features &= ~CPUID_APIC;
1653 }
1654
1655 #endif /* !CONFIG_USER_ONLY */
1656
1657 /* Initialize list of CPU models, filling some non-static fields if necessary
1658 */
1659 void x86_cpudef_setup(void)
1660 {
1661 int i, j;
1662 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1663
1664 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1665 x86_def_t *def = &builtin_x86_defs[i];
1666
1667 /* Look for specific "cpudef" models that */
1668 /* have the QEMU version in .model_id */
1669 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1670 if (strcmp(model_with_versions[j], def->name) == 0) {
1671 pstrcpy(def->model_id, sizeof(def->model_id),
1672 "QEMU Virtual CPU version ");
1673 pstrcat(def->model_id, sizeof(def->model_id),
1674 qemu_get_version());
1675 break;
1676 }
1677 }
1678 }
1679 }
1680
1681 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1682 uint32_t *ecx, uint32_t *edx)
1683 {
1684 *ebx = env->cpuid_vendor1;
1685 *edx = env->cpuid_vendor2;
1686 *ecx = env->cpuid_vendor3;
1687
1688 /* sysenter isn't supported on compatibility mode on AMD, syscall
1689 * isn't supported in compatibility mode on Intel.
1690 * Normally we advertise the actual cpu vendor, but you can override
1691 * this if you want to use KVM's sysenter/syscall emulation
1692 * in compatibility mode and when doing cross vendor migration
1693 */
1694 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1695 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1696 }
1697 }
1698
1699 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1700 uint32_t *eax, uint32_t *ebx,
1701 uint32_t *ecx, uint32_t *edx)
1702 {
1703 X86CPU *cpu = x86_env_get_cpu(env);
1704 CPUState *cs = CPU(cpu);
1705
1706 /* test if maximum index reached */
1707 if (index & 0x80000000) {
1708 if (index > env->cpuid_xlevel) {
1709 if (env->cpuid_xlevel2 > 0) {
1710 /* Handle the Centaur's CPUID instruction. */
1711 if (index > env->cpuid_xlevel2) {
1712 index = env->cpuid_xlevel2;
1713 } else if (index < 0xC0000000) {
1714 index = env->cpuid_xlevel;
1715 }
1716 } else {
1717 /* Intel documentation states that invalid EAX input will
1718 * return the same information as EAX=cpuid_level
1719 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1720 */
1721 index = env->cpuid_level;
1722 }
1723 }
1724 } else {
1725 if (index > env->cpuid_level)
1726 index = env->cpuid_level;
1727 }
1728
1729 switch(index) {
1730 case 0:
1731 *eax = env->cpuid_level;
1732 get_cpuid_vendor(env, ebx, ecx, edx);
1733 break;
1734 case 1:
1735 *eax = env->cpuid_version;
1736 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1737 *ecx = env->cpuid_ext_features;
1738 *edx = env->cpuid_features;
1739 if (cs->nr_cores * cs->nr_threads > 1) {
1740 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1741 *edx |= 1 << 28; /* HTT bit */
1742 }
1743 break;
1744 case 2:
1745 /* cache info: needed for Pentium Pro compatibility */
1746 *eax = 1;
1747 *ebx = 0;
1748 *ecx = 0;
1749 *edx = 0x2c307d;
1750 break;
1751 case 4:
1752 /* cache info: needed for Core compatibility */
1753 if (cs->nr_cores > 1) {
1754 *eax = (cs->nr_cores - 1) << 26;
1755 } else {
1756 *eax = 0;
1757 }
1758 switch (count) {
1759 case 0: /* L1 dcache info */
1760 *eax |= 0x0000121;
1761 *ebx = 0x1c0003f;
1762 *ecx = 0x000003f;
1763 *edx = 0x0000001;
1764 break;
1765 case 1: /* L1 icache info */
1766 *eax |= 0x0000122;
1767 *ebx = 0x1c0003f;
1768 *ecx = 0x000003f;
1769 *edx = 0x0000001;
1770 break;
1771 case 2: /* L2 cache info */
1772 *eax |= 0x0000143;
1773 if (cs->nr_threads > 1) {
1774 *eax |= (cs->nr_threads - 1) << 14;
1775 }
1776 *ebx = 0x3c0003f;
1777 *ecx = 0x0000fff;
1778 *edx = 0x0000001;
1779 break;
1780 default: /* end of info */
1781 *eax = 0;
1782 *ebx = 0;
1783 *ecx = 0;
1784 *edx = 0;
1785 break;
1786 }
1787 break;
1788 case 5:
1789 /* mwait info: needed for Core compatibility */
1790 *eax = 0; /* Smallest monitor-line size in bytes */
1791 *ebx = 0; /* Largest monitor-line size in bytes */
1792 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1793 *edx = 0;
1794 break;
1795 case 6:
1796 /* Thermal and Power Leaf */
1797 *eax = 0;
1798 *ebx = 0;
1799 *ecx = 0;
1800 *edx = 0;
1801 break;
1802 case 7:
1803 /* Structured Extended Feature Flags Enumeration Leaf */
1804 if (count == 0) {
1805 *eax = 0; /* Maximum ECX value for sub-leaves */
1806 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1807 *ecx = 0; /* Reserved */
1808 *edx = 0; /* Reserved */
1809 } else {
1810 *eax = 0;
1811 *ebx = 0;
1812 *ecx = 0;
1813 *edx = 0;
1814 }
1815 break;
1816 case 9:
1817 /* Direct Cache Access Information Leaf */
1818 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1819 *ebx = 0;
1820 *ecx = 0;
1821 *edx = 0;
1822 break;
1823 case 0xA:
1824 /* Architectural Performance Monitoring Leaf */
1825 if (kvm_enabled()) {
1826 KVMState *s = cs->kvm_state;
1827
1828 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1829 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1830 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1831 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1832 } else {
1833 *eax = 0;
1834 *ebx = 0;
1835 *ecx = 0;
1836 *edx = 0;
1837 }
1838 break;
1839 case 0xD:
1840 /* Processor Extended State */
1841 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1842 *eax = 0;
1843 *ebx = 0;
1844 *ecx = 0;
1845 *edx = 0;
1846 break;
1847 }
1848 if (kvm_enabled()) {
1849 KVMState *s = cs->kvm_state;
1850
1851 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1852 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1853 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1854 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1855 } else {
1856 *eax = 0;
1857 *ebx = 0;
1858 *ecx = 0;
1859 *edx = 0;
1860 }
1861 break;
1862 case 0x80000000:
1863 *eax = env->cpuid_xlevel;
1864 *ebx = env->cpuid_vendor1;
1865 *edx = env->cpuid_vendor2;
1866 *ecx = env->cpuid_vendor3;
1867 break;
1868 case 0x80000001:
1869 *eax = env->cpuid_version;
1870 *ebx = 0;
1871 *ecx = env->cpuid_ext3_features;
1872 *edx = env->cpuid_ext2_features;
1873
1874 /* The Linux kernel checks for the CMPLegacy bit and
1875 * discards multiple thread information if it is set.
1876 * So dont set it here for Intel to make Linux guests happy.
1877 */
1878 if (cs->nr_cores * cs->nr_threads > 1) {
1879 uint32_t tebx, tecx, tedx;
1880 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1881 if (tebx != CPUID_VENDOR_INTEL_1 ||
1882 tedx != CPUID_VENDOR_INTEL_2 ||
1883 tecx != CPUID_VENDOR_INTEL_3) {
1884 *ecx |= 1 << 1; /* CmpLegacy bit */
1885 }
1886 }
1887 break;
1888 case 0x80000002:
1889 case 0x80000003:
1890 case 0x80000004:
1891 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1892 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1893 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1894 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1895 break;
1896 case 0x80000005:
1897 /* cache info (L1 cache) */
1898 *eax = 0x01ff01ff;
1899 *ebx = 0x01ff01ff;
1900 *ecx = 0x40020140;
1901 *edx = 0x40020140;
1902 break;
1903 case 0x80000006:
1904 /* cache info (L2 cache) */
1905 *eax = 0;
1906 *ebx = 0x42004200;
1907 *ecx = 0x02008140;
1908 *edx = 0;
1909 break;
1910 case 0x80000008:
1911 /* virtual & phys address size in low 2 bytes. */
1912 /* XXX: This value must match the one used in the MMU code. */
1913 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1914 /* 64 bit processor */
1915 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1916 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1917 } else {
1918 if (env->cpuid_features & CPUID_PSE36)
1919 *eax = 0x00000024; /* 36 bits physical */
1920 else
1921 *eax = 0x00000020; /* 32 bits physical */
1922 }
1923 *ebx = 0;
1924 *ecx = 0;
1925 *edx = 0;
1926 if (cs->nr_cores * cs->nr_threads > 1) {
1927 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1928 }
1929 break;
1930 case 0x8000000A:
1931 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1932 *eax = 0x00000001; /* SVM Revision */
1933 *ebx = 0x00000010; /* nr of ASIDs */
1934 *ecx = 0;
1935 *edx = env->cpuid_svm_features; /* optional features */
1936 } else {
1937 *eax = 0;
1938 *ebx = 0;
1939 *ecx = 0;
1940 *edx = 0;
1941 }
1942 break;
1943 case 0xC0000000:
1944 *eax = env->cpuid_xlevel2;
1945 *ebx = 0;
1946 *ecx = 0;
1947 *edx = 0;
1948 break;
1949 case 0xC0000001:
1950 /* Support for VIA CPU's CPUID instruction */
1951 *eax = env->cpuid_version;
1952 *ebx = 0;
1953 *ecx = 0;
1954 *edx = env->cpuid_ext4_features;
1955 break;
1956 case 0xC0000002:
1957 case 0xC0000003:
1958 case 0xC0000004:
1959 /* Reserved for the future, and now filled with zero */
1960 *eax = 0;
1961 *ebx = 0;
1962 *ecx = 0;
1963 *edx = 0;
1964 break;
1965 default:
1966 /* reserved values: zero */
1967 *eax = 0;
1968 *ebx = 0;
1969 *ecx = 0;
1970 *edx = 0;
1971 break;
1972 }
1973 }
1974
1975 /* CPUClass::reset() */
1976 static void x86_cpu_reset(CPUState *s)
1977 {
1978 X86CPU *cpu = X86_CPU(s);
1979 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1980 CPUX86State *env = &cpu->env;
1981 int i;
1982
1983 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1984 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1985 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1986 }
1987
1988 xcc->parent_reset(s);
1989
1990
1991 memset(env, 0, offsetof(CPUX86State, breakpoints));
1992
1993 tlb_flush(env, 1);
1994
1995 env->old_exception = -1;
1996
1997 /* init to reset state */
1998
1999 #ifdef CONFIG_SOFTMMU
2000 env->hflags |= HF_SOFTMMU_MASK;
2001 #endif
2002 env->hflags2 |= HF2_GIF_MASK;
2003
2004 cpu_x86_update_cr0(env, 0x60000010);
2005 env->a20_mask = ~0x0;
2006 env->smbase = 0x30000;
2007
2008 env->idt.limit = 0xffff;
2009 env->gdt.limit = 0xffff;
2010 env->ldt.limit = 0xffff;
2011 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2012 env->tr.limit = 0xffff;
2013 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2014
2015 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2016 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2017 DESC_R_MASK | DESC_A_MASK);
2018 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2019 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2020 DESC_A_MASK);
2021 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2022 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2023 DESC_A_MASK);
2024 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2025 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2026 DESC_A_MASK);
2027 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2028 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2029 DESC_A_MASK);
2030 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2031 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2032 DESC_A_MASK);
2033
2034 env->eip = 0xfff0;
2035 env->regs[R_EDX] = env->cpuid_version;
2036
2037 env->eflags = 0x2;
2038
2039 /* FPU init */
2040 for (i = 0; i < 8; i++) {
2041 env->fptags[i] = 1;
2042 }
2043 env->fpuc = 0x37f;
2044
2045 env->mxcsr = 0x1f80;
2046
2047 env->pat = 0x0007040600070406ULL;
2048 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2049
2050 memset(env->dr, 0, sizeof(env->dr));
2051 env->dr[6] = DR6_FIXED_1;
2052 env->dr[7] = DR7_FIXED_1;
2053 cpu_breakpoint_remove_all(env, BP_CPU);
2054 cpu_watchpoint_remove_all(env, BP_CPU);
2055
2056 #if !defined(CONFIG_USER_ONLY)
2057 /* We hard-wire the BSP to the first CPU. */
2058 if (s->cpu_index == 0) {
2059 apic_designate_bsp(env->apic_state);
2060 }
2061
2062 env->halted = !cpu_is_bsp(cpu);
2063 #endif
2064 }
2065
2066 #ifndef CONFIG_USER_ONLY
2067 bool cpu_is_bsp(X86CPU *cpu)
2068 {
2069 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2070 }
2071
2072 /* TODO: remove me, when reset over QOM tree is implemented */
2073 static void x86_cpu_machine_reset_cb(void *opaque)
2074 {
2075 X86CPU *cpu = opaque;
2076 cpu_reset(CPU(cpu));
2077 }
2078 #endif
2079
2080 static void mce_init(X86CPU *cpu)
2081 {
2082 CPUX86State *cenv = &cpu->env;
2083 unsigned int bank;
2084
2085 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2086 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2087 (CPUID_MCE | CPUID_MCA)) {
2088 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2089 cenv->mcg_ctl = ~(uint64_t)0;
2090 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2091 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2092 }
2093 }
2094 }
2095
2096 #define MSI_ADDR_BASE 0xfee00000
2097
2098 #ifndef CONFIG_USER_ONLY
2099 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2100 {
2101 static int apic_mapped;
2102 CPUX86State *env = &cpu->env;
2103 APICCommonState *apic;
2104 const char *apic_type = "apic";
2105
2106 if (kvm_irqchip_in_kernel()) {
2107 apic_type = "kvm-apic";
2108 } else if (xen_enabled()) {
2109 apic_type = "xen-apic";
2110 }
2111
2112 env->apic_state = qdev_try_create(NULL, apic_type);
2113 if (env->apic_state == NULL) {
2114 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2115 return;
2116 }
2117
2118 object_property_add_child(OBJECT(cpu), "apic",
2119 OBJECT(env->apic_state), NULL);
2120 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2121 /* TODO: convert to link<> */
2122 apic = APIC_COMMON(env->apic_state);
2123 apic->cpu = cpu;
2124
2125 if (qdev_init(env->apic_state)) {
2126 error_setg(errp, "APIC device '%s' could not be initialized",
2127 object_get_typename(OBJECT(env->apic_state)));
2128 return;
2129 }
2130
2131 /* XXX: mapping more APICs at the same memory location */
2132 if (apic_mapped == 0) {
2133 /* NOTE: the APIC is directly connected to the CPU - it is not
2134 on the global memory bus. */
2135 /* XXX: what if the base changes? */
2136 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
2137 apic_mapped = 1;
2138 }
2139 }
2140 #endif
2141
2142 void x86_cpu_realize(Object *obj, Error **errp)
2143 {
2144 X86CPU *cpu = X86_CPU(obj);
2145 CPUX86State *env = &cpu->env;
2146
2147 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2148 env->cpuid_level = 7;
2149 }
2150
2151 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2152 * CPUID[1].EDX.
2153 */
2154 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2155 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2156 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2157 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2158 env->cpuid_ext2_features |= (env->cpuid_features
2159 & CPUID_EXT2_AMD_ALIASES);
2160 }
2161
2162 if (!kvm_enabled()) {
2163 env->cpuid_features &= TCG_FEATURES;
2164 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2165 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2166 #ifdef TARGET_X86_64
2167 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2168 #endif
2169 );
2170 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2171 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2172 } else {
2173 #ifdef CONFIG_KVM
2174 filter_features_for_kvm(cpu);
2175 #endif
2176 if (check_cpuid && kvm_check_features_against_host(cpu)
2177 && enforce_cpuid) {
2178 error_setg(errp, "Host's CPU doesn't support requested features");
2179 return;
2180 }
2181 }
2182
2183 #ifndef CONFIG_USER_ONLY
2184 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2185
2186 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2187 x86_cpu_apic_init(cpu, errp);
2188 if (error_is_set(errp)) {
2189 return;
2190 }
2191 }
2192 #endif
2193
2194 mce_init(cpu);
2195 qemu_init_vcpu(&cpu->env);
2196 cpu_reset(CPU(cpu));
2197 }
2198
2199 /* Enables contiguous-apic-ID mode, for compatibility */
2200 static bool compat_apic_id_mode;
2201
2202 void enable_compat_apic_id_mode(void)
2203 {
2204 compat_apic_id_mode = true;
2205 }
2206
2207 /* Calculates initial APIC ID for a specific CPU index
2208 *
2209 * Currently we need to be able to calculate the APIC ID from the CPU index
2210 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2211 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2212 * all CPUs up to max_cpus.
2213 */
2214 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2215 {
2216 uint32_t correct_id;
2217 static bool warned;
2218
2219 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2220 if (compat_apic_id_mode) {
2221 if (cpu_index != correct_id && !warned) {
2222 error_report("APIC IDs set in compatibility mode, "
2223 "CPU topology won't match the configuration");
2224 warned = true;
2225 }
2226 return cpu_index;
2227 } else {
2228 return correct_id;
2229 }
2230 }
2231
2232 static void x86_cpu_initfn(Object *obj)
2233 {
2234 CPUState *cs = CPU(obj);
2235 X86CPU *cpu = X86_CPU(obj);
2236 CPUX86State *env = &cpu->env;
2237 static int inited;
2238
2239 cpu_exec_init(env);
2240
2241 object_property_add(obj, "family", "int",
2242 x86_cpuid_version_get_family,
2243 x86_cpuid_version_set_family, NULL, NULL, NULL);
2244 object_property_add(obj, "model", "int",
2245 x86_cpuid_version_get_model,
2246 x86_cpuid_version_set_model, NULL, NULL, NULL);
2247 object_property_add(obj, "stepping", "int",
2248 x86_cpuid_version_get_stepping,
2249 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2250 object_property_add(obj, "level", "int",
2251 x86_cpuid_get_level,
2252 x86_cpuid_set_level, NULL, NULL, NULL);
2253 object_property_add(obj, "xlevel", "int",
2254 x86_cpuid_get_xlevel,
2255 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2256 object_property_add_str(obj, "vendor",
2257 x86_cpuid_get_vendor,
2258 x86_cpuid_set_vendor, NULL);
2259 object_property_add_str(obj, "model-id",
2260 x86_cpuid_get_model_id,
2261 x86_cpuid_set_model_id, NULL);
2262 object_property_add(obj, "tsc-frequency", "int",
2263 x86_cpuid_get_tsc_freq,
2264 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2265
2266 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2267
2268 /* init various static tables used in TCG mode */
2269 if (tcg_enabled() && !inited) {
2270 inited = 1;
2271 optimize_flags_init();
2272 #ifndef CONFIG_USER_ONLY
2273 cpu_set_debug_excp_handler(breakpoint_handler);
2274 #endif
2275 }
2276 }
2277
2278 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2279 {
2280 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2281 CPUClass *cc = CPU_CLASS(oc);
2282
2283 xcc->parent_reset = cc->reset;
2284 cc->reset = x86_cpu_reset;
2285 }
2286
2287 static const TypeInfo x86_cpu_type_info = {
2288 .name = TYPE_X86_CPU,
2289 .parent = TYPE_CPU,
2290 .instance_size = sizeof(X86CPU),
2291 .instance_init = x86_cpu_initfn,
2292 .abstract = false,
2293 .class_size = sizeof(X86CPUClass),
2294 .class_init = x86_cpu_common_class_init,
2295 };
2296
2297 static void x86_cpu_register_types(void)
2298 {
2299 type_register_static(&x86_cpu_type_info);
2300 }
2301
2302 type_init(x86_cpu_register_types)
Qemu copy for testing