]> git.proxmox.com Git - qemu.git/blob - target-i386/cpu.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-i386/cpu.c: Add feature name array for ext4_features
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
30
31 #include "qapi/visitor.h"
32 #include "sysemu/arch_init.h"
33
34 #include "hyperv.h"
35
36 #include "hw/hw.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
39 #endif
40
41 #include "sysemu/sysemu.h"
42 #ifndef CONFIG_USER_ONLY
43 #include "hw/xen.h"
44 #include "hw/sysbus.h"
45 #include "hw/apic_internal.h"
46 #endif
47
48 /* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52 static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61 };
62 static const char *ext_feature_name[] = {
63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
64 "ds_cpl", "vmx", "smx", "est",
65 "tm2", "ssse3", "cid", NULL,
66 "fma", "cx16", "xtpr", "pdcm",
67 NULL, "pcid", "dca", "sse4.1|sse4_1",
68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
69 "tsc-deadline", "aes", "xsave", "osxsave",
70 "avx", "f16c", "rdrand", "hypervisor",
71 };
72 /* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
77 static const char *ext2_feature_name[] = {
78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
85 NULL, "lm|i64", "3dnowext", "3dnow",
86 };
87 static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
90 "3dnowprefetch", "osvw", "ibs", "xop",
91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
95 NULL, NULL, NULL, NULL,
96 };
97
98 static const char *ext4_feature_name[] = {
99 NULL, NULL, "xstore", "xstore-en",
100 NULL, NULL, "xcrypt", "xcrypt-en",
101 "ace2", "ace2-en", "phe", "phe-en",
102 "pmm", "pmm-en", NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 };
108
109 static const char *kvm_feature_name[] = {
110 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
111 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
112 NULL, NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 };
119
120 static const char *svm_feature_name[] = {
121 "npt", "lbrv", "svm_lock", "nrip_save",
122 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
123 NULL, NULL, "pause_filter", NULL,
124 "pfthreshold", NULL, NULL, NULL,
125 NULL, NULL, NULL, NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 };
130
131 static const char *cpuid_7_0_ebx_feature_name[] = {
132 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
133 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
134 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
135 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
136 };
137
138 typedef struct FeatureWordInfo {
139 const char **feat_names;
140 uint32_t cpuid_eax; /* Input EAX for CPUID */
141 int cpuid_reg; /* R_* register constant */
142 } FeatureWordInfo;
143
144 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
145 [FEAT_1_EDX] = {
146 .feat_names = feature_name,
147 .cpuid_eax = 1, .cpuid_reg = R_EDX,
148 },
149 [FEAT_1_ECX] = {
150 .feat_names = ext_feature_name,
151 .cpuid_eax = 1, .cpuid_reg = R_ECX,
152 },
153 [FEAT_8000_0001_EDX] = {
154 .feat_names = ext2_feature_name,
155 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
156 },
157 [FEAT_8000_0001_ECX] = {
158 .feat_names = ext3_feature_name,
159 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
160 },
161 [FEAT_C000_0001_EDX] = {
162 .feat_names = ext4_feature_name,
163 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
164 },
165 [FEAT_KVM] = {
166 .feat_names = kvm_feature_name,
167 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
168 },
169 [FEAT_SVM] = {
170 .feat_names = svm_feature_name,
171 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
172 },
173 [FEAT_7_0_EBX] = {
174 .feat_names = cpuid_7_0_ebx_feature_name,
175 .cpuid_eax = 7, .cpuid_reg = R_EBX,
176 },
177 };
178
179 const char *get_register_name_32(unsigned int reg)
180 {
181 static const char *reg_names[CPU_NB_REGS32] = {
182 [R_EAX] = "EAX",
183 [R_ECX] = "ECX",
184 [R_EDX] = "EDX",
185 [R_EBX] = "EBX",
186 [R_ESP] = "ESP",
187 [R_EBP] = "EBP",
188 [R_ESI] = "ESI",
189 [R_EDI] = "EDI",
190 };
191
192 if (reg > CPU_NB_REGS32) {
193 return NULL;
194 }
195 return reg_names[reg];
196 }
197
198 /* collects per-function cpuid data
199 */
200 typedef struct model_features_t {
201 uint32_t *guest_feat;
202 uint32_t *host_feat;
203 FeatureWord feat_word;
204 } model_features_t;
205
206 int check_cpuid = 0;
207 int enforce_cpuid = 0;
208
209 #if defined(CONFIG_KVM)
210 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
211 (1 << KVM_FEATURE_NOP_IO_DELAY) |
212 (1 << KVM_FEATURE_CLOCKSOURCE2) |
213 (1 << KVM_FEATURE_ASYNC_PF) |
214 (1 << KVM_FEATURE_STEAL_TIME) |
215 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
216 static const uint32_t kvm_pv_eoi_features = (0x1 << KVM_FEATURE_PV_EOI);
217 #else
218 static uint32_t kvm_default_features = 0;
219 static const uint32_t kvm_pv_eoi_features = 0;
220 #endif
221
222 void enable_kvm_pv_eoi(void)
223 {
224 kvm_default_features |= kvm_pv_eoi_features;
225 }
226
227 void host_cpuid(uint32_t function, uint32_t count,
228 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
229 {
230 #if defined(CONFIG_KVM)
231 uint32_t vec[4];
232
233 #ifdef __x86_64__
234 asm volatile("cpuid"
235 : "=a"(vec[0]), "=b"(vec[1]),
236 "=c"(vec[2]), "=d"(vec[3])
237 : "0"(function), "c"(count) : "cc");
238 #else
239 asm volatile("pusha \n\t"
240 "cpuid \n\t"
241 "mov %%eax, 0(%2) \n\t"
242 "mov %%ebx, 4(%2) \n\t"
243 "mov %%ecx, 8(%2) \n\t"
244 "mov %%edx, 12(%2) \n\t"
245 "popa"
246 : : "a"(function), "c"(count), "S"(vec)
247 : "memory", "cc");
248 #endif
249
250 if (eax)
251 *eax = vec[0];
252 if (ebx)
253 *ebx = vec[1];
254 if (ecx)
255 *ecx = vec[2];
256 if (edx)
257 *edx = vec[3];
258 #endif
259 }
260
261 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
262
263 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
264 * a substring. ex if !NULL points to the first char after a substring,
265 * otherwise the string is assumed to sized by a terminating nul.
266 * Return lexical ordering of *s1:*s2.
267 */
268 static int sstrcmp(const char *s1, const char *e1, const char *s2,
269 const char *e2)
270 {
271 for (;;) {
272 if (!*s1 || !*s2 || *s1 != *s2)
273 return (*s1 - *s2);
274 ++s1, ++s2;
275 if (s1 == e1 && s2 == e2)
276 return (0);
277 else if (s1 == e1)
278 return (*s2);
279 else if (s2 == e2)
280 return (*s1);
281 }
282 }
283
284 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
285 * '|' delimited (possibly empty) strings in which case search for a match
286 * within the alternatives proceeds left to right. Return 0 for success,
287 * non-zero otherwise.
288 */
289 static int altcmp(const char *s, const char *e, const char *altstr)
290 {
291 const char *p, *q;
292
293 for (q = p = altstr; ; ) {
294 while (*p && *p != '|')
295 ++p;
296 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
297 return (0);
298 if (!*p)
299 return (1);
300 else
301 q = ++p;
302 }
303 }
304
305 /* search featureset for flag *[s..e), if found set corresponding bit in
306 * *pval and return true, otherwise return false
307 */
308 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
309 const char **featureset)
310 {
311 uint32_t mask;
312 const char **ppc;
313 bool found = false;
314
315 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
316 if (*ppc && !altcmp(s, e, *ppc)) {
317 *pval |= mask;
318 found = true;
319 }
320 }
321 return found;
322 }
323
324 static void add_flagname_to_bitmaps(const char *flagname,
325 FeatureWordArray words)
326 {
327 FeatureWord w;
328 for (w = 0; w < FEATURE_WORDS; w++) {
329 FeatureWordInfo *wi = &feature_word_info[w];
330 if (wi->feat_names &&
331 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
332 break;
333 }
334 }
335 if (w == FEATURE_WORDS) {
336 fprintf(stderr, "CPU feature %s not found\n", flagname);
337 }
338 }
339
340 typedef struct x86_def_t {
341 struct x86_def_t *next;
342 const char *name;
343 uint32_t level;
344 uint32_t vendor1, vendor2, vendor3;
345 int family;
346 int model;
347 int stepping;
348 int tsc_khz;
349 uint32_t features, ext_features, ext2_features, ext3_features;
350 uint32_t kvm_features, svm_features;
351 uint32_t xlevel;
352 char model_id[48];
353 int vendor_override;
354 /* Store the results of Centaur's CPUID instructions */
355 uint32_t ext4_features;
356 uint32_t xlevel2;
357 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
358 uint32_t cpuid_7_0_ebx_features;
359 } x86_def_t;
360
361 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
362 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
363 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
364 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
365 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
366 CPUID_PSE36 | CPUID_FXSR)
367 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
368 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
369 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
370 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
371 CPUID_PAE | CPUID_SEP | CPUID_APIC)
372
373 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
374 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
375 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
376 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
377 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
378 /* partly implemented:
379 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
380 CPUID_PSE36 (needed for Solaris) */
381 /* missing:
382 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
383 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
384 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
385 CPUID_EXT_HYPERVISOR)
386 /* missing:
387 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
388 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
389 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
390 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
391 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
392 /* missing:
393 CPUID_EXT2_PDPE1GB */
394 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
395 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
396 #define TCG_SVM_FEATURES 0
397 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
398
399 /* maintains list of cpu model definitions
400 */
401 static x86_def_t *x86_defs = {NULL};
402
403 /* built-in cpu model definitions (deprecated)
404 */
405 static x86_def_t builtin_x86_defs[] = {
406 {
407 .name = "qemu64",
408 .level = 4,
409 .vendor1 = CPUID_VENDOR_AMD_1,
410 .vendor2 = CPUID_VENDOR_AMD_2,
411 .vendor3 = CPUID_VENDOR_AMD_3,
412 .family = 6,
413 .model = 2,
414 .stepping = 3,
415 .features = PPRO_FEATURES |
416 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
417 CPUID_PSE36,
418 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
419 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
420 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
421 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
422 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
423 .xlevel = 0x8000000A,
424 },
425 {
426 .name = "phenom",
427 .level = 5,
428 .vendor1 = CPUID_VENDOR_AMD_1,
429 .vendor2 = CPUID_VENDOR_AMD_2,
430 .vendor3 = CPUID_VENDOR_AMD_3,
431 .family = 16,
432 .model = 2,
433 .stepping = 3,
434 .features = PPRO_FEATURES |
435 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
436 CPUID_PSE36 | CPUID_VME | CPUID_HT,
437 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
438 CPUID_EXT_POPCNT,
439 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
440 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
441 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
442 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
443 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
444 CPUID_EXT3_CR8LEG,
445 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
446 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
447 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
448 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
449 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
450 .xlevel = 0x8000001A,
451 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
452 },
453 {
454 .name = "core2duo",
455 .level = 10,
456 .vendor1 = CPUID_VENDOR_INTEL_1,
457 .vendor2 = CPUID_VENDOR_INTEL_2,
458 .vendor3 = CPUID_VENDOR_INTEL_3,
459 .family = 6,
460 .model = 15,
461 .stepping = 11,
462 .features = PPRO_FEATURES |
463 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
464 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
465 CPUID_HT | CPUID_TM | CPUID_PBE,
466 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
467 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
468 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
469 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
470 .ext3_features = CPUID_EXT3_LAHF_LM,
471 .xlevel = 0x80000008,
472 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
473 },
474 {
475 .name = "kvm64",
476 .level = 5,
477 .vendor1 = CPUID_VENDOR_INTEL_1,
478 .vendor2 = CPUID_VENDOR_INTEL_2,
479 .vendor3 = CPUID_VENDOR_INTEL_3,
480 .family = 15,
481 .model = 6,
482 .stepping = 1,
483 /* Missing: CPUID_VME, CPUID_HT */
484 .features = PPRO_FEATURES |
485 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
486 CPUID_PSE36,
487 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
488 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
489 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
490 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
491 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
492 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
493 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
494 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
495 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
496 .ext3_features = 0,
497 .xlevel = 0x80000008,
498 .model_id = "Common KVM processor"
499 },
500 {
501 .name = "qemu32",
502 .level = 4,
503 .vendor1 = CPUID_VENDOR_INTEL_1,
504 .vendor2 = CPUID_VENDOR_INTEL_2,
505 .vendor3 = CPUID_VENDOR_INTEL_3,
506 .family = 6,
507 .model = 3,
508 .stepping = 3,
509 .features = PPRO_FEATURES,
510 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
511 .xlevel = 0x80000004,
512 },
513 {
514 .name = "kvm32",
515 .level = 5,
516 .vendor1 = CPUID_VENDOR_INTEL_1,
517 .vendor2 = CPUID_VENDOR_INTEL_2,
518 .vendor3 = CPUID_VENDOR_INTEL_3,
519 .family = 15,
520 .model = 6,
521 .stepping = 1,
522 .features = PPRO_FEATURES |
523 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
524 .ext_features = CPUID_EXT_SSE3,
525 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
526 .ext3_features = 0,
527 .xlevel = 0x80000008,
528 .model_id = "Common 32-bit KVM processor"
529 },
530 {
531 .name = "coreduo",
532 .level = 10,
533 .vendor1 = CPUID_VENDOR_INTEL_1,
534 .vendor2 = CPUID_VENDOR_INTEL_2,
535 .vendor3 = CPUID_VENDOR_INTEL_3,
536 .family = 6,
537 .model = 14,
538 .stepping = 8,
539 .features = PPRO_FEATURES | CPUID_VME |
540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
541 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
542 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
543 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
544 .ext2_features = CPUID_EXT2_NX,
545 .xlevel = 0x80000008,
546 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
547 },
548 {
549 .name = "486",
550 .level = 1,
551 .vendor1 = CPUID_VENDOR_INTEL_1,
552 .vendor2 = CPUID_VENDOR_INTEL_2,
553 .vendor3 = CPUID_VENDOR_INTEL_3,
554 .family = 4,
555 .model = 0,
556 .stepping = 0,
557 .features = I486_FEATURES,
558 .xlevel = 0,
559 },
560 {
561 .name = "pentium",
562 .level = 1,
563 .vendor1 = CPUID_VENDOR_INTEL_1,
564 .vendor2 = CPUID_VENDOR_INTEL_2,
565 .vendor3 = CPUID_VENDOR_INTEL_3,
566 .family = 5,
567 .model = 4,
568 .stepping = 3,
569 .features = PENTIUM_FEATURES,
570 .xlevel = 0,
571 },
572 {
573 .name = "pentium2",
574 .level = 2,
575 .vendor1 = CPUID_VENDOR_INTEL_1,
576 .vendor2 = CPUID_VENDOR_INTEL_2,
577 .vendor3 = CPUID_VENDOR_INTEL_3,
578 .family = 6,
579 .model = 5,
580 .stepping = 2,
581 .features = PENTIUM2_FEATURES,
582 .xlevel = 0,
583 },
584 {
585 .name = "pentium3",
586 .level = 2,
587 .vendor1 = CPUID_VENDOR_INTEL_1,
588 .vendor2 = CPUID_VENDOR_INTEL_2,
589 .vendor3 = CPUID_VENDOR_INTEL_3,
590 .family = 6,
591 .model = 7,
592 .stepping = 3,
593 .features = PENTIUM3_FEATURES,
594 .xlevel = 0,
595 },
596 {
597 .name = "athlon",
598 .level = 2,
599 .vendor1 = CPUID_VENDOR_AMD_1,
600 .vendor2 = CPUID_VENDOR_AMD_2,
601 .vendor3 = CPUID_VENDOR_AMD_3,
602 .family = 6,
603 .model = 2,
604 .stepping = 3,
605 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
606 CPUID_MCA,
607 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
608 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
609 .xlevel = 0x80000008,
610 },
611 {
612 .name = "n270",
613 /* original is on level 10 */
614 .level = 5,
615 .vendor1 = CPUID_VENDOR_INTEL_1,
616 .vendor2 = CPUID_VENDOR_INTEL_2,
617 .vendor3 = CPUID_VENDOR_INTEL_3,
618 .family = 6,
619 .model = 28,
620 .stepping = 2,
621 .features = PPRO_FEATURES |
622 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
623 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
624 /* Some CPUs got no CPUID_SEP */
625 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
626 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
627 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
628 CPUID_EXT2_NX,
629 .ext3_features = CPUID_EXT3_LAHF_LM,
630 .xlevel = 0x8000000A,
631 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
632 },
633 {
634 .name = "Conroe",
635 .level = 2,
636 .vendor1 = CPUID_VENDOR_INTEL_1,
637 .vendor2 = CPUID_VENDOR_INTEL_2,
638 .vendor3 = CPUID_VENDOR_INTEL_3,
639 .family = 6,
640 .model = 2,
641 .stepping = 3,
642 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
643 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
644 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
645 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
646 CPUID_DE | CPUID_FP87,
647 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
648 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
649 .ext3_features = CPUID_EXT3_LAHF_LM,
650 .xlevel = 0x8000000A,
651 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
652 },
653 {
654 .name = "Penryn",
655 .level = 2,
656 .vendor1 = CPUID_VENDOR_INTEL_1,
657 .vendor2 = CPUID_VENDOR_INTEL_2,
658 .vendor3 = CPUID_VENDOR_INTEL_3,
659 .family = 6,
660 .model = 2,
661 .stepping = 3,
662 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
663 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
664 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
665 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
666 CPUID_DE | CPUID_FP87,
667 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
668 CPUID_EXT_SSE3,
669 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
670 .ext3_features = CPUID_EXT3_LAHF_LM,
671 .xlevel = 0x8000000A,
672 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
673 },
674 {
675 .name = "Nehalem",
676 .level = 2,
677 .vendor1 = CPUID_VENDOR_INTEL_1,
678 .vendor2 = CPUID_VENDOR_INTEL_2,
679 .vendor3 = CPUID_VENDOR_INTEL_3,
680 .family = 6,
681 .model = 2,
682 .stepping = 3,
683 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
684 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
685 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
686 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
687 CPUID_DE | CPUID_FP87,
688 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
689 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
690 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
691 .ext3_features = CPUID_EXT3_LAHF_LM,
692 .xlevel = 0x8000000A,
693 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
694 },
695 {
696 .name = "Westmere",
697 .level = 11,
698 .vendor1 = CPUID_VENDOR_INTEL_1,
699 .vendor2 = CPUID_VENDOR_INTEL_2,
700 .vendor3 = CPUID_VENDOR_INTEL_3,
701 .family = 6,
702 .model = 44,
703 .stepping = 1,
704 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
705 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
706 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
707 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
708 CPUID_DE | CPUID_FP87,
709 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
710 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
711 CPUID_EXT_SSE3,
712 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
713 .ext3_features = CPUID_EXT3_LAHF_LM,
714 .xlevel = 0x8000000A,
715 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
716 },
717 {
718 .name = "SandyBridge",
719 .level = 0xd,
720 .vendor1 = CPUID_VENDOR_INTEL_1,
721 .vendor2 = CPUID_VENDOR_INTEL_2,
722 .vendor3 = CPUID_VENDOR_INTEL_3,
723 .family = 6,
724 .model = 42,
725 .stepping = 1,
726 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
727 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
728 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
729 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
730 CPUID_DE | CPUID_FP87,
731 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
732 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
733 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
734 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
735 CPUID_EXT_SSE3,
736 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
737 CPUID_EXT2_SYSCALL,
738 .ext3_features = CPUID_EXT3_LAHF_LM,
739 .xlevel = 0x8000000A,
740 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
741 },
742 {
743 .name = "Haswell",
744 .level = 0xd,
745 .vendor1 = CPUID_VENDOR_INTEL_1,
746 .vendor2 = CPUID_VENDOR_INTEL_2,
747 .vendor3 = CPUID_VENDOR_INTEL_3,
748 .family = 6,
749 .model = 60,
750 .stepping = 1,
751 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
752 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
753 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
754 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
755 CPUID_DE | CPUID_FP87,
756 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
757 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
758 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
759 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
760 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
761 CPUID_EXT_PCID,
762 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
763 CPUID_EXT2_SYSCALL,
764 .ext3_features = CPUID_EXT3_LAHF_LM,
765 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
766 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
767 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
768 CPUID_7_0_EBX_RTM,
769 .xlevel = 0x8000000A,
770 .model_id = "Intel Core Processor (Haswell)",
771 },
772 {
773 .name = "Opteron_G1",
774 .level = 5,
775 .vendor1 = CPUID_VENDOR_AMD_1,
776 .vendor2 = CPUID_VENDOR_AMD_2,
777 .vendor3 = CPUID_VENDOR_AMD_3,
778 .family = 15,
779 .model = 6,
780 .stepping = 1,
781 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
782 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
783 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
784 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
785 CPUID_DE | CPUID_FP87,
786 .ext_features = CPUID_EXT_SSE3,
787 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
788 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
789 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
790 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
791 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
792 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
793 .xlevel = 0x80000008,
794 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
795 },
796 {
797 .name = "Opteron_G2",
798 .level = 5,
799 .vendor1 = CPUID_VENDOR_AMD_1,
800 .vendor2 = CPUID_VENDOR_AMD_2,
801 .vendor3 = CPUID_VENDOR_AMD_3,
802 .family = 15,
803 .model = 6,
804 .stepping = 1,
805 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
809 CPUID_DE | CPUID_FP87,
810 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
811 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
812 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
813 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
814 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
815 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
816 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
817 CPUID_EXT2_DE | CPUID_EXT2_FPU,
818 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
819 .xlevel = 0x80000008,
820 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
821 },
822 {
823 .name = "Opteron_G3",
824 .level = 5,
825 .vendor1 = CPUID_VENDOR_AMD_1,
826 .vendor2 = CPUID_VENDOR_AMD_2,
827 .vendor3 = CPUID_VENDOR_AMD_3,
828 .family = 15,
829 .model = 6,
830 .stepping = 1,
831 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
835 CPUID_DE | CPUID_FP87,
836 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
837 CPUID_EXT_SSE3,
838 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
839 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
840 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
841 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
842 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
843 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
844 CPUID_EXT2_DE | CPUID_EXT2_FPU,
845 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
846 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
847 .xlevel = 0x80000008,
848 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
849 },
850 {
851 .name = "Opteron_G4",
852 .level = 0xd,
853 .vendor1 = CPUID_VENDOR_AMD_1,
854 .vendor2 = CPUID_VENDOR_AMD_2,
855 .vendor3 = CPUID_VENDOR_AMD_3,
856 .family = 21,
857 .model = 1,
858 .stepping = 2,
859 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
860 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
861 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
862 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
863 CPUID_DE | CPUID_FP87,
864 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
865 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
866 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
867 CPUID_EXT_SSE3,
868 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
869 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
870 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
871 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
872 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
873 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
874 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
875 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
876 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
877 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
878 CPUID_EXT3_LAHF_LM,
879 .xlevel = 0x8000001A,
880 .model_id = "AMD Opteron 62xx class CPU",
881 },
882 {
883 .name = "Opteron_G5",
884 .level = 0xd,
885 .vendor1 = CPUID_VENDOR_AMD_1,
886 .vendor2 = CPUID_VENDOR_AMD_2,
887 .vendor3 = CPUID_VENDOR_AMD_3,
888 .family = 21,
889 .model = 2,
890 .stepping = 0,
891 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
892 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
893 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
894 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
895 CPUID_DE | CPUID_FP87,
896 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
897 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
898 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
899 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
900 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
901 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
902 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
903 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
904 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
905 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
906 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
907 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
908 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
909 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
910 CPUID_EXT3_LAHF_LM,
911 .xlevel = 0x8000001A,
912 .model_id = "AMD Opteron 63xx class CPU",
913 },
914 };
915
916 #ifdef CONFIG_KVM
917 static int cpu_x86_fill_model_id(char *str)
918 {
919 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
920 int i;
921
922 for (i = 0; i < 3; i++) {
923 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
924 memcpy(str + i * 16 + 0, &eax, 4);
925 memcpy(str + i * 16 + 4, &ebx, 4);
926 memcpy(str + i * 16 + 8, &ecx, 4);
927 memcpy(str + i * 16 + 12, &edx, 4);
928 }
929 return 0;
930 }
931 #endif
932
933 /* Fill a x86_def_t struct with information about the host CPU, and
934 * the CPU features supported by the host hardware + host kernel
935 *
936 * This function may be called only if KVM is enabled.
937 */
938 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
939 {
940 #ifdef CONFIG_KVM
941 KVMState *s = kvm_state;
942 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
943
944 assert(kvm_enabled());
945
946 x86_cpu_def->name = "host";
947 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
948 x86_cpu_def->vendor1 = ebx;
949 x86_cpu_def->vendor2 = edx;
950 x86_cpu_def->vendor3 = ecx;
951
952 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
953 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
954 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
955 x86_cpu_def->stepping = eax & 0x0F;
956
957 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
958 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
959 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
960
961 if (x86_cpu_def->level >= 7) {
962 x86_cpu_def->cpuid_7_0_ebx_features =
963 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
964 } else {
965 x86_cpu_def->cpuid_7_0_ebx_features = 0;
966 }
967
968 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
969 x86_cpu_def->ext2_features =
970 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
971 x86_cpu_def->ext3_features =
972 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
973
974 cpu_x86_fill_model_id(x86_cpu_def->model_id);
975 x86_cpu_def->vendor_override = 0;
976
977 /* Call Centaur's CPUID instruction. */
978 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
979 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
980 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
981 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
982 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
983 if (eax >= 0xC0000001) {
984 /* Support VIA max extended level */
985 x86_cpu_def->xlevel2 = eax;
986 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
987 x86_cpu_def->ext4_features =
988 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
989 }
990 }
991
992 /* Other KVM-specific feature fields: */
993 x86_cpu_def->svm_features =
994 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
995 x86_cpu_def->kvm_features =
996 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
997
998 #endif /* CONFIG_KVM */
999 }
1000
1001 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1002 {
1003 int i;
1004
1005 for (i = 0; i < 32; ++i)
1006 if (1 << i & mask) {
1007 const char *reg = get_register_name_32(f->cpuid_reg);
1008 assert(reg);
1009 fprintf(stderr, "warning: host doesn't support requested feature: "
1010 "CPUID.%02XH:%s%s%s [bit %d]\n",
1011 f->cpuid_eax, reg,
1012 f->feat_names[i] ? "." : "",
1013 f->feat_names[i] ? f->feat_names[i] : "", i);
1014 break;
1015 }
1016 return 0;
1017 }
1018
1019 /* best effort attempt to inform user requested cpu flags aren't making
1020 * their way to the guest.
1021 *
1022 * This function may be called only if KVM is enabled.
1023 */
1024 static int kvm_check_features_against_host(x86_def_t *guest_def)
1025 {
1026 x86_def_t host_def;
1027 uint32_t mask;
1028 int rv, i;
1029 struct model_features_t ft[] = {
1030 {&guest_def->features, &host_def.features,
1031 FEAT_1_EDX },
1032 {&guest_def->ext_features, &host_def.ext_features,
1033 FEAT_1_ECX },
1034 {&guest_def->ext2_features, &host_def.ext2_features,
1035 FEAT_8000_0001_EDX },
1036 {&guest_def->ext3_features, &host_def.ext3_features,
1037 FEAT_8000_0001_ECX },
1038 };
1039
1040 assert(kvm_enabled());
1041
1042 kvm_cpu_fill_host(&host_def);
1043 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1044 FeatureWord w = ft[i].feat_word;
1045 FeatureWordInfo *wi = &feature_word_info[w];
1046 for (mask = 1; mask; mask <<= 1) {
1047 if (*ft[i].guest_feat & mask &&
1048 !(*ft[i].host_feat & mask)) {
1049 unavailable_host_feature(wi, mask);
1050 rv = 1;
1051 }
1052 }
1053 }
1054 return rv;
1055 }
1056
1057 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1058 const char *name, Error **errp)
1059 {
1060 X86CPU *cpu = X86_CPU(obj);
1061 CPUX86State *env = &cpu->env;
1062 int64_t value;
1063
1064 value = (env->cpuid_version >> 8) & 0xf;
1065 if (value == 0xf) {
1066 value += (env->cpuid_version >> 20) & 0xff;
1067 }
1068 visit_type_int(v, &value, name, errp);
1069 }
1070
1071 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1072 const char *name, Error **errp)
1073 {
1074 X86CPU *cpu = X86_CPU(obj);
1075 CPUX86State *env = &cpu->env;
1076 const int64_t min = 0;
1077 const int64_t max = 0xff + 0xf;
1078 int64_t value;
1079
1080 visit_type_int(v, &value, name, errp);
1081 if (error_is_set(errp)) {
1082 return;
1083 }
1084 if (value < min || value > max) {
1085 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1086 name ? name : "null", value, min, max);
1087 return;
1088 }
1089
1090 env->cpuid_version &= ~0xff00f00;
1091 if (value > 0x0f) {
1092 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1093 } else {
1094 env->cpuid_version |= value << 8;
1095 }
1096 }
1097
1098 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1099 const char *name, Error **errp)
1100 {
1101 X86CPU *cpu = X86_CPU(obj);
1102 CPUX86State *env = &cpu->env;
1103 int64_t value;
1104
1105 value = (env->cpuid_version >> 4) & 0xf;
1106 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1107 visit_type_int(v, &value, name, errp);
1108 }
1109
1110 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1111 const char *name, Error **errp)
1112 {
1113 X86CPU *cpu = X86_CPU(obj);
1114 CPUX86State *env = &cpu->env;
1115 const int64_t min = 0;
1116 const int64_t max = 0xff;
1117 int64_t value;
1118
1119 visit_type_int(v, &value, name, errp);
1120 if (error_is_set(errp)) {
1121 return;
1122 }
1123 if (value < min || value > max) {
1124 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1125 name ? name : "null", value, min, max);
1126 return;
1127 }
1128
1129 env->cpuid_version &= ~0xf00f0;
1130 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1131 }
1132
1133 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1134 void *opaque, const char *name,
1135 Error **errp)
1136 {
1137 X86CPU *cpu = X86_CPU(obj);
1138 CPUX86State *env = &cpu->env;
1139 int64_t value;
1140
1141 value = env->cpuid_version & 0xf;
1142 visit_type_int(v, &value, name, errp);
1143 }
1144
1145 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1146 void *opaque, const char *name,
1147 Error **errp)
1148 {
1149 X86CPU *cpu = X86_CPU(obj);
1150 CPUX86State *env = &cpu->env;
1151 const int64_t min = 0;
1152 const int64_t max = 0xf;
1153 int64_t value;
1154
1155 visit_type_int(v, &value, name, errp);
1156 if (error_is_set(errp)) {
1157 return;
1158 }
1159 if (value < min || value > max) {
1160 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1161 name ? name : "null", value, min, max);
1162 return;
1163 }
1164
1165 env->cpuid_version &= ~0xf;
1166 env->cpuid_version |= value & 0xf;
1167 }
1168
1169 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1170 const char *name, Error **errp)
1171 {
1172 X86CPU *cpu = X86_CPU(obj);
1173
1174 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1175 }
1176
1177 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1178 const char *name, Error **errp)
1179 {
1180 X86CPU *cpu = X86_CPU(obj);
1181
1182 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1183 }
1184
1185 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1186 const char *name, Error **errp)
1187 {
1188 X86CPU *cpu = X86_CPU(obj);
1189
1190 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1191 }
1192
1193 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1194 const char *name, Error **errp)
1195 {
1196 X86CPU *cpu = X86_CPU(obj);
1197
1198 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1199 }
1200
1201 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1202 {
1203 X86CPU *cpu = X86_CPU(obj);
1204 CPUX86State *env = &cpu->env;
1205 char *value;
1206 int i;
1207
1208 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1209 for (i = 0; i < 4; i++) {
1210 value[i ] = env->cpuid_vendor1 >> (8 * i);
1211 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1212 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1213 }
1214 value[CPUID_VENDOR_SZ] = '\0';
1215 return value;
1216 }
1217
1218 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1219 Error **errp)
1220 {
1221 X86CPU *cpu = X86_CPU(obj);
1222 CPUX86State *env = &cpu->env;
1223 int i;
1224
1225 if (strlen(value) != CPUID_VENDOR_SZ) {
1226 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1227 "vendor", value);
1228 return;
1229 }
1230
1231 env->cpuid_vendor1 = 0;
1232 env->cpuid_vendor2 = 0;
1233 env->cpuid_vendor3 = 0;
1234 for (i = 0; i < 4; i++) {
1235 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1236 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1237 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1238 }
1239 env->cpuid_vendor_override = 1;
1240 }
1241
1242 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1243 {
1244 X86CPU *cpu = X86_CPU(obj);
1245 CPUX86State *env = &cpu->env;
1246 char *value;
1247 int i;
1248
1249 value = g_malloc(48 + 1);
1250 for (i = 0; i < 48; i++) {
1251 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1252 }
1253 value[48] = '\0';
1254 return value;
1255 }
1256
1257 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1258 Error **errp)
1259 {
1260 X86CPU *cpu = X86_CPU(obj);
1261 CPUX86State *env = &cpu->env;
1262 int c, len, i;
1263
1264 if (model_id == NULL) {
1265 model_id = "";
1266 }
1267 len = strlen(model_id);
1268 memset(env->cpuid_model, 0, 48);
1269 for (i = 0; i < 48; i++) {
1270 if (i >= len) {
1271 c = '\0';
1272 } else {
1273 c = (uint8_t)model_id[i];
1274 }
1275 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1276 }
1277 }
1278
1279 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1280 const char *name, Error **errp)
1281 {
1282 X86CPU *cpu = X86_CPU(obj);
1283 int64_t value;
1284
1285 value = cpu->env.tsc_khz * 1000;
1286 visit_type_int(v, &value, name, errp);
1287 }
1288
1289 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1290 const char *name, Error **errp)
1291 {
1292 X86CPU *cpu = X86_CPU(obj);
1293 const int64_t min = 0;
1294 const int64_t max = INT64_MAX;
1295 int64_t value;
1296
1297 visit_type_int(v, &value, name, errp);
1298 if (error_is_set(errp)) {
1299 return;
1300 }
1301 if (value < min || value > max) {
1302 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1303 name ? name : "null", value, min, max);
1304 return;
1305 }
1306
1307 cpu->env.tsc_khz = value / 1000;
1308 }
1309
1310 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1311 {
1312 x86_def_t *def;
1313
1314 for (def = x86_defs; def; def = def->next) {
1315 if (name && !strcmp(name, def->name)) {
1316 break;
1317 }
1318 }
1319 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1320 kvm_cpu_fill_host(x86_cpu_def);
1321 } else if (!def) {
1322 return -1;
1323 } else {
1324 memcpy(x86_cpu_def, def, sizeof(*def));
1325 }
1326
1327 return 0;
1328 }
1329
1330 /* Parse "+feature,-feature,feature=foo" CPU feature string
1331 */
1332 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1333 {
1334 unsigned int i;
1335 char *featurestr; /* Single 'key=value" string being parsed */
1336 /* Features to be added */
1337 FeatureWordArray plus_features = {
1338 [FEAT_KVM] = kvm_default_features,
1339 };
1340 /* Features to be removed */
1341 FeatureWordArray minus_features = { 0 };
1342 uint32_t numvalue;
1343
1344 add_flagname_to_bitmaps("hypervisor", plus_features);
1345
1346 featurestr = features ? strtok(features, ",") : NULL;
1347
1348 while (featurestr) {
1349 char *val;
1350 if (featurestr[0] == '+') {
1351 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1352 } else if (featurestr[0] == '-') {
1353 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1354 } else if ((val = strchr(featurestr, '='))) {
1355 *val = 0; val++;
1356 if (!strcmp(featurestr, "family")) {
1357 char *err;
1358 numvalue = strtoul(val, &err, 0);
1359 if (!*val || *err || numvalue > 0xff + 0xf) {
1360 fprintf(stderr, "bad numerical value %s\n", val);
1361 goto error;
1362 }
1363 x86_cpu_def->family = numvalue;
1364 } else if (!strcmp(featurestr, "model")) {
1365 char *err;
1366 numvalue = strtoul(val, &err, 0);
1367 if (!*val || *err || numvalue > 0xff) {
1368 fprintf(stderr, "bad numerical value %s\n", val);
1369 goto error;
1370 }
1371 x86_cpu_def->model = numvalue;
1372 } else if (!strcmp(featurestr, "stepping")) {
1373 char *err;
1374 numvalue = strtoul(val, &err, 0);
1375 if (!*val || *err || numvalue > 0xf) {
1376 fprintf(stderr, "bad numerical value %s\n", val);
1377 goto error;
1378 }
1379 x86_cpu_def->stepping = numvalue ;
1380 } else if (!strcmp(featurestr, "level")) {
1381 char *err;
1382 numvalue = strtoul(val, &err, 0);
1383 if (!*val || *err) {
1384 fprintf(stderr, "bad numerical value %s\n", val);
1385 goto error;
1386 }
1387 x86_cpu_def->level = numvalue;
1388 } else if (!strcmp(featurestr, "xlevel")) {
1389 char *err;
1390 numvalue = strtoul(val, &err, 0);
1391 if (!*val || *err) {
1392 fprintf(stderr, "bad numerical value %s\n", val);
1393 goto error;
1394 }
1395 if (numvalue < 0x80000000) {
1396 numvalue += 0x80000000;
1397 }
1398 x86_cpu_def->xlevel = numvalue;
1399 } else if (!strcmp(featurestr, "vendor")) {
1400 if (strlen(val) != 12) {
1401 fprintf(stderr, "vendor string must be 12 chars long\n");
1402 goto error;
1403 }
1404 x86_cpu_def->vendor1 = 0;
1405 x86_cpu_def->vendor2 = 0;
1406 x86_cpu_def->vendor3 = 0;
1407 for(i = 0; i < 4; i++) {
1408 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1409 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1410 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1411 }
1412 x86_cpu_def->vendor_override = 1;
1413 } else if (!strcmp(featurestr, "model_id")) {
1414 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1415 val);
1416 } else if (!strcmp(featurestr, "tsc_freq")) {
1417 int64_t tsc_freq;
1418 char *err;
1419
1420 tsc_freq = strtosz_suffix_unit(val, &err,
1421 STRTOSZ_DEFSUFFIX_B, 1000);
1422 if (tsc_freq < 0 || *err) {
1423 fprintf(stderr, "bad numerical value %s\n", val);
1424 goto error;
1425 }
1426 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1427 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1428 char *err;
1429 numvalue = strtoul(val, &err, 0);
1430 if (!*val || *err) {
1431 fprintf(stderr, "bad numerical value %s\n", val);
1432 goto error;
1433 }
1434 hyperv_set_spinlock_retries(numvalue);
1435 } else {
1436 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1437 goto error;
1438 }
1439 } else if (!strcmp(featurestr, "check")) {
1440 check_cpuid = 1;
1441 } else if (!strcmp(featurestr, "enforce")) {
1442 check_cpuid = enforce_cpuid = 1;
1443 } else if (!strcmp(featurestr, "hv_relaxed")) {
1444 hyperv_enable_relaxed_timing(true);
1445 } else if (!strcmp(featurestr, "hv_vapic")) {
1446 hyperv_enable_vapic_recommended(true);
1447 } else {
1448 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1449 goto error;
1450 }
1451 featurestr = strtok(NULL, ",");
1452 }
1453 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1454 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1455 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1456 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
1457 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
1458 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1459 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1460 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1461 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1462 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1463 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1464 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1465 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1466 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1467 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1468 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1469 if (check_cpuid && kvm_enabled()) {
1470 if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid)
1471 goto error;
1472 }
1473 return 0;
1474
1475 error:
1476 return -1;
1477 }
1478
1479 /* generate a composite string into buf of all cpuid names in featureset
1480 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1481 * if flags, suppress names undefined in featureset.
1482 */
1483 static void listflags(char *buf, int bufsize, uint32_t fbits,
1484 const char **featureset, uint32_t flags)
1485 {
1486 const char **p = &featureset[31];
1487 char *q, *b, bit;
1488 int nc;
1489
1490 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1491 *buf = '\0';
1492 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1493 if (fbits & 1 << bit && (*p || !flags)) {
1494 if (*p)
1495 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1496 else
1497 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1498 if (bufsize <= nc) {
1499 if (b) {
1500 memcpy(b, "...", sizeof("..."));
1501 }
1502 return;
1503 }
1504 q += nc;
1505 bufsize -= nc;
1506 }
1507 }
1508
1509 /* generate CPU information. */
1510 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1511 {
1512 x86_def_t *def;
1513 char buf[256];
1514
1515 for (def = x86_defs; def; def = def->next) {
1516 snprintf(buf, sizeof(buf), "%s", def->name);
1517 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1518 }
1519 if (kvm_enabled()) {
1520 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1521 }
1522 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1523 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1524 (*cpu_fprintf)(f, " %s\n", buf);
1525 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1526 (*cpu_fprintf)(f, " %s\n", buf);
1527 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1528 (*cpu_fprintf)(f, " %s\n", buf);
1529 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1530 (*cpu_fprintf)(f, " %s\n", buf);
1531 }
1532
1533 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1534 {
1535 CpuDefinitionInfoList *cpu_list = NULL;
1536 x86_def_t *def;
1537
1538 for (def = x86_defs; def; def = def->next) {
1539 CpuDefinitionInfoList *entry;
1540 CpuDefinitionInfo *info;
1541
1542 info = g_malloc0(sizeof(*info));
1543 info->name = g_strdup(def->name);
1544
1545 entry = g_malloc0(sizeof(*entry));
1546 entry->value = info;
1547 entry->next = cpu_list;
1548 cpu_list = entry;
1549 }
1550
1551 return cpu_list;
1552 }
1553
1554 #ifdef CONFIG_KVM
1555 static void filter_features_for_kvm(X86CPU *cpu)
1556 {
1557 CPUX86State *env = &cpu->env;
1558 KVMState *s = kvm_state;
1559
1560 env->cpuid_features &=
1561 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1562 env->cpuid_ext_features &=
1563 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1564 env->cpuid_ext2_features &=
1565 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1566 env->cpuid_ext3_features &=
1567 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1568 env->cpuid_svm_features &=
1569 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1570 env->cpuid_7_0_ebx_features &=
1571 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1572 env->cpuid_kvm_features &=
1573 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1574 env->cpuid_ext4_features &=
1575 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1576
1577 }
1578 #endif
1579
1580 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1581 {
1582 CPUX86State *env = &cpu->env;
1583 x86_def_t def1, *def = &def1;
1584 Error *error = NULL;
1585 char *name, *features;
1586 gchar **model_pieces;
1587
1588 memset(def, 0, sizeof(*def));
1589
1590 model_pieces = g_strsplit(cpu_model, ",", 2);
1591 if (!model_pieces[0]) {
1592 goto error;
1593 }
1594 name = model_pieces[0];
1595 features = model_pieces[1];
1596
1597 if (cpu_x86_find_by_name(def, name) < 0) {
1598 goto error;
1599 }
1600
1601 if (cpu_x86_parse_featurestr(def, features) < 0) {
1602 goto error;
1603 }
1604 assert(def->vendor1);
1605 env->cpuid_vendor1 = def->vendor1;
1606 env->cpuid_vendor2 = def->vendor2;
1607 env->cpuid_vendor3 = def->vendor3;
1608 env->cpuid_vendor_override = def->vendor_override;
1609 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1610 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1611 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1612 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1613 env->cpuid_features = def->features;
1614 env->cpuid_ext_features = def->ext_features;
1615 env->cpuid_ext2_features = def->ext2_features;
1616 env->cpuid_ext3_features = def->ext3_features;
1617 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1618 env->cpuid_kvm_features = def->kvm_features;
1619 env->cpuid_svm_features = def->svm_features;
1620 env->cpuid_ext4_features = def->ext4_features;
1621 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1622 env->cpuid_xlevel2 = def->xlevel2;
1623 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1624 "tsc-frequency", &error);
1625
1626 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1627 if (error) {
1628 fprintf(stderr, "%s\n", error_get_pretty(error));
1629 error_free(error);
1630 goto error;
1631 }
1632
1633 g_strfreev(model_pieces);
1634 return 0;
1635 error:
1636 g_strfreev(model_pieces);
1637 return -1;
1638 }
1639
1640 #if !defined(CONFIG_USER_ONLY)
1641
1642 void cpu_clear_apic_feature(CPUX86State *env)
1643 {
1644 env->cpuid_features &= ~CPUID_APIC;
1645 }
1646
1647 #endif /* !CONFIG_USER_ONLY */
1648
1649 /* Initialize list of CPU models, filling some non-static fields if necessary
1650 */
1651 void x86_cpudef_setup(void)
1652 {
1653 int i, j;
1654 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1655
1656 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1657 x86_def_t *def = &builtin_x86_defs[i];
1658 def->next = x86_defs;
1659
1660 /* Look for specific "cpudef" models that */
1661 /* have the QEMU version in .model_id */
1662 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1663 if (strcmp(model_with_versions[j], def->name) == 0) {
1664 pstrcpy(def->model_id, sizeof(def->model_id),
1665 "QEMU Virtual CPU version ");
1666 pstrcat(def->model_id, sizeof(def->model_id),
1667 qemu_get_version());
1668 break;
1669 }
1670 }
1671
1672 x86_defs = def;
1673 }
1674 }
1675
1676 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1677 uint32_t *ecx, uint32_t *edx)
1678 {
1679 *ebx = env->cpuid_vendor1;
1680 *edx = env->cpuid_vendor2;
1681 *ecx = env->cpuid_vendor3;
1682
1683 /* sysenter isn't supported on compatibility mode on AMD, syscall
1684 * isn't supported in compatibility mode on Intel.
1685 * Normally we advertise the actual cpu vendor, but you can override
1686 * this if you want to use KVM's sysenter/syscall emulation
1687 * in compatibility mode and when doing cross vendor migration
1688 */
1689 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1690 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1691 }
1692 }
1693
1694 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1695 uint32_t *eax, uint32_t *ebx,
1696 uint32_t *ecx, uint32_t *edx)
1697 {
1698 X86CPU *cpu = x86_env_get_cpu(env);
1699 CPUState *cs = CPU(cpu);
1700
1701 /* test if maximum index reached */
1702 if (index & 0x80000000) {
1703 if (index > env->cpuid_xlevel) {
1704 if (env->cpuid_xlevel2 > 0) {
1705 /* Handle the Centaur's CPUID instruction. */
1706 if (index > env->cpuid_xlevel2) {
1707 index = env->cpuid_xlevel2;
1708 } else if (index < 0xC0000000) {
1709 index = env->cpuid_xlevel;
1710 }
1711 } else {
1712 /* Intel documentation states that invalid EAX input will
1713 * return the same information as EAX=cpuid_level
1714 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1715 */
1716 index = env->cpuid_level;
1717 }
1718 }
1719 } else {
1720 if (index > env->cpuid_level)
1721 index = env->cpuid_level;
1722 }
1723
1724 switch(index) {
1725 case 0:
1726 *eax = env->cpuid_level;
1727 get_cpuid_vendor(env, ebx, ecx, edx);
1728 break;
1729 case 1:
1730 *eax = env->cpuid_version;
1731 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1732 *ecx = env->cpuid_ext_features;
1733 *edx = env->cpuid_features;
1734 if (cs->nr_cores * cs->nr_threads > 1) {
1735 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1736 *edx |= 1 << 28; /* HTT bit */
1737 }
1738 break;
1739 case 2:
1740 /* cache info: needed for Pentium Pro compatibility */
1741 *eax = 1;
1742 *ebx = 0;
1743 *ecx = 0;
1744 *edx = 0x2c307d;
1745 break;
1746 case 4:
1747 /* cache info: needed for Core compatibility */
1748 if (cs->nr_cores > 1) {
1749 *eax = (cs->nr_cores - 1) << 26;
1750 } else {
1751 *eax = 0;
1752 }
1753 switch (count) {
1754 case 0: /* L1 dcache info */
1755 *eax |= 0x0000121;
1756 *ebx = 0x1c0003f;
1757 *ecx = 0x000003f;
1758 *edx = 0x0000001;
1759 break;
1760 case 1: /* L1 icache info */
1761 *eax |= 0x0000122;
1762 *ebx = 0x1c0003f;
1763 *ecx = 0x000003f;
1764 *edx = 0x0000001;
1765 break;
1766 case 2: /* L2 cache info */
1767 *eax |= 0x0000143;
1768 if (cs->nr_threads > 1) {
1769 *eax |= (cs->nr_threads - 1) << 14;
1770 }
1771 *ebx = 0x3c0003f;
1772 *ecx = 0x0000fff;
1773 *edx = 0x0000001;
1774 break;
1775 default: /* end of info */
1776 *eax = 0;
1777 *ebx = 0;
1778 *ecx = 0;
1779 *edx = 0;
1780 break;
1781 }
1782 break;
1783 case 5:
1784 /* mwait info: needed for Core compatibility */
1785 *eax = 0; /* Smallest monitor-line size in bytes */
1786 *ebx = 0; /* Largest monitor-line size in bytes */
1787 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1788 *edx = 0;
1789 break;
1790 case 6:
1791 /* Thermal and Power Leaf */
1792 *eax = 0;
1793 *ebx = 0;
1794 *ecx = 0;
1795 *edx = 0;
1796 break;
1797 case 7:
1798 /* Structured Extended Feature Flags Enumeration Leaf */
1799 if (count == 0) {
1800 *eax = 0; /* Maximum ECX value for sub-leaves */
1801 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1802 *ecx = 0; /* Reserved */
1803 *edx = 0; /* Reserved */
1804 } else {
1805 *eax = 0;
1806 *ebx = 0;
1807 *ecx = 0;
1808 *edx = 0;
1809 }
1810 break;
1811 case 9:
1812 /* Direct Cache Access Information Leaf */
1813 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1814 *ebx = 0;
1815 *ecx = 0;
1816 *edx = 0;
1817 break;
1818 case 0xA:
1819 /* Architectural Performance Monitoring Leaf */
1820 if (kvm_enabled()) {
1821 KVMState *s = cs->kvm_state;
1822
1823 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1824 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1825 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1826 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1827 } else {
1828 *eax = 0;
1829 *ebx = 0;
1830 *ecx = 0;
1831 *edx = 0;
1832 }
1833 break;
1834 case 0xD:
1835 /* Processor Extended State */
1836 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1837 *eax = 0;
1838 *ebx = 0;
1839 *ecx = 0;
1840 *edx = 0;
1841 break;
1842 }
1843 if (kvm_enabled()) {
1844 KVMState *s = cs->kvm_state;
1845
1846 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1847 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1848 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1849 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1850 } else {
1851 *eax = 0;
1852 *ebx = 0;
1853 *ecx = 0;
1854 *edx = 0;
1855 }
1856 break;
1857 case 0x80000000:
1858 *eax = env->cpuid_xlevel;
1859 *ebx = env->cpuid_vendor1;
1860 *edx = env->cpuid_vendor2;
1861 *ecx = env->cpuid_vendor3;
1862 break;
1863 case 0x80000001:
1864 *eax = env->cpuid_version;
1865 *ebx = 0;
1866 *ecx = env->cpuid_ext3_features;
1867 *edx = env->cpuid_ext2_features;
1868
1869 /* The Linux kernel checks for the CMPLegacy bit and
1870 * discards multiple thread information if it is set.
1871 * So dont set it here for Intel to make Linux guests happy.
1872 */
1873 if (cs->nr_cores * cs->nr_threads > 1) {
1874 uint32_t tebx, tecx, tedx;
1875 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1876 if (tebx != CPUID_VENDOR_INTEL_1 ||
1877 tedx != CPUID_VENDOR_INTEL_2 ||
1878 tecx != CPUID_VENDOR_INTEL_3) {
1879 *ecx |= 1 << 1; /* CmpLegacy bit */
1880 }
1881 }
1882 break;
1883 case 0x80000002:
1884 case 0x80000003:
1885 case 0x80000004:
1886 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1887 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1888 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1889 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1890 break;
1891 case 0x80000005:
1892 /* cache info (L1 cache) */
1893 *eax = 0x01ff01ff;
1894 *ebx = 0x01ff01ff;
1895 *ecx = 0x40020140;
1896 *edx = 0x40020140;
1897 break;
1898 case 0x80000006:
1899 /* cache info (L2 cache) */
1900 *eax = 0;
1901 *ebx = 0x42004200;
1902 *ecx = 0x02008140;
1903 *edx = 0;
1904 break;
1905 case 0x80000008:
1906 /* virtual & phys address size in low 2 bytes. */
1907 /* XXX: This value must match the one used in the MMU code. */
1908 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1909 /* 64 bit processor */
1910 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1911 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1912 } else {
1913 if (env->cpuid_features & CPUID_PSE36)
1914 *eax = 0x00000024; /* 36 bits physical */
1915 else
1916 *eax = 0x00000020; /* 32 bits physical */
1917 }
1918 *ebx = 0;
1919 *ecx = 0;
1920 *edx = 0;
1921 if (cs->nr_cores * cs->nr_threads > 1) {
1922 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1923 }
1924 break;
1925 case 0x8000000A:
1926 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1927 *eax = 0x00000001; /* SVM Revision */
1928 *ebx = 0x00000010; /* nr of ASIDs */
1929 *ecx = 0;
1930 *edx = env->cpuid_svm_features; /* optional features */
1931 } else {
1932 *eax = 0;
1933 *ebx = 0;
1934 *ecx = 0;
1935 *edx = 0;
1936 }
1937 break;
1938 case 0xC0000000:
1939 *eax = env->cpuid_xlevel2;
1940 *ebx = 0;
1941 *ecx = 0;
1942 *edx = 0;
1943 break;
1944 case 0xC0000001:
1945 /* Support for VIA CPU's CPUID instruction */
1946 *eax = env->cpuid_version;
1947 *ebx = 0;
1948 *ecx = 0;
1949 *edx = env->cpuid_ext4_features;
1950 break;
1951 case 0xC0000002:
1952 case 0xC0000003:
1953 case 0xC0000004:
1954 /* Reserved for the future, and now filled with zero */
1955 *eax = 0;
1956 *ebx = 0;
1957 *ecx = 0;
1958 *edx = 0;
1959 break;
1960 default:
1961 /* reserved values: zero */
1962 *eax = 0;
1963 *ebx = 0;
1964 *ecx = 0;
1965 *edx = 0;
1966 break;
1967 }
1968 }
1969
1970 /* CPUClass::reset() */
1971 static void x86_cpu_reset(CPUState *s)
1972 {
1973 X86CPU *cpu = X86_CPU(s);
1974 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1975 CPUX86State *env = &cpu->env;
1976 int i;
1977
1978 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1979 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1980 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1981 }
1982
1983 xcc->parent_reset(s);
1984
1985
1986 memset(env, 0, offsetof(CPUX86State, breakpoints));
1987
1988 tlb_flush(env, 1);
1989
1990 env->old_exception = -1;
1991
1992 /* init to reset state */
1993
1994 #ifdef CONFIG_SOFTMMU
1995 env->hflags |= HF_SOFTMMU_MASK;
1996 #endif
1997 env->hflags2 |= HF2_GIF_MASK;
1998
1999 cpu_x86_update_cr0(env, 0x60000010);
2000 env->a20_mask = ~0x0;
2001 env->smbase = 0x30000;
2002
2003 env->idt.limit = 0xffff;
2004 env->gdt.limit = 0xffff;
2005 env->ldt.limit = 0xffff;
2006 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2007 env->tr.limit = 0xffff;
2008 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2009
2010 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2011 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2012 DESC_R_MASK | DESC_A_MASK);
2013 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2014 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2015 DESC_A_MASK);
2016 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2017 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2018 DESC_A_MASK);
2019 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2020 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2021 DESC_A_MASK);
2022 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2023 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2024 DESC_A_MASK);
2025 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2026 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2027 DESC_A_MASK);
2028
2029 env->eip = 0xfff0;
2030 env->regs[R_EDX] = env->cpuid_version;
2031
2032 env->eflags = 0x2;
2033
2034 /* FPU init */
2035 for (i = 0; i < 8; i++) {
2036 env->fptags[i] = 1;
2037 }
2038 env->fpuc = 0x37f;
2039
2040 env->mxcsr = 0x1f80;
2041
2042 env->pat = 0x0007040600070406ULL;
2043 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2044
2045 memset(env->dr, 0, sizeof(env->dr));
2046 env->dr[6] = DR6_FIXED_1;
2047 env->dr[7] = DR7_FIXED_1;
2048 cpu_breakpoint_remove_all(env, BP_CPU);
2049 cpu_watchpoint_remove_all(env, BP_CPU);
2050
2051 #if !defined(CONFIG_USER_ONLY)
2052 /* We hard-wire the BSP to the first CPU. */
2053 if (s->cpu_index == 0) {
2054 apic_designate_bsp(env->apic_state);
2055 }
2056
2057 env->halted = !cpu_is_bsp(cpu);
2058 #endif
2059 }
2060
2061 #ifndef CONFIG_USER_ONLY
2062 bool cpu_is_bsp(X86CPU *cpu)
2063 {
2064 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2065 }
2066
2067 /* TODO: remove me, when reset over QOM tree is implemented */
2068 static void x86_cpu_machine_reset_cb(void *opaque)
2069 {
2070 X86CPU *cpu = opaque;
2071 cpu_reset(CPU(cpu));
2072 }
2073 #endif
2074
2075 static void mce_init(X86CPU *cpu)
2076 {
2077 CPUX86State *cenv = &cpu->env;
2078 unsigned int bank;
2079
2080 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2081 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2082 (CPUID_MCE | CPUID_MCA)) {
2083 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2084 cenv->mcg_ctl = ~(uint64_t)0;
2085 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2086 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2087 }
2088 }
2089 }
2090
2091 #define MSI_ADDR_BASE 0xfee00000
2092
2093 #ifndef CONFIG_USER_ONLY
2094 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2095 {
2096 static int apic_mapped;
2097 CPUX86State *env = &cpu->env;
2098 APICCommonState *apic;
2099 const char *apic_type = "apic";
2100
2101 if (kvm_irqchip_in_kernel()) {
2102 apic_type = "kvm-apic";
2103 } else if (xen_enabled()) {
2104 apic_type = "xen-apic";
2105 }
2106
2107 env->apic_state = qdev_try_create(NULL, apic_type);
2108 if (env->apic_state == NULL) {
2109 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2110 return;
2111 }
2112
2113 object_property_add_child(OBJECT(cpu), "apic",
2114 OBJECT(env->apic_state), NULL);
2115 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2116 /* TODO: convert to link<> */
2117 apic = APIC_COMMON(env->apic_state);
2118 apic->cpu = cpu;
2119
2120 if (qdev_init(env->apic_state)) {
2121 error_setg(errp, "APIC device '%s' could not be initialized",
2122 object_get_typename(OBJECT(env->apic_state)));
2123 return;
2124 }
2125
2126 /* XXX: mapping more APICs at the same memory location */
2127 if (apic_mapped == 0) {
2128 /* NOTE: the APIC is directly connected to the CPU - it is not
2129 on the global memory bus. */
2130 /* XXX: what if the base changes? */
2131 sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE);
2132 apic_mapped = 1;
2133 }
2134 }
2135 #endif
2136
2137 void x86_cpu_realize(Object *obj, Error **errp)
2138 {
2139 X86CPU *cpu = X86_CPU(obj);
2140 CPUX86State *env = &cpu->env;
2141
2142 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2143 env->cpuid_level = 7;
2144 }
2145
2146 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2147 * CPUID[1].EDX.
2148 */
2149 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2150 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2151 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2152 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2153 env->cpuid_ext2_features |= (env->cpuid_features
2154 & CPUID_EXT2_AMD_ALIASES);
2155 }
2156
2157 if (!kvm_enabled()) {
2158 env->cpuid_features &= TCG_FEATURES;
2159 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2160 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2161 #ifdef TARGET_X86_64
2162 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2163 #endif
2164 );
2165 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2166 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2167 } else {
2168 #ifdef CONFIG_KVM
2169 filter_features_for_kvm(cpu);
2170 #endif
2171 }
2172
2173 #ifndef CONFIG_USER_ONLY
2174 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2175
2176 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2177 x86_cpu_apic_init(cpu, errp);
2178 if (error_is_set(errp)) {
2179 return;
2180 }
2181 }
2182 #endif
2183
2184 mce_init(cpu);
2185 qemu_init_vcpu(&cpu->env);
2186 cpu_reset(CPU(cpu));
2187 }
2188
2189 static void x86_cpu_initfn(Object *obj)
2190 {
2191 CPUState *cs = CPU(obj);
2192 X86CPU *cpu = X86_CPU(obj);
2193 CPUX86State *env = &cpu->env;
2194 static int inited;
2195
2196 cpu_exec_init(env);
2197
2198 object_property_add(obj, "family", "int",
2199 x86_cpuid_version_get_family,
2200 x86_cpuid_version_set_family, NULL, NULL, NULL);
2201 object_property_add(obj, "model", "int",
2202 x86_cpuid_version_get_model,
2203 x86_cpuid_version_set_model, NULL, NULL, NULL);
2204 object_property_add(obj, "stepping", "int",
2205 x86_cpuid_version_get_stepping,
2206 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2207 object_property_add(obj, "level", "int",
2208 x86_cpuid_get_level,
2209 x86_cpuid_set_level, NULL, NULL, NULL);
2210 object_property_add(obj, "xlevel", "int",
2211 x86_cpuid_get_xlevel,
2212 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2213 object_property_add_str(obj, "vendor",
2214 x86_cpuid_get_vendor,
2215 x86_cpuid_set_vendor, NULL);
2216 object_property_add_str(obj, "model-id",
2217 x86_cpuid_get_model_id,
2218 x86_cpuid_set_model_id, NULL);
2219 object_property_add(obj, "tsc-frequency", "int",
2220 x86_cpuid_get_tsc_freq,
2221 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2222
2223 env->cpuid_apic_id = cs->cpu_index;
2224
2225 /* init various static tables used in TCG mode */
2226 if (tcg_enabled() && !inited) {
2227 inited = 1;
2228 optimize_flags_init();
2229 #ifndef CONFIG_USER_ONLY
2230 cpu_set_debug_excp_handler(breakpoint_handler);
2231 #endif
2232 }
2233 }
2234
2235 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2236 {
2237 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2238 CPUClass *cc = CPU_CLASS(oc);
2239
2240 xcc->parent_reset = cc->reset;
2241 cc->reset = x86_cpu_reset;
2242 }
2243
2244 static const TypeInfo x86_cpu_type_info = {
2245 .name = TYPE_X86_CPU,
2246 .parent = TYPE_CPU,
2247 .instance_size = sizeof(X86CPU),
2248 .instance_init = x86_cpu_initfn,
2249 .abstract = false,
2250 .class_size = sizeof(X86CPUClass),
2251 .class_init = x86_cpu_common_class_init,
2252 };
2253
2254 static void x86_cpu_register_types(void)
2255 {
2256 type_register_static(&x86_cpu_type_info);
2257 }
2258
2259 type_init(x86_cpu_register_types)
Qemu copy for testing