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target-i386: Introduce x86_cpu_apic_id_from_index() function
[qemu.git] / target-i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26
27 #include "qemu/option.h"
28 #include "qemu/config-file.h"
29 #include "qapi/qmp/qerror.h"
30
31 #include "qapi/visitor.h"
32 #include "sysemu/arch_init.h"
33
34 #include "hyperv.h"
35
36 #include "hw/hw.h"
37 #if defined(CONFIG_KVM)
38 #include <linux/kvm_para.h>
39 #endif
40
41 #include "sysemu/sysemu.h"
42 #ifndef CONFIG_USER_ONLY
43 #include "hw/xen.h"
44 #include "hw/sysbus.h"
45 #include "hw/apic_internal.h"
46 #endif
47
48 /* feature flags taken from "Intel Processor Identification and the CPUID
49 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
50 * between feature naming conventions, aliases may be added.
51 */
52 static const char *feature_name[] = {
53 "fpu", "vme", "de", "pse",
54 "tsc", "msr", "pae", "mce",
55 "cx8", "apic", NULL, "sep",
56 "mtrr", "pge", "mca", "cmov",
57 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
58 NULL, "ds" /* Intel dts */, "acpi", "mmx",
59 "fxsr", "sse", "sse2", "ss",
60 "ht" /* Intel htt */, "tm", "ia64", "pbe",
61 };
62 static const char *ext_feature_name[] = {
63 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
64 "ds_cpl", "vmx", "smx", "est",
65 "tm2", "ssse3", "cid", NULL,
66 "fma", "cx16", "xtpr", "pdcm",
67 NULL, "pcid", "dca", "sse4.1|sse4_1",
68 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
69 "tsc-deadline", "aes", "xsave", "osxsave",
70 "avx", "f16c", "rdrand", "hypervisor",
71 };
72 /* Feature names that are already defined on feature_name[] but are set on
73 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
74 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
75 * if and only if CPU vendor is AMD.
76 */
77 static const char *ext2_feature_name[] = {
78 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
79 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
80 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
81 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
82 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
83 "nx|xd", NULL, "mmxext", NULL /* mmx */,
84 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
85 NULL, "lm|i64", "3dnowext", "3dnow",
86 };
87 static const char *ext3_feature_name[] = {
88 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
89 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
90 "3dnowprefetch", "osvw", "ibs", "xop",
91 "skinit", "wdt", NULL, "lwp",
92 "fma4", "tce", NULL, "nodeid_msr",
93 NULL, "tbm", "topoext", "perfctr_core",
94 "perfctr_nb", NULL, NULL, NULL,
95 NULL, NULL, NULL, NULL,
96 };
97
98 static const char *ext4_feature_name[] = {
99 NULL, NULL, "xstore", "xstore-en",
100 NULL, NULL, "xcrypt", "xcrypt-en",
101 "ace2", "ace2-en", "phe", "phe-en",
102 "pmm", "pmm-en", NULL, NULL,
103 NULL, NULL, NULL, NULL,
104 NULL, NULL, NULL, NULL,
105 NULL, NULL, NULL, NULL,
106 NULL, NULL, NULL, NULL,
107 };
108
109 static const char *kvm_feature_name[] = {
110 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
111 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
112 NULL, NULL, NULL, NULL,
113 NULL, NULL, NULL, NULL,
114 NULL, NULL, NULL, NULL,
115 NULL, NULL, NULL, NULL,
116 NULL, NULL, NULL, NULL,
117 NULL, NULL, NULL, NULL,
118 };
119
120 static const char *svm_feature_name[] = {
121 "npt", "lbrv", "svm_lock", "nrip_save",
122 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
123 NULL, NULL, "pause_filter", NULL,
124 "pfthreshold", NULL, NULL, NULL,
125 NULL, NULL, NULL, NULL,
126 NULL, NULL, NULL, NULL,
127 NULL, NULL, NULL, NULL,
128 NULL, NULL, NULL, NULL,
129 };
130
131 static const char *cpuid_7_0_ebx_feature_name[] = {
132 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
133 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
134 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
135 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
136 };
137
138 typedef struct FeatureWordInfo {
139 const char **feat_names;
140 uint32_t cpuid_eax; /* Input EAX for CPUID */
141 int cpuid_reg; /* R_* register constant */
142 } FeatureWordInfo;
143
144 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
145 [FEAT_1_EDX] = {
146 .feat_names = feature_name,
147 .cpuid_eax = 1, .cpuid_reg = R_EDX,
148 },
149 [FEAT_1_ECX] = {
150 .feat_names = ext_feature_name,
151 .cpuid_eax = 1, .cpuid_reg = R_ECX,
152 },
153 [FEAT_8000_0001_EDX] = {
154 .feat_names = ext2_feature_name,
155 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
156 },
157 [FEAT_8000_0001_ECX] = {
158 .feat_names = ext3_feature_name,
159 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
160 },
161 [FEAT_C000_0001_EDX] = {
162 .feat_names = ext4_feature_name,
163 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
164 },
165 [FEAT_KVM] = {
166 .feat_names = kvm_feature_name,
167 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
168 },
169 [FEAT_SVM] = {
170 .feat_names = svm_feature_name,
171 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
172 },
173 [FEAT_7_0_EBX] = {
174 .feat_names = cpuid_7_0_ebx_feature_name,
175 .cpuid_eax = 7, .cpuid_reg = R_EBX,
176 },
177 };
178
179 const char *get_register_name_32(unsigned int reg)
180 {
181 static const char *reg_names[CPU_NB_REGS32] = {
182 [R_EAX] = "EAX",
183 [R_ECX] = "ECX",
184 [R_EDX] = "EDX",
185 [R_EBX] = "EBX",
186 [R_ESP] = "ESP",
187 [R_EBP] = "EBP",
188 [R_ESI] = "ESI",
189 [R_EDI] = "EDI",
190 };
191
192 if (reg > CPU_NB_REGS32) {
193 return NULL;
194 }
195 return reg_names[reg];
196 }
197
198 /* collects per-function cpuid data
199 */
200 typedef struct model_features_t {
201 uint32_t *guest_feat;
202 uint32_t *host_feat;
203 FeatureWord feat_word;
204 } model_features_t;
205
206 int check_cpuid = 0;
207 int enforce_cpuid = 0;
208
209 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
210 (1 << KVM_FEATURE_NOP_IO_DELAY) |
211 (1 << KVM_FEATURE_CLOCKSOURCE2) |
212 (1 << KVM_FEATURE_ASYNC_PF) |
213 (1 << KVM_FEATURE_STEAL_TIME) |
214 (1 << KVM_FEATURE_PV_EOI) |
215 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
216
217 void disable_kvm_pv_eoi(void)
218 {
219 kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
220 }
221
222 void host_cpuid(uint32_t function, uint32_t count,
223 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
224 {
225 #if defined(CONFIG_KVM)
226 uint32_t vec[4];
227
228 #ifdef __x86_64__
229 asm volatile("cpuid"
230 : "=a"(vec[0]), "=b"(vec[1]),
231 "=c"(vec[2]), "=d"(vec[3])
232 : "0"(function), "c"(count) : "cc");
233 #else
234 asm volatile("pusha \n\t"
235 "cpuid \n\t"
236 "mov %%eax, 0(%2) \n\t"
237 "mov %%ebx, 4(%2) \n\t"
238 "mov %%ecx, 8(%2) \n\t"
239 "mov %%edx, 12(%2) \n\t"
240 "popa"
241 : : "a"(function), "c"(count), "S"(vec)
242 : "memory", "cc");
243 #endif
244
245 if (eax)
246 *eax = vec[0];
247 if (ebx)
248 *ebx = vec[1];
249 if (ecx)
250 *ecx = vec[2];
251 if (edx)
252 *edx = vec[3];
253 #endif
254 }
255
256 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
257
258 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
259 * a substring. ex if !NULL points to the first char after a substring,
260 * otherwise the string is assumed to sized by a terminating nul.
261 * Return lexical ordering of *s1:*s2.
262 */
263 static int sstrcmp(const char *s1, const char *e1, const char *s2,
264 const char *e2)
265 {
266 for (;;) {
267 if (!*s1 || !*s2 || *s1 != *s2)
268 return (*s1 - *s2);
269 ++s1, ++s2;
270 if (s1 == e1 && s2 == e2)
271 return (0);
272 else if (s1 == e1)
273 return (*s2);
274 else if (s2 == e2)
275 return (*s1);
276 }
277 }
278
279 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
280 * '|' delimited (possibly empty) strings in which case search for a match
281 * within the alternatives proceeds left to right. Return 0 for success,
282 * non-zero otherwise.
283 */
284 static int altcmp(const char *s, const char *e, const char *altstr)
285 {
286 const char *p, *q;
287
288 for (q = p = altstr; ; ) {
289 while (*p && *p != '|')
290 ++p;
291 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
292 return (0);
293 if (!*p)
294 return (1);
295 else
296 q = ++p;
297 }
298 }
299
300 /* search featureset for flag *[s..e), if found set corresponding bit in
301 * *pval and return true, otherwise return false
302 */
303 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
304 const char **featureset)
305 {
306 uint32_t mask;
307 const char **ppc;
308 bool found = false;
309
310 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
311 if (*ppc && !altcmp(s, e, *ppc)) {
312 *pval |= mask;
313 found = true;
314 }
315 }
316 return found;
317 }
318
319 static void add_flagname_to_bitmaps(const char *flagname,
320 FeatureWordArray words)
321 {
322 FeatureWord w;
323 for (w = 0; w < FEATURE_WORDS; w++) {
324 FeatureWordInfo *wi = &feature_word_info[w];
325 if (wi->feat_names &&
326 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
327 break;
328 }
329 }
330 if (w == FEATURE_WORDS) {
331 fprintf(stderr, "CPU feature %s not found\n", flagname);
332 }
333 }
334
335 typedef struct x86_def_t {
336 struct x86_def_t *next;
337 const char *name;
338 uint32_t level;
339 uint32_t vendor1, vendor2, vendor3;
340 int family;
341 int model;
342 int stepping;
343 int tsc_khz;
344 uint32_t features, ext_features, ext2_features, ext3_features;
345 uint32_t kvm_features, svm_features;
346 uint32_t xlevel;
347 char model_id[48];
348 int vendor_override;
349 /* Store the results of Centaur's CPUID instructions */
350 uint32_t ext4_features;
351 uint32_t xlevel2;
352 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
353 uint32_t cpuid_7_0_ebx_features;
354 } x86_def_t;
355
356 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
357 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
358 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
359 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
360 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
361 CPUID_PSE36 | CPUID_FXSR)
362 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
363 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
364 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
365 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
366 CPUID_PAE | CPUID_SEP | CPUID_APIC)
367
368 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
369 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
370 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
371 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
372 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
373 /* partly implemented:
374 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
375 CPUID_PSE36 (needed for Solaris) */
376 /* missing:
377 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
378 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
379 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
380 CPUID_EXT_HYPERVISOR)
381 /* missing:
382 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
383 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
384 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
385 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
386 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
387 /* missing:
388 CPUID_EXT2_PDPE1GB */
389 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
390 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
391 #define TCG_SVM_FEATURES 0
392 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
393
394 /* maintains list of cpu model definitions
395 */
396 static x86_def_t *x86_defs = {NULL};
397
398 /* built-in cpu model definitions (deprecated)
399 */
400 static x86_def_t builtin_x86_defs[] = {
401 {
402 .name = "qemu64",
403 .level = 4,
404 .vendor1 = CPUID_VENDOR_AMD_1,
405 .vendor2 = CPUID_VENDOR_AMD_2,
406 .vendor3 = CPUID_VENDOR_AMD_3,
407 .family = 6,
408 .model = 2,
409 .stepping = 3,
410 .features = PPRO_FEATURES |
411 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
412 CPUID_PSE36,
413 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
414 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
415 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
416 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
417 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
418 .xlevel = 0x8000000A,
419 },
420 {
421 .name = "phenom",
422 .level = 5,
423 .vendor1 = CPUID_VENDOR_AMD_1,
424 .vendor2 = CPUID_VENDOR_AMD_2,
425 .vendor3 = CPUID_VENDOR_AMD_3,
426 .family = 16,
427 .model = 2,
428 .stepping = 3,
429 .features = PPRO_FEATURES |
430 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
431 CPUID_PSE36 | CPUID_VME | CPUID_HT,
432 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
433 CPUID_EXT_POPCNT,
434 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
435 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
436 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
437 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
438 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
439 CPUID_EXT3_CR8LEG,
440 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
441 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
442 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
443 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
444 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
445 .xlevel = 0x8000001A,
446 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
447 },
448 {
449 .name = "core2duo",
450 .level = 10,
451 .vendor1 = CPUID_VENDOR_INTEL_1,
452 .vendor2 = CPUID_VENDOR_INTEL_2,
453 .vendor3 = CPUID_VENDOR_INTEL_3,
454 .family = 6,
455 .model = 15,
456 .stepping = 11,
457 .features = PPRO_FEATURES |
458 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
459 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
460 CPUID_HT | CPUID_TM | CPUID_PBE,
461 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
462 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
463 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
464 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
465 .ext3_features = CPUID_EXT3_LAHF_LM,
466 .xlevel = 0x80000008,
467 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
468 },
469 {
470 .name = "kvm64",
471 .level = 5,
472 .vendor1 = CPUID_VENDOR_INTEL_1,
473 .vendor2 = CPUID_VENDOR_INTEL_2,
474 .vendor3 = CPUID_VENDOR_INTEL_3,
475 .family = 15,
476 .model = 6,
477 .stepping = 1,
478 /* Missing: CPUID_VME, CPUID_HT */
479 .features = PPRO_FEATURES |
480 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
481 CPUID_PSE36,
482 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
483 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
484 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
485 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
486 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
487 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
488 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
489 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
490 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
491 .ext3_features = 0,
492 .xlevel = 0x80000008,
493 .model_id = "Common KVM processor"
494 },
495 {
496 .name = "qemu32",
497 .level = 4,
498 .vendor1 = CPUID_VENDOR_INTEL_1,
499 .vendor2 = CPUID_VENDOR_INTEL_2,
500 .vendor3 = CPUID_VENDOR_INTEL_3,
501 .family = 6,
502 .model = 3,
503 .stepping = 3,
504 .features = PPRO_FEATURES,
505 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
506 .xlevel = 0x80000004,
507 },
508 {
509 .name = "kvm32",
510 .level = 5,
511 .vendor1 = CPUID_VENDOR_INTEL_1,
512 .vendor2 = CPUID_VENDOR_INTEL_2,
513 .vendor3 = CPUID_VENDOR_INTEL_3,
514 .family = 15,
515 .model = 6,
516 .stepping = 1,
517 .features = PPRO_FEATURES |
518 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
519 .ext_features = CPUID_EXT_SSE3,
520 .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
521 .ext3_features = 0,
522 .xlevel = 0x80000008,
523 .model_id = "Common 32-bit KVM processor"
524 },
525 {
526 .name = "coreduo",
527 .level = 10,
528 .vendor1 = CPUID_VENDOR_INTEL_1,
529 .vendor2 = CPUID_VENDOR_INTEL_2,
530 .vendor3 = CPUID_VENDOR_INTEL_3,
531 .family = 6,
532 .model = 14,
533 .stepping = 8,
534 .features = PPRO_FEATURES | CPUID_VME |
535 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
536 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
537 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
538 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
539 .ext2_features = CPUID_EXT2_NX,
540 .xlevel = 0x80000008,
541 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
542 },
543 {
544 .name = "486",
545 .level = 1,
546 .vendor1 = CPUID_VENDOR_INTEL_1,
547 .vendor2 = CPUID_VENDOR_INTEL_2,
548 .vendor3 = CPUID_VENDOR_INTEL_3,
549 .family = 4,
550 .model = 0,
551 .stepping = 0,
552 .features = I486_FEATURES,
553 .xlevel = 0,
554 },
555 {
556 .name = "pentium",
557 .level = 1,
558 .vendor1 = CPUID_VENDOR_INTEL_1,
559 .vendor2 = CPUID_VENDOR_INTEL_2,
560 .vendor3 = CPUID_VENDOR_INTEL_3,
561 .family = 5,
562 .model = 4,
563 .stepping = 3,
564 .features = PENTIUM_FEATURES,
565 .xlevel = 0,
566 },
567 {
568 .name = "pentium2",
569 .level = 2,
570 .vendor1 = CPUID_VENDOR_INTEL_1,
571 .vendor2 = CPUID_VENDOR_INTEL_2,
572 .vendor3 = CPUID_VENDOR_INTEL_3,
573 .family = 6,
574 .model = 5,
575 .stepping = 2,
576 .features = PENTIUM2_FEATURES,
577 .xlevel = 0,
578 },
579 {
580 .name = "pentium3",
581 .level = 2,
582 .vendor1 = CPUID_VENDOR_INTEL_1,
583 .vendor2 = CPUID_VENDOR_INTEL_2,
584 .vendor3 = CPUID_VENDOR_INTEL_3,
585 .family = 6,
586 .model = 7,
587 .stepping = 3,
588 .features = PENTIUM3_FEATURES,
589 .xlevel = 0,
590 },
591 {
592 .name = "athlon",
593 .level = 2,
594 .vendor1 = CPUID_VENDOR_AMD_1,
595 .vendor2 = CPUID_VENDOR_AMD_2,
596 .vendor3 = CPUID_VENDOR_AMD_3,
597 .family = 6,
598 .model = 2,
599 .stepping = 3,
600 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
601 CPUID_MCA,
602 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
603 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
604 .xlevel = 0x80000008,
605 },
606 {
607 .name = "n270",
608 /* original is on level 10 */
609 .level = 5,
610 .vendor1 = CPUID_VENDOR_INTEL_1,
611 .vendor2 = CPUID_VENDOR_INTEL_2,
612 .vendor3 = CPUID_VENDOR_INTEL_3,
613 .family = 6,
614 .model = 28,
615 .stepping = 2,
616 .features = PPRO_FEATURES |
617 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
618 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
619 /* Some CPUs got no CPUID_SEP */
620 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
621 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
622 .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
623 CPUID_EXT2_NX,
624 .ext3_features = CPUID_EXT3_LAHF_LM,
625 .xlevel = 0x8000000A,
626 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
627 },
628 {
629 .name = "Conroe",
630 .level = 2,
631 .vendor1 = CPUID_VENDOR_INTEL_1,
632 .vendor2 = CPUID_VENDOR_INTEL_2,
633 .vendor3 = CPUID_VENDOR_INTEL_3,
634 .family = 6,
635 .model = 2,
636 .stepping = 3,
637 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
638 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
639 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
640 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
641 CPUID_DE | CPUID_FP87,
642 .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
643 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
644 .ext3_features = CPUID_EXT3_LAHF_LM,
645 .xlevel = 0x8000000A,
646 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
647 },
648 {
649 .name = "Penryn",
650 .level = 2,
651 .vendor1 = CPUID_VENDOR_INTEL_1,
652 .vendor2 = CPUID_VENDOR_INTEL_2,
653 .vendor3 = CPUID_VENDOR_INTEL_3,
654 .family = 6,
655 .model = 2,
656 .stepping = 3,
657 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
658 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
659 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
660 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
661 CPUID_DE | CPUID_FP87,
662 .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
663 CPUID_EXT_SSE3,
664 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
665 .ext3_features = CPUID_EXT3_LAHF_LM,
666 .xlevel = 0x8000000A,
667 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
668 },
669 {
670 .name = "Nehalem",
671 .level = 2,
672 .vendor1 = CPUID_VENDOR_INTEL_1,
673 .vendor2 = CPUID_VENDOR_INTEL_2,
674 .vendor3 = CPUID_VENDOR_INTEL_3,
675 .family = 6,
676 .model = 2,
677 .stepping = 3,
678 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
679 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
680 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
681 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
682 CPUID_DE | CPUID_FP87,
683 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
684 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
685 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
686 .ext3_features = CPUID_EXT3_LAHF_LM,
687 .xlevel = 0x8000000A,
688 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
689 },
690 {
691 .name = "Westmere",
692 .level = 11,
693 .vendor1 = CPUID_VENDOR_INTEL_1,
694 .vendor2 = CPUID_VENDOR_INTEL_2,
695 .vendor3 = CPUID_VENDOR_INTEL_3,
696 .family = 6,
697 .model = 44,
698 .stepping = 1,
699 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
700 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
701 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
702 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
703 CPUID_DE | CPUID_FP87,
704 .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
705 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
706 CPUID_EXT_SSE3,
707 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
708 .ext3_features = CPUID_EXT3_LAHF_LM,
709 .xlevel = 0x8000000A,
710 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
711 },
712 {
713 .name = "SandyBridge",
714 .level = 0xd,
715 .vendor1 = CPUID_VENDOR_INTEL_1,
716 .vendor2 = CPUID_VENDOR_INTEL_2,
717 .vendor3 = CPUID_VENDOR_INTEL_3,
718 .family = 6,
719 .model = 42,
720 .stepping = 1,
721 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
722 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
723 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
724 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
725 CPUID_DE | CPUID_FP87,
726 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
727 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
728 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
729 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
730 CPUID_EXT_SSE3,
731 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
732 CPUID_EXT2_SYSCALL,
733 .ext3_features = CPUID_EXT3_LAHF_LM,
734 .xlevel = 0x8000000A,
735 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
736 },
737 {
738 .name = "Haswell",
739 .level = 0xd,
740 .vendor1 = CPUID_VENDOR_INTEL_1,
741 .vendor2 = CPUID_VENDOR_INTEL_2,
742 .vendor3 = CPUID_VENDOR_INTEL_3,
743 .family = 6,
744 .model = 60,
745 .stepping = 1,
746 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
747 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
748 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
749 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
750 CPUID_DE | CPUID_FP87,
751 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
752 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
753 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
754 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
755 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
756 CPUID_EXT_PCID,
757 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
758 CPUID_EXT2_SYSCALL,
759 .ext3_features = CPUID_EXT3_LAHF_LM,
760 .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
761 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
762 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
763 CPUID_7_0_EBX_RTM,
764 .xlevel = 0x8000000A,
765 .model_id = "Intel Core Processor (Haswell)",
766 },
767 {
768 .name = "Opteron_G1",
769 .level = 5,
770 .vendor1 = CPUID_VENDOR_AMD_1,
771 .vendor2 = CPUID_VENDOR_AMD_2,
772 .vendor3 = CPUID_VENDOR_AMD_3,
773 .family = 15,
774 .model = 6,
775 .stepping = 1,
776 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
777 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
778 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
779 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
780 CPUID_DE | CPUID_FP87,
781 .ext_features = CPUID_EXT_SSE3,
782 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
783 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
784 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
785 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
786 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
787 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
788 .xlevel = 0x80000008,
789 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
790 },
791 {
792 .name = "Opteron_G2",
793 .level = 5,
794 .vendor1 = CPUID_VENDOR_AMD_1,
795 .vendor2 = CPUID_VENDOR_AMD_2,
796 .vendor3 = CPUID_VENDOR_AMD_3,
797 .family = 15,
798 .model = 6,
799 .stepping = 1,
800 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
801 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
802 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
803 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
804 CPUID_DE | CPUID_FP87,
805 .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
806 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
807 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
808 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
809 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
810 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
811 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
812 CPUID_EXT2_DE | CPUID_EXT2_FPU,
813 .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
814 .xlevel = 0x80000008,
815 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
816 },
817 {
818 .name = "Opteron_G3",
819 .level = 5,
820 .vendor1 = CPUID_VENDOR_AMD_1,
821 .vendor2 = CPUID_VENDOR_AMD_2,
822 .vendor3 = CPUID_VENDOR_AMD_3,
823 .family = 15,
824 .model = 6,
825 .stepping = 1,
826 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
827 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
828 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
829 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
830 CPUID_DE | CPUID_FP87,
831 .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
832 CPUID_EXT_SSE3,
833 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
834 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
835 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
836 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
837 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
838 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
839 CPUID_EXT2_DE | CPUID_EXT2_FPU,
840 .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
841 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
842 .xlevel = 0x80000008,
843 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
844 },
845 {
846 .name = "Opteron_G4",
847 .level = 0xd,
848 .vendor1 = CPUID_VENDOR_AMD_1,
849 .vendor2 = CPUID_VENDOR_AMD_2,
850 .vendor3 = CPUID_VENDOR_AMD_3,
851 .family = 21,
852 .model = 1,
853 .stepping = 2,
854 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
855 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
856 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
857 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
858 CPUID_DE | CPUID_FP87,
859 .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
860 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
861 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
862 CPUID_EXT_SSE3,
863 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
864 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
865 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
866 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
867 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
868 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
869 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
870 .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
871 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
872 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
873 CPUID_EXT3_LAHF_LM,
874 .xlevel = 0x8000001A,
875 .model_id = "AMD Opteron 62xx class CPU",
876 },
877 {
878 .name = "Opteron_G5",
879 .level = 0xd,
880 .vendor1 = CPUID_VENDOR_AMD_1,
881 .vendor2 = CPUID_VENDOR_AMD_2,
882 .vendor3 = CPUID_VENDOR_AMD_3,
883 .family = 21,
884 .model = 2,
885 .stepping = 0,
886 .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
887 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
888 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
889 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
890 CPUID_DE | CPUID_FP87,
891 .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
892 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
893 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
894 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
895 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
896 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
897 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
898 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
899 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
900 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
901 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
902 .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
903 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
904 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
905 CPUID_EXT3_LAHF_LM,
906 .xlevel = 0x8000001A,
907 .model_id = "AMD Opteron 63xx class CPU",
908 },
909 };
910
911 #ifdef CONFIG_KVM
912 static int cpu_x86_fill_model_id(char *str)
913 {
914 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
915 int i;
916
917 for (i = 0; i < 3; i++) {
918 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
919 memcpy(str + i * 16 + 0, &eax, 4);
920 memcpy(str + i * 16 + 4, &ebx, 4);
921 memcpy(str + i * 16 + 8, &ecx, 4);
922 memcpy(str + i * 16 + 12, &edx, 4);
923 }
924 return 0;
925 }
926 #endif
927
928 /* Fill a x86_def_t struct with information about the host CPU, and
929 * the CPU features supported by the host hardware + host kernel
930 *
931 * This function may be called only if KVM is enabled.
932 */
933 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
934 {
935 #ifdef CONFIG_KVM
936 KVMState *s = kvm_state;
937 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
938
939 assert(kvm_enabled());
940
941 x86_cpu_def->name = "host";
942 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
943 x86_cpu_def->vendor1 = ebx;
944 x86_cpu_def->vendor2 = edx;
945 x86_cpu_def->vendor3 = ecx;
946
947 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
948 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
949 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
950 x86_cpu_def->stepping = eax & 0x0F;
951
952 x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
953 x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
954 x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
955
956 if (x86_cpu_def->level >= 7) {
957 x86_cpu_def->cpuid_7_0_ebx_features =
958 kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
959 } else {
960 x86_cpu_def->cpuid_7_0_ebx_features = 0;
961 }
962
963 x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
964 x86_cpu_def->ext2_features =
965 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
966 x86_cpu_def->ext3_features =
967 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
968
969 cpu_x86_fill_model_id(x86_cpu_def->model_id);
970 x86_cpu_def->vendor_override = 0;
971
972 /* Call Centaur's CPUID instruction. */
973 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
974 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
975 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
976 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
977 eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
978 if (eax >= 0xC0000001) {
979 /* Support VIA max extended level */
980 x86_cpu_def->xlevel2 = eax;
981 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
982 x86_cpu_def->ext4_features =
983 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
984 }
985 }
986
987 /* Other KVM-specific feature fields: */
988 x86_cpu_def->svm_features =
989 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
990 x86_cpu_def->kvm_features =
991 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
992
993 #endif /* CONFIG_KVM */
994 }
995
996 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
997 {
998 int i;
999
1000 for (i = 0; i < 32; ++i)
1001 if (1 << i & mask) {
1002 const char *reg = get_register_name_32(f->cpuid_reg);
1003 assert(reg);
1004 fprintf(stderr, "warning: host doesn't support requested feature: "
1005 "CPUID.%02XH:%s%s%s [bit %d]\n",
1006 f->cpuid_eax, reg,
1007 f->feat_names[i] ? "." : "",
1008 f->feat_names[i] ? f->feat_names[i] : "", i);
1009 break;
1010 }
1011 return 0;
1012 }
1013
1014 /* Check if all requested cpu flags are making their way to the guest
1015 *
1016 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1017 *
1018 * This function may be called only if KVM is enabled.
1019 */
1020 static int kvm_check_features_against_host(X86CPU *cpu)
1021 {
1022 CPUX86State *env = &cpu->env;
1023 x86_def_t host_def;
1024 uint32_t mask;
1025 int rv, i;
1026 struct model_features_t ft[] = {
1027 {&env->cpuid_features, &host_def.features,
1028 FEAT_1_EDX },
1029 {&env->cpuid_ext_features, &host_def.ext_features,
1030 FEAT_1_ECX },
1031 {&env->cpuid_ext2_features, &host_def.ext2_features,
1032 FEAT_8000_0001_EDX },
1033 {&env->cpuid_ext3_features, &host_def.ext3_features,
1034 FEAT_8000_0001_ECX },
1035 {&env->cpuid_ext4_features, &host_def.ext4_features,
1036 FEAT_C000_0001_EDX },
1037 {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
1038 FEAT_7_0_EBX },
1039 {&env->cpuid_svm_features, &host_def.svm_features,
1040 FEAT_SVM },
1041 {&env->cpuid_kvm_features, &host_def.kvm_features,
1042 FEAT_KVM },
1043 };
1044
1045 assert(kvm_enabled());
1046
1047 kvm_cpu_fill_host(&host_def);
1048 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1049 FeatureWord w = ft[i].feat_word;
1050 FeatureWordInfo *wi = &feature_word_info[w];
1051 for (mask = 1; mask; mask <<= 1) {
1052 if (*ft[i].guest_feat & mask &&
1053 !(*ft[i].host_feat & mask)) {
1054 unavailable_host_feature(wi, mask);
1055 rv = 1;
1056 }
1057 }
1058 }
1059 return rv;
1060 }
1061
1062 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1063 const char *name, Error **errp)
1064 {
1065 X86CPU *cpu = X86_CPU(obj);
1066 CPUX86State *env = &cpu->env;
1067 int64_t value;
1068
1069 value = (env->cpuid_version >> 8) & 0xf;
1070 if (value == 0xf) {
1071 value += (env->cpuid_version >> 20) & 0xff;
1072 }
1073 visit_type_int(v, &value, name, errp);
1074 }
1075
1076 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1077 const char *name, Error **errp)
1078 {
1079 X86CPU *cpu = X86_CPU(obj);
1080 CPUX86State *env = &cpu->env;
1081 const int64_t min = 0;
1082 const int64_t max = 0xff + 0xf;
1083 int64_t value;
1084
1085 visit_type_int(v, &value, name, errp);
1086 if (error_is_set(errp)) {
1087 return;
1088 }
1089 if (value < min || value > max) {
1090 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1091 name ? name : "null", value, min, max);
1092 return;
1093 }
1094
1095 env->cpuid_version &= ~0xff00f00;
1096 if (value > 0x0f) {
1097 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1098 } else {
1099 env->cpuid_version |= value << 8;
1100 }
1101 }
1102
1103 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1104 const char *name, Error **errp)
1105 {
1106 X86CPU *cpu = X86_CPU(obj);
1107 CPUX86State *env = &cpu->env;
1108 int64_t value;
1109
1110 value = (env->cpuid_version >> 4) & 0xf;
1111 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1112 visit_type_int(v, &value, name, errp);
1113 }
1114
1115 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1116 const char *name, Error **errp)
1117 {
1118 X86CPU *cpu = X86_CPU(obj);
1119 CPUX86State *env = &cpu->env;
1120 const int64_t min = 0;
1121 const int64_t max = 0xff;
1122 int64_t value;
1123
1124 visit_type_int(v, &value, name, errp);
1125 if (error_is_set(errp)) {
1126 return;
1127 }
1128 if (value < min || value > max) {
1129 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1130 name ? name : "null", value, min, max);
1131 return;
1132 }
1133
1134 env->cpuid_version &= ~0xf00f0;
1135 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1136 }
1137
1138 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1139 void *opaque, const char *name,
1140 Error **errp)
1141 {
1142 X86CPU *cpu = X86_CPU(obj);
1143 CPUX86State *env = &cpu->env;
1144 int64_t value;
1145
1146 value = env->cpuid_version & 0xf;
1147 visit_type_int(v, &value, name, errp);
1148 }
1149
1150 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1151 void *opaque, const char *name,
1152 Error **errp)
1153 {
1154 X86CPU *cpu = X86_CPU(obj);
1155 CPUX86State *env = &cpu->env;
1156 const int64_t min = 0;
1157 const int64_t max = 0xf;
1158 int64_t value;
1159
1160 visit_type_int(v, &value, name, errp);
1161 if (error_is_set(errp)) {
1162 return;
1163 }
1164 if (value < min || value > max) {
1165 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1166 name ? name : "null", value, min, max);
1167 return;
1168 }
1169
1170 env->cpuid_version &= ~0xf;
1171 env->cpuid_version |= value & 0xf;
1172 }
1173
1174 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1175 const char *name, Error **errp)
1176 {
1177 X86CPU *cpu = X86_CPU(obj);
1178
1179 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1180 }
1181
1182 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1183 const char *name, Error **errp)
1184 {
1185 X86CPU *cpu = X86_CPU(obj);
1186
1187 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1188 }
1189
1190 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1191 const char *name, Error **errp)
1192 {
1193 X86CPU *cpu = X86_CPU(obj);
1194
1195 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1196 }
1197
1198 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1199 const char *name, Error **errp)
1200 {
1201 X86CPU *cpu = X86_CPU(obj);
1202
1203 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1204 }
1205
1206 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1207 {
1208 X86CPU *cpu = X86_CPU(obj);
1209 CPUX86State *env = &cpu->env;
1210 char *value;
1211 int i;
1212
1213 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1214 for (i = 0; i < 4; i++) {
1215 value[i ] = env->cpuid_vendor1 >> (8 * i);
1216 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
1217 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
1218 }
1219 value[CPUID_VENDOR_SZ] = '\0';
1220 return value;
1221 }
1222
1223 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1224 Error **errp)
1225 {
1226 X86CPU *cpu = X86_CPU(obj);
1227 CPUX86State *env = &cpu->env;
1228 int i;
1229
1230 if (strlen(value) != CPUID_VENDOR_SZ) {
1231 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1232 "vendor", value);
1233 return;
1234 }
1235
1236 env->cpuid_vendor1 = 0;
1237 env->cpuid_vendor2 = 0;
1238 env->cpuid_vendor3 = 0;
1239 for (i = 0; i < 4; i++) {
1240 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1241 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1242 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1243 }
1244 env->cpuid_vendor_override = 1;
1245 }
1246
1247 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1248 {
1249 X86CPU *cpu = X86_CPU(obj);
1250 CPUX86State *env = &cpu->env;
1251 char *value;
1252 int i;
1253
1254 value = g_malloc(48 + 1);
1255 for (i = 0; i < 48; i++) {
1256 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1257 }
1258 value[48] = '\0';
1259 return value;
1260 }
1261
1262 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1263 Error **errp)
1264 {
1265 X86CPU *cpu = X86_CPU(obj);
1266 CPUX86State *env = &cpu->env;
1267 int c, len, i;
1268
1269 if (model_id == NULL) {
1270 model_id = "";
1271 }
1272 len = strlen(model_id);
1273 memset(env->cpuid_model, 0, 48);
1274 for (i = 0; i < 48; i++) {
1275 if (i >= len) {
1276 c = '\0';
1277 } else {
1278 c = (uint8_t)model_id[i];
1279 }
1280 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1281 }
1282 }
1283
1284 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1285 const char *name, Error **errp)
1286 {
1287 X86CPU *cpu = X86_CPU(obj);
1288 int64_t value;
1289
1290 value = cpu->env.tsc_khz * 1000;
1291 visit_type_int(v, &value, name, errp);
1292 }
1293
1294 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1295 const char *name, Error **errp)
1296 {
1297 X86CPU *cpu = X86_CPU(obj);
1298 const int64_t min = 0;
1299 const int64_t max = INT64_MAX;
1300 int64_t value;
1301
1302 visit_type_int(v, &value, name, errp);
1303 if (error_is_set(errp)) {
1304 return;
1305 }
1306 if (value < min || value > max) {
1307 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1308 name ? name : "null", value, min, max);
1309 return;
1310 }
1311
1312 cpu->env.tsc_khz = value / 1000;
1313 }
1314
1315 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1316 {
1317 x86_def_t *def;
1318
1319 for (def = x86_defs; def; def = def->next) {
1320 if (name && !strcmp(name, def->name)) {
1321 break;
1322 }
1323 }
1324 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
1325 kvm_cpu_fill_host(x86_cpu_def);
1326 } else if (!def) {
1327 return -1;
1328 } else {
1329 memcpy(x86_cpu_def, def, sizeof(*def));
1330 }
1331
1332 return 0;
1333 }
1334
1335 /* Parse "+feature,-feature,feature=foo" CPU feature string
1336 */
1337 static int cpu_x86_parse_featurestr(x86_def_t *x86_cpu_def, char *features)
1338 {
1339 unsigned int i;
1340 char *featurestr; /* Single 'key=value" string being parsed */
1341 /* Features to be added */
1342 FeatureWordArray plus_features = { 0 };
1343 /* Features to be removed */
1344 FeatureWordArray minus_features = { 0 };
1345 uint32_t numvalue;
1346
1347 featurestr = features ? strtok(features, ",") : NULL;
1348
1349 while (featurestr) {
1350 char *val;
1351 if (featurestr[0] == '+') {
1352 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1353 } else if (featurestr[0] == '-') {
1354 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1355 } else if ((val = strchr(featurestr, '='))) {
1356 *val = 0; val++;
1357 if (!strcmp(featurestr, "family")) {
1358 char *err;
1359 numvalue = strtoul(val, &err, 0);
1360 if (!*val || *err || numvalue > 0xff + 0xf) {
1361 fprintf(stderr, "bad numerical value %s\n", val);
1362 goto error;
1363 }
1364 x86_cpu_def->family = numvalue;
1365 } else if (!strcmp(featurestr, "model")) {
1366 char *err;
1367 numvalue = strtoul(val, &err, 0);
1368 if (!*val || *err || numvalue > 0xff) {
1369 fprintf(stderr, "bad numerical value %s\n", val);
1370 goto error;
1371 }
1372 x86_cpu_def->model = numvalue;
1373 } else if (!strcmp(featurestr, "stepping")) {
1374 char *err;
1375 numvalue = strtoul(val, &err, 0);
1376 if (!*val || *err || numvalue > 0xf) {
1377 fprintf(stderr, "bad numerical value %s\n", val);
1378 goto error;
1379 }
1380 x86_cpu_def->stepping = numvalue ;
1381 } else if (!strcmp(featurestr, "level")) {
1382 char *err;
1383 numvalue = strtoul(val, &err, 0);
1384 if (!*val || *err) {
1385 fprintf(stderr, "bad numerical value %s\n", val);
1386 goto error;
1387 }
1388 x86_cpu_def->level = numvalue;
1389 } else if (!strcmp(featurestr, "xlevel")) {
1390 char *err;
1391 numvalue = strtoul(val, &err, 0);
1392 if (!*val || *err) {
1393 fprintf(stderr, "bad numerical value %s\n", val);
1394 goto error;
1395 }
1396 if (numvalue < 0x80000000) {
1397 numvalue += 0x80000000;
1398 }
1399 x86_cpu_def->xlevel = numvalue;
1400 } else if (!strcmp(featurestr, "vendor")) {
1401 if (strlen(val) != 12) {
1402 fprintf(stderr, "vendor string must be 12 chars long\n");
1403 goto error;
1404 }
1405 x86_cpu_def->vendor1 = 0;
1406 x86_cpu_def->vendor2 = 0;
1407 x86_cpu_def->vendor3 = 0;
1408 for(i = 0; i < 4; i++) {
1409 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
1410 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
1411 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
1412 }
1413 x86_cpu_def->vendor_override = 1;
1414 } else if (!strcmp(featurestr, "model_id")) {
1415 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
1416 val);
1417 } else if (!strcmp(featurestr, "tsc_freq")) {
1418 int64_t tsc_freq;
1419 char *err;
1420
1421 tsc_freq = strtosz_suffix_unit(val, &err,
1422 STRTOSZ_DEFSUFFIX_B, 1000);
1423 if (tsc_freq < 0 || *err) {
1424 fprintf(stderr, "bad numerical value %s\n", val);
1425 goto error;
1426 }
1427 x86_cpu_def->tsc_khz = tsc_freq / 1000;
1428 } else if (!strcmp(featurestr, "hv_spinlocks")) {
1429 char *err;
1430 numvalue = strtoul(val, &err, 0);
1431 if (!*val || *err) {
1432 fprintf(stderr, "bad numerical value %s\n", val);
1433 goto error;
1434 }
1435 hyperv_set_spinlock_retries(numvalue);
1436 } else {
1437 fprintf(stderr, "unrecognized feature %s\n", featurestr);
1438 goto error;
1439 }
1440 } else if (!strcmp(featurestr, "check")) {
1441 check_cpuid = 1;
1442 } else if (!strcmp(featurestr, "enforce")) {
1443 check_cpuid = enforce_cpuid = 1;
1444 } else if (!strcmp(featurestr, "hv_relaxed")) {
1445 hyperv_enable_relaxed_timing(true);
1446 } else if (!strcmp(featurestr, "hv_vapic")) {
1447 hyperv_enable_vapic_recommended(true);
1448 } else {
1449 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1450 goto error;
1451 }
1452 featurestr = strtok(NULL, ",");
1453 }
1454 x86_cpu_def->features |= plus_features[FEAT_1_EDX];
1455 x86_cpu_def->ext_features |= plus_features[FEAT_1_ECX];
1456 x86_cpu_def->ext2_features |= plus_features[FEAT_8000_0001_EDX];
1457 x86_cpu_def->ext3_features |= plus_features[FEAT_8000_0001_ECX];
1458 x86_cpu_def->ext4_features |= plus_features[FEAT_C000_0001_EDX];
1459 x86_cpu_def->kvm_features |= plus_features[FEAT_KVM];
1460 x86_cpu_def->svm_features |= plus_features[FEAT_SVM];
1461 x86_cpu_def->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1462 x86_cpu_def->features &= ~minus_features[FEAT_1_EDX];
1463 x86_cpu_def->ext_features &= ~minus_features[FEAT_1_ECX];
1464 x86_cpu_def->ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1465 x86_cpu_def->ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1466 x86_cpu_def->ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1467 x86_cpu_def->kvm_features &= ~minus_features[FEAT_KVM];
1468 x86_cpu_def->svm_features &= ~minus_features[FEAT_SVM];
1469 x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1470 return 0;
1471
1472 error:
1473 return -1;
1474 }
1475
1476 /* generate a composite string into buf of all cpuid names in featureset
1477 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1478 * if flags, suppress names undefined in featureset.
1479 */
1480 static void listflags(char *buf, int bufsize, uint32_t fbits,
1481 const char **featureset, uint32_t flags)
1482 {
1483 const char **p = &featureset[31];
1484 char *q, *b, bit;
1485 int nc;
1486
1487 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1488 *buf = '\0';
1489 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1490 if (fbits & 1 << bit && (*p || !flags)) {
1491 if (*p)
1492 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1493 else
1494 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1495 if (bufsize <= nc) {
1496 if (b) {
1497 memcpy(b, "...", sizeof("..."));
1498 }
1499 return;
1500 }
1501 q += nc;
1502 bufsize -= nc;
1503 }
1504 }
1505
1506 /* generate CPU information. */
1507 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1508 {
1509 x86_def_t *def;
1510 char buf[256];
1511
1512 for (def = x86_defs; def; def = def->next) {
1513 snprintf(buf, sizeof(buf), "%s", def->name);
1514 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1515 }
1516 if (kvm_enabled()) {
1517 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1518 }
1519 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1520 listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1);
1521 (*cpu_fprintf)(f, " %s\n", buf);
1522 listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1);
1523 (*cpu_fprintf)(f, " %s\n", buf);
1524 listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1);
1525 (*cpu_fprintf)(f, " %s\n", buf);
1526 listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1);
1527 (*cpu_fprintf)(f, " %s\n", buf);
1528 }
1529
1530 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1531 {
1532 CpuDefinitionInfoList *cpu_list = NULL;
1533 x86_def_t *def;
1534
1535 for (def = x86_defs; def; def = def->next) {
1536 CpuDefinitionInfoList *entry;
1537 CpuDefinitionInfo *info;
1538
1539 info = g_malloc0(sizeof(*info));
1540 info->name = g_strdup(def->name);
1541
1542 entry = g_malloc0(sizeof(*entry));
1543 entry->value = info;
1544 entry->next = cpu_list;
1545 cpu_list = entry;
1546 }
1547
1548 return cpu_list;
1549 }
1550
1551 #ifdef CONFIG_KVM
1552 static void filter_features_for_kvm(X86CPU *cpu)
1553 {
1554 CPUX86State *env = &cpu->env;
1555 KVMState *s = kvm_state;
1556
1557 env->cpuid_features &=
1558 kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1559 env->cpuid_ext_features &=
1560 kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1561 env->cpuid_ext2_features &=
1562 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1563 env->cpuid_ext3_features &=
1564 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1565 env->cpuid_svm_features &=
1566 kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1567 env->cpuid_7_0_ebx_features &=
1568 kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1569 env->cpuid_kvm_features &=
1570 kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1571 env->cpuid_ext4_features &=
1572 kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1573
1574 }
1575 #endif
1576
1577 int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
1578 {
1579 CPUX86State *env = &cpu->env;
1580 x86_def_t def1, *def = &def1;
1581 Error *error = NULL;
1582 char *name, *features;
1583 gchar **model_pieces;
1584
1585 memset(def, 0, sizeof(*def));
1586
1587 model_pieces = g_strsplit(cpu_model, ",", 2);
1588 if (!model_pieces[0]) {
1589 error_setg(&error, "Invalid/empty CPU model name");
1590 goto out;
1591 }
1592 name = model_pieces[0];
1593 features = model_pieces[1];
1594
1595 if (cpu_x86_find_by_name(def, name) < 0) {
1596 error_setg(&error, "Unable to find CPU definition: %s", name);
1597 goto out;
1598 }
1599
1600 if (kvm_enabled()) {
1601 def->kvm_features |= kvm_default_features;
1602 }
1603 def->ext_features |= CPUID_EXT_HYPERVISOR;
1604
1605 if (cpu_x86_parse_featurestr(def, features) < 0) {
1606 error_setg(&error, "Invalid cpu_model string format: %s", cpu_model);
1607 goto out;
1608 }
1609 assert(def->vendor1);
1610 env->cpuid_vendor1 = def->vendor1;
1611 env->cpuid_vendor2 = def->vendor2;
1612 env->cpuid_vendor3 = def->vendor3;
1613 env->cpuid_vendor_override = def->vendor_override;
1614 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
1615 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
1616 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
1617 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
1618 env->cpuid_features = def->features;
1619 env->cpuid_ext_features = def->ext_features;
1620 env->cpuid_ext2_features = def->ext2_features;
1621 env->cpuid_ext3_features = def->ext3_features;
1622 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
1623 env->cpuid_kvm_features = def->kvm_features;
1624 env->cpuid_svm_features = def->svm_features;
1625 env->cpuid_ext4_features = def->ext4_features;
1626 env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1627 env->cpuid_xlevel2 = def->xlevel2;
1628 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1629 "tsc-frequency", &error);
1630
1631 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
1632
1633 out:
1634 g_strfreev(model_pieces);
1635 if (error) {
1636 fprintf(stderr, "%s\n", error_get_pretty(error));
1637 error_free(error);
1638 return -1;
1639 }
1640 return 0;
1641 }
1642
1643 #if !defined(CONFIG_USER_ONLY)
1644
1645 void cpu_clear_apic_feature(CPUX86State *env)
1646 {
1647 env->cpuid_features &= ~CPUID_APIC;
1648 }
1649
1650 #endif /* !CONFIG_USER_ONLY */
1651
1652 /* Initialize list of CPU models, filling some non-static fields if necessary
1653 */
1654 void x86_cpudef_setup(void)
1655 {
1656 int i, j;
1657 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1658
1659 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1660 x86_def_t *def = &builtin_x86_defs[i];
1661 def->next = x86_defs;
1662
1663 /* Look for specific "cpudef" models that */
1664 /* have the QEMU version in .model_id */
1665 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1666 if (strcmp(model_with_versions[j], def->name) == 0) {
1667 pstrcpy(def->model_id, sizeof(def->model_id),
1668 "QEMU Virtual CPU version ");
1669 pstrcat(def->model_id, sizeof(def->model_id),
1670 qemu_get_version());
1671 break;
1672 }
1673 }
1674
1675 x86_defs = def;
1676 }
1677 }
1678
1679 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1680 uint32_t *ecx, uint32_t *edx)
1681 {
1682 *ebx = env->cpuid_vendor1;
1683 *edx = env->cpuid_vendor2;
1684 *ecx = env->cpuid_vendor3;
1685
1686 /* sysenter isn't supported on compatibility mode on AMD, syscall
1687 * isn't supported in compatibility mode on Intel.
1688 * Normally we advertise the actual cpu vendor, but you can override
1689 * this if you want to use KVM's sysenter/syscall emulation
1690 * in compatibility mode and when doing cross vendor migration
1691 */
1692 if (kvm_enabled() && ! env->cpuid_vendor_override) {
1693 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1694 }
1695 }
1696
1697 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1698 uint32_t *eax, uint32_t *ebx,
1699 uint32_t *ecx, uint32_t *edx)
1700 {
1701 X86CPU *cpu = x86_env_get_cpu(env);
1702 CPUState *cs = CPU(cpu);
1703
1704 /* test if maximum index reached */
1705 if (index & 0x80000000) {
1706 if (index > env->cpuid_xlevel) {
1707 if (env->cpuid_xlevel2 > 0) {
1708 /* Handle the Centaur's CPUID instruction. */
1709 if (index > env->cpuid_xlevel2) {
1710 index = env->cpuid_xlevel2;
1711 } else if (index < 0xC0000000) {
1712 index = env->cpuid_xlevel;
1713 }
1714 } else {
1715 /* Intel documentation states that invalid EAX input will
1716 * return the same information as EAX=cpuid_level
1717 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1718 */
1719 index = env->cpuid_level;
1720 }
1721 }
1722 } else {
1723 if (index > env->cpuid_level)
1724 index = env->cpuid_level;
1725 }
1726
1727 switch(index) {
1728 case 0:
1729 *eax = env->cpuid_level;
1730 get_cpuid_vendor(env, ebx, ecx, edx);
1731 break;
1732 case 1:
1733 *eax = env->cpuid_version;
1734 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1735 *ecx = env->cpuid_ext_features;
1736 *edx = env->cpuid_features;
1737 if (cs->nr_cores * cs->nr_threads > 1) {
1738 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1739 *edx |= 1 << 28; /* HTT bit */
1740 }
1741 break;
1742 case 2:
1743 /* cache info: needed for Pentium Pro compatibility */
1744 *eax = 1;
1745 *ebx = 0;
1746 *ecx = 0;
1747 *edx = 0x2c307d;
1748 break;
1749 case 4:
1750 /* cache info: needed for Core compatibility */
1751 if (cs->nr_cores > 1) {
1752 *eax = (cs->nr_cores - 1) << 26;
1753 } else {
1754 *eax = 0;
1755 }
1756 switch (count) {
1757 case 0: /* L1 dcache info */
1758 *eax |= 0x0000121;
1759 *ebx = 0x1c0003f;
1760 *ecx = 0x000003f;
1761 *edx = 0x0000001;
1762 break;
1763 case 1: /* L1 icache info */
1764 *eax |= 0x0000122;
1765 *ebx = 0x1c0003f;
1766 *ecx = 0x000003f;
1767 *edx = 0x0000001;
1768 break;
1769 case 2: /* L2 cache info */
1770 *eax |= 0x0000143;
1771 if (cs->nr_threads > 1) {
1772 *eax |= (cs->nr_threads - 1) << 14;
1773 }
1774 *ebx = 0x3c0003f;
1775 *ecx = 0x0000fff;
1776 *edx = 0x0000001;
1777 break;
1778 default: /* end of info */
1779 *eax = 0;
1780 *ebx = 0;
1781 *ecx = 0;
1782 *edx = 0;
1783 break;
1784 }
1785 break;
1786 case 5:
1787 /* mwait info: needed for Core compatibility */
1788 *eax = 0; /* Smallest monitor-line size in bytes */
1789 *ebx = 0; /* Largest monitor-line size in bytes */
1790 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1791 *edx = 0;
1792 break;
1793 case 6:
1794 /* Thermal and Power Leaf */
1795 *eax = 0;
1796 *ebx = 0;
1797 *ecx = 0;
1798 *edx = 0;
1799 break;
1800 case 7:
1801 /* Structured Extended Feature Flags Enumeration Leaf */
1802 if (count == 0) {
1803 *eax = 0; /* Maximum ECX value for sub-leaves */
1804 *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1805 *ecx = 0; /* Reserved */
1806 *edx = 0; /* Reserved */
1807 } else {
1808 *eax = 0;
1809 *ebx = 0;
1810 *ecx = 0;
1811 *edx = 0;
1812 }
1813 break;
1814 case 9:
1815 /* Direct Cache Access Information Leaf */
1816 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1817 *ebx = 0;
1818 *ecx = 0;
1819 *edx = 0;
1820 break;
1821 case 0xA:
1822 /* Architectural Performance Monitoring Leaf */
1823 if (kvm_enabled()) {
1824 KVMState *s = cs->kvm_state;
1825
1826 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1827 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1828 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1829 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1830 } else {
1831 *eax = 0;
1832 *ebx = 0;
1833 *ecx = 0;
1834 *edx = 0;
1835 }
1836 break;
1837 case 0xD:
1838 /* Processor Extended State */
1839 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1840 *eax = 0;
1841 *ebx = 0;
1842 *ecx = 0;
1843 *edx = 0;
1844 break;
1845 }
1846 if (kvm_enabled()) {
1847 KVMState *s = cs->kvm_state;
1848
1849 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1850 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1851 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1852 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1853 } else {
1854 *eax = 0;
1855 *ebx = 0;
1856 *ecx = 0;
1857 *edx = 0;
1858 }
1859 break;
1860 case 0x80000000:
1861 *eax = env->cpuid_xlevel;
1862 *ebx = env->cpuid_vendor1;
1863 *edx = env->cpuid_vendor2;
1864 *ecx = env->cpuid_vendor3;
1865 break;
1866 case 0x80000001:
1867 *eax = env->cpuid_version;
1868 *ebx = 0;
1869 *ecx = env->cpuid_ext3_features;
1870 *edx = env->cpuid_ext2_features;
1871
1872 /* The Linux kernel checks for the CMPLegacy bit and
1873 * discards multiple thread information if it is set.
1874 * So dont set it here for Intel to make Linux guests happy.
1875 */
1876 if (cs->nr_cores * cs->nr_threads > 1) {
1877 uint32_t tebx, tecx, tedx;
1878 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1879 if (tebx != CPUID_VENDOR_INTEL_1 ||
1880 tedx != CPUID_VENDOR_INTEL_2 ||
1881 tecx != CPUID_VENDOR_INTEL_3) {
1882 *ecx |= 1 << 1; /* CmpLegacy bit */
1883 }
1884 }
1885 break;
1886 case 0x80000002:
1887 case 0x80000003:
1888 case 0x80000004:
1889 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1890 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1891 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1892 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1893 break;
1894 case 0x80000005:
1895 /* cache info (L1 cache) */
1896 *eax = 0x01ff01ff;
1897 *ebx = 0x01ff01ff;
1898 *ecx = 0x40020140;
1899 *edx = 0x40020140;
1900 break;
1901 case 0x80000006:
1902 /* cache info (L2 cache) */
1903 *eax = 0;
1904 *ebx = 0x42004200;
1905 *ecx = 0x02008140;
1906 *edx = 0;
1907 break;
1908 case 0x80000008:
1909 /* virtual & phys address size in low 2 bytes. */
1910 /* XXX: This value must match the one used in the MMU code. */
1911 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1912 /* 64 bit processor */
1913 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1914 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1915 } else {
1916 if (env->cpuid_features & CPUID_PSE36)
1917 *eax = 0x00000024; /* 36 bits physical */
1918 else
1919 *eax = 0x00000020; /* 32 bits physical */
1920 }
1921 *ebx = 0;
1922 *ecx = 0;
1923 *edx = 0;
1924 if (cs->nr_cores * cs->nr_threads > 1) {
1925 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1926 }
1927 break;
1928 case 0x8000000A:
1929 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1930 *eax = 0x00000001; /* SVM Revision */
1931 *ebx = 0x00000010; /* nr of ASIDs */
1932 *ecx = 0;
1933 *edx = env->cpuid_svm_features; /* optional features */
1934 } else {
1935 *eax = 0;
1936 *ebx = 0;
1937 *ecx = 0;
1938 *edx = 0;
1939 }
1940 break;
1941 case 0xC0000000:
1942 *eax = env->cpuid_xlevel2;
1943 *ebx = 0;
1944 *ecx = 0;
1945 *edx = 0;
1946 break;
1947 case 0xC0000001:
1948 /* Support for VIA CPU's CPUID instruction */
1949 *eax = env->cpuid_version;
1950 *ebx = 0;
1951 *ecx = 0;
1952 *edx = env->cpuid_ext4_features;
1953 break;
1954 case 0xC0000002:
1955 case 0xC0000003:
1956 case 0xC0000004:
1957 /* Reserved for the future, and now filled with zero */
1958 *eax = 0;
1959 *ebx = 0;
1960 *ecx = 0;
1961 *edx = 0;
1962 break;
1963 default:
1964 /* reserved values: zero */
1965 *eax = 0;
1966 *ebx = 0;
1967 *ecx = 0;
1968 *edx = 0;
1969 break;
1970 }
1971 }
1972
1973 /* CPUClass::reset() */
1974 static void x86_cpu_reset(CPUState *s)
1975 {
1976 X86CPU *cpu = X86_CPU(s);
1977 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1978 CPUX86State *env = &cpu->env;
1979 int i;
1980
1981 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1982 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
1983 log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
1984 }
1985
1986 xcc->parent_reset(s);
1987
1988
1989 memset(env, 0, offsetof(CPUX86State, breakpoints));
1990
1991 tlb_flush(env, 1);
1992
1993 env->old_exception = -1;
1994
1995 /* init to reset state */
1996
1997 #ifdef CONFIG_SOFTMMU
1998 env->hflags |= HF_SOFTMMU_MASK;
1999 #endif
2000 env->hflags2 |= HF2_GIF_MASK;
2001
2002 cpu_x86_update_cr0(env, 0x60000010);
2003 env->a20_mask = ~0x0;
2004 env->smbase = 0x30000;
2005
2006 env->idt.limit = 0xffff;
2007 env->gdt.limit = 0xffff;
2008 env->ldt.limit = 0xffff;
2009 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2010 env->tr.limit = 0xffff;
2011 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2012
2013 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2014 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2015 DESC_R_MASK | DESC_A_MASK);
2016 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2017 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2018 DESC_A_MASK);
2019 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2020 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2021 DESC_A_MASK);
2022 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2023 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2024 DESC_A_MASK);
2025 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2026 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2027 DESC_A_MASK);
2028 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2029 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2030 DESC_A_MASK);
2031
2032 env->eip = 0xfff0;
2033 env->regs[R_EDX] = env->cpuid_version;
2034
2035 env->eflags = 0x2;
2036
2037 /* FPU init */
2038 for (i = 0; i < 8; i++) {
2039 env->fptags[i] = 1;
2040 }
2041 env->fpuc = 0x37f;
2042
2043 env->mxcsr = 0x1f80;
2044
2045 env->pat = 0x0007040600070406ULL;
2046 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2047
2048 memset(env->dr, 0, sizeof(env->dr));
2049 env->dr[6] = DR6_FIXED_1;
2050 env->dr[7] = DR7_FIXED_1;
2051 cpu_breakpoint_remove_all(env, BP_CPU);
2052 cpu_watchpoint_remove_all(env, BP_CPU);
2053
2054 #if !defined(CONFIG_USER_ONLY)
2055 /* We hard-wire the BSP to the first CPU. */
2056 if (s->cpu_index == 0) {
2057 apic_designate_bsp(env->apic_state);
2058 }
2059
2060 env->halted = !cpu_is_bsp(cpu);
2061 #endif
2062 }
2063
2064 #ifndef CONFIG_USER_ONLY
2065 bool cpu_is_bsp(X86CPU *cpu)
2066 {
2067 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2068 }
2069
2070 /* TODO: remove me, when reset over QOM tree is implemented */
2071 static void x86_cpu_machine_reset_cb(void *opaque)
2072 {
2073 X86CPU *cpu = opaque;
2074 cpu_reset(CPU(cpu));
2075 }
2076 #endif
2077
2078 static void mce_init(X86CPU *cpu)
2079 {
2080 CPUX86State *cenv = &cpu->env;
2081 unsigned int bank;
2082
2083 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2084 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2085 (CPUID_MCE | CPUID_MCA)) {
2086 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2087 cenv->mcg_ctl = ~(uint64_t)0;
2088 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2089 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2090 }
2091 }
2092 }
2093
2094 #define MSI_ADDR_BASE 0xfee00000
2095
2096 #ifndef CONFIG_USER_ONLY
2097 static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
2098 {
2099 static int apic_mapped;
2100 CPUX86State *env = &cpu->env;
2101 APICCommonState *apic;
2102 const char *apic_type = "apic";
2103
2104 if (kvm_irqchip_in_kernel()) {
2105 apic_type = "kvm-apic";
2106 } else if (xen_enabled()) {
2107 apic_type = "xen-apic";
2108 }
2109
2110 env->apic_state = qdev_try_create(NULL, apic_type);
2111 if (env->apic_state == NULL) {
2112 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2113 return;
2114 }
2115
2116 object_property_add_child(OBJECT(cpu), "apic",
2117 OBJECT(env->apic_state), NULL);
2118 qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2119 /* TODO: convert to link<> */
2120 apic = APIC_COMMON(env->apic_state);
2121 apic->cpu = cpu;
2122
2123 if (qdev_init(env->apic_state)) {
2124 error_setg(errp, "APIC device '%s' could not be initialized",
2125 object_get_typename(OBJECT(env->apic_state)));
2126 return;
2127 }
2128
2129 /* XXX: mapping more APICs at the same memory location */
2130 if (apic_mapped == 0) {
2131 /* NOTE: the APIC is directly connected to the CPU - it is not
2132 on the global memory bus. */
2133 /* XXX: what if the base changes? */
2134 sysbus_mmio_map(SYS_BUS_DEVICE(env->apic_state), 0, MSI_ADDR_BASE);
2135 apic_mapped = 1;
2136 }
2137 }
2138 #endif
2139
2140 void x86_cpu_realize(Object *obj, Error **errp)
2141 {
2142 X86CPU *cpu = X86_CPU(obj);
2143 CPUX86State *env = &cpu->env;
2144
2145 if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2146 env->cpuid_level = 7;
2147 }
2148
2149 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2150 * CPUID[1].EDX.
2151 */
2152 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2153 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2154 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2155 env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2156 env->cpuid_ext2_features |= (env->cpuid_features
2157 & CPUID_EXT2_AMD_ALIASES);
2158 }
2159
2160 if (!kvm_enabled()) {
2161 env->cpuid_features &= TCG_FEATURES;
2162 env->cpuid_ext_features &= TCG_EXT_FEATURES;
2163 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2164 #ifdef TARGET_X86_64
2165 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2166 #endif
2167 );
2168 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2169 env->cpuid_svm_features &= TCG_SVM_FEATURES;
2170 } else {
2171 #ifdef CONFIG_KVM
2172 filter_features_for_kvm(cpu);
2173 #endif
2174 if (check_cpuid && kvm_check_features_against_host(cpu)
2175 && enforce_cpuid) {
2176 error_setg(errp, "Host's CPU doesn't support requested features");
2177 return;
2178 }
2179 }
2180
2181 #ifndef CONFIG_USER_ONLY
2182 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2183
2184 if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2185 x86_cpu_apic_init(cpu, errp);
2186 if (error_is_set(errp)) {
2187 return;
2188 }
2189 }
2190 #endif
2191
2192 mce_init(cpu);
2193 qemu_init_vcpu(&cpu->env);
2194 cpu_reset(CPU(cpu));
2195 }
2196
2197 /* Calculates initial APIC ID for a specific CPU index
2198 *
2199 * Currently we need to be able to calculate the APIC ID from the CPU index
2200 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2201 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2202 * all CPUs up to max_cpus.
2203 */
2204 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2205 {
2206 /* right now APIC ID == CPU index. this will eventually change to use
2207 * the CPU topology configuration properly
2208 */
2209 return cpu_index;
2210 }
2211
2212 static void x86_cpu_initfn(Object *obj)
2213 {
2214 CPUState *cs = CPU(obj);
2215 X86CPU *cpu = X86_CPU(obj);
2216 CPUX86State *env = &cpu->env;
2217 static int inited;
2218
2219 cpu_exec_init(env);
2220
2221 object_property_add(obj, "family", "int",
2222 x86_cpuid_version_get_family,
2223 x86_cpuid_version_set_family, NULL, NULL, NULL);
2224 object_property_add(obj, "model", "int",
2225 x86_cpuid_version_get_model,
2226 x86_cpuid_version_set_model, NULL, NULL, NULL);
2227 object_property_add(obj, "stepping", "int",
2228 x86_cpuid_version_get_stepping,
2229 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2230 object_property_add(obj, "level", "int",
2231 x86_cpuid_get_level,
2232 x86_cpuid_set_level, NULL, NULL, NULL);
2233 object_property_add(obj, "xlevel", "int",
2234 x86_cpuid_get_xlevel,
2235 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2236 object_property_add_str(obj, "vendor",
2237 x86_cpuid_get_vendor,
2238 x86_cpuid_set_vendor, NULL);
2239 object_property_add_str(obj, "model-id",
2240 x86_cpuid_get_model_id,
2241 x86_cpuid_set_model_id, NULL);
2242 object_property_add(obj, "tsc-frequency", "int",
2243 x86_cpuid_get_tsc_freq,
2244 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2245
2246 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2247
2248 /* init various static tables used in TCG mode */
2249 if (tcg_enabled() && !inited) {
2250 inited = 1;
2251 optimize_flags_init();
2252 #ifndef CONFIG_USER_ONLY
2253 cpu_set_debug_excp_handler(breakpoint_handler);
2254 #endif
2255 }
2256 }
2257
2258 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2259 {
2260 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2261 CPUClass *cc = CPU_CLASS(oc);
2262
2263 xcc->parent_reset = cc->reset;
2264 cc->reset = x86_cpu_reset;
2265 }
2266
2267 static const TypeInfo x86_cpu_type_info = {
2268 .name = TYPE_X86_CPU,
2269 .parent = TYPE_CPU,
2270 .instance_size = sizeof(X86CPU),
2271 .instance_init = x86_cpu_initfn,
2272 .abstract = false,
2273 .class_size = sizeof(X86CPUClass),
2274 .class_init = x86_cpu_common_class_init,
2275 };
2276
2277 static void x86_cpu_register_types(void)
2278 {
2279 type_register_static(&x86_cpu_type_info);
2280 }
2281
2282 type_init(x86_cpu_register_types)
Qemu copy for testing