2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
26 #define TARGET_LONG_BITS 64
28 #define TARGET_LONG_BITS 32
31 /* target supports implicit self modifying code */
32 #define TARGET_HAS_SMC
33 /* support for self modifying code even if the modified instruction is
34 close to the modifying instruction */
35 #define TARGET_HAS_PRECISE_SMC
37 #define TARGET_HAS_ICE 1
40 #define ELF_MACHINE EM_X86_64
42 #define ELF_MACHINE EM_386
45 #define CPUArchState struct CPUX86State
49 #include "softfloat.h"
76 /* segment descriptor fields */
77 #define DESC_G_MASK (1 << 23)
78 #define DESC_B_SHIFT 22
79 #define DESC_B_MASK (1 << DESC_B_SHIFT)
80 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
81 #define DESC_L_MASK (1 << DESC_L_SHIFT)
82 #define DESC_AVL_MASK (1 << 20)
83 #define DESC_P_MASK (1 << 15)
84 #define DESC_DPL_SHIFT 13
85 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
86 #define DESC_S_MASK (1 << 12)
87 #define DESC_TYPE_SHIFT 8
88 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
89 #define DESC_A_MASK (1 << 8)
91 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
92 #define DESC_C_MASK (1 << 10) /* code: conforming */
93 #define DESC_R_MASK (1 << 9) /* code: readable */
95 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
96 #define DESC_W_MASK (1 << 9) /* data: writable */
98 #define DESC_TSS_BUSY_MASK (1 << 9)
109 #define IOPL_SHIFT 12
112 #define TF_MASK 0x00000100
113 #define IF_MASK 0x00000200
114 #define DF_MASK 0x00000400
115 #define IOPL_MASK 0x00003000
116 #define NT_MASK 0x00004000
117 #define RF_MASK 0x00010000
118 #define VM_MASK 0x00020000
119 #define AC_MASK 0x00040000
120 #define VIF_MASK 0x00080000
121 #define VIP_MASK 0x00100000
122 #define ID_MASK 0x00200000
124 /* hidden flags - used internally by qemu to represent additional cpu
125 states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
126 redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
127 position to ease oring with eflags. */
129 #define HF_CPL_SHIFT 0
130 /* true if soft mmu is being used */
131 #define HF_SOFTMMU_SHIFT 2
132 /* true if hardware interrupts must be disabled for next instruction */
133 #define HF_INHIBIT_IRQ_SHIFT 3
134 /* 16 or 32 segments */
135 #define HF_CS32_SHIFT 4
136 #define HF_SS32_SHIFT 5
137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
138 #define HF_ADDSEG_SHIFT 6
139 /* copy of CR0.PE (protected mode) */
140 #define HF_PE_SHIFT 7
141 #define HF_TF_SHIFT 8 /* must be same as eflags */
142 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
143 #define HF_EM_SHIFT 10
144 #define HF_TS_SHIFT 11
145 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
146 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
147 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
148 #define HF_RF_SHIFT 16 /* must be same as eflags */
149 #define HF_VM_SHIFT 17 /* must be same as eflags */
150 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
151 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
152 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
153 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
155 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
156 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
157 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
158 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
159 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
160 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
161 #define HF_PE_MASK (1 << HF_PE_SHIFT)
162 #define HF_TF_MASK (1 << HF_TF_SHIFT)
163 #define HF_MP_MASK (1 << HF_MP_SHIFT)
164 #define HF_EM_MASK (1 << HF_EM_SHIFT)
165 #define HF_TS_MASK (1 << HF_TS_SHIFT)
166 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
167 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
168 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
169 #define HF_RF_MASK (1 << HF_RF_SHIFT)
170 #define HF_VM_MASK (1 << HF_VM_SHIFT)
171 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
172 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
173 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
174 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
178 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
179 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
180 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
181 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
183 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
184 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
185 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
186 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
188 #define CR0_PE_SHIFT 0
189 #define CR0_MP_SHIFT 1
191 #define CR0_PE_MASK (1 << 0)
192 #define CR0_MP_MASK (1 << 1)
193 #define CR0_EM_MASK (1 << 2)
194 #define CR0_TS_MASK (1 << 3)
195 #define CR0_ET_MASK (1 << 4)
196 #define CR0_NE_MASK (1 << 5)
197 #define CR0_WP_MASK (1 << 16)
198 #define CR0_AM_MASK (1 << 18)
199 #define CR0_PG_MASK (1 << 31)
201 #define CR4_VME_MASK (1 << 0)
202 #define CR4_PVI_MASK (1 << 1)
203 #define CR4_TSD_MASK (1 << 2)
204 #define CR4_DE_MASK (1 << 3)
205 #define CR4_PSE_MASK (1 << 4)
206 #define CR4_PAE_MASK (1 << 5)
207 #define CR4_MCE_MASK (1 << 6)
208 #define CR4_PGE_MASK (1 << 7)
209 #define CR4_PCE_MASK (1 << 8)
210 #define CR4_OSFXSR_SHIFT 9
211 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
212 #define CR4_OSXMMEXCPT_MASK (1 << 10)
214 #define DR6_BD (1 << 13)
215 #define DR6_BS (1 << 14)
216 #define DR6_BT (1 << 15)
217 #define DR6_FIXED_1 0xffff0ff0
219 #define DR7_GD (1 << 13)
220 #define DR7_TYPE_SHIFT 16
221 #define DR7_LEN_SHIFT 18
222 #define DR7_FIXED_1 0x00000400
224 #define PG_PRESENT_BIT 0
226 #define PG_USER_BIT 2
229 #define PG_ACCESSED_BIT 5
230 #define PG_DIRTY_BIT 6
232 #define PG_GLOBAL_BIT 8
235 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
236 #define PG_RW_MASK (1 << PG_RW_BIT)
237 #define PG_USER_MASK (1 << PG_USER_BIT)
238 #define PG_PWT_MASK (1 << PG_PWT_BIT)
239 #define PG_PCD_MASK (1 << PG_PCD_BIT)
240 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
241 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
242 #define PG_PSE_MASK (1 << PG_PSE_BIT)
243 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
244 #define PG_HI_USER_MASK 0x7ff0000000000000LL
245 #define PG_NX_MASK (1LL << PG_NX_BIT)
247 #define PG_ERROR_W_BIT 1
249 #define PG_ERROR_P_MASK 0x01
250 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
251 #define PG_ERROR_U_MASK 0x04
252 #define PG_ERROR_RSVD_MASK 0x08
253 #define PG_ERROR_I_D_MASK 0x10
255 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
256 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
258 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
259 #define MCE_BANKS_DEF 10
261 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
262 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
263 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
265 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
266 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
267 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
268 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
269 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
270 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
271 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
272 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
273 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
275 /* MISC register defines */
276 #define MCM_ADDR_SEGOFF 0 /* segment offset */
277 #define MCM_ADDR_LINEAR 1 /* linear address */
278 #define MCM_ADDR_PHYS 2 /* physical address */
279 #define MCM_ADDR_MEM 3 /* memory address */
280 #define MCM_ADDR_GENERIC 7 /* generic */
282 #define MSR_IA32_TSC 0x10
283 #define MSR_IA32_APICBASE 0x1b
284 #define MSR_IA32_APICBASE_BSP (1<<8)
285 #define MSR_IA32_APICBASE_ENABLE (1<<11)
286 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
287 #define MSR_IA32_TSCDEADLINE 0x6e0
289 #define MSR_MTRRcap 0xfe
290 #define MSR_MTRRcap_VCNT 8
291 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
292 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
294 #define MSR_IA32_SYSENTER_CS 0x174
295 #define MSR_IA32_SYSENTER_ESP 0x175
296 #define MSR_IA32_SYSENTER_EIP 0x176
298 #define MSR_MCG_CAP 0x179
299 #define MSR_MCG_STATUS 0x17a
300 #define MSR_MCG_CTL 0x17b
302 #define MSR_IA32_PERF_STATUS 0x198
304 #define MSR_IA32_MISC_ENABLE 0x1a0
305 /* Indicates good rep/movs microcode on some processors: */
306 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
308 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
309 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
311 #define MSR_MTRRfix64K_00000 0x250
312 #define MSR_MTRRfix16K_80000 0x258
313 #define MSR_MTRRfix16K_A0000 0x259
314 #define MSR_MTRRfix4K_C0000 0x268
315 #define MSR_MTRRfix4K_C8000 0x269
316 #define MSR_MTRRfix4K_D0000 0x26a
317 #define MSR_MTRRfix4K_D8000 0x26b
318 #define MSR_MTRRfix4K_E0000 0x26c
319 #define MSR_MTRRfix4K_E8000 0x26d
320 #define MSR_MTRRfix4K_F0000 0x26e
321 #define MSR_MTRRfix4K_F8000 0x26f
323 #define MSR_PAT 0x277
325 #define MSR_MTRRdefType 0x2ff
327 #define MSR_MC0_CTL 0x400
328 #define MSR_MC0_STATUS 0x401
329 #define MSR_MC0_ADDR 0x402
330 #define MSR_MC0_MISC 0x403
332 #define MSR_EFER 0xc0000080
334 #define MSR_EFER_SCE (1 << 0)
335 #define MSR_EFER_LME (1 << 8)
336 #define MSR_EFER_LMA (1 << 10)
337 #define MSR_EFER_NXE (1 << 11)
338 #define MSR_EFER_SVME (1 << 12)
339 #define MSR_EFER_FFXSR (1 << 14)
341 #define MSR_STAR 0xc0000081
342 #define MSR_LSTAR 0xc0000082
343 #define MSR_CSTAR 0xc0000083
344 #define MSR_FMASK 0xc0000084
345 #define MSR_FSBASE 0xc0000100
346 #define MSR_GSBASE 0xc0000101
347 #define MSR_KERNELGSBASE 0xc0000102
348 #define MSR_TSC_AUX 0xc0000103
350 #define MSR_VM_HSAVE_PA 0xc0010117
352 /* cpuid_features bits */
353 #define CPUID_FP87 (1 << 0)
354 #define CPUID_VME (1 << 1)
355 #define CPUID_DE (1 << 2)
356 #define CPUID_PSE (1 << 3)
357 #define CPUID_TSC (1 << 4)
358 #define CPUID_MSR (1 << 5)
359 #define CPUID_PAE (1 << 6)
360 #define CPUID_MCE (1 << 7)
361 #define CPUID_CX8 (1 << 8)
362 #define CPUID_APIC (1 << 9)
363 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */
364 #define CPUID_MTRR (1 << 12)
365 #define CPUID_PGE (1 << 13)
366 #define CPUID_MCA (1 << 14)
367 #define CPUID_CMOV (1 << 15)
368 #define CPUID_PAT (1 << 16)
369 #define CPUID_PSE36 (1 << 17)
370 #define CPUID_PN (1 << 18)
371 #define CPUID_CLFLUSH (1 << 19)
372 #define CPUID_DTS (1 << 21)
373 #define CPUID_ACPI (1 << 22)
374 #define CPUID_MMX (1 << 23)
375 #define CPUID_FXSR (1 << 24)
376 #define CPUID_SSE (1 << 25)
377 #define CPUID_SSE2 (1 << 26)
378 #define CPUID_SS (1 << 27)
379 #define CPUID_HT (1 << 28)
380 #define CPUID_TM (1 << 29)
381 #define CPUID_IA64 (1 << 30)
382 #define CPUID_PBE (1 << 31)
384 #define CPUID_EXT_SSE3 (1 << 0)
385 #define CPUID_EXT_PCLMULQDQ (1 << 1)
386 #define CPUID_EXT_DTES64 (1 << 2)
387 #define CPUID_EXT_MONITOR (1 << 3)
388 #define CPUID_EXT_DSCPL (1 << 4)
389 #define CPUID_EXT_VMX (1 << 5)
390 #define CPUID_EXT_SMX (1 << 6)
391 #define CPUID_EXT_EST (1 << 7)
392 #define CPUID_EXT_TM2 (1 << 8)
393 #define CPUID_EXT_SSSE3 (1 << 9)
394 #define CPUID_EXT_CID (1 << 10)
395 #define CPUID_EXT_CX16 (1 << 13)
396 #define CPUID_EXT_XTPR (1 << 14)
397 #define CPUID_EXT_PDCM (1 << 15)
398 #define CPUID_EXT_DCA (1 << 18)
399 #define CPUID_EXT_SSE41 (1 << 19)
400 #define CPUID_EXT_SSE42 (1 << 20)
401 #define CPUID_EXT_X2APIC (1 << 21)
402 #define CPUID_EXT_MOVBE (1 << 22)
403 #define CPUID_EXT_POPCNT (1 << 23)
404 #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
405 #define CPUID_EXT_AES (1 << 25)
406 #define CPUID_EXT_XSAVE (1 << 26)
407 #define CPUID_EXT_OSXSAVE (1 << 27)
408 #define CPUID_EXT_AVX (1 << 28)
409 #define CPUID_EXT_HYPERVISOR (1 << 31)
411 #define CPUID_EXT2_FPU (1 << 0)
412 #define CPUID_EXT2_VME (1 << 1)
413 #define CPUID_EXT2_DE (1 << 2)
414 #define CPUID_EXT2_PSE (1 << 3)
415 #define CPUID_EXT2_TSC (1 << 4)
416 #define CPUID_EXT2_MSR (1 << 5)
417 #define CPUID_EXT2_PAE (1 << 6)
418 #define CPUID_EXT2_MCE (1 << 7)
419 #define CPUID_EXT2_CX8 (1 << 8)
420 #define CPUID_EXT2_APIC (1 << 9)
421 #define CPUID_EXT2_SYSCALL (1 << 11)
422 #define CPUID_EXT2_MTRR (1 << 12)
423 #define CPUID_EXT2_PGE (1 << 13)
424 #define CPUID_EXT2_MCA (1 << 14)
425 #define CPUID_EXT2_CMOV (1 << 15)
426 #define CPUID_EXT2_PAT (1 << 16)
427 #define CPUID_EXT2_PSE36 (1 << 17)
428 #define CPUID_EXT2_MP (1 << 19)
429 #define CPUID_EXT2_NX (1 << 20)
430 #define CPUID_EXT2_MMXEXT (1 << 22)
431 #define CPUID_EXT2_MMX (1 << 23)
432 #define CPUID_EXT2_FXSR (1 << 24)
433 #define CPUID_EXT2_FFXSR (1 << 25)
434 #define CPUID_EXT2_PDPE1GB (1 << 26)
435 #define CPUID_EXT2_RDTSCP (1 << 27)
436 #define CPUID_EXT2_LM (1 << 29)
437 #define CPUID_EXT2_3DNOWEXT (1 << 30)
438 #define CPUID_EXT2_3DNOW (1 << 31)
440 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
441 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
442 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
443 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
444 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
445 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
446 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
447 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
448 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
449 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
451 #define CPUID_EXT3_LAHF_LM (1 << 0)
452 #define CPUID_EXT3_CMP_LEG (1 << 1)
453 #define CPUID_EXT3_SVM (1 << 2)
454 #define CPUID_EXT3_EXTAPIC (1 << 3)
455 #define CPUID_EXT3_CR8LEG (1 << 4)
456 #define CPUID_EXT3_ABM (1 << 5)
457 #define CPUID_EXT3_SSE4A (1 << 6)
458 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
459 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
460 #define CPUID_EXT3_OSVW (1 << 9)
461 #define CPUID_EXT3_IBS (1 << 10)
462 #define CPUID_EXT3_XOP (1 << 11)
463 #define CPUID_EXT3_SKINIT (1 << 12)
464 #define CPUID_EXT3_FMA4 (1 << 16)
466 #define CPUID_SVM_NPT (1 << 0)
467 #define CPUID_SVM_LBRV (1 << 1)
468 #define CPUID_SVM_SVMLOCK (1 << 2)
469 #define CPUID_SVM_NRIPSAVE (1 << 3)
470 #define CPUID_SVM_TSCSCALE (1 << 4)
471 #define CPUID_SVM_VMCBCLEAN (1 << 5)
472 #define CPUID_SVM_FLUSHASID (1 << 6)
473 #define CPUID_SVM_DECODEASSIST (1 << 7)
474 #define CPUID_SVM_PAUSEFILTER (1 << 10)
475 #define CPUID_SVM_PFTHRESHOLD (1 << 12)
477 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
478 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
479 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
481 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
482 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
483 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
485 #define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */
486 #define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */
487 #define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */
489 #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */
490 #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */
492 #define EXCP00_DIVZ 0
495 #define EXCP03_INT3 3
496 #define EXCP04_INTO 4
497 #define EXCP05_BOUND 5
498 #define EXCP06_ILLOP 6
499 #define EXCP07_PREX 7
500 #define EXCP08_DBLE 8
501 #define EXCP09_XERR 9
502 #define EXCP0A_TSS 10
503 #define EXCP0B_NOSEG 11
504 #define EXCP0C_STACK 12
505 #define EXCP0D_GPF 13
506 #define EXCP0E_PAGE 14
507 #define EXCP10_COPR 16
508 #define EXCP11_ALGN 17
509 #define EXCP12_MCHK 18
511 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
512 for syscall instruction */
514 /* i386-specific interrupt pending bits. */
515 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
516 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
517 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
518 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
519 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
520 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
521 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
522 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3
526 CC_OP_DYNAMIC
, /* must use dynamic code to get cc_op */
527 CC_OP_EFLAGS
, /* all cc are explicitly computed, CC_SRC = flags */
529 CC_OP_MULB
, /* modify all flags, C, O = (CC_SRC != 0) */
534 CC_OP_ADDB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
539 CC_OP_ADCB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
544 CC_OP_SUBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
549 CC_OP_SBBB
, /* modify all flags, CC_DST = res, CC_SRC = src1 */
554 CC_OP_LOGICB
, /* modify all flags, CC_DST = res */
559 CC_OP_INCB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
564 CC_OP_DECB
, /* modify all flags except, CC_DST = res, CC_SRC = C */
569 CC_OP_SHLB
, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
574 CC_OP_SARB
, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
582 typedef struct SegmentCache
{
606 #ifdef HOST_WORDS_BIGENDIAN
607 #define XMM_B(n) _b[15 - (n)]
608 #define XMM_W(n) _w[7 - (n)]
609 #define XMM_L(n) _l[3 - (n)]
610 #define XMM_S(n) _s[3 - (n)]
611 #define XMM_Q(n) _q[1 - (n)]
612 #define XMM_D(n) _d[1 - (n)]
614 #define MMX_B(n) _b[7 - (n)]
615 #define MMX_W(n) _w[3 - (n)]
616 #define MMX_L(n) _l[1 - (n)]
617 #define MMX_S(n) _s[1 - (n)]
619 #define XMM_B(n) _b[n]
620 #define XMM_W(n) _w[n]
621 #define XMM_L(n) _l[n]
622 #define XMM_S(n) _s[n]
623 #define XMM_Q(n) _q[n]
624 #define XMM_D(n) _d[n]
626 #define MMX_B(n) _b[n]
627 #define MMX_W(n) _w[n]
628 #define MMX_L(n) _l[n]
629 #define MMX_S(n) _s[n]
634 floatx80 d
__attribute__((aligned(16)));
643 #define CPU_NB_REGS64 16
644 #define CPU_NB_REGS32 8
647 #define CPU_NB_REGS CPU_NB_REGS64
649 #define CPU_NB_REGS CPU_NB_REGS32
652 #define NB_MMU_MODES 2
654 typedef enum TPRAccess
{
659 typedef struct CPUX86State
{
660 /* standard registers */
661 target_ulong regs
[CPU_NB_REGS
];
663 target_ulong eflags
; /* eflags register. During CPU emulation, CC
664 flags and DF are set to zero because they are
667 /* emulator internal eflags handling */
671 int32_t df
; /* D flag : 1 if D = 0, -1 if D = 1 */
672 uint32_t hflags
; /* TB flags, see HF_xxx constants. These flags
673 are known at translation time. */
674 uint32_t hflags2
; /* various other flags, see HF2_xxx constants. */
677 SegmentCache segs
[6]; /* selector values */
680 SegmentCache gdt
; /* only base and limit are used */
681 SegmentCache idt
; /* only base and limit are used */
683 target_ulong cr
[5]; /* NOTE: cr1 is unused */
687 unsigned int fpstt
; /* top of stack index */
690 uint8_t fptags
[8]; /* 0 = valid, 1 = empty */
692 /* KVM-only so far */
697 /* emulator internal variables */
698 float_status fp_status
;
701 float_status mmx_status
; /* for 3DNow! float ops */
702 float_status sse_status
;
704 XMMReg xmm_regs
[CPU_NB_REGS
];
707 target_ulong cc_tmp
; /* temporary for rcr/rcl */
709 /* sysenter registers */
710 uint32_t sysenter_cs
;
711 target_ulong sysenter_esp
;
712 target_ulong sysenter_eip
;
720 uint16_t intercept_cr_read
;
721 uint16_t intercept_cr_write
;
722 uint16_t intercept_dr_read
;
723 uint16_t intercept_dr_write
;
724 uint32_t intercept_exceptions
;
731 target_ulong kernelgsbase
;
733 uint64_t system_time_msr
;
734 uint64_t wall_clock_msr
;
735 uint64_t async_pf_en_msr
;
736 uint64_t pv_eoi_en_msr
;
739 uint64_t tsc_deadline
;
742 uint64_t msr_ia32_misc_enable
;
744 /* exception/interrupt handling */
746 int exception_is_int
;
747 target_ulong exception_next_eip
;
748 target_ulong dr
[8]; /* debug registers */
750 CPUBreakpoint
*cpu_breakpoint
[4];
751 CPUWatchpoint
*cpu_watchpoint
[4];
752 }; /* break/watchpoints for dr[0..3] */
754 int old_exception
; /* exception in flight */
756 /* KVM states, automatically cleared on reset */
757 uint8_t nmi_injected
;
764 /* processor features (e.g. for CPUID insn) */
765 uint32_t cpuid_level
;
766 uint32_t cpuid_vendor1
;
767 uint32_t cpuid_vendor2
;
768 uint32_t cpuid_vendor3
;
769 uint32_t cpuid_version
;
770 uint32_t cpuid_features
;
771 uint32_t cpuid_ext_features
;
772 uint32_t cpuid_xlevel
;
773 uint32_t cpuid_model
[12];
774 uint32_t cpuid_ext2_features
;
775 uint32_t cpuid_ext3_features
;
776 uint32_t cpuid_apic_id
;
777 int cpuid_vendor_override
;
778 /* Store the results of Centaur's CPUID instructions */
779 uint32_t cpuid_xlevel2
;
780 uint32_t cpuid_ext4_features
;
781 /* Flags from CPUID[EAX=7,ECX=0].EBX */
782 uint32_t cpuid_7_0_ebx
;
785 uint64_t mtrr_fixed
[11];
786 uint64_t mtrr_deftype
;
791 int32_t exception_injected
;
792 int32_t interrupt_injected
;
793 uint8_t soft_interrupt
;
794 uint8_t has_error_code
;
795 uint32_t sipi_vector
;
796 uint32_t cpuid_kvm_features
;
797 uint32_t cpuid_svm_features
;
802 /* in order to simplify APIC support, we leave this pointer to the
804 struct DeviceState
*apic_state
;
808 uint64_t mce_banks
[MCE_BANKS_DEF
*4];
813 uint16_t fpus_vmstate
;
814 uint16_t fptag_vmstate
;
815 uint16_t fpregs_format_vmstate
;
818 XMMReg ymmh_regs
[CPU_NB_REGS
];
822 TPRAccess tpr_access_type
;
827 X86CPU
*cpu_x86_init(const char *cpu_model
);
828 int cpu_x86_exec(CPUX86State
*s
);
829 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
830 void x86_cpudef_setup(void);
831 int cpu_x86_support_mca_broadcast(CPUX86State
*env
);
833 int cpu_get_pic_interrupt(CPUX86State
*s
);
834 /* MSDOS compatibility mode FPU exception support */
835 void cpu_set_ferr(CPUX86State
*s
);
837 /* this function must always be used to load data in the segment
838 cache: it synchronizes the hflags with the segment cache values */
839 static inline void cpu_x86_load_seg_cache(CPUX86State
*env
,
840 int seg_reg
, unsigned int selector
,
846 unsigned int new_hflags
;
848 sc
= &env
->segs
[seg_reg
];
849 sc
->selector
= selector
;
854 /* update the hidden flags */
856 if (seg_reg
== R_CS
) {
858 if ((env
->hflags
& HF_LMA_MASK
) && (flags
& DESC_L_MASK
)) {
860 env
->hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
861 env
->hflags
&= ~(HF_ADDSEG_MASK
);
865 /* legacy / compatibility case */
866 new_hflags
= (env
->segs
[R_CS
].flags
& DESC_B_MASK
)
867 >> (DESC_B_SHIFT
- HF_CS32_SHIFT
);
868 env
->hflags
= (env
->hflags
& ~(HF_CS32_MASK
| HF_CS64_MASK
)) |
872 new_hflags
= (env
->segs
[R_SS
].flags
& DESC_B_MASK
)
873 >> (DESC_B_SHIFT
- HF_SS32_SHIFT
);
874 if (env
->hflags
& HF_CS64_MASK
) {
875 /* zero base assumed for DS, ES and SS in long mode */
876 } else if (!(env
->cr
[0] & CR0_PE_MASK
) ||
877 (env
->eflags
& VM_MASK
) ||
878 !(env
->hflags
& HF_CS32_MASK
)) {
879 /* XXX: try to avoid this test. The problem comes from the
880 fact that is real mode or vm86 mode we only modify the
881 'base' and 'selector' fields of the segment cache to go
882 faster. A solution may be to force addseg to one in
884 new_hflags
|= HF_ADDSEG_MASK
;
886 new_hflags
|= ((env
->segs
[R_DS
].base
|
887 env
->segs
[R_ES
].base
|
888 env
->segs
[R_SS
].base
) != 0) <<
891 env
->hflags
= (env
->hflags
&
892 ~(HF_SS32_MASK
| HF_ADDSEG_MASK
)) | new_hflags
;
896 static inline void cpu_x86_load_seg_cache_sipi(CPUX86State
*env
,
900 cpu_x86_load_seg_cache(env
, R_CS
, sipi_vector
<< 8,
902 env
->segs
[R_CS
].limit
,
903 env
->segs
[R_CS
].flags
);
907 int cpu_x86_get_descr_debug(CPUX86State
*env
, unsigned int selector
,
908 target_ulong
*base
, unsigned int *limit
,
909 unsigned int *flags
);
911 /* wrapper, just in case memory mappings must be changed */
912 static inline void cpu_x86_set_cpl(CPUX86State
*s
, int cpl
)
915 s
->hflags
= (s
->hflags
& ~HF_CPL_MASK
) | cpl
;
917 #error HF_CPL_MASK is hardcoded
922 /* used for debug or cpu save/restore */
923 void cpu_get_fp80(uint64_t *pmant
, uint16_t *pexp
, floatx80 f
);
924 floatx80
cpu_set_fp80(uint64_t mant
, uint16_t upper
);
927 /* the following helpers are only usable in user mode simulation as
928 they can trigger unexpected exceptions */
929 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
);
930 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
);
931 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
);
933 /* you can call this signal handler from your SIGBUS and SIGSEGV
934 signal handlers to inform the virtual CPU of exceptions. non zero
935 is returned if the signal was handled by the virtual CPU. */
936 int cpu_x86_signal_handler(int host_signum
, void *pinfo
,
940 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
941 uint32_t *eax
, uint32_t *ebx
,
942 uint32_t *ecx
, uint32_t *edx
);
943 int cpu_x86_register(X86CPU
*cpu
, const char *cpu_model
);
944 void cpu_clear_apic_feature(CPUX86State
*env
);
945 void host_cpuid(uint32_t function
, uint32_t count
,
946 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
);
949 int cpu_x86_handle_mmu_fault(CPUX86State
*env
, target_ulong addr
,
950 int is_write
, int mmu_idx
);
951 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
952 void cpu_x86_set_a20(CPUX86State
*env
, int a20_state
);
954 static inline int hw_breakpoint_enabled(unsigned long dr7
, int index
)
956 return (dr7
>> (index
* 2)) & 3;
959 static inline int hw_breakpoint_type(unsigned long dr7
, int index
)
961 return (dr7
>> (DR7_TYPE_SHIFT
+ (index
* 4))) & 3;
964 static inline int hw_breakpoint_len(unsigned long dr7
, int index
)
966 int len
= ((dr7
>> (DR7_LEN_SHIFT
+ (index
* 4))) & 3);
967 return (len
== 2) ? 8 : len
+ 1;
970 void hw_breakpoint_insert(CPUX86State
*env
, int index
);
971 void hw_breakpoint_remove(CPUX86State
*env
, int index
);
972 int check_hw_breakpoints(CPUX86State
*env
, int force_dr6_update
);
973 void breakpoint_handler(CPUX86State
*env
);
975 /* will be suppressed */
976 void cpu_x86_update_cr0(CPUX86State
*env
, uint32_t new_cr0
);
977 void cpu_x86_update_cr3(CPUX86State
*env
, target_ulong new_cr3
);
978 void cpu_x86_update_cr4(CPUX86State
*env
, uint32_t new_cr4
);
981 void cpu_smm_update(CPUX86State
*env
);
982 uint64_t cpu_get_tsc(CPUX86State
*env
);
985 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */
986 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
988 #define TARGET_PAGE_BITS 12
991 #define TARGET_PHYS_ADDR_SPACE_BITS 52
992 /* ??? This is really 48 bits, sign-extended, but the only thing
993 accessible to userland with bit 48 set is the VSYSCALL, and that
994 is handled via other mechanisms. */
995 #define TARGET_VIRT_ADDR_SPACE_BITS 47
997 #define TARGET_PHYS_ADDR_SPACE_BITS 36
998 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1001 static inline CPUX86State
*cpu_init(const char *cpu_model
)
1003 X86CPU
*cpu
= cpu_x86_init(cpu_model
);
1010 #define cpu_exec cpu_x86_exec
1011 #define cpu_gen_code cpu_x86_gen_code
1012 #define cpu_signal_handler cpu_x86_signal_handler
1013 #define cpu_list x86_cpu_list
1014 #define cpudef_setup x86_cpudef_setup
1016 #define CPU_SAVE_VERSION 12
1018 /* MMU modes definitions */
1019 #define MMU_MODE0_SUFFIX _kernel
1020 #define MMU_MODE1_SUFFIX _user
1021 #define MMU_USER_IDX 1
1022 static inline int cpu_mmu_index (CPUX86State
*env
)
1024 return (env
->hflags
& HF_CPL_MASK
) == 3 ? 1 : 0;
1028 #define EAX (env->regs[R_EAX])
1030 #define ECX (env->regs[R_ECX])
1032 #define EDX (env->regs[R_EDX])
1034 #define EBX (env->regs[R_EBX])
1036 #define ESP (env->regs[R_ESP])
1038 #define EBP (env->regs[R_EBP])
1040 #define ESI (env->regs[R_ESI])
1042 #define EDI (env->regs[R_EDI])
1044 #define EIP (env->eip)
1045 #define DF (env->df)
1047 #define CC_SRC (env->cc_src)
1048 #define CC_DST (env->cc_dst)
1049 #define CC_OP (env->cc_op)
1051 /* n must be a constant to be efficient */
1052 static inline target_long
lshift(target_long x
, int n
)
1062 #define FT0 (env->ft0)
1063 #define ST0 (env->fpregs[env->fpstt].d)
1064 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1068 void optimize_flags_init(void);
1070 #if defined(CONFIG_USER_ONLY)
1071 static inline void cpu_clone_regs(CPUX86State
*env
, target_ulong newsp
)
1074 env
->regs
[R_ESP
] = newsp
;
1075 env
->regs
[R_EAX
] = 0;
1079 #include "cpu-all.h"
1082 #if !defined(CONFIG_USER_ONLY)
1083 #include "hw/apic.h"
1086 static inline bool cpu_has_work(CPUX86State
*env
)
1088 return ((env
->interrupt_request
& (CPU_INTERRUPT_HARD
|
1089 CPU_INTERRUPT_POLL
)) &&
1090 (env
->eflags
& IF_MASK
)) ||
1091 (env
->interrupt_request
& (CPU_INTERRUPT_NMI
|
1092 CPU_INTERRUPT_INIT
|
1093 CPU_INTERRUPT_SIPI
|
1094 CPU_INTERRUPT_MCE
));
1097 #include "exec-all.h"
1099 static inline void cpu_pc_from_tb(CPUX86State
*env
, TranslationBlock
*tb
)
1101 env
->eip
= tb
->pc
- tb
->cs_base
;
1104 static inline void cpu_get_tb_cpu_state(CPUX86State
*env
, target_ulong
*pc
,
1105 target_ulong
*cs_base
, int *flags
)
1107 *cs_base
= env
->segs
[R_CS
].base
;
1108 *pc
= *cs_base
+ env
->eip
;
1109 *flags
= env
->hflags
|
1110 (env
->eflags
& (IOPL_MASK
| TF_MASK
| RF_MASK
| VM_MASK
));
1113 void do_cpu_init(X86CPU
*cpu
);
1114 void do_cpu_sipi(X86CPU
*cpu
);
1116 #define MCE_INJECT_BROADCAST 1
1117 #define MCE_INJECT_UNCOND_AO 2
1119 void cpu_x86_inject_mce(Monitor
*mon
, CPUX86State
*cenv
, int bank
,
1120 uint64_t status
, uint64_t mcg_status
, uint64_t addr
,
1121 uint64_t misc
, int flags
);
1124 void QEMU_NORETURN
raise_exception(CPUX86State
*env
, int exception_index
);
1125 void QEMU_NORETURN
raise_exception_err(CPUX86State
*env
, int exception_index
,
1127 void QEMU_NORETURN
raise_interrupt(CPUX86State
*nenv
, int intno
, int is_int
,
1128 int error_code
, int next_eip_addend
);
1131 extern const uint8_t parity_table
[256];
1132 uint32_t cpu_cc_compute_all(CPUX86State
*env1
, int op
);
1134 static inline uint32_t cpu_compute_eflags(CPUX86State
*env
)
1136 return env
->eflags
| cpu_cc_compute_all(env
, CC_OP
) | (DF
& DF_MASK
);
1139 /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
1140 static inline void cpu_load_eflags(CPUX86State
*env
, int eflags
,
1143 CC_SRC
= eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
1144 DF
= 1 - (2 * ((eflags
>> 10) & 1));
1145 env
->eflags
= (env
->eflags
& ~update_mask
) |
1146 (eflags
& update_mask
) | 0x2;
1149 /* load efer and update the corresponding hflags. XXX: do consistency
1150 checks with cpuid bits? */
1151 static inline void cpu_load_efer(CPUX86State
*env
, uint64_t val
)
1154 env
->hflags
&= ~(HF_LMA_MASK
| HF_SVME_MASK
);
1155 if (env
->efer
& MSR_EFER_LMA
) {
1156 env
->hflags
|= HF_LMA_MASK
;
1158 if (env
->efer
& MSR_EFER_SVME
) {
1159 env
->hflags
|= HF_SVME_MASK
;
1164 void cpu_svm_check_intercept_param(CPUX86State
*env1
, uint32_t type
,
1166 void cpu_vmexit(CPUX86State
*nenv
, uint32_t exit_code
, uint64_t exit_info_1
);
1169 void do_interrupt(CPUX86State
*env
);
1170 void do_interrupt_x86_hardirq(CPUX86State
*env
, int intno
, int is_hw
);
1172 void do_smm_enter(CPUX86State
*env1
);
1174 void cpu_report_tpr_access(CPUX86State
*env
, TPRAccess access
);
1176 #endif /* CPU_I386_H */